2 * Copyright (c) 2003,2004 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
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34 * $DragonFly: src/sys/platform/vkernel/platform/pmap_inval.c,v 1.4 2007/07/02 02:22:58 dillon Exp $
38 * pmap invalidation support code. Certain hardware requirements must
39 * be dealt with when manipulating page table entries and page directory
40 * entries within a pmap. In particular, we cannot safely manipulate
41 * page tables which are in active use by another cpu (even if it is
42 * running in userland) for two reasons: First, TLB writebacks will
43 * race against our own modifications and tests. Second, even if we
44 * were to use bus-locked instruction we can still screw up the
45 * target cpu's instruction pipeline due to Intel cpu errata.
47 * For our virtual page tables, the real kernel will handle SMP interactions
48 * with pmaps that may be active on other cpus. Even so, we have to be
49 * careful about bit setting races particularly when we are trying to clean
50 * a page and test the modified bit to avoid races where the modified bit
51 * might get set after our poll but before we clear the field.
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/kernel.h>
57 #include <sys/vmmeter.h>
58 #include <sys/thread2.h>
61 #include <sys/vmspace.h>
65 #include <vm/vm_object.h>
67 #include <machine/cputypes.h>
68 #include <machine/md_var.h>
69 #include <machine/specialreg.h>
70 #include <machine/smp.h>
71 #include <machine/globaldata.h>
72 #include <machine/pmap.h>
73 #include <machine/pmap_inval.h>
77 pmap_inval_cpu(struct pmap *pmap, vm_offset_t va, size_t bytes)
79 if (pmap == &kernel_pmap) {
80 madvise((void *)va, bytes, MADV_INVAL);
82 vmspace_mcontrol(pmap, (void *)va, bytes, MADV_INVAL, 0);
87 * Invalidate a pte in a pmap and synchronize with target cpus
88 * as required. Throw away the modified and access bits. Use
89 * pmap_clean_pte() to do the same thing but also get an interlocked
90 * modified/access status.
92 * Clearing the field first (basically clearing VPTE_V) prevents any
93 * new races from occuring while we invalidate the TLB (i.e. the pmap
94 * on the real cpu), then clear it again to clean out any race that
95 * might have occured before the invalidation completed.
98 pmap_inval_pte(volatile vpte_t *ptep, struct pmap *pmap, vm_offset_t va)
101 pmap_inval_cpu(pmap, va, PAGE_SIZE);
106 * Same as pmap_inval_pte() but only synchronize with the current
107 * cpu. For the moment its the same as the non-quick version.
110 pmap_inval_pte_quick(volatile vpte_t *ptep, struct pmap *pmap, vm_offset_t va)
113 pmap_inval_cpu(pmap, va, PAGE_SIZE);
118 * Invalidating page directory entries requires some additional
119 * sophistication. The cachemask must be cleared so the kernel
120 * resynchronizes its temporary page table mappings cache.
123 pmap_inval_pde(volatile vpte_t *ptep, struct pmap *pmap, vm_offset_t va)
126 pmap_inval_cpu(pmap, va, SEG_SIZE);
128 pmap->pm_cpucachemask = 0;
132 pmap_inval_pde_quick(volatile vpte_t *ptep, struct pmap *pmap, vm_offset_t va)
134 pmap_inval_pde(ptep, pmap, va);
138 * These carefully handle interactions with other cpus and return
139 * the original vpte. Clearing VPTE_RW prevents us from racing the
140 * setting of VPTE_M, allowing us to invalidate the tlb (the real cpu's
141 * pmap) and get good status for VPTE_M.
143 * When messing with page directory entries we have to clear the cpu
144 * mask to force a reload of the kernel's page table mapping cache.
146 * clean: clear VPTE_M and VPTE_RW
147 * setro: clear VPTE_RW
148 * load&clear: clear entire field
151 pmap_clean_pte(volatile vpte_t *ptep, struct pmap *pmap, vm_offset_t va)
157 atomic_clear_long(ptep, VPTE_RW);
158 pmap_inval_cpu(pmap, va, PAGE_SIZE);
160 atomic_clear_long(ptep, VPTE_RW|VPTE_M);
166 pmap_clean_pde(volatile vpte_t *ptep, struct pmap *pmap, vm_offset_t va)
172 atomic_clear_long(ptep, VPTE_RW);
173 pmap_inval_cpu(pmap, va, SEG_SIZE);
175 atomic_clear_long(ptep, VPTE_RW|VPTE_M);
176 pmap->pm_cpucachemask = 0;
182 * This is an odd case and I'm not sure whether it even occurs in normal
183 * operation. Turn off write access to the page, clean out the tlb
184 * (the real cpu's pmap), and deal with any VPTE_M race that may have
185 * occured. VPTE_M is not cleared.
188 pmap_setro_pte(volatile vpte_t *ptep, struct pmap *pmap, vm_offset_t va)
195 atomic_clear_long(ptep, VPTE_RW);
196 pmap_inval_cpu(pmap, va, PAGE_SIZE);
197 pte |= *ptep & VPTE_M;
203 * This is a combination of pmap_inval_pte() and pmap_clean_pte().
204 * Firts prevent races with the 'A' and 'M' bits, then clean out
205 * the tlb (the real cpu's pmap), then incorporate any races that
206 * may have occured in the mean time, and finally zero out the pte.
209 pmap_inval_loadandclear(volatile vpte_t *ptep, struct pmap *pmap,
217 atomic_clear_long(ptep, VPTE_RW);
218 pmap_inval_cpu(pmap, va, PAGE_SIZE);
219 pte |= *ptep & (VPTE_A | VPTE_M);