1 /******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw);
40 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
43 * e1000_init_mac_ops_generic - Initialize MAC function pointers
44 * @hw: pointer to the HW structure
46 * Setups up the function pointers to no-op functions
48 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
50 struct e1000_mac_info *mac = &hw->mac;
51 DEBUGFUNC("e1000_init_mac_ops_generic");
54 mac->ops.init_params = e1000_null_ops_generic;
55 mac->ops.init_hw = e1000_null_ops_generic;
56 mac->ops.reset_hw = e1000_null_ops_generic;
57 mac->ops.setup_physical_interface = e1000_null_ops_generic;
58 mac->ops.get_bus_info = e1000_null_ops_generic;
59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
64 mac->ops.cleanup_led = e1000_null_ops_generic;
65 mac->ops.setup_led = e1000_null_ops_generic;
66 mac->ops.blink_led = e1000_null_ops_generic;
67 mac->ops.led_on = e1000_null_ops_generic;
68 mac->ops.led_off = e1000_null_ops_generic;
70 mac->ops.setup_link = e1000_null_ops_generic;
71 mac->ops.get_link_up_info = e1000_null_link_info;
72 mac->ops.check_for_link = e1000_null_ops_generic;
73 mac->ops.set_obff_timer = e1000_null_set_obff_timer;
75 mac->ops.check_mng_mode = e1000_null_mng_mode;
77 mac->ops.update_mc_addr_list = e1000_null_update_mc;
78 mac->ops.clear_vfta = e1000_null_mac_generic;
79 mac->ops.write_vfta = e1000_null_write_vfta;
80 mac->ops.rar_set = e1000_rar_set_generic;
81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
85 * e1000_null_ops_generic - No-op function, returns 0
86 * @hw: pointer to the HW structure
88 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
90 DEBUGFUNC("e1000_null_ops_generic");
95 * e1000_null_mac_generic - No-op function, return void
96 * @hw: pointer to the HW structure
98 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
100 DEBUGFUNC("e1000_null_mac_generic");
105 * e1000_null_link_info - No-op function, return 0
106 * @hw: pointer to the HW structure
108 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,
109 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)
111 DEBUGFUNC("e1000_null_link_info");
112 return E1000_SUCCESS;
116 * e1000_null_mng_mode - No-op function, return FALSE
117 * @hw: pointer to the HW structure
119 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
121 DEBUGFUNC("e1000_null_mng_mode");
126 * e1000_null_update_mc - No-op function, return void
127 * @hw: pointer to the HW structure
129 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,
130 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
132 DEBUGFUNC("e1000_null_update_mc");
137 * e1000_null_write_vfta - No-op function, return void
138 * @hw: pointer to the HW structure
140 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,
141 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
143 DEBUGFUNC("e1000_null_write_vfta");
148 * e1000_null_rar_set - No-op function, return 0
149 * @hw: pointer to the HW structure
151 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
152 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
154 DEBUGFUNC("e1000_null_rar_set");
155 return E1000_SUCCESS;
159 * e1000_null_set_obff_timer - No-op function, return 0
160 * @hw: pointer to the HW structure
162 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw,
163 u32 E1000_UNUSEDARG a)
165 DEBUGFUNC("e1000_null_set_obff_timer");
166 return E1000_SUCCESS;
170 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
171 * @hw: pointer to the HW structure
173 * Determines and stores the system bus information for a particular
174 * network interface. The following bus information is determined and stored:
175 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
177 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
179 struct e1000_mac_info *mac = &hw->mac;
180 struct e1000_bus_info *bus = &hw->bus;
181 u32 status = E1000_READ_REG(hw, E1000_STATUS);
182 s32 ret_val = E1000_SUCCESS;
184 DEBUGFUNC("e1000_get_bus_info_pci_generic");
187 bus->type = (status & E1000_STATUS_PCIX_MODE)
188 ? e1000_bus_type_pcix
189 : e1000_bus_type_pci;
192 if (bus->type == e1000_bus_type_pci) {
193 bus->speed = (status & E1000_STATUS_PCI66)
195 : e1000_bus_speed_33;
197 switch (status & E1000_STATUS_PCIX_SPEED) {
198 case E1000_STATUS_PCIX_SPEED_66:
199 bus->speed = e1000_bus_speed_66;
201 case E1000_STATUS_PCIX_SPEED_100:
202 bus->speed = e1000_bus_speed_100;
204 case E1000_STATUS_PCIX_SPEED_133:
205 bus->speed = e1000_bus_speed_133;
208 bus->speed = e1000_bus_speed_reserved;
214 bus->width = (status & E1000_STATUS_BUS64)
216 : e1000_bus_width_32;
218 /* Which PCI(-X) function? */
219 mac->ops.set_lan_id(hw);
225 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
226 * @hw: pointer to the HW structure
228 * Determines and stores the system bus information for a particular
229 * network interface. The following bus information is determined and stored:
230 * bus speed, bus width, type (PCIe), and PCIe function.
232 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
234 struct e1000_mac_info *mac = &hw->mac;
235 struct e1000_bus_info *bus = &hw->bus;
237 u16 pcie_link_status;
239 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
241 bus->type = e1000_bus_type_pci_express;
243 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
246 bus->width = e1000_bus_width_unknown;
247 bus->speed = e1000_bus_speed_unknown;
249 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
250 case PCIE_LINK_SPEED_2500:
251 bus->speed = e1000_bus_speed_2500;
253 case PCIE_LINK_SPEED_5000:
254 bus->speed = e1000_bus_speed_5000;
257 bus->speed = e1000_bus_speed_unknown;
261 bus->width = (enum e1000_bus_width)((pcie_link_status &
262 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
265 mac->ops.set_lan_id(hw);
267 return E1000_SUCCESS;
271 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
273 * @hw: pointer to the HW structure
275 * Determines the LAN function id by reading memory-mapped registers
276 * and swaps the port value if requested.
278 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
280 struct e1000_bus_info *bus = &hw->bus;
283 /* The status register reports the correct function number
284 * for the device regardless of function swap state.
286 reg = E1000_READ_REG(hw, E1000_STATUS);
287 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
291 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
292 * @hw: pointer to the HW structure
294 * Determines the LAN function id by reading PCI config space.
296 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
298 struct e1000_bus_info *bus = &hw->bus;
302 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
303 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
304 status = E1000_READ_REG(hw, E1000_STATUS);
305 bus->func = (status & E1000_STATUS_FUNC_MASK)
306 >> E1000_STATUS_FUNC_SHIFT;
313 * e1000_set_lan_id_single_port - Set LAN id for a single port device
314 * @hw: pointer to the HW structure
316 * Sets the LAN function id to zero for a single port device.
318 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
320 struct e1000_bus_info *bus = &hw->bus;
326 * e1000_clear_vfta_generic - Clear VLAN filter table
327 * @hw: pointer to the HW structure
329 * Clears the register array which contains the VLAN filter table by
330 * setting all the values to 0.
332 void e1000_clear_vfta_generic(struct e1000_hw *hw)
336 DEBUGFUNC("e1000_clear_vfta_generic");
338 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
339 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
340 E1000_WRITE_FLUSH(hw);
345 * e1000_write_vfta_generic - Write value to VLAN filter table
346 * @hw: pointer to the HW structure
347 * @offset: register offset in VLAN filter table
348 * @value: register value written to VLAN filter table
350 * Writes value at the given offset in the register array which stores
351 * the VLAN filter table.
353 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
355 DEBUGFUNC("e1000_write_vfta_generic");
357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
358 E1000_WRITE_FLUSH(hw);
362 * e1000_init_rx_addrs_generic - Initialize receive address's
363 * @hw: pointer to the HW structure
364 * @rar_count: receive address registers
366 * Setup the receive address registers by setting the base receive address
367 * register to the devices MAC address and clearing all the other receive
368 * address registers to 0.
370 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
373 u8 mac_addr[ETH_ADDR_LEN] = {0};
375 DEBUGFUNC("e1000_init_rx_addrs_generic");
377 /* Setup the receive address */
378 DEBUGOUT("Programming MAC Address into RAR[0]\n");
380 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
382 /* Zero out the other (rar_entry_count - 1) receive addresses */
383 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
384 for (i = 1; i < rar_count; i++)
385 hw->mac.ops.rar_set(hw, mac_addr, i);
389 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
390 * @hw: pointer to the HW structure
392 * Checks the nvm for an alternate MAC address. An alternate MAC address
393 * can be setup by pre-boot software and must be treated like a permanent
394 * address and must override the actual permanent MAC address. If an
395 * alternate MAC address is found it is programmed into RAR0, replacing
396 * the permanent address that was installed into RAR0 by the Si on reset.
397 * This function will return SUCCESS unless it encounters an error while
398 * reading the EEPROM.
400 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
404 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
405 u8 alt_mac_addr[ETH_ADDR_LEN];
407 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
409 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
413 /* not supported on older hardware or 82573 */
414 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
415 return E1000_SUCCESS;
417 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
418 &nvm_alt_mac_addr_offset);
420 DEBUGOUT("NVM Read Error\n");
424 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
425 (nvm_alt_mac_addr_offset == 0x0000))
426 /* There is no Alternate MAC Address */
427 return E1000_SUCCESS;
429 if (hw->bus.func == E1000_FUNC_1)
430 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
431 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
432 offset = nvm_alt_mac_addr_offset + (i >> 1);
433 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
435 DEBUGOUT("NVM Read Error\n");
439 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
440 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
443 /* if multicast bit is set, the alternate address will not be used */
444 if (alt_mac_addr[0] & 0x01) {
445 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
446 return E1000_SUCCESS;
449 /* We have a valid alternate MAC address, and we want to treat it the
450 * same as the normal permanent MAC address stored by the HW into the
451 * RAR. Do this by mapping this address into RAR0.
453 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
455 return E1000_SUCCESS;
459 * e1000_rar_set_generic - Set receive address register
460 * @hw: pointer to the HW structure
461 * @addr: pointer to the receive address
462 * @index: receive address array register
464 * Sets the receive address array register at index to the address passed
467 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
469 u32 rar_low, rar_high;
471 DEBUGFUNC("e1000_rar_set_generic");
473 /* HW expects these in little endian so we reverse the byte order
474 * from network order (big endian) to little endian
476 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
477 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
479 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
481 /* If MAC address zero, no need to set the AV bit */
482 if (rar_low || rar_high)
483 rar_high |= E1000_RAH_AV;
485 /* Some bridges will combine consecutive 32-bit writes into
486 * a single burst write, which will malfunction on some parts.
487 * The flushes avoid this.
489 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
490 E1000_WRITE_FLUSH(hw);
491 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
492 E1000_WRITE_FLUSH(hw);
494 return E1000_SUCCESS;
498 * e1000_hash_mc_addr_generic - Generate a multicast hash value
499 * @hw: pointer to the HW structure
500 * @mc_addr: pointer to a multicast address
502 * Generates a multicast address hash value which is used to determine
503 * the multicast filter table array address and new table value.
505 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
507 u32 hash_value, hash_mask;
510 DEBUGFUNC("e1000_hash_mc_addr_generic");
512 /* Register count multiplied by bits per register */
513 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
515 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
516 * where 0xFF would still fall within the hash mask.
518 while (hash_mask >> bit_shift != 0xFF)
521 /* The portion of the address that is used for the hash table
522 * is determined by the mc_filter_type setting.
523 * The algorithm is such that there is a total of 8 bits of shifting.
524 * The bit_shift for a mc_filter_type of 0 represents the number of
525 * left-shifts where the MSB of mc_addr[5] would still fall within
526 * the hash_mask. Case 0 does this exactly. Since there are a total
527 * of 8 bits of shifting, then mc_addr[4] will shift right the
528 * remaining number of bits. Thus 8 - bit_shift. The rest of the
529 * cases are a variation of this algorithm...essentially raising the
530 * number of bits to shift mc_addr[5] left, while still keeping the
531 * 8-bit shifting total.
533 * For example, given the following Destination MAC Address and an
534 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
535 * we can see that the bit_shift for case 0 is 4. These are the hash
536 * values resulting from each mc_filter_type...
537 * [0] [1] [2] [3] [4] [5]
541 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
542 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
543 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
544 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
546 switch (hw->mac.mc_filter_type) {
561 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
562 (((u16) mc_addr[5]) << bit_shift)));
568 * e1000_update_mc_addr_list_generic - Update Multicast addresses
569 * @hw: pointer to the HW structure
570 * @mc_addr_list: array of multicast addresses to program
571 * @mc_addr_count: number of multicast addresses to program
573 * Updates entire Multicast Table Array.
574 * The caller must have a packed mc_addr_list of multicast addresses.
576 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
577 u8 *mc_addr_list, u32 mc_addr_count)
579 u32 hash_value, hash_bit, hash_reg;
582 DEBUGFUNC("e1000_update_mc_addr_list_generic");
584 /* clear mta_shadow */
585 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
587 /* update mta_shadow from mc_addr_list */
588 for (i = 0; (u32) i < mc_addr_count; i++) {
589 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
591 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
592 hash_bit = hash_value & 0x1F;
594 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
595 mc_addr_list += (ETH_ADDR_LEN);
598 /* replace the entire MTA table */
599 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
600 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
601 E1000_WRITE_FLUSH(hw);
605 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
606 * @hw: pointer to the HW structure
608 * In certain situations, a system BIOS may report that the PCIx maximum
609 * memory read byte count (MMRBC) value is higher than than the actual
610 * value. We check the PCIx command register with the current PCIx status
613 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
617 u16 pcix_stat_hi_word;
620 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
622 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
623 if (hw->bus.type != e1000_bus_type_pcix)
626 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
627 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
628 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
629 PCIX_COMMAND_MMRBC_SHIFT;
630 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
631 PCIX_STATUS_HI_MMRBC_SHIFT;
632 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
633 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
634 if (cmd_mmrbc > stat_mmrbc) {
635 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
636 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
637 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
642 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
643 * @hw: pointer to the HW structure
645 * Clears the base hardware counters by reading the counter registers.
647 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
649 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
651 E1000_READ_REG(hw, E1000_CRCERRS);
652 E1000_READ_REG(hw, E1000_SYMERRS);
653 E1000_READ_REG(hw, E1000_MPC);
654 E1000_READ_REG(hw, E1000_SCC);
655 E1000_READ_REG(hw, E1000_ECOL);
656 E1000_READ_REG(hw, E1000_MCC);
657 E1000_READ_REG(hw, E1000_LATECOL);
658 E1000_READ_REG(hw, E1000_COLC);
659 E1000_READ_REG(hw, E1000_DC);
660 E1000_READ_REG(hw, E1000_SEC);
661 E1000_READ_REG(hw, E1000_RLEC);
662 E1000_READ_REG(hw, E1000_XONRXC);
663 E1000_READ_REG(hw, E1000_XONTXC);
664 E1000_READ_REG(hw, E1000_XOFFRXC);
665 E1000_READ_REG(hw, E1000_XOFFTXC);
666 E1000_READ_REG(hw, E1000_FCRUC);
667 E1000_READ_REG(hw, E1000_GPRC);
668 E1000_READ_REG(hw, E1000_BPRC);
669 E1000_READ_REG(hw, E1000_MPRC);
670 E1000_READ_REG(hw, E1000_GPTC);
671 E1000_READ_REG(hw, E1000_GORCL);
672 E1000_READ_REG(hw, E1000_GORCH);
673 E1000_READ_REG(hw, E1000_GOTCL);
674 E1000_READ_REG(hw, E1000_GOTCH);
675 E1000_READ_REG(hw, E1000_RNBC);
676 E1000_READ_REG(hw, E1000_RUC);
677 E1000_READ_REG(hw, E1000_RFC);
678 E1000_READ_REG(hw, E1000_ROC);
679 E1000_READ_REG(hw, E1000_RJC);
680 E1000_READ_REG(hw, E1000_TORL);
681 E1000_READ_REG(hw, E1000_TORH);
682 E1000_READ_REG(hw, E1000_TOTL);
683 E1000_READ_REG(hw, E1000_TOTH);
684 E1000_READ_REG(hw, E1000_TPR);
685 E1000_READ_REG(hw, E1000_TPT);
686 E1000_READ_REG(hw, E1000_MPTC);
687 E1000_READ_REG(hw, E1000_BPTC);
691 * e1000_check_for_copper_link_generic - Check for link (Copper)
692 * @hw: pointer to the HW structure
694 * Checks to see of the link status of the hardware has changed. If a
695 * change in link status has been detected, then we read the PHY registers
696 * to get the current speed/duplex if link exists.
698 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
700 struct e1000_mac_info *mac = &hw->mac;
704 DEBUGFUNC("e1000_check_for_copper_link");
706 /* We only want to go out to the PHY registers to see if Auto-Neg
707 * has completed and/or if our link status has changed. The
708 * get_link_status flag is set upon receiving a Link Status
709 * Change or Rx Sequence Error interrupt.
711 if (!mac->get_link_status)
712 return E1000_SUCCESS;
714 /* First we want to see if the MII Status Register reports
715 * link. If so, then we want to get the current speed/duplex
718 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
723 return E1000_SUCCESS; /* No link detected */
725 mac->get_link_status = FALSE;
727 /* Check if there was DownShift, must be checked
728 * immediately after link-up
730 e1000_check_downshift_generic(hw);
732 /* If we are forcing speed/duplex, then we simply return since
733 * we have already determined whether we have link or not.
736 return -E1000_ERR_CONFIG;
738 /* Auto-Neg is enabled. Auto Speed Detection takes care
739 * of MAC speed/duplex configuration. So we only need to
740 * configure Collision Distance in the MAC.
742 mac->ops.config_collision_dist(hw);
744 /* Configure Flow Control now that Auto-Neg has completed.
745 * First, we need to restore the desired flow control
746 * settings because we may have had to re-autoneg with a
747 * different link partner.
749 ret_val = e1000_config_fc_after_link_up_generic(hw);
751 DEBUGOUT("Error configuring flow control\n");
757 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
758 * @hw: pointer to the HW structure
760 * Checks for link up on the hardware. If link is not up and we have
761 * a signal, then we need to force link up.
763 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
765 struct e1000_mac_info *mac = &hw->mac;
771 DEBUGFUNC("e1000_check_for_fiber_link_generic");
773 ctrl = E1000_READ_REG(hw, E1000_CTRL);
774 status = E1000_READ_REG(hw, E1000_STATUS);
775 rxcw = E1000_READ_REG(hw, E1000_RXCW);
777 /* If we don't have link (auto-negotiation failed or link partner
778 * cannot auto-negotiate), the cable is plugged in (we have signal),
779 * and our link partner is not trying to auto-negotiate with us (we
780 * are receiving idles or data), we need to force link up. We also
781 * need to give auto-negotiation time to complete, in case the cable
782 * was just plugged in. The autoneg_failed flag does this.
784 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
785 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
786 !(rxcw & E1000_RXCW_C)) {
787 if (!mac->autoneg_failed) {
788 mac->autoneg_failed = TRUE;
789 return E1000_SUCCESS;
791 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
793 /* Disable auto-negotiation in the TXCW register */
794 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
796 /* Force link-up and also force full-duplex. */
797 ctrl = E1000_READ_REG(hw, E1000_CTRL);
798 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
799 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
801 /* Configure Flow Control after forcing link up. */
802 ret_val = e1000_config_fc_after_link_up_generic(hw);
804 DEBUGOUT("Error configuring flow control\n");
807 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
808 /* If we are forcing link and we are receiving /C/ ordered
809 * sets, re-enable auto-negotiation in the TXCW register
810 * and disable forced link in the Device Control register
811 * in an attempt to auto-negotiate with our link partner.
813 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
814 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
815 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
817 mac->serdes_has_link = TRUE;
820 return E1000_SUCCESS;
824 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
825 * @hw: pointer to the HW structure
827 * Checks for link up on the hardware. If link is not up and we have
828 * a signal, then we need to force link up.
830 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
832 struct e1000_mac_info *mac = &hw->mac;
838 DEBUGFUNC("e1000_check_for_serdes_link_generic");
840 ctrl = E1000_READ_REG(hw, E1000_CTRL);
841 status = E1000_READ_REG(hw, E1000_STATUS);
842 rxcw = E1000_READ_REG(hw, E1000_RXCW);
844 /* If we don't have link (auto-negotiation failed or link partner
845 * cannot auto-negotiate), and our link partner is not trying to
846 * auto-negotiate with us (we are receiving idles or data),
847 * we need to force link up. We also need to give auto-negotiation
850 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
851 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
852 if (!mac->autoneg_failed) {
853 mac->autoneg_failed = TRUE;
854 return E1000_SUCCESS;
856 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
858 /* Disable auto-negotiation in the TXCW register */
859 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
861 /* Force link-up and also force full-duplex. */
862 ctrl = E1000_READ_REG(hw, E1000_CTRL);
863 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
864 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
866 /* Configure Flow Control after forcing link up. */
867 ret_val = e1000_config_fc_after_link_up_generic(hw);
869 DEBUGOUT("Error configuring flow control\n");
872 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
873 /* If we are forcing link and we are receiving /C/ ordered
874 * sets, re-enable auto-negotiation in the TXCW register
875 * and disable forced link in the Device Control register
876 * in an attempt to auto-negotiate with our link partner.
878 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
879 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
880 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
882 mac->serdes_has_link = TRUE;
883 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
884 /* If we force link for non-auto-negotiation switch, check
885 * link status based on MAC synchronization for internal
888 /* SYNCH bit and IV bit are sticky. */
890 rxcw = E1000_READ_REG(hw, E1000_RXCW);
891 if (rxcw & E1000_RXCW_SYNCH) {
892 if (!(rxcw & E1000_RXCW_IV)) {
893 mac->serdes_has_link = TRUE;
894 DEBUGOUT("SERDES: Link up - forced.\n");
897 mac->serdes_has_link = FALSE;
898 DEBUGOUT("SERDES: Link down - force failed.\n");
902 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
903 status = E1000_READ_REG(hw, E1000_STATUS);
904 if (status & E1000_STATUS_LU) {
905 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
907 rxcw = E1000_READ_REG(hw, E1000_RXCW);
908 if (rxcw & E1000_RXCW_SYNCH) {
909 if (!(rxcw & E1000_RXCW_IV)) {
910 mac->serdes_has_link = TRUE;
911 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
913 mac->serdes_has_link = FALSE;
914 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
917 mac->serdes_has_link = FALSE;
918 DEBUGOUT("SERDES: Link down - no sync.\n");
921 mac->serdes_has_link = FALSE;
922 DEBUGOUT("SERDES: Link down - autoneg failed\n");
926 return E1000_SUCCESS;
930 * e1000_set_default_fc_generic - Set flow control default values
931 * @hw: pointer to the HW structure
933 * Read the EEPROM for the default values for flow control and store the
936 #ifdef NO_82542_SUPPORT
937 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
939 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
945 DEBUGFUNC("e1000_set_default_fc_generic");
947 /* Read and store word 0x0F of the EEPROM. This word contains bits
948 * that determine the hardware's default PAUSE (flow control) mode,
949 * a bit that determines whether the HW defaults to enabling or
950 * disabling auto-negotiation, and the direction of the
951 * SW defined pins. If there is no SW over-ride of the flow
952 * control setting, then the variable hw->fc will
953 * be initialized based on a value in the EEPROM.
955 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
958 DEBUGOUT("NVM Read Error\n");
962 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
963 hw->fc.requested_mode = e1000_fc_none;
964 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
966 hw->fc.requested_mode = e1000_fc_tx_pause;
968 hw->fc.requested_mode = e1000_fc_full;
970 return E1000_SUCCESS;
974 * e1000_setup_link_generic - Setup flow control and link settings
975 * @hw: pointer to the HW structure
977 * Determines which flow control settings to use, then configures flow
978 * control. Calls the appropriate media-specific link configuration
979 * function. Assuming the adapter has a valid link partner, a valid link
980 * should be established. Assumes the hardware has previously been reset
981 * and the transmitter and receiver are not enabled.
983 s32 e1000_setup_link_generic(struct e1000_hw *hw)
987 DEBUGFUNC("e1000_setup_link_generic");
989 /* In the case of the phy reset being blocked, we already have a link.
990 * We do not need to set it up again.
992 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
993 return E1000_SUCCESS;
995 /* If requested flow control is set to default, set flow control
996 * based on the EEPROM flow control settings.
998 if (hw->fc.requested_mode == e1000_fc_default) {
999 ret_val = e1000_set_default_fc_generic(hw);
1004 /* Save off the requested flow control mode for use later. Depending
1005 * on the link partner's capabilities, we may or may not use this mode.
1007 hw->fc.current_mode = hw->fc.requested_mode;
1009 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1010 hw->fc.current_mode);
1012 /* Call the necessary media_type subroutine to configure the link. */
1013 ret_val = hw->mac.ops.setup_physical_interface(hw);
1017 /* Initialize the flow control address, type, and PAUSE timer
1018 * registers to their default values. This is done even if flow
1019 * control is disabled, because it does not hurt anything to
1020 * initialize these registers.
1022 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1023 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1024 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1025 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1027 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1029 return e1000_set_fc_watermarks_generic(hw);
1033 * e1000_commit_fc_settings_generic - Configure flow control
1034 * @hw: pointer to the HW structure
1036 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1037 * base on the flow control settings in e1000_mac_info.
1039 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1041 struct e1000_mac_info *mac = &hw->mac;
1044 DEBUGFUNC("e1000_commit_fc_settings_generic");
1046 /* Check for a software override of the flow control settings, and
1047 * setup the device accordingly. If auto-negotiation is enabled, then
1048 * software will have to set the "PAUSE" bits to the correct value in
1049 * the Transmit Config Word Register (TXCW) and re-start auto-
1050 * negotiation. However, if auto-negotiation is disabled, then
1051 * software will have to manually configure the two flow control enable
1052 * bits in the CTRL register.
1054 * The possible values of the "fc" parameter are:
1055 * 0: Flow control is completely disabled
1056 * 1: Rx flow control is enabled (we can receive pause frames,
1057 * but not send pause frames).
1058 * 2: Tx flow control is enabled (we can send pause frames but we
1059 * do not support receiving pause frames).
1060 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1062 switch (hw->fc.current_mode) {
1064 /* Flow control completely disabled by a software over-ride. */
1065 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1067 case e1000_fc_rx_pause:
1068 /* Rx Flow control is enabled and Tx Flow control is disabled
1069 * by a software over-ride. Since there really isn't a way to
1070 * advertise that we are capable of Rx Pause ONLY, we will
1071 * advertise that we support both symmetric and asymmetric Rx
1072 * PAUSE. Later, we will disable the adapter's ability to send
1075 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1077 case e1000_fc_tx_pause:
1078 /* Tx Flow control is enabled, and Rx Flow control is disabled,
1079 * by a software over-ride.
1081 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1084 /* Flow control (both Rx and Tx) is enabled by a software
1087 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1090 DEBUGOUT("Flow control param set incorrectly\n");
1091 return -E1000_ERR_CONFIG;
1095 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1098 return E1000_SUCCESS;
1102 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1103 * @hw: pointer to the HW structure
1105 * Polls for link up by reading the status register, if link fails to come
1106 * up with auto-negotiation, then the link is forced if a signal is detected.
1108 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1110 struct e1000_mac_info *mac = &hw->mac;
1114 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1116 /* If we have a signal (the cable is plugged in, or assumed TRUE for
1117 * serdes media) then poll for a "Link-Up" indication in the Device
1118 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1119 * seconds (Auto-negotiation should complete in less than 500
1120 * milliseconds even if the other end is doing it in SW).
1122 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1124 status = E1000_READ_REG(hw, E1000_STATUS);
1125 if (status & E1000_STATUS_LU)
1128 if (i == FIBER_LINK_UP_LIMIT) {
1129 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1130 mac->autoneg_failed = TRUE;
1131 /* AutoNeg failed to achieve a link, so we'll call
1132 * mac->check_for_link. This routine will force the
1133 * link up if we detect a signal. This will allow us to
1134 * communicate with non-autonegotiating link partners.
1136 ret_val = mac->ops.check_for_link(hw);
1138 DEBUGOUT("Error while checking for link\n");
1141 mac->autoneg_failed = FALSE;
1143 mac->autoneg_failed = FALSE;
1144 DEBUGOUT("Valid Link Found\n");
1147 return E1000_SUCCESS;
1151 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1152 * @hw: pointer to the HW structure
1154 * Configures collision distance and flow control for fiber and serdes
1155 * links. Upon successful setup, poll for link.
1157 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1162 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1164 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1166 /* Take the link out of reset */
1167 ctrl &= ~E1000_CTRL_LRST;
1169 hw->mac.ops.config_collision_dist(hw);
1171 ret_val = e1000_commit_fc_settings_generic(hw);
1175 /* Since auto-negotiation is enabled, take the link out of reset (the
1176 * link will be in reset, because we previously reset the chip). This
1177 * will restart auto-negotiation. If auto-negotiation is successful
1178 * then the link-up status bit will be set and the flow control enable
1179 * bits (RFCE and TFCE) will be set according to their negotiated value.
1181 DEBUGOUT("Auto-negotiation enabled\n");
1183 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1184 E1000_WRITE_FLUSH(hw);
1187 /* For these adapters, the SW definable pin 1 is set when the optics
1188 * detect a signal. If we have a signal, then poll for a "Link-Up"
1191 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1192 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1193 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1195 DEBUGOUT("No signal detected\n");
1202 * e1000_config_collision_dist_generic - Configure collision distance
1203 * @hw: pointer to the HW structure
1205 * Configures the collision distance to the default value and is used
1206 * during link setup.
1208 static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1212 DEBUGFUNC("e1000_config_collision_dist_generic");
1214 tctl = E1000_READ_REG(hw, E1000_TCTL);
1216 tctl &= ~E1000_TCTL_COLD;
1217 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1219 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1220 E1000_WRITE_FLUSH(hw);
1224 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1225 * @hw: pointer to the HW structure
1227 * Sets the flow control high/low threshold (watermark) registers. If
1228 * flow control XON frame transmission is enabled, then set XON frame
1229 * transmission as well.
1231 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1233 u32 fcrtl = 0, fcrth = 0;
1235 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1237 /* Set the flow control receive threshold registers. Normally,
1238 * these registers will be set to a default threshold that may be
1239 * adjusted later by the driver's runtime code. However, if the
1240 * ability to transmit pause frames is not enabled, then these
1241 * registers will be set to 0.
1243 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1244 /* We need to set up the Receive Threshold high and low water
1245 * marks as well as (optionally) enabling the transmission of
1248 fcrtl = hw->fc.low_water;
1249 if (hw->fc.send_xon)
1250 fcrtl |= E1000_FCRTL_XONE;
1252 fcrth = hw->fc.high_water;
1254 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1255 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1257 return E1000_SUCCESS;
1261 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1262 * @hw: pointer to the HW structure
1264 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1265 * device control register to reflect the adapter settings. TFCE and RFCE
1266 * need to be explicitly set by software when a copper PHY is used because
1267 * autonegotiation is managed by the PHY rather than the MAC. Software must
1268 * also configure these bits when link is forced on a fiber connection.
1270 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1274 DEBUGFUNC("e1000_force_mac_fc_generic");
1276 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1278 /* Because we didn't get link via the internal auto-negotiation
1279 * mechanism (we either forced link or we got link via PHY
1280 * auto-neg), we have to manually enable/disable transmit an
1281 * receive flow control.
1283 * The "Case" statement below enables/disable flow control
1284 * according to the "hw->fc.current_mode" parameter.
1286 * The possible values of the "fc" parameter are:
1287 * 0: Flow control is completely disabled
1288 * 1: Rx flow control is enabled (we can receive pause
1289 * frames but not send pause frames).
1290 * 2: Tx flow control is enabled (we can send pause frames
1291 * frames but we do not receive pause frames).
1292 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1293 * other: No other values should be possible at this point.
1295 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1297 switch (hw->fc.current_mode) {
1299 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1301 case e1000_fc_rx_pause:
1302 ctrl &= (~E1000_CTRL_TFCE);
1303 ctrl |= E1000_CTRL_RFCE;
1305 case e1000_fc_tx_pause:
1306 ctrl &= (~E1000_CTRL_RFCE);
1307 ctrl |= E1000_CTRL_TFCE;
1310 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1313 DEBUGOUT("Flow control param set incorrectly\n");
1314 return -E1000_ERR_CONFIG;
1317 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1319 return E1000_SUCCESS;
1323 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1324 * @hw: pointer to the HW structure
1326 * Checks the status of auto-negotiation after link up to ensure that the
1327 * speed and duplex were not forced. If the link needed to be forced, then
1328 * flow control needs to be forced also. If auto-negotiation is enabled
1329 * and did not fail, then we configure flow control based on our link
1332 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1334 struct e1000_mac_info *mac = &hw->mac;
1335 s32 ret_val = E1000_SUCCESS;
1336 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1337 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1340 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1342 /* Check for the case where we have fiber media and auto-neg failed
1343 * so we had to force link. In this case, we need to force the
1344 * configuration of the MAC to match the "fc" parameter.
1346 if (mac->autoneg_failed) {
1347 if (hw->phy.media_type == e1000_media_type_fiber ||
1348 hw->phy.media_type == e1000_media_type_internal_serdes)
1349 ret_val = e1000_force_mac_fc_generic(hw);
1351 if (hw->phy.media_type == e1000_media_type_copper)
1352 ret_val = e1000_force_mac_fc_generic(hw);
1356 DEBUGOUT("Error forcing flow control settings\n");
1360 /* Check for the case where we have copper media and auto-neg is
1361 * enabled. In this case, we need to check and see if Auto-Neg
1362 * has completed, and if so, how the PHY and link partner has
1363 * flow control configured.
1365 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1366 /* Read the MII Status Register and check to see if AutoNeg
1367 * has completed. We read this twice because this reg has
1368 * some "sticky" (latched) bits.
1370 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1373 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1377 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1378 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1382 /* The AutoNeg process has completed, so we now need to
1383 * read both the Auto Negotiation Advertisement
1384 * Register (Address 4) and the Auto_Negotiation Base
1385 * Page Ability Register (Address 5) to determine how
1386 * flow control was negotiated.
1388 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1392 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1393 &mii_nway_lp_ability_reg);
1397 /* Two bits in the Auto Negotiation Advertisement Register
1398 * (Address 4) and two bits in the Auto Negotiation Base
1399 * Page Ability Register (Address 5) determine flow control
1400 * for both the PHY and the link partner. The following
1401 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1402 * 1999, describes these PAUSE resolution bits and how flow
1403 * control is determined based upon these settings.
1404 * NOTE: DC = Don't Care
1406 * LOCAL DEVICE | LINK PARTNER
1407 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1408 *-------|---------|-------|---------|--------------------
1409 * 0 | 0 | DC | DC | e1000_fc_none
1410 * 0 | 1 | 0 | DC | e1000_fc_none
1411 * 0 | 1 | 1 | 0 | e1000_fc_none
1412 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1413 * 1 | 0 | 0 | DC | e1000_fc_none
1414 * 1 | DC | 1 | DC | e1000_fc_full
1415 * 1 | 1 | 0 | 0 | e1000_fc_none
1416 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1418 * Are both PAUSE bits set to 1? If so, this implies
1419 * Symmetric Flow Control is enabled at both ends. The
1420 * ASM_DIR bits are irrelevant per the spec.
1422 * For Symmetric Flow Control:
1424 * LOCAL DEVICE | LINK PARTNER
1425 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1426 *-------|---------|-------|---------|--------------------
1427 * 1 | DC | 1 | DC | E1000_fc_full
1430 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1431 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1432 /* Now we need to check if the user selected Rx ONLY
1433 * of pause frames. In this case, we had to advertise
1434 * FULL flow control because we could not advertise Rx
1435 * ONLY. Hence, we must now check to see if we need to
1436 * turn OFF the TRANSMISSION of PAUSE frames.
1438 if (hw->fc.requested_mode == e1000_fc_full) {
1439 hw->fc.current_mode = e1000_fc_full;
1440 DEBUGOUT("Flow Control = FULL.\n");
1442 hw->fc.current_mode = e1000_fc_rx_pause;
1443 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1446 /* For receiving PAUSE frames ONLY.
1448 * LOCAL DEVICE | LINK PARTNER
1449 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1450 *-------|---------|-------|---------|--------------------
1451 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1453 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1454 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1455 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1456 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1457 hw->fc.current_mode = e1000_fc_tx_pause;
1458 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1460 /* For transmitting PAUSE frames ONLY.
1462 * LOCAL DEVICE | LINK PARTNER
1463 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1464 *-------|---------|-------|---------|--------------------
1465 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1467 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1468 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1469 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1470 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1471 hw->fc.current_mode = e1000_fc_rx_pause;
1472 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1474 /* Per the IEEE spec, at this point flow control
1475 * should be disabled.
1477 hw->fc.current_mode = e1000_fc_none;
1478 DEBUGOUT("Flow Control = NONE.\n");
1481 /* Now we need to do one last check... If we auto-
1482 * negotiated to HALF DUPLEX, flow control should not be
1483 * enabled per IEEE 802.3 spec.
1485 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1487 DEBUGOUT("Error getting link speed and duplex\n");
1491 if (duplex == HALF_DUPLEX)
1492 hw->fc.current_mode = e1000_fc_none;
1494 /* Now we call a subroutine to actually force the MAC
1495 * controller to use the correct flow control settings.
1497 ret_val = e1000_force_mac_fc_generic(hw);
1499 DEBUGOUT("Error forcing flow control settings\n");
1504 /* Check for the case where we have SerDes media and auto-neg is
1505 * enabled. In this case, we need to check and see if Auto-Neg
1506 * has completed, and if so, how the PHY and link partner has
1507 * flow control configured.
1509 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1511 /* Read the PCS_LSTS and check to see if AutoNeg
1514 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1516 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1517 DEBUGOUT("PCS Auto Neg has not completed.\n");
1521 /* The AutoNeg process has completed, so we now need to
1522 * read both the Auto Negotiation Advertisement
1523 * Register (PCS_ANADV) and the Auto_Negotiation Base
1524 * Page Ability Register (PCS_LPAB) to determine how
1525 * flow control was negotiated.
1527 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1528 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1530 /* Two bits in the Auto Negotiation Advertisement Register
1531 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1532 * Page Ability Register (PCS_LPAB) determine flow control
1533 * for both the PHY and the link partner. The following
1534 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1535 * 1999, describes these PAUSE resolution bits and how flow
1536 * control is determined based upon these settings.
1537 * NOTE: DC = Don't Care
1539 * LOCAL DEVICE | LINK PARTNER
1540 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1541 *-------|---------|-------|---------|--------------------
1542 * 0 | 0 | DC | DC | e1000_fc_none
1543 * 0 | 1 | 0 | DC | e1000_fc_none
1544 * 0 | 1 | 1 | 0 | e1000_fc_none
1545 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1546 * 1 | 0 | 0 | DC | e1000_fc_none
1547 * 1 | DC | 1 | DC | e1000_fc_full
1548 * 1 | 1 | 0 | 0 | e1000_fc_none
1549 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1551 * Are both PAUSE bits set to 1? If so, this implies
1552 * Symmetric Flow Control is enabled at both ends. The
1553 * ASM_DIR bits are irrelevant per the spec.
1555 * For Symmetric Flow Control:
1557 * LOCAL DEVICE | LINK PARTNER
1558 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1559 *-------|---------|-------|---------|--------------------
1560 * 1 | DC | 1 | DC | e1000_fc_full
1563 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1564 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1565 /* Now we need to check if the user selected Rx ONLY
1566 * of pause frames. In this case, we had to advertise
1567 * FULL flow control because we could not advertise Rx
1568 * ONLY. Hence, we must now check to see if we need to
1569 * turn OFF the TRANSMISSION of PAUSE frames.
1571 if (hw->fc.requested_mode == e1000_fc_full) {
1572 hw->fc.current_mode = e1000_fc_full;
1573 DEBUGOUT("Flow Control = FULL.\n");
1575 hw->fc.current_mode = e1000_fc_rx_pause;
1576 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1579 /* For receiving PAUSE frames ONLY.
1581 * LOCAL DEVICE | LINK PARTNER
1582 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1583 *-------|---------|-------|---------|--------------------
1584 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1586 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1587 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1588 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1589 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1590 hw->fc.current_mode = e1000_fc_tx_pause;
1591 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1593 /* For transmitting PAUSE frames ONLY.
1595 * LOCAL DEVICE | LINK PARTNER
1596 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1597 *-------|---------|-------|---------|--------------------
1598 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1600 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1601 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1602 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1603 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1604 hw->fc.current_mode = e1000_fc_rx_pause;
1605 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1607 /* Per the IEEE spec, at this point flow control
1608 * should be disabled.
1610 hw->fc.current_mode = e1000_fc_none;
1611 DEBUGOUT("Flow Control = NONE.\n");
1614 /* Now we call a subroutine to actually force the MAC
1615 * controller to use the correct flow control settings.
1617 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1618 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1619 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1621 ret_val = e1000_force_mac_fc_generic(hw);
1623 DEBUGOUT("Error forcing flow control settings\n");
1628 return E1000_SUCCESS;
1632 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1633 * @hw: pointer to the HW structure
1634 * @speed: stores the current speed
1635 * @duplex: stores the current duplex
1637 * Read the status register for the current speed/duplex and store the current
1638 * speed and duplex for copper connections.
1640 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1645 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1647 status = E1000_READ_REG(hw, E1000_STATUS);
1648 if (status & E1000_STATUS_SPEED_1000) {
1649 *speed = SPEED_1000;
1650 DEBUGOUT("1000 Mbs, ");
1651 } else if (status & E1000_STATUS_SPEED_100) {
1653 DEBUGOUT("100 Mbs, ");
1656 DEBUGOUT("10 Mbs, ");
1659 if (status & E1000_STATUS_FD) {
1660 *duplex = FULL_DUPLEX;
1661 DEBUGOUT("Full Duplex\n");
1663 *duplex = HALF_DUPLEX;
1664 DEBUGOUT("Half Duplex\n");
1667 return E1000_SUCCESS;
1671 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1672 * @hw: pointer to the HW structure
1673 * @speed: stores the current speed
1674 * @duplex: stores the current duplex
1676 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1677 * for fiber/serdes links.
1679 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,
1680 u16 *speed, u16 *duplex)
1682 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1684 *speed = SPEED_1000;
1685 *duplex = FULL_DUPLEX;
1687 return E1000_SUCCESS;
1691 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1692 * @hw: pointer to the HW structure
1694 * Acquire the HW semaphore to access the PHY or NVM
1696 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1699 s32 timeout = hw->nvm.word_size + 1;
1702 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1704 /* Get the SW semaphore */
1705 while (i < timeout) {
1706 swsm = E1000_READ_REG(hw, E1000_SWSM);
1707 if (!(swsm & E1000_SWSM_SMBI))
1715 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1716 return -E1000_ERR_NVM;
1719 /* Get the FW semaphore. */
1720 for (i = 0; i < timeout; i++) {
1721 swsm = E1000_READ_REG(hw, E1000_SWSM);
1722 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1724 /* Semaphore acquired if bit latched */
1725 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1732 /* Release semaphores */
1733 e1000_put_hw_semaphore_generic(hw);
1734 DEBUGOUT("Driver can't access the NVM\n");
1735 return -E1000_ERR_NVM;
1738 return E1000_SUCCESS;
1742 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1743 * @hw: pointer to the HW structure
1745 * Release hardware semaphore used to access the PHY or NVM
1747 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1751 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1753 swsm = E1000_READ_REG(hw, E1000_SWSM);
1755 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1757 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1761 * e1000_get_auto_rd_done_generic - Check for auto read completion
1762 * @hw: pointer to the HW structure
1764 * Check EEPROM for Auto Read done bit.
1766 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1770 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1772 while (i < AUTO_READ_DONE_TIMEOUT) {
1773 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1779 if (i == AUTO_READ_DONE_TIMEOUT) {
1780 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1781 return -E1000_ERR_RESET;
1784 return E1000_SUCCESS;
1788 * e1000_valid_led_default_generic - Verify a valid default LED config
1789 * @hw: pointer to the HW structure
1790 * @data: pointer to the NVM (EEPROM)
1792 * Read the EEPROM for the current default LED configuration. If the
1793 * LED configuration is not valid, set to a valid LED configuration.
1795 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1799 DEBUGFUNC("e1000_valid_led_default_generic");
1801 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1803 DEBUGOUT("NVM Read Error\n");
1807 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1808 *data = ID_LED_DEFAULT;
1810 return E1000_SUCCESS;
1814 * e1000_id_led_init_generic -
1815 * @hw: pointer to the HW structure
1818 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1820 struct e1000_mac_info *mac = &hw->mac;
1822 const u32 ledctl_mask = 0x000000FF;
1823 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1824 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1826 const u16 led_mask = 0x0F;
1828 DEBUGFUNC("e1000_id_led_init_generic");
1830 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1834 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1835 mac->ledctl_mode1 = mac->ledctl_default;
1836 mac->ledctl_mode2 = mac->ledctl_default;
1838 for (i = 0; i < 4; i++) {
1839 temp = (data >> (i << 2)) & led_mask;
1841 case ID_LED_ON1_DEF2:
1842 case ID_LED_ON1_ON2:
1843 case ID_LED_ON1_OFF2:
1844 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1845 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1847 case ID_LED_OFF1_DEF2:
1848 case ID_LED_OFF1_ON2:
1849 case ID_LED_OFF1_OFF2:
1850 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1851 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1858 case ID_LED_DEF1_ON2:
1859 case ID_LED_ON1_ON2:
1860 case ID_LED_OFF1_ON2:
1861 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1862 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1864 case ID_LED_DEF1_OFF2:
1865 case ID_LED_ON1_OFF2:
1866 case ID_LED_OFF1_OFF2:
1867 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1868 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1876 return E1000_SUCCESS;
1880 * e1000_setup_led_generic - Configures SW controllable LED
1881 * @hw: pointer to the HW structure
1883 * This prepares the SW controllable LED for use and saves the current state
1884 * of the LED so it can be later restored.
1886 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1890 DEBUGFUNC("e1000_setup_led_generic");
1892 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1893 return -E1000_ERR_CONFIG;
1895 if (hw->phy.media_type == e1000_media_type_fiber) {
1896 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1897 hw->mac.ledctl_default = ledctl;
1899 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1900 E1000_LEDCTL_LED0_MODE_MASK);
1901 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1902 E1000_LEDCTL_LED0_MODE_SHIFT);
1903 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1904 } else if (hw->phy.media_type == e1000_media_type_copper) {
1905 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1908 return E1000_SUCCESS;
1912 * e1000_cleanup_led_generic - Set LED config to default operation
1913 * @hw: pointer to the HW structure
1915 * Remove the current LED configuration and set the LED configuration
1916 * to the default value, saved from the EEPROM.
1918 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1920 DEBUGFUNC("e1000_cleanup_led_generic");
1922 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1923 return E1000_SUCCESS;
1927 * e1000_blink_led_generic - Blink LED
1928 * @hw: pointer to the HW structure
1930 * Blink the LEDs which are set to be on.
1932 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1934 u32 ledctl_blink = 0;
1937 DEBUGFUNC("e1000_blink_led_generic");
1939 if (hw->phy.media_type == e1000_media_type_fiber) {
1940 /* always blink LED0 for PCI-E fiber */
1941 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1942 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1944 /* Set the blink bit for each LED that's "on" (0x0E)
1945 * (or "off" if inverted) in ledctl_mode2. The blink
1946 * logic in hardware only works when mode is set to "on"
1947 * so it must be changed accordingly when the mode is
1948 * "off" and inverted.
1950 ledctl_blink = hw->mac.ledctl_mode2;
1951 for (i = 0; i < 32; i += 8) {
1952 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1953 E1000_LEDCTL_LED0_MODE_MASK;
1954 u32 led_default = hw->mac.ledctl_default >> i;
1956 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1957 (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1958 ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1959 (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1961 ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1962 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1963 E1000_LEDCTL_MODE_LED_ON) << i;
1968 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1970 return E1000_SUCCESS;
1974 * e1000_led_on_generic - Turn LED on
1975 * @hw: pointer to the HW structure
1979 s32 e1000_led_on_generic(struct e1000_hw *hw)
1983 DEBUGFUNC("e1000_led_on_generic");
1985 switch (hw->phy.media_type) {
1986 case e1000_media_type_fiber:
1987 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1988 ctrl &= ~E1000_CTRL_SWDPIN0;
1989 ctrl |= E1000_CTRL_SWDPIO0;
1990 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1992 case e1000_media_type_copper:
1993 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1999 return E1000_SUCCESS;
2003 * e1000_led_off_generic - Turn LED off
2004 * @hw: pointer to the HW structure
2008 s32 e1000_led_off_generic(struct e1000_hw *hw)
2012 DEBUGFUNC("e1000_led_off_generic");
2014 switch (hw->phy.media_type) {
2015 case e1000_media_type_fiber:
2016 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2017 ctrl |= E1000_CTRL_SWDPIN0;
2018 ctrl |= E1000_CTRL_SWDPIO0;
2019 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2021 case e1000_media_type_copper:
2022 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2028 return E1000_SUCCESS;
2032 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2033 * @hw: pointer to the HW structure
2034 * @no_snoop: bitmap of snoop events
2036 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2038 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2042 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2044 if (hw->bus.type != e1000_bus_type_pci_express)
2048 gcr = E1000_READ_REG(hw, E1000_GCR);
2049 gcr &= ~(PCIE_NO_SNOOP_ALL);
2051 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2056 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2057 * @hw: pointer to the HW structure
2059 * Returns E1000_SUCCESS if successful, else returns -10
2060 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2061 * the master requests to be disabled.
2063 * Disables PCI-Express master access and verifies there are no pending
2066 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2069 s32 timeout = MASTER_DISABLE_TIMEOUT;
2071 DEBUGFUNC("e1000_disable_pcie_master_generic");
2073 if (hw->bus.type != e1000_bus_type_pci_express)
2074 return E1000_SUCCESS;
2076 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2077 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2078 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2081 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2082 E1000_STATUS_GIO_MASTER_ENABLE))
2089 DEBUGOUT("Master requests are pending.\n");
2090 return -E1000_ERR_MASTER_REQUESTS_PENDING;
2093 return E1000_SUCCESS;
2097 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2098 * @hw: pointer to the HW structure
2100 * Reset the Adaptive Interframe Spacing throttle to default values.
2102 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2104 struct e1000_mac_info *mac = &hw->mac;
2106 DEBUGFUNC("e1000_reset_adaptive_generic");
2108 if (!mac->adaptive_ifs) {
2109 DEBUGOUT("Not in Adaptive IFS mode!\n");
2113 mac->current_ifs_val = 0;
2114 mac->ifs_min_val = IFS_MIN;
2115 mac->ifs_max_val = IFS_MAX;
2116 mac->ifs_step_size = IFS_STEP;
2117 mac->ifs_ratio = IFS_RATIO;
2119 mac->in_ifs_mode = FALSE;
2120 E1000_WRITE_REG(hw, E1000_AIT, 0);
2124 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2125 * @hw: pointer to the HW structure
2127 * Update the Adaptive Interframe Spacing Throttle value based on the
2128 * time between transmitted packets and time between collisions.
2130 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2132 struct e1000_mac_info *mac = &hw->mac;
2134 DEBUGFUNC("e1000_update_adaptive_generic");
2136 if (!mac->adaptive_ifs) {
2137 DEBUGOUT("Not in Adaptive IFS mode!\n");
2141 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2142 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2143 mac->in_ifs_mode = TRUE;
2144 if (mac->current_ifs_val < mac->ifs_max_val) {
2145 if (!mac->current_ifs_val)
2146 mac->current_ifs_val = mac->ifs_min_val;
2148 mac->current_ifs_val +=
2150 E1000_WRITE_REG(hw, E1000_AIT,
2151 mac->current_ifs_val);
2155 if (mac->in_ifs_mode &&
2156 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2157 mac->current_ifs_val = 0;
2158 mac->in_ifs_mode = FALSE;
2159 E1000_WRITE_REG(hw, E1000_AIT, 0);
2165 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2166 * @hw: pointer to the HW structure
2168 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2169 * set, which is forced to MDI mode only.
2171 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2173 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2175 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2176 DEBUGOUT("Invalid MDI setting detected\n");
2178 return -E1000_ERR_CONFIG;
2181 return E1000_SUCCESS;
2185 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2186 * @hw: pointer to the HW structure
2188 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2191 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2193 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2195 return E1000_SUCCESS;