2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <sys/resourcevar.h>
56 #include <sys/sfbuf.h>
59 #include <drm/i915_drm.h>
61 #include "intel_drv.h"
62 #include "intel_ringbuffer.h"
63 #include <linux/completion.h>
64 #include <linux/jiffies.h>
65 #include <linux/time.h>
67 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
70 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
72 bool map_and_fenceable,
74 static int i915_gem_phys_pwrite(struct drm_device *dev,
75 struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
76 uint64_t size, struct drm_file *file_priv);
78 static void i915_gem_write_fence(struct drm_device *dev, int reg,
79 struct drm_i915_gem_object *obj);
80 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
81 struct drm_i915_fence_reg *fence,
84 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
86 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
87 uint32_t size, int tiling_mode);
88 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
90 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
91 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
93 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
96 i915_gem_release_mmap(obj);
98 /* As we do not have an associated fence register, we will force
99 * a tiling change if we ever need to acquire one.
101 obj->fence_dirty = false;
102 obj->fence_reg = I915_FENCE_REG_NONE;
105 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
106 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
107 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
108 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
109 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
110 uint32_t flush_domains);
111 static void i915_gem_reset_fences(struct drm_device *dev);
112 static void i915_gem_lowmem(void *arg);
114 static int i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
115 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file);
117 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
118 long i915_gem_wired_pages_cnt;
120 /* some bookkeeping */
121 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
124 dev_priv->mm.object_count++;
125 dev_priv->mm.object_memory += size;
128 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
131 dev_priv->mm.object_count--;
132 dev_priv->mm.object_memory -= size;
136 i915_gem_wait_for_error(struct drm_device *dev)
138 struct drm_i915_private *dev_priv = dev->dev_private;
139 struct completion *x = &dev_priv->error_completion;
142 if (!atomic_read(&dev_priv->mm.wedged))
146 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
147 * userspace. If it takes that long something really bad is going on and
148 * we should simply try to bail out and fail as gracefully as possible.
150 ret = wait_for_completion_interruptible_timeout(x, 10*hz);
152 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
154 } else if (ret < 0) {
158 if (atomic_read(&dev_priv->mm.wedged)) {
159 /* GPU is hung, bump the completion count to account for
160 * the token we just consumed so that we never hit zero and
161 * end up waiting upon a subsequent completion event that
164 spin_lock(&x->wait.lock);
166 spin_unlock(&x->wait.lock);
171 int i915_mutex_lock_interruptible(struct drm_device *dev)
175 ret = i915_gem_wait_for_error(dev);
179 ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
183 WARN_ON(i915_verify_lists(dev));
188 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
194 i915_gem_init_ioctl(struct drm_device *dev, void *data,
195 struct drm_file *file)
197 struct drm_i915_gem_init *args = data;
199 if (drm_core_check_feature(dev, DRIVER_MODESET))
202 if (args->gtt_start >= args->gtt_end ||
203 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
206 /* GEM with user mode setting was never supported on ilk and later. */
207 if (INTEL_INFO(dev)->gen >= 5)
210 lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
211 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
212 lockmgr(&dev->dev_lock, LK_RELEASE);
218 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
219 struct drm_file *file)
221 struct drm_i915_private *dev_priv = dev->dev_private;
222 struct drm_i915_gem_get_aperture *args = data;
223 struct drm_i915_gem_object *obj;
228 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
230 pinned += obj->gtt_space->size;
233 args->aper_size = dev_priv->mm.gtt_total;
234 args->aper_available_size = args->aper_size - pinned;
240 i915_gem_create(struct drm_file *file,
241 struct drm_device *dev,
245 struct drm_i915_gem_object *obj;
249 size = roundup(size, PAGE_SIZE);
253 /* Allocate the new object */
254 obj = i915_gem_alloc_object(dev, size);
259 ret = drm_gem_handle_create(file, &obj->base, &handle);
261 drm_gem_object_release(&obj->base);
262 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
263 drm_free(obj, DRM_I915_GEM);
267 /* drop reference from allocate - handle holds it now */
268 drm_gem_object_unreference(&obj->base);
274 i915_gem_dumb_create(struct drm_file *file,
275 struct drm_device *dev,
276 struct drm_mode_create_dumb *args)
279 /* have to work out size/pitch and return them */
280 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
281 args->size = args->pitch * args->height;
282 return i915_gem_create(file, dev,
283 args->size, &args->handle);
286 int i915_gem_dumb_destroy(struct drm_file *file,
287 struct drm_device *dev,
291 return drm_gem_handle_delete(file, handle);
295 * Creates a new mm object and returns a handle to it.
298 i915_gem_create_ioctl(struct drm_device *dev, void *data,
299 struct drm_file *file)
301 struct drm_i915_gem_create *args = data;
303 return i915_gem_create(file, dev,
304 args->size, &args->handle);
307 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
309 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
311 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
312 obj->tiling_mode != I915_TILING_NONE;
316 * Reads data from the object referenced by handle.
318 * On error, the contents of *data are undefined.
321 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
322 struct drm_file *file)
324 struct drm_i915_gem_pread *args = data;
326 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
327 args->offset, UIO_READ, file));
331 * Writes data to the object referenced by handle.
333 * On error, the contents of the buffer that were to be modified are undefined.
336 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
337 struct drm_file *file)
339 struct drm_i915_gem_pwrite *args = data;
341 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
342 args->offset, UIO_WRITE, file));
346 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
349 if (atomic_read(&dev_priv->mm.wedged)) {
350 struct completion *x = &dev_priv->error_completion;
351 bool recovery_complete;
353 /* Give the error handler a chance to run. */
354 spin_lock(&x->wait.lock);
355 recovery_complete = x->done > 0;
356 spin_unlock(&x->wait.lock);
358 /* Non-interruptible callers can't handle -EAGAIN, hence return
359 * -EIO unconditionally for these. */
363 /* Recovery complete, but still wedged means reset failure. */
364 if (recovery_complete)
374 * Compare seqno against outstanding lazy request. Emit a request if they are
378 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
382 DRM_LOCK_ASSERT(ring->dev);
385 if (seqno == ring->outstanding_lazy_request)
386 ret = i915_add_request(ring, NULL, NULL);
392 * __wait_seqno - wait until execution of seqno has finished
393 * @ring: the ring expected to report seqno
395 * @interruptible: do an interruptible wait (normally yes)
396 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
398 * Returns 0 if the seqno was found within the alloted time. Else returns the
399 * errno with remaining time filled in timeout argument.
401 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
402 bool interruptible, struct timespec *timeout)
404 drm_i915_private_t *dev_priv = ring->dev->dev_private;
405 struct timespec before, now, wait_time={1,0};
406 unsigned long timeout_jiffies;
408 bool wait_forever = true;
411 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
414 if (timeout != NULL) {
415 wait_time = *timeout;
416 wait_forever = false;
419 timeout_jiffies = timespec_to_jiffies(&wait_time);
421 if (WARN_ON(!ring->irq_get(ring)))
424 /* Record current time in case interrupted by signal, or wedged * */
425 getrawmonotonic(&before);
428 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
429 atomic_read(&dev_priv->mm.wedged))
432 end = wait_event_interruptible_timeout(ring->irq_queue,
436 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
439 ret = i915_gem_check_wedge(dev_priv, interruptible);
442 } while (end == 0 && wait_forever);
444 getrawmonotonic(&now);
450 struct timespec sleep_time = timespec_sub(now, before);
451 *timeout = timespec_sub(*timeout, sleep_time);
456 case -EAGAIN: /* Wedged */
457 case -ERESTARTSYS: /* Signal */
459 case 0: /* Timeout */
461 set_normalized_timespec(timeout, 0, 0);
462 return -ETIMEDOUT; /* -ETIME on Linux */
463 default: /* Completed */
464 WARN_ON(end < 0); /* We're not aware of other errors */
470 * Waits for a sequence number to be signaled, and cleans up the
471 * request and object lists appropriately for that event.
474 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
476 struct drm_device *dev = ring->dev;
477 struct drm_i915_private *dev_priv = dev->dev_private;
480 DRM_LOCK_ASSERT(dev);
483 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
487 ret = i915_gem_check_olr(ring, seqno);
491 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
497 * Ensures that all rendering to the object has completed and the object is
498 * safe to unbind from the GTT or access from the CPU.
500 static __must_check int
501 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
504 struct intel_ring_buffer *ring = obj->ring;
508 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
512 ret = i915_wait_seqno(ring, seqno);
516 i915_gem_retire_requests_ring(ring);
518 /* Manually manage the write flush as we may have not yet
519 * retired the buffer.
521 if (obj->last_write_seqno &&
522 i915_seqno_passed(seqno, obj->last_write_seqno)) {
523 obj->last_write_seqno = 0;
524 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
530 /* A nonblocking variant of the above wait. This is a highly dangerous routine
531 * as the object state may change during this call.
533 static __must_check int
534 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
537 struct drm_device *dev = obj->base.dev;
538 struct drm_i915_private *dev_priv = dev->dev_private;
539 struct intel_ring_buffer *ring = obj->ring;
543 DRM_LOCK_ASSERT(dev);
544 BUG_ON(!dev_priv->mm.interruptible);
546 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
550 ret = i915_gem_check_wedge(dev_priv, true);
554 ret = i915_gem_check_olr(ring, seqno);
559 ret = __wait_seqno(ring, seqno, true, NULL);
562 i915_gem_retire_requests_ring(ring);
564 /* Manually manage the write flush as we may have not yet
565 * retired the buffer.
567 if (obj->last_write_seqno &&
568 i915_seqno_passed(seqno, obj->last_write_seqno)) {
569 obj->last_write_seqno = 0;
570 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
577 * Called when user space prepares to use an object with the CPU, either
578 * through the mmap ioctl's mapping or a GTT mapping.
581 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
582 struct drm_file *file)
584 struct drm_i915_gem_set_domain *args = data;
585 struct drm_i915_gem_object *obj;
586 uint32_t read_domains = args->read_domains;
587 uint32_t write_domain = args->write_domain;
590 /* Only handle setting domains to types used by the CPU. */
591 if (write_domain & I915_GEM_GPU_DOMAINS)
594 if (read_domains & I915_GEM_GPU_DOMAINS)
597 /* Having something in the write domain implies it's in the read
598 * domain, and only that read domain. Enforce that in the request.
600 if (write_domain != 0 && read_domains != write_domain)
603 ret = i915_mutex_lock_interruptible(dev);
607 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
608 if (&obj->base == NULL) {
613 /* Try to flush the object off the GPU without holding the lock.
614 * We will repeat the flush holding the lock in the normal manner
615 * to catch cases where we are gazumped.
617 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
621 if (read_domains & I915_GEM_DOMAIN_GTT) {
622 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
624 /* Silently promote "you're not bound, there was nothing to do"
625 * to success, since the client was just asking us to
626 * make sure everything was done.
631 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
635 drm_gem_object_unreference(&obj->base);
642 * Called when user space has done writes to this buffer
645 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
646 struct drm_file *file)
648 struct drm_i915_gem_sw_finish *args = data;
649 struct drm_i915_gem_object *obj;
652 ret = i915_mutex_lock_interruptible(dev);
655 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
656 if (&obj->base == NULL) {
661 /* Pinned buffers may be scanout, so flush the cache */
663 i915_gem_object_flush_cpu_write_domain(obj);
665 drm_gem_object_unreference(&obj->base);
672 * Maps the contents of an object, returning the address it is mapped
675 * While the mapping holds a reference on the contents of the object, it doesn't
676 * imply a ref on the object itself.
679 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
680 struct drm_file *file)
682 struct drm_i915_gem_mmap *args = data;
683 struct drm_gem_object *obj;
684 struct proc *p = curproc;
685 vm_map_t map = &p->p_vmspace->vm_map;
690 obj = drm_gem_object_lookup(dev, file, args->handle);
697 size = round_page(args->size);
699 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
707 vm_object_hold(obj->vm_obj);
708 vm_object_reference_locked(obj->vm_obj);
709 vm_object_drop(obj->vm_obj);
710 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
711 PAGE_SIZE, /* align */
713 VM_MAPTYPE_NORMAL, /* maptype */
714 VM_PROT_READ | VM_PROT_WRITE, /* prot */
715 VM_PROT_READ | VM_PROT_WRITE, /* max */
716 MAP_SHARED /* cow */);
717 if (rv != KERN_SUCCESS) {
718 vm_object_deallocate(obj->vm_obj);
719 error = -vm_mmap_to_errno(rv);
721 args->addr_ptr = (uint64_t)addr;
724 drm_gem_object_unreference(obj);
729 * i915_gem_release_mmap - remove physical page mappings
730 * @obj: obj in question
732 * Preserve the reservation of the mmapping with the DRM core code, but
733 * relinquish ownership of the pages back to the system.
735 * It is vital that we remove the page mapping if we have mapped a tiled
736 * object through the GTT and then lose the fence register due to
737 * resource pressure. Similarly if the object has been moved out of the
738 * aperture, than pages mapped into userspace must be revoked. Removing the
739 * mapping will then trigger a page fault on the next user access, allowing
740 * fixup by i915_gem_fault().
743 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
749 if (!obj->fault_mappable)
752 devobj = cdev_pager_lookup(obj);
753 if (devobj != NULL) {
754 page_count = OFF_TO_IDX(obj->base.size);
756 VM_OBJECT_LOCK(devobj);
757 for (i = 0; i < page_count; i++) {
758 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
761 cdev_pager_free_page(devobj, m);
763 VM_OBJECT_UNLOCK(devobj);
764 vm_object_deallocate(devobj);
767 obj->fault_mappable = false;
771 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
775 if (INTEL_INFO(dev)->gen >= 4 ||
776 tiling_mode == I915_TILING_NONE)
779 /* Previous chips need a power-of-two fence region when tiling */
780 if (INTEL_INFO(dev)->gen == 3)
781 gtt_size = 1024*1024;
785 while (gtt_size < size)
792 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
793 * @obj: object to check
795 * Return the required GTT alignment for an object, taking into account
796 * potential fence register mapping.
799 i915_gem_get_gtt_alignment(struct drm_device *dev,
805 * Minimum alignment is 4k (GTT page size), but might be greater
806 * if a fence register is needed for the object.
808 if (INTEL_INFO(dev)->gen >= 4 ||
809 tiling_mode == I915_TILING_NONE)
813 * Previous chips need to be aligned to the size of the smallest
814 * fence register that can contain the object.
816 return i915_gem_get_gtt_size(dev, size, tiling_mode);
820 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
823 * @size: size of the object
824 * @tiling_mode: tiling mode of the object
826 * Return the required GTT alignment for an object, only taking into account
827 * unfenced tiled surface requirements.
830 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
835 * Minimum alignment is 4k (GTT page size) for sane hw.
837 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
838 tiling_mode == I915_TILING_NONE)
841 /* Previous hardware however needs to be aligned to a power-of-two
842 * tile height. The simplest method for determining this is to reuse
843 * the power-of-tile object size.
845 return i915_gem_get_gtt_size(dev, size, tiling_mode);
849 i915_gem_mmap_gtt(struct drm_file *file,
850 struct drm_device *dev,
854 struct drm_i915_private *dev_priv = dev->dev_private;
855 struct drm_i915_gem_object *obj;
858 ret = i915_mutex_lock_interruptible(dev);
862 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
863 if (&obj->base == NULL) {
868 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
873 if (obj->madv != I915_MADV_WILLNEED) {
874 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
879 ret = drm_gem_create_mmap_offset(&obj->base);
883 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
886 drm_gem_object_unreference(&obj->base);
893 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
895 * @data: GTT mapping ioctl data
896 * @file: GEM object info
898 * Simply returns the fake offset to userspace so it can mmap it.
899 * The mmap call will end up in drm_gem_mmap(), which will set things
900 * up so we can get faults in the handler above.
902 * The fault handler will take care of binding the object into the GTT
903 * (since it may have been evicted to make room for something), allocating
904 * a fence register, and mapping the appropriate aperture address into
908 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
909 struct drm_file *file)
911 struct drm_i915_gem_mmap_gtt *args = data;
913 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
916 /* Immediately discard the backing storage */
918 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
922 vm_obj = obj->base.vm_obj;
923 VM_OBJECT_LOCK(vm_obj);
924 vm_object_page_remove(vm_obj, 0, 0, false);
925 VM_OBJECT_UNLOCK(vm_obj);
926 obj->madv = __I915_MADV_PURGED;
930 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
932 return obj->madv == I915_MADV_DONTNEED;
935 static inline void vm_page_reference(vm_page_t m)
937 vm_page_flag_set(m, PG_REFERENCED);
941 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
946 BUG_ON(obj->madv == __I915_MADV_PURGED);
948 if (obj->tiling_mode != I915_TILING_NONE)
949 i915_gem_object_save_bit_17_swizzle(obj);
950 if (obj->madv == I915_MADV_DONTNEED)
952 page_count = obj->base.size / PAGE_SIZE;
953 VM_OBJECT_LOCK(obj->base.vm_obj);
954 #if GEM_PARANOID_CHECK_GTT
955 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
957 for (i = 0; i < page_count; i++) {
961 if (obj->madv == I915_MADV_WILLNEED)
962 vm_page_reference(m);
963 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
964 vm_page_unwire(obj->pages[i], 1);
965 vm_page_wakeup(obj->pages[i]);
966 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
968 VM_OBJECT_UNLOCK(obj->base.vm_obj);
970 drm_free(obj->pages, DRM_I915_GEM);
975 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
978 struct drm_device *dev;
981 int page_count, i, j;
984 KASSERT(obj->pages == NULL, ("Obj already has pages"));
985 page_count = obj->base.size / PAGE_SIZE;
986 obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
988 vm_obj = obj->base.vm_obj;
989 VM_OBJECT_LOCK(vm_obj);
990 for (i = 0; i < page_count; i++) {
991 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
994 VM_OBJECT_UNLOCK(vm_obj);
995 if (i915_gem_object_needs_bit17_swizzle(obj))
996 i915_gem_object_do_bit_17_swizzle(obj);
1000 for (j = 0; j < i; j++) {
1002 vm_page_busy_wait(m, FALSE, "i915gem");
1003 vm_page_unwire(m, 0);
1005 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
1007 VM_OBJECT_UNLOCK(vm_obj);
1008 drm_free(obj->pages, DRM_I915_GEM);
1014 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1015 struct intel_ring_buffer *ring)
1017 struct drm_device *dev = obj->base.dev;
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 seqno = intel_ring_get_seqno(ring);
1021 BUG_ON(ring == NULL);
1024 /* Add a reference if we're newly entering the active list. */
1026 drm_gem_object_reference(&obj->base);
1030 /* Move from whatever list we were on to the tail of execution. */
1031 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1032 list_move_tail(&obj->ring_list, &ring->active_list);
1034 obj->last_read_seqno = seqno;
1036 if (obj->fenced_gpu_access) {
1037 obj->last_fenced_seqno = seqno;
1039 /* Bump MRU to take account of the delayed flush */
1040 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1041 struct drm_i915_fence_reg *reg;
1043 reg = &dev_priv->fence_regs[obj->fence_reg];
1044 list_move_tail(®->lru_list,
1045 &dev_priv->mm.fence_list);
1051 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1053 struct drm_device *dev = obj->base.dev;
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1056 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1057 BUG_ON(!obj->active);
1059 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1061 list_del_init(&obj->ring_list);
1064 obj->last_read_seqno = 0;
1065 obj->last_write_seqno = 0;
1066 obj->base.write_domain = 0;
1068 obj->last_fenced_seqno = 0;
1069 obj->fenced_gpu_access = false;
1072 drm_gem_object_unreference(&obj->base);
1074 WARN_ON(i915_verify_lists(dev));
1078 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 struct intel_ring_buffer *ring;
1084 /* The hardware uses various monotonic 32-bit counters, if we
1085 * detect that they will wraparound we need to idle the GPU
1086 * and reset those counters.
1089 for_each_ring(ring, dev_priv, i) {
1090 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1091 ret |= ring->sync_seqno[j] != 0;
1096 ret = i915_gpu_idle(dev);
1100 i915_gem_retire_requests(dev);
1101 for_each_ring(ring, dev_priv, i) {
1102 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1103 ring->sync_seqno[j] = 0;
1110 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1114 /* reserve 0 for non-seqno */
1115 if (dev_priv->next_seqno == 0) {
1116 int ret = i915_gem_handle_seqno_wrap(dev);
1120 dev_priv->next_seqno = 1;
1123 *seqno = dev_priv->next_seqno++;
1128 i915_add_request(struct intel_ring_buffer *ring,
1129 struct drm_file *file,
1132 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1133 struct drm_i915_gem_request *request;
1134 u32 request_ring_position;
1139 * Emit any outstanding flushes - execbuf can fail to emit the flush
1140 * after having emitted the batchbuffer command. Hence we need to fix
1141 * things up similar to emitting the lazy request. The difference here
1142 * is that the flush _must_ happen before the next request, no matter
1145 if (ring->gpu_caches_dirty) {
1146 ret = i915_gem_flush_ring(ring, 0, I915_GEM_GPU_DOMAINS);
1150 ring->gpu_caches_dirty = false;
1153 request = kmalloc(sizeof(*request), DRM_I915_GEM, M_WAITOK | M_ZERO);
1154 if (request == NULL)
1158 /* Record the position of the start of the request so that
1159 * should we detect the updated seqno part-way through the
1160 * GPU processing the request, we never over-estimate the
1161 * position of the head.
1163 request_ring_position = intel_ring_get_tail(ring);
1165 ret = ring->add_request(ring);
1167 kfree(request, DRM_I915_GEM);
1171 request->seqno = intel_ring_get_seqno(ring);
1172 request->ring = ring;
1173 request->tail = request_ring_position;
1174 request->emitted_jiffies = jiffies;
1175 was_empty = list_empty(&ring->request_list);
1176 list_add_tail(&request->list, &ring->request_list);
1177 request->file_priv = NULL;
1180 struct drm_i915_file_private *file_priv = file->driver_priv;
1182 spin_lock(&file_priv->mm.lock);
1183 request->file_priv = file_priv;
1184 list_add_tail(&request->client_list,
1185 &file_priv->mm.request_list);
1186 spin_unlock(&file_priv->mm.lock);
1189 ring->outstanding_lazy_request = 0;
1191 if (!dev_priv->mm.suspended) {
1192 if (i915_enable_hangcheck) {
1193 mod_timer(&dev_priv->hangcheck_timer,
1194 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1197 queue_delayed_work(dev_priv->wq,
1198 &dev_priv->mm.retire_work,
1199 round_jiffies_up_relative(hz));
1200 intel_mark_busy(dev_priv->dev);
1205 *out_seqno = request->seqno;
1210 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1212 struct drm_i915_file_private *file_priv = request->file_priv;
1217 spin_lock(&file_priv->mm.lock);
1218 if (request->file_priv) {
1219 list_del(&request->client_list);
1220 request->file_priv = NULL;
1222 spin_unlock(&file_priv->mm.lock);
1225 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1226 struct intel_ring_buffer *ring)
1228 while (!list_empty(&ring->request_list)) {
1229 struct drm_i915_gem_request *request;
1231 request = list_first_entry(&ring->request_list,
1232 struct drm_i915_gem_request,
1235 list_del(&request->list);
1236 i915_gem_request_remove_from_client(request);
1237 drm_free(request, DRM_I915_GEM);
1240 while (!list_empty(&ring->active_list)) {
1241 struct drm_i915_gem_object *obj;
1243 obj = list_first_entry(&ring->active_list,
1244 struct drm_i915_gem_object,
1247 list_del_init(&obj->gpu_write_list);
1248 i915_gem_object_move_to_inactive(obj);
1252 static void i915_gem_reset_fences(struct drm_device *dev)
1254 struct drm_i915_private *dev_priv = dev->dev_private;
1257 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1258 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1260 i915_gem_write_fence(dev, i, NULL);
1263 i915_gem_object_fence_lost(reg->obj);
1267 INIT_LIST_HEAD(®->lru_list);
1270 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1273 void i915_gem_reset(struct drm_device *dev)
1275 struct drm_i915_private *dev_priv = dev->dev_private;
1276 struct drm_i915_gem_object *obj;
1277 struct intel_ring_buffer *ring;
1280 for_each_ring(ring, dev_priv, i)
1281 i915_gem_reset_ring_lists(dev_priv, ring);
1283 /* Move everything out of the GPU domains to ensure we do any
1284 * necessary invalidation upon reuse.
1286 list_for_each_entry(obj,
1287 &dev_priv->mm.inactive_list,
1290 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1293 /* The fence registers are invalidated so clear them out */
1294 i915_gem_reset_fences(dev);
1298 * This function clears the request list as sequence numbers are passed.
1301 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1305 if (list_empty(&ring->request_list))
1308 WARN_ON(i915_verify_lists(ring->dev));
1310 seqno = ring->get_seqno(ring, true);
1312 while (!list_empty(&ring->request_list)) {
1313 struct drm_i915_gem_request *request;
1315 request = list_first_entry(&ring->request_list,
1316 struct drm_i915_gem_request,
1319 if (!i915_seqno_passed(seqno, request->seqno))
1322 /* We know the GPU must have read the request to have
1323 * sent us the seqno + interrupt, so use the position
1324 * of tail of the request to update the last known position
1327 ring->last_retired_head = request->tail;
1329 list_del(&request->list);
1330 i915_gem_request_remove_from_client(request);
1331 kfree(request, DRM_I915_GEM);
1334 /* Move any buffers on the active list that are no longer referenced
1335 * by the ringbuffer to the flushing/inactive lists as appropriate.
1337 while (!list_empty(&ring->active_list)) {
1338 struct drm_i915_gem_object *obj;
1340 obj = list_first_entry(&ring->active_list,
1341 struct drm_i915_gem_object,
1344 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
1347 i915_gem_object_move_to_inactive(obj);
1350 if (unlikely(ring->trace_irq_seqno &&
1351 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1352 ring->irq_put(ring);
1353 ring->trace_irq_seqno = 0;
1359 i915_gem_retire_requests(struct drm_device *dev)
1361 drm_i915_private_t *dev_priv = dev->dev_private;
1362 struct intel_ring_buffer *ring;
1365 for_each_ring(ring, dev_priv, i)
1366 i915_gem_retire_requests_ring(ring);
1370 i915_gem_retire_work_handler(struct work_struct *work)
1372 drm_i915_private_t *dev_priv;
1373 struct drm_device *dev;
1374 struct intel_ring_buffer *ring;
1378 dev_priv = container_of(work, drm_i915_private_t,
1379 mm.retire_work.work);
1380 dev = dev_priv->dev;
1382 /* Come back later if the device is busy... */
1383 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
1384 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1385 round_jiffies_up_relative(hz));
1389 i915_gem_retire_requests(dev);
1391 /* Send a periodic flush down the ring so we don't hold onto GEM
1392 * objects indefinitely.
1395 for_each_ring(ring, dev_priv, i) {
1396 if (ring->gpu_caches_dirty)
1397 i915_add_request(ring, NULL, NULL);
1399 idle &= list_empty(&ring->request_list);
1402 if (!dev_priv->mm.suspended && !idle)
1403 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
1404 round_jiffies_up_relative(hz));
1406 intel_mark_idle(dev);
1411 * Ensures that an object will eventually get non-busy by flushing any required
1412 * write domains, emitting any outstanding lazy request and retiring and
1413 * completed requests.
1416 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
1421 ret = i915_gem_object_flush_gpu_write_domain(obj);
1425 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
1429 i915_gem_retire_requests_ring(obj->ring);
1436 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
1437 * @DRM_IOCTL_ARGS: standard ioctl arguments
1439 * Returns 0 if successful, else an error is returned with the remaining time in
1440 * the timeout parameter.
1441 * -ETIME: object is still busy after timeout
1442 * -ERESTARTSYS: signal interrupted the wait
1443 * -ENONENT: object doesn't exist
1444 * Also possible, but rare:
1445 * -EAGAIN: GPU wedged
1447 * -ENODEV: Internal IRQ fail
1448 * -E?: The add request failed
1450 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
1451 * non-zero timeout parameter the wait ioctl will wait for the given number of
1452 * nanoseconds on an object becoming unbusy. Since the wait itself does so
1453 * without holding struct_mutex the object may become re-busied before this
1454 * function completes. A similar but shorter * race condition exists in the busy
1458 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1460 struct drm_i915_gem_wait *args = data;
1461 struct drm_i915_gem_object *obj;
1462 struct intel_ring_buffer *ring = NULL;
1463 struct timespec timeout_stack, *timeout = NULL;
1467 if (args->timeout_ns >= 0) {
1468 timeout_stack = ns_to_timespec(args->timeout_ns);
1469 timeout = &timeout_stack;
1472 ret = i915_mutex_lock_interruptible(dev);
1476 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
1477 if (&obj->base == NULL) {
1482 /* Need to make sure the object gets inactive eventually. */
1483 ret = i915_gem_object_flush_active(obj);
1488 seqno = obj->last_read_seqno;
1495 /* Do this after OLR check to make sure we make forward progress polling
1496 * on this IOCTL with a 0 timeout (like busy ioctl)
1498 if (!args->timeout_ns) {
1503 drm_gem_object_unreference(&obj->base);
1506 ret = __wait_seqno(ring, seqno, true, timeout);
1508 WARN_ON(!timespec_valid(timeout));
1509 args->timeout_ns = timespec_to_ns(timeout);
1514 drm_gem_object_unreference(&obj->base);
1520 * i915_gem_object_sync - sync an object to a ring.
1522 * @obj: object which may be in use on another ring.
1523 * @to: ring we wish to use the object on. May be NULL.
1525 * This code is meant to abstract object synchronization with the GPU.
1526 * Calling with NULL implies synchronizing the object with the CPU
1527 * rather than a particular GPU ring.
1529 * Returns 0 if successful, else propagates up the lower layer error.
1532 i915_gem_object_sync(struct drm_i915_gem_object *obj,
1533 struct intel_ring_buffer *to)
1535 struct intel_ring_buffer *from = obj->ring;
1539 if (from == NULL || to == from)
1542 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
1543 return i915_gem_object_wait_rendering(obj, false);
1545 idx = intel_ring_sync_index(from, to);
1547 seqno = obj->last_read_seqno;
1548 if (seqno <= from->sync_seqno[idx])
1551 ret = i915_gem_check_olr(obj->ring, seqno);
1555 ret = to->sync_to(to, from, seqno);
1557 /* We use last_read_seqno because sync_to()
1558 * might have just caused seqno wrap under
1561 from->sync_seqno[idx] = obj->last_read_seqno;
1566 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
1568 u32 old_write_domain, old_read_domains;
1570 /* Act a barrier for all accesses through the GTT */
1573 /* Force a pagefault for domain tracking on next user access */
1574 i915_gem_release_mmap(obj);
1576 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
1579 old_read_domains = obj->base.read_domains;
1580 old_write_domain = obj->base.write_domain;
1582 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
1583 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
1588 * Unbinds an object from the GTT aperture.
1591 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
1593 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1596 if (obj->gtt_space == NULL)
1602 ret = i915_gem_object_finish_gpu(obj);
1605 /* Continue on if we fail due to EIO, the GPU is hung so we
1606 * should be safe and we need to cleanup or else we might
1607 * cause memory corruption through use-after-free.
1610 i915_gem_object_finish_gtt(obj);
1612 /* Move the object to the CPU domain to ensure that
1613 * any possible CPU writes while it's not in the GTT
1614 * are flushed when we go to remap it.
1617 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1618 if (ret == -ERESTART || ret == -EINTR)
1621 /* In the event of a disaster, abandon all caches and
1622 * hope for the best.
1624 i915_gem_clflush_object(obj);
1625 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1628 /* release the fence reg _after_ flushing */
1629 ret = i915_gem_object_put_fence(obj);
1633 if (obj->has_global_gtt_mapping)
1634 i915_gem_gtt_unbind_object(obj);
1635 if (obj->has_aliasing_ppgtt_mapping) {
1636 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
1637 obj->has_aliasing_ppgtt_mapping = 0;
1639 i915_gem_gtt_finish_object(obj);
1641 i915_gem_object_put_pages_gtt(obj);
1643 list_del_init(&obj->gtt_list);
1644 list_del_init(&obj->mm_list);
1645 /* Avoid an unnecessary call to unbind on rebind. */
1646 obj->map_and_fenceable = true;
1648 drm_mm_put_block(obj->gtt_space);
1649 obj->gtt_space = NULL;
1650 obj->gtt_offset = 0;
1652 if (i915_gem_object_is_purgeable(obj))
1653 i915_gem_object_truncate(obj);
1658 int i915_gpu_idle(struct drm_device *dev)
1660 drm_i915_private_t *dev_priv = dev->dev_private;
1661 struct intel_ring_buffer *ring;
1664 /* Flush everything onto the inactive list. */
1665 for_each_ring(ring, dev_priv, i) {
1666 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
1670 ret = intel_ring_idle(ring);
1678 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
1679 struct drm_i915_gem_object *obj)
1681 drm_i915_private_t *dev_priv = dev->dev_private;
1685 u32 size = obj->gtt_space->size;
1687 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1689 val |= obj->gtt_offset & 0xfffff000;
1690 val |= (uint64_t)((obj->stride / 128) - 1) <<
1691 SANDYBRIDGE_FENCE_PITCH_SHIFT;
1693 if (obj->tiling_mode == I915_TILING_Y)
1694 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1695 val |= I965_FENCE_REG_VALID;
1699 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
1700 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
1703 static void i965_write_fence_reg(struct drm_device *dev, int reg,
1704 struct drm_i915_gem_object *obj)
1706 drm_i915_private_t *dev_priv = dev->dev_private;
1710 u32 size = obj->gtt_space->size;
1712 val = (uint64_t)((obj->gtt_offset + size - 4096) &
1714 val |= obj->gtt_offset & 0xfffff000;
1715 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1716 if (obj->tiling_mode == I915_TILING_Y)
1717 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1718 val |= I965_FENCE_REG_VALID;
1722 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
1723 POSTING_READ(FENCE_REG_965_0 + reg * 8);
1726 static void i915_write_fence_reg(struct drm_device *dev, int reg,
1727 struct drm_i915_gem_object *obj)
1729 drm_i915_private_t *dev_priv = dev->dev_private;
1733 u32 size = obj->gtt_space->size;
1737 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
1738 (size & -size) != size ||
1739 (obj->gtt_offset & (size - 1)),
1740 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
1741 obj->gtt_offset, obj->map_and_fenceable, size);
1743 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1748 /* Note: pitch better be a power of two tile widths */
1749 pitch_val = obj->stride / tile_width;
1750 pitch_val = ffs(pitch_val) - 1;
1752 val = obj->gtt_offset;
1753 if (obj->tiling_mode == I915_TILING_Y)
1754 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1755 val |= I915_FENCE_SIZE_BITS(size);
1756 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1757 val |= I830_FENCE_REG_VALID;
1762 reg = FENCE_REG_830_0 + reg * 4;
1764 reg = FENCE_REG_945_8 + (reg - 8) * 4;
1766 I915_WRITE(reg, val);
1770 static void i830_write_fence_reg(struct drm_device *dev, int reg,
1771 struct drm_i915_gem_object *obj)
1773 drm_i915_private_t *dev_priv = dev->dev_private;
1777 u32 size = obj->gtt_space->size;
1780 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
1781 (size & -size) != size ||
1782 (obj->gtt_offset & (size - 1)),
1783 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
1784 obj->gtt_offset, size);
1786 pitch_val = obj->stride / 128;
1787 pitch_val = ffs(pitch_val) - 1;
1789 val = obj->gtt_offset;
1790 if (obj->tiling_mode == I915_TILING_Y)
1791 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1792 val |= I830_FENCE_SIZE_BITS(size);
1793 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1794 val |= I830_FENCE_REG_VALID;
1798 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
1799 POSTING_READ(FENCE_REG_830_0 + reg * 4);
1802 static void i915_gem_write_fence(struct drm_device *dev, int reg,
1803 struct drm_i915_gem_object *obj)
1805 switch (INTEL_INFO(dev)->gen) {
1807 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
1809 case 4: i965_write_fence_reg(dev, reg, obj); break;
1810 case 3: i915_write_fence_reg(dev, reg, obj); break;
1811 case 2: i830_write_fence_reg(dev, reg, obj); break;
1816 static inline int fence_number(struct drm_i915_private *dev_priv,
1817 struct drm_i915_fence_reg *fence)
1819 return fence - dev_priv->fence_regs;
1822 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
1823 struct drm_i915_fence_reg *fence,
1826 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1827 int reg = fence_number(dev_priv, fence);
1829 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
1832 obj->fence_reg = reg;
1834 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
1836 obj->fence_reg = I915_FENCE_REG_NONE;
1838 list_del_init(&fence->lru_list);
1843 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
1847 if (obj->fenced_gpu_access) {
1848 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1849 ret = i915_gem_flush_ring(obj->ring,
1850 0, obj->base.write_domain);
1855 obj->fenced_gpu_access = false;
1858 if (obj->last_fenced_seqno) {
1859 ret = i915_wait_seqno(obj->ring,
1860 obj->last_fenced_seqno);
1864 obj->last_fenced_seqno = 0;
1867 /* Ensure that all CPU reads are completed before installing a fence
1868 * and all writes before removing the fence.
1870 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
1877 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
1879 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1882 ret = i915_gem_object_flush_fence(obj);
1886 if (obj->fence_reg == I915_FENCE_REG_NONE)
1889 i915_gem_object_update_fence(obj,
1890 &dev_priv->fence_regs[obj->fence_reg],
1892 i915_gem_object_fence_lost(obj);
1897 static struct drm_i915_fence_reg *
1898 i915_find_fence_reg(struct drm_device *dev)
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 struct drm_i915_fence_reg *reg, *avail;
1904 /* First try to find a free reg */
1906 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1907 reg = &dev_priv->fence_regs[i];
1911 if (!reg->pin_count)
1918 /* None available, try to steal one or wait for a user to finish */
1919 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
1930 * i915_gem_object_get_fence - set up fencing for an object
1931 * @obj: object to map through a fence reg
1933 * When mapping objects through the GTT, userspace wants to be able to write
1934 * to them without having to worry about swizzling if the object is tiled.
1935 * This function walks the fence regs looking for a free one for @obj,
1936 * stealing one if it can't find any.
1938 * It then sets up the reg based on the object's properties: address, pitch
1939 * and tiling format.
1941 * For an untiled surface, this removes any existing fence.
1944 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
1946 struct drm_device *dev = obj->base.dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 bool enable = obj->tiling_mode != I915_TILING_NONE;
1949 struct drm_i915_fence_reg *reg;
1952 /* Have we updated the tiling parameters upon the object and so
1953 * will need to serialise the write to the associated fence register?
1955 if (obj->fence_dirty) {
1956 ret = i915_gem_object_flush_fence(obj);
1961 /* Just update our place in the LRU if our fence is getting reused. */
1962 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1963 reg = &dev_priv->fence_regs[obj->fence_reg];
1964 if (!obj->fence_dirty) {
1965 list_move_tail(®->lru_list,
1966 &dev_priv->mm.fence_list);
1969 } else if (enable) {
1970 reg = i915_find_fence_reg(dev);
1975 struct drm_i915_gem_object *old = reg->obj;
1977 ret = i915_gem_object_flush_fence(old);
1981 i915_gem_object_fence_lost(old);
1986 i915_gem_object_update_fence(obj, reg, enable);
1987 obj->fence_dirty = false;
1993 * Finds free space in the GTT aperture and binds the object there.
1996 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
1998 bool map_and_fenceable,
2001 struct drm_device *dev = obj->base.dev;
2002 drm_i915_private_t *dev_priv = dev->dev_private;
2003 struct drm_mm_node *free_space;
2004 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
2005 bool mappable, fenceable;
2008 if (obj->madv != I915_MADV_WILLNEED) {
2009 DRM_ERROR("Attempting to bind a purgeable object\n");
2013 fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
2015 fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
2017 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
2018 obj->base.size, obj->tiling_mode);
2020 alignment = map_and_fenceable ? fence_alignment :
2022 if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
2023 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2027 size = map_and_fenceable ? fence_size : obj->base.size;
2029 /* If the object is bigger than the entire aperture, reject it early
2030 * before evicting everything in a vain attempt to find space.
2032 if (obj->base.size > (map_and_fenceable ?
2033 dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2035 "Attempting to bind an object larger than the aperture\n");
2040 if (map_and_fenceable)
2041 free_space = drm_mm_search_free_in_range(
2042 &dev_priv->mm.gtt_space, size, alignment, 0,
2043 dev_priv->mm.gtt_mappable_end, 0);
2045 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2046 size, alignment, 0);
2047 if (free_space != NULL) {
2049 if (map_and_fenceable)
2050 obj->gtt_space = drm_mm_get_block_range_generic(
2051 free_space, size, alignment, color, 0,
2052 dev_priv->mm.gtt_mappable_end, 1);
2054 obj->gtt_space = drm_mm_get_block_generic(free_space,
2055 size, alignment, color, 1);
2057 if (obj->gtt_space == NULL) {
2058 ret = i915_gem_evict_something(dev, size, alignment,
2068 * NOTE: i915_gem_object_get_pages_gtt() cannot
2069 * return ENOMEM, since we used VM_ALLOC_RETRY.
2071 ret = i915_gem_object_get_pages_gtt(obj, 0);
2073 drm_mm_put_block(obj->gtt_space);
2074 obj->gtt_space = NULL;
2078 i915_gem_gtt_bind_object(obj, obj->cache_level);
2080 i915_gem_object_put_pages_gtt(obj);
2081 drm_mm_put_block(obj->gtt_space);
2082 obj->gtt_space = NULL;
2083 if (i915_gem_evict_everything(dev))
2088 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2089 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2091 obj->gtt_offset = obj->gtt_space->start;
2094 obj->gtt_space->size == fence_size &&
2095 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2098 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2099 obj->map_and_fenceable = mappable && fenceable;
2105 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2108 /* If we don't have a page list set up, then we're not pinned
2109 * to GPU, and we can ignore the cache flush because it'll happen
2110 * again at bind time.
2112 if (obj->pages == NULL)
2115 /* If the GPU is snooping the contents of the CPU cache,
2116 * we do not need to manually clear the CPU cache lines. However,
2117 * the caches are only snooped when the render cache is
2118 * flushed/invalidated. As we always have to emit invalidations
2119 * and flushes when moving into and out of the RENDER domain, correct
2120 * snooping behaviour occurs naturally as the result of our domain
2123 if (obj->cache_level != I915_CACHE_NONE)
2126 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2129 /** Flushes the GTT write domain for the object if it's dirty. */
2131 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2133 uint32_t old_write_domain;
2135 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2138 /* No actual flushing is required for the GTT write domain. Writes
2139 * to it immediately go to main memory as far as we know, so there's
2140 * no chipset flush. It also doesn't land in render cache.
2142 * However, we do have to enforce the order so that all writes through
2143 * the GTT land before any writes to the device, such as updates to
2148 old_write_domain = obj->base.write_domain;
2149 obj->base.write_domain = 0;
2152 /** Flushes the CPU write domain for the object if it's dirty. */
2154 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2156 uint32_t old_write_domain;
2158 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2161 i915_gem_clflush_object(obj);
2162 intel_gtt_chipset_flush();
2163 old_write_domain = obj->base.write_domain;
2164 obj->base.write_domain = 0;
2168 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2171 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2173 return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
2177 * Moves a single object to the GTT read, and possibly write domain.
2179 * This function returns when the move is complete, including waiting on
2183 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2185 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2186 uint32_t old_write_domain, old_read_domains;
2189 /* Not valid to be called on unbound objects. */
2190 if (obj->gtt_space == NULL)
2193 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2196 ret = i915_gem_object_flush_gpu_write_domain(obj);
2200 ret = i915_gem_object_wait_rendering(obj, !write);
2204 i915_gem_object_flush_cpu_write_domain(obj);
2206 old_write_domain = obj->base.write_domain;
2207 old_read_domains = obj->base.read_domains;
2209 /* It should now be out of any other write domains, and we can update
2210 * the domain values for our changes.
2212 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2213 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2215 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2216 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2220 /* And bump the LRU for this access */
2221 if (i915_gem_object_is_inactive(obj))
2222 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2227 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2228 enum i915_cache_level cache_level)
2230 struct drm_device *dev = obj->base.dev;
2231 drm_i915_private_t *dev_priv = dev->dev_private;
2234 if (obj->cache_level == cache_level)
2237 if (obj->pin_count) {
2238 DRM_DEBUG("can not change the cache level of pinned objects\n");
2242 if (obj->gtt_space) {
2243 ret = i915_gem_object_finish_gpu(obj);
2247 i915_gem_object_finish_gtt(obj);
2249 /* Before SandyBridge, you could not use tiling or fence
2250 * registers with snooped memory, so relinquish any fences
2251 * currently pointing to our region in the aperture.
2253 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2254 ret = i915_gem_object_put_fence(obj);
2259 if (obj->has_global_gtt_mapping)
2260 i915_gem_gtt_bind_object(obj, cache_level);
2261 if (obj->has_aliasing_ppgtt_mapping)
2262 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2266 if (cache_level == I915_CACHE_NONE) {
2267 u32 old_read_domains, old_write_domain;
2269 /* If we're coming from LLC cached, then we haven't
2270 * actually been tracking whether the data is in the
2271 * CPU cache or not, since we only allow one bit set
2272 * in obj->write_domain and have been skipping the clflushes.
2273 * Just set it to the CPU cache for now.
2275 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
2276 ("obj %p in CPU write domain", obj));
2277 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
2278 ("obj %p in CPU read domain", obj));
2280 old_read_domains = obj->base.read_domains;
2281 old_write_domain = obj->base.write_domain;
2283 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2284 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2288 obj->cache_level = cache_level;
2292 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2293 struct drm_file *file)
2295 struct drm_i915_gem_caching *args = data;
2296 struct drm_i915_gem_object *obj;
2299 ret = i915_mutex_lock_interruptible(dev);
2303 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2304 if (&obj->base == NULL) {
2309 args->caching = obj->cache_level != I915_CACHE_NONE;
2311 drm_gem_object_unreference(&obj->base);
2317 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2318 struct drm_file *file)
2320 struct drm_i915_gem_caching *args = data;
2321 struct drm_i915_gem_object *obj;
2322 enum i915_cache_level level;
2325 switch (args->caching) {
2326 case I915_CACHING_NONE:
2327 level = I915_CACHE_NONE;
2329 case I915_CACHING_CACHED:
2330 level = I915_CACHE_LLC;
2336 ret = i915_mutex_lock_interruptible(dev);
2340 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2341 if (&obj->base == NULL) {
2346 ret = i915_gem_object_set_cache_level(obj, level);
2348 drm_gem_object_unreference(&obj->base);
2355 * Prepare buffer for display plane (scanout, cursors, etc).
2356 * Can be called from an uninterruptible phase (modesetting) and allows
2357 * any flushes to be pipelined (for pageflips).
2360 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2362 struct intel_ring_buffer *pipelined)
2364 u32 old_read_domains, old_write_domain;
2367 ret = i915_gem_object_flush_gpu_write_domain(obj);
2371 if (pipelined != obj->ring) {
2372 ret = i915_gem_object_sync(obj, pipelined);
2377 /* The display engine is not coherent with the LLC cache on gen6. As
2378 * a result, we make sure that the pinning that is about to occur is
2379 * done with uncached PTEs. This is lowest common denominator for all
2382 * However for gen6+, we could do better by using the GFDT bit instead
2383 * of uncaching, which would allow us to flush all the LLC-cached data
2384 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2386 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2390 /* As the user may map the buffer once pinned in the display plane
2391 * (e.g. libkms for the bootup splash), we have to ensure that we
2392 * always use map_and_fenceable for all scanout buffers.
2394 ret = i915_gem_object_pin(obj, alignment, true, false);
2398 i915_gem_object_flush_cpu_write_domain(obj);
2400 old_write_domain = obj->base.write_domain;
2401 old_read_domains = obj->base.read_domains;
2403 /* It should now be out of any other write domains, and we can update
2404 * the domain values for our changes.
2406 obj->base.write_domain = 0;
2407 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2413 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2417 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2420 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2421 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2426 ret = i915_gem_object_wait_rendering(obj, false);
2430 /* Ensure that we invalidate the GPU's caches and TLBs. */
2431 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2436 * Moves a single object to the CPU read, and possibly write domain.
2438 * This function returns when the move is complete, including waiting on
2442 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2444 uint32_t old_write_domain, old_read_domains;
2447 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2450 ret = i915_gem_object_flush_gpu_write_domain(obj);
2454 ret = i915_gem_object_wait_rendering(obj, !write);
2458 i915_gem_object_flush_gtt_write_domain(obj);
2460 old_write_domain = obj->base.write_domain;
2461 old_read_domains = obj->base.read_domains;
2463 /* Flush the CPU cache if it's still invalid. */
2464 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2465 i915_gem_clflush_object(obj);
2467 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2470 /* It should now be out of any other write domains, and we can update
2471 * the domain values for our changes.
2473 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2475 /* If we're writing through the CPU, then the GPU read domains will
2476 * need to be invalidated at next use.
2479 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2480 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2486 /* Throttle our rendering by waiting until the ring has completed our requests
2487 * emitted over 20 msec ago.
2489 * Note that if we were to use the current jiffies each time around the loop,
2490 * we wouldn't escape the function with any frames outstanding if the time to
2491 * render a frame was over 20ms.
2493 * This should get us reasonable parallelism between CPU and GPU but also
2494 * relatively low latency when blocking on a particular request to finish.
2497 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
2499 struct drm_i915_private *dev_priv = dev->dev_private;
2500 struct drm_i915_file_private *file_priv = file->driver_priv;
2501 unsigned long recent_enough = ticks - (20 * hz / 1000);
2502 struct drm_i915_gem_request *request;
2503 struct intel_ring_buffer *ring = NULL;
2507 if (atomic_read(&dev_priv->mm.wedged))
2510 spin_lock(&file_priv->mm.lock);
2511 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
2512 if (time_after_eq(request->emitted_jiffies, recent_enough))
2515 ring = request->ring;
2516 seqno = request->seqno;
2518 spin_unlock(&file_priv->mm.lock);
2523 ret = __wait_seqno(ring, seqno, true, NULL);
2526 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
2532 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2534 bool map_and_fenceable,
2539 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
2542 if (obj->gtt_space != NULL) {
2543 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
2544 (map_and_fenceable && !obj->map_and_fenceable)) {
2545 WARN(obj->pin_count,
2546 "bo is already pinned with incorrect alignment:"
2547 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
2548 " obj->map_and_fenceable=%d\n",
2549 obj->gtt_offset, alignment,
2551 obj->map_and_fenceable);
2552 ret = i915_gem_object_unbind(obj);
2558 if (obj->gtt_space == NULL) {
2559 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2561 ret = i915_gem_object_bind_to_gtt(obj, alignment,
2567 if (!dev_priv->mm.aliasing_ppgtt)
2568 i915_gem_gtt_bind_object(obj, obj->cache_level);
2571 if (!obj->has_global_gtt_mapping && map_and_fenceable)
2572 i915_gem_gtt_bind_object(obj, obj->cache_level);
2575 obj->pin_mappable |= map_and_fenceable;
2581 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
2583 BUG_ON(obj->pin_count == 0);
2584 BUG_ON(obj->gtt_space == NULL);
2586 if (--obj->pin_count == 0)
2587 obj->pin_mappable = false;
2591 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2592 struct drm_file *file)
2594 struct drm_i915_gem_pin *args = data;
2595 struct drm_i915_gem_object *obj;
2598 ret = i915_mutex_lock_interruptible(dev);
2602 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2603 if (&obj->base == NULL) {
2608 if (obj->madv != I915_MADV_WILLNEED) {
2609 DRM_ERROR("Attempting to pin a purgeable buffer\n");
2614 if (obj->pin_filp != NULL && obj->pin_filp != file) {
2615 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2621 if (obj->user_pin_count == 0) {
2622 ret = i915_gem_object_pin(obj, args->alignment, true, false);
2627 obj->user_pin_count++;
2628 obj->pin_filp = file;
2630 /* XXX - flush the CPU caches for pinned objects
2631 * as the X server doesn't manage domains yet
2633 i915_gem_object_flush_cpu_write_domain(obj);
2634 args->offset = obj->gtt_offset;
2636 drm_gem_object_unreference(&obj->base);
2643 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2644 struct drm_file *file)
2646 struct drm_i915_gem_pin *args = data;
2647 struct drm_i915_gem_object *obj;
2650 ret = i915_mutex_lock_interruptible(dev);
2654 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2655 if (&obj->base == NULL) {
2660 if (obj->pin_filp != file) {
2661 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2666 obj->user_pin_count--;
2667 if (obj->user_pin_count == 0) {
2668 obj->pin_filp = NULL;
2669 i915_gem_object_unpin(obj);
2673 drm_gem_object_unreference(&obj->base);
2680 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2681 struct drm_file *file)
2683 struct drm_i915_gem_busy *args = data;
2684 struct drm_i915_gem_object *obj;
2687 ret = i915_mutex_lock_interruptible(dev);
2691 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
2692 if (&obj->base == NULL) {
2697 /* Count all active objects as busy, even if they are currently not used
2698 * by the gpu. Users of this interface expect objects to eventually
2699 * become non-busy without any further actions, therefore emit any
2700 * necessary flushes here.
2702 ret = i915_gem_object_flush_active(obj);
2704 args->busy = obj->active;
2706 args->busy |= intel_ring_flag(obj->ring) << 17;
2709 drm_gem_object_unreference(&obj->base);
2716 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2717 struct drm_file *file_priv)
2719 return i915_gem_ring_throttle(dev, file_priv);
2723 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2724 struct drm_file *file_priv)
2726 struct drm_i915_gem_madvise *args = data;
2727 struct drm_i915_gem_object *obj;
2730 switch (args->madv) {
2731 case I915_MADV_DONTNEED:
2732 case I915_MADV_WILLNEED:
2738 ret = i915_mutex_lock_interruptible(dev);
2742 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
2743 if (&obj->base == NULL) {
2748 if (obj->pin_count) {
2753 if (obj->madv != __I915_MADV_PURGED)
2754 obj->madv = args->madv;
2756 /* if the object is no longer attached, discard its backing storage */
2757 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
2758 i915_gem_object_truncate(obj);
2760 args->retained = obj->madv != __I915_MADV_PURGED;
2763 drm_gem_object_unreference(&obj->base);
2769 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2772 struct drm_i915_private *dev_priv;
2773 struct drm_i915_gem_object *obj;
2775 dev_priv = dev->dev_private;
2777 obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
2779 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
2780 drm_free(obj, DRM_I915_GEM);
2784 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2785 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2788 /* On some devices, we can have the GPU use the LLC (the CPU
2789 * cache) for about a 10% performance improvement
2790 * compared to uncached. Graphics requests other than
2791 * display scanout are coherent with the CPU in
2792 * accessing this cache. This means in this mode we
2793 * don't need to clflush on the CPU side, and on the
2794 * GPU side we only need to flush internal caches to
2795 * get data visible to the CPU.
2797 * However, we maintain the display planes as UC, and so
2798 * need to rebind when first used as such.
2800 obj->cache_level = I915_CACHE_LLC;
2802 obj->cache_level = I915_CACHE_NONE;
2803 obj->base.driver_private = NULL;
2804 obj->fence_reg = I915_FENCE_REG_NONE;
2805 INIT_LIST_HEAD(&obj->mm_list);
2806 INIT_LIST_HEAD(&obj->gtt_list);
2807 INIT_LIST_HEAD(&obj->ring_list);
2808 INIT_LIST_HEAD(&obj->exec_list);
2809 INIT_LIST_HEAD(&obj->gpu_write_list);
2810 obj->madv = I915_MADV_WILLNEED;
2811 /* Avoid an unnecessary call to unbind on the first bind. */
2812 obj->map_and_fenceable = true;
2814 i915_gem_info_add_obj(dev_priv, size);
2819 int i915_gem_init_object(struct drm_gem_object *obj)
2826 void i915_gem_free_object(struct drm_gem_object *gem_obj)
2828 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
2829 struct drm_device *dev = obj->base.dev;
2830 drm_i915_private_t *dev_priv = dev->dev_private;
2833 i915_gem_detach_phys_object(dev, obj);
2836 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
2837 bool was_interruptible;
2839 was_interruptible = dev_priv->mm.interruptible;
2840 dev_priv->mm.interruptible = false;
2842 WARN_ON(i915_gem_object_unbind(obj));
2844 dev_priv->mm.interruptible = was_interruptible;
2847 drm_gem_free_mmap_offset(&obj->base);
2849 drm_gem_object_release(&obj->base);
2850 i915_gem_info_remove_obj(dev_priv, obj->base.size);
2852 drm_free(obj->bit_17, DRM_I915_GEM);
2853 drm_free(obj, DRM_I915_GEM);
2857 i915_gem_do_init(struct drm_device *dev, unsigned long start,
2858 unsigned long mappable_end, unsigned long end)
2860 drm_i915_private_t *dev_priv;
2861 unsigned long mappable;
2864 dev_priv = dev->dev_private;
2865 mappable = min(end, mappable_end) - start;
2867 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
2869 dev_priv->mm.gtt_start = start;
2870 dev_priv->mm.gtt_mappable_end = mappable_end;
2871 dev_priv->mm.gtt_end = end;
2872 dev_priv->mm.gtt_total = end - start;
2873 dev_priv->mm.mappable_gtt_total = mappable;
2875 /* Take over this portion of the GTT */
2876 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
2877 device_printf(dev->dev,
2878 "taking over the fictitious range 0x%lx-0x%lx\n",
2879 dev->agp->base + start, dev->agp->base + start + mappable);
2880 error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
2881 dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
2886 i915_gem_idle(struct drm_device *dev)
2888 drm_i915_private_t *dev_priv = dev->dev_private;
2893 if (dev_priv->mm.suspended) {
2898 ret = i915_gpu_idle(dev);
2903 i915_gem_retire_requests(dev);
2905 /* Under UMS, be paranoid and evict. */
2906 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2907 i915_gem_evict_everything(dev);
2909 i915_gem_reset_fences(dev);
2911 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2912 * We need to replace this with a semaphore, or something.
2913 * And not confound mm.suspended!
2915 dev_priv->mm.suspended = 1;
2916 del_timer_sync(&dev_priv->hangcheck_timer);
2918 i915_kernel_lost_context(dev);
2919 i915_gem_cleanup_ringbuffer(dev);
2923 /* Cancel the retire work handler, which should be idle now. */
2924 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2929 void i915_gem_l3_remap(struct drm_device *dev)
2931 drm_i915_private_t *dev_priv = dev->dev_private;
2935 if (!HAS_L3_GPU_CACHE(dev))
2938 if (!dev_priv->l3_parity.remap_info)
2941 misccpctl = I915_READ(GEN7_MISCCPCTL);
2942 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
2943 POSTING_READ(GEN7_MISCCPCTL);
2945 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
2946 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
2947 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
2948 DRM_DEBUG("0x%x was already programmed to %x\n",
2949 GEN7_L3LOG_BASE + i, remap);
2950 if (remap && !dev_priv->l3_parity.remap_info[i/4])
2951 DRM_DEBUG_DRIVER("Clearing remapped register\n");
2952 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
2955 /* Make sure all the writes land before disabling dop clock gating */
2956 POSTING_READ(GEN7_L3LOG_BASE);
2958 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
2961 void i915_gem_init_swizzling(struct drm_device *dev)
2963 drm_i915_private_t *dev_priv = dev->dev_private;
2965 if (INTEL_INFO(dev)->gen < 5 ||
2966 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
2969 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
2970 DISP_TILE_SURFACE_SWIZZLING);
2975 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
2977 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
2979 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
2983 intel_enable_blt(struct drm_device *dev)
2990 /* The blitter was dysfunctional on early prototypes */
2991 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
2992 if (IS_GEN6(dev) && revision < 8) {
2993 DRM_INFO("BLT not supported on this pre-production hardware;"
2994 " graphics performance will be degraded.\n");
3002 i915_gem_init_hw(struct drm_device *dev)
3004 drm_i915_private_t *dev_priv = dev->dev_private;
3007 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3008 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3010 i915_gem_l3_remap(dev);
3012 i915_gem_init_swizzling(dev);
3014 ret = intel_init_render_ring_buffer(dev);
3019 ret = intel_init_bsd_ring_buffer(dev);
3021 goto cleanup_render_ring;
3024 if (intel_enable_blt(dev)) {
3025 ret = intel_init_blt_ring_buffer(dev);
3027 goto cleanup_bsd_ring;
3030 dev_priv->next_seqno = 1;
3033 * XXX: There was some w/a described somewhere suggesting loading
3034 * contexts before PPGTT.
3036 i915_gem_context_init(dev);
3037 i915_gem_init_ppgtt(dev);
3042 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3043 cleanup_render_ring:
3044 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3049 intel_enable_ppgtt(struct drm_device *dev)
3051 if (i915_enable_ppgtt >= 0)
3052 return i915_enable_ppgtt;
3054 /* Disable ppgtt on SNB if VT-d is on. */
3055 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
3061 int i915_gem_init(struct drm_device *dev)
3063 struct drm_i915_private *dev_priv = dev->dev_private;
3064 unsigned long prealloc_size, gtt_size, mappable_size;
3067 prealloc_size = dev_priv->mm.gtt->stolen_size;
3068 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3069 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3071 /* Basic memrange allocator for stolen space */
3072 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
3075 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3076 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3077 * aperture accordingly when using aliasing ppgtt. */
3078 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3079 /* For paranoia keep the guard page in between. */
3080 gtt_size -= PAGE_SIZE;
3082 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
3084 ret = i915_gem_init_aliasing_ppgtt(dev);
3090 /* Let GEM Manage all of the aperture.
3092 * However, leave one page at the end still bound to the scratch
3093 * page. There are a number of places where the hardware
3094 * apparently prefetches past the end of the object, and we've
3095 * seen multiple hangs with the GPU head pointer stuck in a
3096 * batchbuffer bound at the last page of the aperture. One page
3097 * should be enough to keep any prefetching inside of the
3100 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
3103 ret = i915_gem_init_hw(dev);
3106 i915_gem_cleanup_aliasing_ppgtt(dev);
3111 /* Try to set up FBC with a reasonable compressed buffer size */
3112 if (I915_HAS_FBC(dev) && i915_powersave) {
3115 /* Leave 1M for line length buffer & misc. */
3117 /* Try to get a 32M buffer... */
3118 if (prealloc_size > (36*1024*1024))
3119 cfb_size = 32*1024*1024;
3120 else /* fall back to 7/8 of the stolen space */
3121 cfb_size = prealloc_size * 7 / 8;
3122 i915_setup_compression(dev, cfb_size);
3126 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3127 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3128 dev_priv->dri1.allow_batchbuffer = 1;
3133 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3135 drm_i915_private_t *dev_priv = dev->dev_private;
3136 struct intel_ring_buffer *ring;
3139 for_each_ring(ring, dev_priv, i)
3140 intel_cleanup_ring_buffer(ring);
3144 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3145 struct drm_file *file_priv)
3147 drm_i915_private_t *dev_priv = dev->dev_private;
3150 if (drm_core_check_feature(dev, DRIVER_MODESET))
3153 if (atomic_read(&dev_priv->mm.wedged)) {
3154 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3155 atomic_set(&dev_priv->mm.wedged, 0);
3159 dev_priv->mm.suspended = 0;
3161 ret = i915_gem_init_hw(dev);
3167 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
3170 ret = drm_irq_install(dev);
3172 goto cleanup_ringbuffer;
3178 i915_gem_cleanup_ringbuffer(dev);
3179 dev_priv->mm.suspended = 1;
3186 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3187 struct drm_file *file_priv)
3189 if (drm_core_check_feature(dev, DRIVER_MODESET))
3192 drm_irq_uninstall(dev);
3193 return i915_gem_idle(dev);
3197 i915_gem_lastclose(struct drm_device *dev)
3201 if (drm_core_check_feature(dev, DRIVER_MODESET))
3204 ret = i915_gem_idle(dev);
3206 DRM_ERROR("failed to idle hardware: %d\n", ret);
3210 init_ring_lists(struct intel_ring_buffer *ring)
3212 INIT_LIST_HEAD(&ring->active_list);
3213 INIT_LIST_HEAD(&ring->request_list);
3214 INIT_LIST_HEAD(&ring->gpu_write_list);
3218 i915_gem_load(struct drm_device *dev)
3221 drm_i915_private_t *dev_priv = dev->dev_private;
3223 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3224 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3225 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3226 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3227 for (i = 0; i < I915_NUM_RINGS; i++)
3228 init_ring_lists(&dev_priv->ring[i]);
3229 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3230 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3231 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3232 i915_gem_retire_work_handler);
3233 init_completion(&dev_priv->error_completion);
3235 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3237 I915_WRITE(MI_ARB_STATE,
3238 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3241 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3243 /* Old X drivers will take 0-2 for front, back, depth buffers */
3244 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3245 dev_priv->fence_reg_start = 3;
3247 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3248 dev_priv->num_fence_regs = 16;
3250 dev_priv->num_fence_regs = 8;
3252 /* Initialize fence registers to zero */
3253 i915_gem_reset_fences(dev);
3255 i915_gem_detect_bit_6_swizzle(dev);
3256 init_waitqueue_head(&dev_priv->pending_flip_queue);
3258 dev_priv->mm.interruptible = true;
3261 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3262 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3263 register_shrinker(&dev_priv->mm.inactive_shrinker);
3265 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
3266 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
3271 * Create a physically contiguous memory object for this object
3272 * e.g. for cursor + overlay regs
3274 static int i915_gem_init_phys_object(struct drm_device *dev,
3275 int id, int size, int align)
3277 drm_i915_private_t *dev_priv = dev->dev_private;
3278 struct drm_i915_gem_phys_object *phys_obj;
3281 if (dev_priv->mm.phys_objs[id - 1] || !size)
3284 phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3291 phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3292 if (!phys_obj->handle) {
3296 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3297 size / PAGE_SIZE, PAT_WRITE_COMBINING);
3299 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3304 drm_free(phys_obj, DRM_I915_GEM);
3308 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3310 drm_i915_private_t *dev_priv = dev->dev_private;
3311 struct drm_i915_gem_phys_object *phys_obj;
3313 if (!dev_priv->mm.phys_objs[id - 1])
3316 phys_obj = dev_priv->mm.phys_objs[id - 1];
3317 if (phys_obj->cur_obj) {
3318 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3321 drm_pci_free(dev, phys_obj->handle);
3322 drm_free(phys_obj, DRM_I915_GEM);
3323 dev_priv->mm.phys_objs[id - 1] = NULL;
3326 void i915_gem_free_all_phys_object(struct drm_device *dev)
3330 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3331 i915_gem_free_phys_object(dev, i);
3334 void i915_gem_detach_phys_object(struct drm_device *dev,
3335 struct drm_i915_gem_object *obj)
3344 vaddr = obj->phys_obj->handle->vaddr;
3346 page_count = obj->base.size / PAGE_SIZE;
3347 VM_OBJECT_LOCK(obj->base.vm_obj);
3348 for (i = 0; i < page_count; i++) {
3349 m = i915_gem_wire_page(obj->base.vm_obj, i);
3353 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3354 sf = sf_buf_alloc(m);
3356 dst = (char *)sf_buf_kva(sf);
3357 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3360 drm_clflush_pages(&m, 1);
3362 VM_OBJECT_LOCK(obj->base.vm_obj);
3363 vm_page_reference(m);
3365 vm_page_busy_wait(m, FALSE, "i915gem");
3366 vm_page_unwire(m, 0);
3368 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3370 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3371 intel_gtt_chipset_flush();
3373 obj->phys_obj->cur_obj = NULL;
3374 obj->phys_obj = NULL;
3378 i915_gem_attach_phys_object(struct drm_device *dev,
3379 struct drm_i915_gem_object *obj,
3383 drm_i915_private_t *dev_priv = dev->dev_private;
3387 int i, page_count, ret;
3389 if (id > I915_MAX_PHYS_OBJECT)
3392 if (obj->phys_obj) {
3393 if (obj->phys_obj->id == id)
3395 i915_gem_detach_phys_object(dev, obj);
3398 /* create a new object */
3399 if (!dev_priv->mm.phys_objs[id - 1]) {
3400 ret = i915_gem_init_phys_object(dev, id,
3401 obj->base.size, align);
3403 DRM_ERROR("failed to init phys object %d size: %zu\n",
3404 id, obj->base.size);
3409 /* bind to the object */
3410 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3411 obj->phys_obj->cur_obj = obj;
3413 page_count = obj->base.size / PAGE_SIZE;
3415 VM_OBJECT_LOCK(obj->base.vm_obj);
3417 for (i = 0; i < page_count; i++) {
3418 m = i915_gem_wire_page(obj->base.vm_obj, i);
3423 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3424 sf = sf_buf_alloc(m);
3425 src = (char *)sf_buf_kva(sf);
3426 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3427 memcpy(dst, src, PAGE_SIZE);
3430 VM_OBJECT_LOCK(obj->base.vm_obj);
3432 vm_page_reference(m);
3433 vm_page_busy_wait(m, FALSE, "i915gem");
3434 vm_page_unwire(m, 0);
3436 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3438 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3444 i915_gem_phys_pwrite(struct drm_device *dev,
3445 struct drm_i915_gem_object *obj,
3449 struct drm_file *file_priv)
3451 char *user_data, *vaddr;
3454 vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3455 user_data = (char *)(uintptr_t)data_ptr;
3457 if (copyin_nofault(user_data, vaddr, size) != 0) {
3458 /* The physical object once assigned is fixed for the lifetime
3459 * of the obj, so we can safely drop the lock and continue
3463 ret = -copyin(user_data, vaddr, size);
3469 intel_gtt_chipset_flush();
3473 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
3475 struct drm_i915_file_private *file_priv = file->driver_priv;
3477 /* Clean up our request list when the client is going away, so that
3478 * later retire_requests won't dereference our soon-to-be-gone
3481 spin_lock(&file_priv->mm.lock);
3482 while (!list_empty(&file_priv->mm.request_list)) {
3483 struct drm_i915_gem_request *request;
3485 request = list_first_entry(&file_priv->mm.request_list,
3486 struct drm_i915_gem_request,
3488 list_del(&request->client_list);
3489 request->file_priv = NULL;
3491 spin_unlock(&file_priv->mm.lock);
3495 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
3496 uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
3497 struct drm_file *file)
3504 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
3506 if (obj->gtt_offset != 0 && rw == UIO_READ)
3507 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
3509 do_bit17_swizzling = 0;
3512 vm_obj = obj->base.vm_obj;
3515 VM_OBJECT_LOCK(vm_obj);
3516 vm_object_pip_add(vm_obj, 1);
3518 obj_pi = OFF_TO_IDX(offset);
3519 obj_po = offset & PAGE_MASK;
3521 m = i915_gem_wire_page(vm_obj, obj_pi);
3522 VM_OBJECT_UNLOCK(vm_obj);
3524 sf = sf_buf_alloc(m);
3525 mkva = sf_buf_kva(sf);
3526 length = min(size, PAGE_SIZE - obj_po);
3527 while (length > 0) {
3528 if (do_bit17_swizzling &&
3529 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
3530 cnt = roundup2(obj_po + 1, 64);
3531 cnt = min(cnt - obj_po, length);
3532 swizzled_po = obj_po ^ 64;
3535 swizzled_po = obj_po;
3538 ret = -copyout_nofault(
3539 (char *)mkva + swizzled_po,
3540 (void *)(uintptr_t)data_ptr, cnt);
3542 ret = -copyin_nofault(
3543 (void *)(uintptr_t)data_ptr,
3544 (char *)mkva + swizzled_po, cnt);
3554 VM_OBJECT_LOCK(vm_obj);
3555 if (rw == UIO_WRITE)
3557 vm_page_reference(m);
3558 vm_page_busy_wait(m, FALSE, "i915gem");
3559 vm_page_unwire(m, 1);
3561 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3566 vm_object_pip_wakeup(vm_obj);
3567 VM_OBJECT_UNLOCK(vm_obj);
3573 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
3574 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
3580 * Pass the unaligned physical address and size to pmap_mapdev_attr()
3581 * so it can properly calculate whether an extra page needs to be
3582 * mapped or not to cover the requested range. The function will
3583 * add the page offset into the returned mkva for us.
3585 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
3586 offset, size, PAT_WRITE_COMBINING);
3587 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
3588 pmap_unmapdev(mkva, size);
3593 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
3594 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
3596 struct drm_i915_gem_object *obj;
3598 vm_offset_t start, end;
3603 start = trunc_page(data_ptr);
3604 end = round_page(data_ptr + size);
3605 npages = howmany(end - start, PAGE_SIZE);
3606 ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
3608 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
3609 (vm_offset_t)data_ptr, size,
3610 (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
3616 ret = i915_mutex_lock_interruptible(dev);
3620 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
3621 if (&obj->base == NULL) {
3625 if (offset > obj->base.size || size > obj->base.size - offset) {
3630 if (rw == UIO_READ) {
3631 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3634 if (obj->phys_obj) {
3635 ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
3637 } else if (obj->gtt_space &&
3638 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
3639 ret = i915_gem_object_pin(obj, 0, true, false);
3642 ret = i915_gem_object_set_to_gtt_domain(obj, true);
3645 ret = i915_gem_object_put_fence(obj);
3648 ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
3651 i915_gem_object_unpin(obj);
3653 ret = i915_gem_object_set_to_cpu_domain(obj, true);
3656 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
3661 drm_gem_object_unreference(&obj->base);
3665 vm_page_unhold_pages(ma, npages);
3667 drm_free(ma, DRM_I915_GEM);
3672 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
3673 vm_ooffset_t foff, struct ucred *cred, u_short *color)
3676 *color = 0; /* XXXKIB */
3683 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
3686 struct drm_gem_object *gem_obj;
3687 struct drm_i915_gem_object *obj;
3688 struct drm_device *dev;
3689 drm_i915_private_t *dev_priv;
3694 gem_obj = vm_obj->handle;
3695 obj = to_intel_bo(gem_obj);
3696 dev = obj->base.dev;
3697 dev_priv = dev->dev_private;
3699 write = (prot & VM_PROT_WRITE) != 0;
3703 vm_object_pip_add(vm_obj, 1);
3706 * Remove the placeholder page inserted by vm_fault() from the
3707 * object before dropping the object lock. If
3708 * i915_gem_release_mmap() is active in parallel on this gem
3709 * object, then it owns the drm device sx and might find the
3710 * placeholder already. Then, since the page is busy,
3711 * i915_gem_release_mmap() sleeps waiting for the busy state
3712 * of the page cleared. We will be not able to acquire drm
3713 * device lock until i915_gem_release_mmap() is able to make a
3716 if (*mres != NULL) {
3718 vm_page_remove(oldm);
3723 VM_OBJECT_UNLOCK(vm_obj);
3729 ret = i915_mutex_lock_interruptible(dev);
3738 * Since the object lock was dropped, other thread might have
3739 * faulted on the same GTT address and instantiated the
3740 * mapping for the page. Recheck.
3742 VM_OBJECT_LOCK(vm_obj);
3743 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
3745 if ((m->flags & PG_BUSY) != 0) {
3748 vm_page_sleep(m, "915pee");
3754 VM_OBJECT_UNLOCK(vm_obj);
3756 /* Now bind it into the GTT if needed */
3757 if (!obj->map_and_fenceable) {
3758 ret = i915_gem_object_unbind(obj);
3764 if (!obj->gtt_space) {
3765 ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
3771 ret = i915_gem_object_set_to_gtt_domain(obj, write);
3778 if (obj->tiling_mode == I915_TILING_NONE)
3779 ret = i915_gem_object_put_fence(obj);
3781 ret = i915_gem_object_get_fence(obj);
3787 if (i915_gem_object_is_inactive(obj))
3788 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3790 obj->fault_mappable = true;
3791 VM_OBJECT_LOCK(vm_obj);
3792 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
3799 KASSERT((m->flags & PG_FICTITIOUS) != 0,
3800 ("not fictitious %p", m));
3801 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
3803 if ((m->flags & PG_BUSY) != 0) {
3806 vm_page_sleep(m, "915pbs");
3810 m->valid = VM_PAGE_BITS_ALL;
3811 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
3814 vm_page_busy_try(m, false);
3820 vm_object_pip_wakeup(vm_obj);
3821 return (VM_PAGER_OK);
3826 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
3827 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
3828 goto unlocked_vmobj;
3830 VM_OBJECT_LOCK(vm_obj);
3831 vm_object_pip_wakeup(vm_obj);
3832 return (VM_PAGER_ERROR);
3836 i915_gem_pager_dtor(void *handle)
3838 struct drm_gem_object *obj;
3839 struct drm_device *dev;
3845 drm_gem_free_mmap_offset(obj);
3846 i915_gem_release_mmap(to_intel_bo(obj));
3847 drm_gem_object_unreference(obj);
3851 struct cdev_pager_ops i915_gem_pager_ops = {
3852 .cdev_pg_fault = i915_gem_pager_fault,
3853 .cdev_pg_ctor = i915_gem_pager_ctor,
3854 .cdev_pg_dtor = i915_gem_pager_dtor
3857 #define GEM_PARANOID_CHECK_GTT 0
3858 #if GEM_PARANOID_CHECK_GTT
3860 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
3863 struct drm_i915_private *dev_priv;
3865 unsigned long start, end;
3869 dev_priv = dev->dev_private;
3870 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
3871 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
3872 for (i = start; i < end; i++) {
3873 pa = intel_gtt_read_pte_paddr(i);
3874 for (j = 0; j < page_count; j++) {
3875 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
3876 panic("Page %p in GTT pte index %d pte %x",
3877 ma[i], i, intel_gtt_read_pte(i));
3885 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
3886 uint32_t flush_domains)
3888 struct drm_i915_gem_object *obj, *next;
3889 uint32_t old_write_domain;
3891 list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
3893 if (obj->base.write_domain & flush_domains) {
3894 old_write_domain = obj->base.write_domain;
3895 obj->base.write_domain = 0;
3896 list_del_init(&obj->gpu_write_list);
3897 i915_gem_object_move_to_active(obj, ring);
3902 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
3905 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
3910 VM_OBJECT_LOCK_ASSERT_OWNED(object);
3911 m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
3912 if (m->valid != VM_PAGE_BITS_ALL) {
3913 if (vm_pager_has_page(object, pindex)) {
3914 rv = vm_pager_get_page(object, &m, 1);
3915 m = vm_page_lookup(object, pindex);
3918 if (rv != VM_PAGER_OK) {
3923 pmap_zero_page(VM_PAGE_TO_PHYS(m));
3924 m->valid = VM_PAGE_BITS_ALL;
3930 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
3935 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
3936 uint32_t flush_domains)
3940 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
3943 ret = ring->flush(ring, invalidate_domains, flush_domains);
3947 if (flush_domains & I915_GEM_GPU_DOMAINS)
3948 i915_gem_process_flushing_list(ring, flush_domains);
3953 i915_gpu_is_active(struct drm_device *dev)
3955 drm_i915_private_t *dev_priv = dev->dev_private;
3957 return !list_empty(&dev_priv->mm.active_list);
3961 i915_gem_lowmem(void *arg)
3963 struct drm_device *dev;
3964 struct drm_i915_private *dev_priv;
3965 struct drm_i915_gem_object *obj, *next;
3966 int cnt, cnt_fail, cnt_total;
3969 dev_priv = dev->dev_private;
3971 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3975 /* first scan for clean buffers */
3976 i915_gem_retire_requests(dev);
3978 cnt_total = cnt_fail = cnt = 0;
3980 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3982 if (i915_gem_object_is_purgeable(obj)) {
3983 if (i915_gem_object_unbind(obj) != 0)
3989 /* second pass, evict/count anything still on the inactive list */
3990 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3992 if (i915_gem_object_unbind(obj) == 0)
3998 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
4000 * We are desperate for pages, so as a last resort, wait
4001 * for the GPU to finish and discard whatever we can.
4002 * This has a dramatic impact to reduce the number of
4003 * OOM-killer events whilst running the GPU aggressively.
4005 if (i915_gpu_idle(dev) == 0)
4012 i915_gem_unload(struct drm_device *dev)
4014 struct drm_i915_private *dev_priv;
4016 dev_priv = dev->dev_private;
4017 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);