2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.18 2005/05/24 20:59:02 dillon Exp $
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
52 #include <net/ifq_var.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
60 #include <net/vlan/if_vlan_var.h>
62 #include <vm/vm.h> /* for vtophys */
63 #include <vm/pmap.h> /* for vtophys */
64 #include <machine/bus_memio.h>
65 #include <machine/bus_pio.h>
66 #include <machine/bus.h>
67 #include <machine/resource.h>
68 #include <machine/clock.h> /* for DELAY */
72 #include <bus/pci/pcireg.h>
73 #include <bus/pci/pcivar.h>
75 #include "../mii_layer/mii.h"
76 #include "../mii_layer/miivar.h"
77 #include "../mii_layer/miidevs.h"
78 #include "../mii_layer/lxtphyreg.h"
80 #include "miibus_if.h"
85 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
86 static void epic_intr(void *);
87 static void epic_tx_underrun(epic_softc_t *);
88 static int epic_common_attach(epic_softc_t *);
89 static void epic_ifstart(struct ifnet *);
90 static void epic_ifwatchdog(struct ifnet *);
91 static void epic_stats_update(void *);
92 static int epic_init(epic_softc_t *);
93 static void epic_stop(epic_softc_t *);
94 static void epic_rx_done(epic_softc_t *);
95 static void epic_tx_done(epic_softc_t *);
96 static int epic_init_rings(epic_softc_t *);
97 static void epic_free_rings(epic_softc_t *);
98 static void epic_stop_activity(epic_softc_t *);
99 static int epic_queue_last_packet(epic_softc_t *);
100 static void epic_start_activity(epic_softc_t *);
101 static void epic_set_rx_mode(epic_softc_t *);
102 static void epic_set_tx_mode(epic_softc_t *);
103 static void epic_set_mc_table(epic_softc_t *);
104 static u_int8_t epic_calchash(caddr_t);
105 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
106 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
107 static u_int16_t epic_input_eepromw(epic_softc_t *);
108 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
109 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
110 static u_int8_t epic_read_eepromreg(epic_softc_t *);
112 static int epic_read_phy_reg(epic_softc_t *, int, int);
113 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
115 static int epic_miibus_readreg(device_t, int, int);
116 static int epic_miibus_writereg(device_t, int, int, int);
117 static void epic_miibus_statchg(device_t);
118 static void epic_miibus_mediainit(device_t);
120 static int epic_ifmedia_upd(struct ifnet *);
121 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
123 static int epic_probe(device_t);
124 static int epic_attach(device_t);
125 static void epic_shutdown(device_t);
126 static int epic_detach(device_t);
127 static struct epic_type *epic_devtype(device_t);
129 static device_method_t epic_methods[] = {
130 /* Device interface */
131 DEVMETHOD(device_probe, epic_probe),
132 DEVMETHOD(device_attach, epic_attach),
133 DEVMETHOD(device_detach, epic_detach),
134 DEVMETHOD(device_shutdown, epic_shutdown),
137 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
138 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
139 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
140 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
145 static driver_t epic_driver = {
151 static devclass_t epic_devclass;
153 DECLARE_DUMMY_MODULE(if_tx);
154 MODULE_DEPEND(if_tx, miibus, 1, 1, 1);
155 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
156 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
158 static struct epic_type epic_devs[] = {
159 { SMC_VENDORID, SMC_DEVICEID_83C170,
160 "SMC EtherPower II 10/100" },
170 t = epic_devtype(dev);
173 device_set_desc(dev, t->name);
180 static struct epic_type *
188 while(t->name != NULL) {
189 if ((pci_get_vendor(dev) == t->ven_id) &&
190 (pci_get_device(dev) == t->dev_id)) {
198 #if defined(EPIC_USEIOSPACE)
199 #define EPIC_RES SYS_RES_IOPORT
200 #define EPIC_RID PCIR_BASEIO
202 #define EPIC_RES SYS_RES_MEMORY
203 #define EPIC_RID PCIR_BASEMEM
207 * Attach routine: map registers, allocate softc, rings and descriptors.
208 * Reset to known state.
222 sc = device_get_softc(dev);
223 unit = device_get_unit(dev);
225 /* Preinitialize softc structure */
226 bzero(sc, sizeof(epic_softc_t));
229 callout_init(&sc->tx_stat_timer);
231 /* Fill ifnet structure */
233 if_initname(ifp, "tx", unit);
235 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
236 ifp->if_ioctl = epic_ifioctl;
237 ifp->if_start = epic_ifstart;
238 ifp->if_watchdog = epic_ifwatchdog;
239 ifp->if_init = (if_init_f_t*)epic_init;
241 ifp->if_baudrate = 10000000;
242 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
243 ifq_set_ready(&ifp->if_snd);
245 /* Enable ports, memory and busmastering */
246 command = pci_read_config(dev, PCIR_COMMAND, 4);
247 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
248 pci_write_config(dev, PCIR_COMMAND, command, 4);
249 command = pci_read_config(dev, PCIR_COMMAND, 4);
251 #if defined(EPIC_USEIOSPACE)
252 if ((command & PCIM_CMD_PORTEN) == 0) {
253 device_printf(dev, "failed to enable I/O mapping!\n");
258 if ((command & PCIM_CMD_MEMEN) == 0) {
259 device_printf(dev, "failed to enable memory mapping!\n");
266 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
268 if (sc->res == NULL) {
269 device_printf(dev, "couldn't map ports/memory\n");
274 sc->sc_st = rman_get_bustag(sc->res);
275 sc->sc_sh = rman_get_bushandle(sc->res);
277 /* Allocate interrupt */
279 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
280 RF_SHAREABLE | RF_ACTIVE);
282 if (sc->irq == NULL) {
283 device_printf(dev, "couldn't map interrupt\n");
284 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
289 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
290 epic_intr, sc, &sc->sc_ih, NULL);
293 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
294 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
295 device_printf(dev, "couldn't set up irq\n");
299 /* Do OS independent part, including chip wakeup and reset */
300 error = epic_common_attach(sc);
302 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
303 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
304 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
309 /* Do ifmedia setup */
310 if (mii_phy_probe(dev, &sc->miibus,
311 epic_ifmedia_upd, epic_ifmedia_sts)) {
312 device_printf(dev, "ERROR! MII without any PHY!?\n");
313 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
314 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
315 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
320 /* board type and ... */
322 for(i=0x2c;i<0x32;i++) {
323 tmp = epic_read_eeprom(sc, i);
324 if (' ' == (u_int8_t)tmp) break;
325 printf("%c", (u_int8_t)tmp);
327 if (' ' == (u_int8_t)tmp) break;
328 printf("%c", (u_int8_t)tmp);
332 /* Attach to OS's managers */
333 ether_ifattach(ifp, sc->sc_macaddr);
334 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
343 * Detach driver and free resources
355 sc = device_get_softc(dev);
356 ifp = &sc->arpcom.ac_if;
362 bus_generic_detach(dev);
363 device_delete_child(dev, sc->miibus);
365 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
366 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
367 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
369 free(sc->tx_flist, M_DEVBUF);
370 free(sc->tx_desc, M_DEVBUF);
371 free(sc->rx_desc, M_DEVBUF);
382 * Stop all chip I/O so that the kernel's probe routines don't
383 * get confused by errant DMAs when rebooting.
391 sc = device_get_softc(dev);
399 * This is if_ioctl handler.
402 epic_ifioctl(ifp, command, data, cr)
408 epic_softc_t *sc = ifp->if_softc;
409 struct mii_data *mii;
410 struct ifreq *ifr = (struct ifreq *) data;
418 error = ether_ioctl(ifp, command, data);
421 if (ifp->if_mtu == ifr->ifr_mtu)
424 /* XXX Though the datasheet doesn't imply any
425 * limitations on RX and TX sizes beside max 64Kb
426 * DMA transfer, seems we can't send more then 1600
427 * data bytes per ethernet packet. (Transmitter hangs
428 * up if more data is sent)
430 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
431 ifp->if_mtu = ifr->ifr_mtu;
440 * If the interface is marked up and stopped, then start it.
441 * If it is marked down and running, then stop it.
443 if (ifp->if_flags & IFF_UP) {
444 if ((ifp->if_flags & IFF_RUNNING) == 0) {
449 if (ifp->if_flags & IFF_RUNNING) {
455 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
456 epic_stop_activity(sc);
457 epic_set_mc_table(sc);
458 epic_set_rx_mode(sc);
459 epic_start_activity(sc);
464 epic_set_mc_table(sc);
470 mii = device_get_softc(sc->miibus);
471 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
483 * OS-independed part of attach process. allocate memory for descriptors
484 * and frag lists, wake up chip, read MAC address and PHY identyfier.
485 * Return -1 on failure.
488 epic_common_attach(sc)
493 sc->tx_flist = malloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
494 M_DEVBUF, M_WAITOK | M_ZERO);
495 sc->tx_desc = malloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
496 M_DEVBUF, M_WAITOK | M_ZERO);
497 sc->rx_desc = malloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
498 M_DEVBUF, M_WAITOK | M_ZERO);
500 /* Bring the chip out of low-power mode. */
501 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
504 /* Workaround for Application Note 7-15 */
505 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
507 /* Read mac address from EEPROM */
508 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
509 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
511 /* Set Non-Volatile Control Register from EEPROM */
512 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
515 sc->tx_threshold = TRANSMIT_THRESHOLD;
516 sc->txcon = TXCON_DEFAULT;
517 sc->miicfg = MIICFG_SMI_ENABLE;
518 sc->phyid = EPIC_UNKN_PHY;
522 sc->cardvend = pci_read_config(sc->dev, PCIR_SUBVEND_0, 2);
523 sc->cardid = pci_read_config(sc->dev, PCIR_SUBDEV_0, 2);
525 if (sc->cardvend != SMC_VENDORID)
526 device_printf(sc->dev, "unknown card vendor %04xh\n", sc->cardvend);
532 * This is if_start handler. It takes mbufs from if_snd queue
533 * and queue them for transmit, one by one, until TX ring become full
534 * or queue become empty.
540 epic_softc_t *sc = ifp->if_softc;
541 struct epic_tx_buffer *buf;
542 struct epic_tx_desc *desc;
543 struct epic_frag_list *flist;
548 while (sc->pending_txs < TX_RING_SIZE) {
549 buf = sc->tx_buffer + sc->cur_tx;
550 desc = sc->tx_desc + sc->cur_tx;
551 flist = sc->tx_flist + sc->cur_tx;
553 /* Get next packet to send */
554 m0 = ifq_dequeue(&ifp->if_snd);
556 /* If nothing to send, return */
560 /* Fill fragments list */
562 (NULL != m) && (i < EPIC_MAX_FRAGS);
563 m = m->m_next, i++) {
564 flist->frag[i].fraglen = m->m_len;
565 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
569 /* If packet was more than EPIC_MAX_FRAGS parts, */
570 /* recopy packet to new allocated mbuf cluster */
579 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
580 flist->frag[0].fraglen =
581 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
582 m->m_pkthdr.rcvif = ifp;
585 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
592 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
593 desc->control = 0x01;
595 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
596 desc->status = 0x8000;
597 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
599 /* Set watchdog timer */
605 ifp->if_flags |= IFF_OACTIVE;
612 * Synopsis: Finish all received frames.
619 struct ifnet *ifp = &sc->sc_if;
620 struct epic_rx_buffer *buf;
621 struct epic_rx_desc *desc;
624 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
625 buf = sc->rx_buffer + sc->cur_rx;
626 desc = sc->rx_desc + sc->cur_rx;
628 /* Switch to next descriptor */
629 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
632 * Check for RX errors. This should only happen if
633 * SAVE_ERRORED_PACKETS is set. RX errors generate
634 * RXE interrupt usually.
636 if ((desc->status & 1) == 0) {
637 sc->sc_if.if_ierrors++;
638 desc->status = 0x8000;
642 /* Save packet length and mbuf contained packet */
643 len = desc->rxlength - ETHER_CRC_LEN;
646 /* Try to get mbuf cluster */
647 EPIC_MGETCLUSTER(buf->mbuf);
648 if (NULL == buf->mbuf) {
650 desc->status = 0x8000;
655 /* Point to new mbuf, and give descriptor to chip */
656 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
657 desc->status = 0x8000;
659 /* First mbuf in packet holds the ethernet and packet headers */
660 m->m_pkthdr.rcvif = ifp;
661 m->m_pkthdr.len = m->m_len = len;
663 /* Give mbuf to OS */
664 (*ifp->if_input)(ifp, m);
666 /* Successfuly received frame */
674 * Synopsis: Do last phase of transmission. I.e. if desc is
675 * transmitted, decrease pending_txs counter, free mbuf contained
676 * packet, switch to next descriptor and repeat until no packets
677 * are pending or descriptor is not transmitted yet.
683 struct epic_tx_buffer *buf;
684 struct epic_tx_desc *desc;
687 while (sc->pending_txs > 0) {
688 buf = sc->tx_buffer + sc->dirty_tx;
689 desc = sc->tx_desc + sc->dirty_tx;
690 status = desc->status;
692 /* If packet is not transmitted, thou followed */
693 /* packets are not transmitted too */
694 if (status & 0x8000) break;
696 /* Packet is transmitted. Switch to next and */
699 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
703 /* Check for errors and collisions */
704 if (status & 0x0001) sc->sc_if.if_opackets++;
705 else sc->sc_if.if_oerrors++;
706 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
707 #if defined(EPIC_DIAG)
708 if ((status & 0x1001) == 0x1001)
709 device_printf(sc->dev, "Tx ERROR: excessive coll. number\n");
713 if (sc->pending_txs < TX_RING_SIZE)
714 sc->sc_if.if_flags &= ~IFF_OACTIVE;
724 epic_softc_t * sc = (epic_softc_t *) arg;
727 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
728 CSR_WRITE_4(sc, INTSTAT, status);
730 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
732 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
733 #if defined(EPIC_DIAG)
734 if (status & INTSTAT_OVW)
735 device_printf(sc->dev, "RX buffer overflow\n");
736 if (status & INTSTAT_RQE)
737 device_printf(sc->dev, "RX FIFO overflow\n");
739 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
740 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
741 sc->sc_if.if_ierrors++;
745 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
747 if (!ifq_is_empty(&sc->sc_if.if_snd))
748 epic_ifstart(&sc->sc_if);
751 /* Check for rare errors */
752 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
753 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
754 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
755 INTSTAT_APE|INTSTAT_DPE)) {
756 device_printf(sc->dev, "PCI fatal errors occured: %s%s%s%s\n",
757 (status&INTSTAT_PMA)?"PMA ":"",
758 (status&INTSTAT_PTA)?"PTA ":"",
759 (status&INTSTAT_APE)?"APE ":"",
760 (status&INTSTAT_DPE)?"DPE":""
769 if (status & INTSTAT_RXE) {
770 #if defined(EPIC_DIAG)
771 device_printf(sc->dev, "CRC/Alignment error\n");
773 sc->sc_if.if_ierrors++;
776 if (status & INTSTAT_TXU) {
777 epic_tx_underrun(sc);
778 sc->sc_if.if_oerrors++;
783 /* If no packets are pending, then no timeouts */
784 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
790 * Handle the TX underrun error: increase the TX threshold
791 * and restart the transmitter.
797 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
798 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
799 #if defined(EPIC_DIAG)
800 device_printf(sc->dev, "Tx UNDERRUN: early TX disabled\n");
803 sc->tx_threshold += 0x40;
804 #if defined(EPIC_DIAG)
805 device_printf(sc->dev, "Tx UNDERRUN: TX threshold increased to %d\n",
810 /* We must set TXUGO to reset the stuck transmitter */
811 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
813 /* Update the TX threshold */
814 epic_stop_activity(sc);
815 epic_set_tx_mode(sc);
816 epic_start_activity(sc);
822 * Synopsis: This one is called if packets wasn't transmitted
823 * during timeout. Try to deallocate transmitted packets, and
824 * if success continue to work.
830 epic_softc_t *sc = ifp->if_softc;
835 device_printf(sc->dev, "device timeout %d packets\n", sc->pending_txs);
837 /* Try to finish queued packets */
840 /* If not successful */
841 if (sc->pending_txs > 0) {
843 ifp->if_oerrors+=sc->pending_txs;
845 /* Reinitialize board */
846 device_printf(sc->dev, "reinitialization\n");
851 device_printf(sc->dev, "seems we can continue normaly\n");
854 if (!ifq_is_empty(&ifp->if_snd))
861 * Despite the name of this function, it doesn't update statistics, it only
862 * helps in autonegotiation process.
865 epic_stats_update(void *xsc)
867 epic_softc_t *sc = xsc;
868 struct mii_data * mii;
873 mii = device_get_softc(sc->miibus);
876 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
885 epic_ifmedia_upd(ifp)
889 struct mii_data *mii;
891 struct mii_softc *miisc;
895 mii = device_get_softc(sc->miibus);
896 ifm = &mii->mii_media;
897 media = ifm->ifm_cur->ifm_media;
899 /* Do not do anything if interface is not up */
900 if ((ifp->if_flags & IFF_UP) == 0)
904 * Lookup current selected PHY
906 if (IFM_INST(media) == sc->serinst) {
907 sc->phyid = EPIC_SERIAL;
910 /* If we're not selecting serial interface, select MII mode */
911 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
912 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
914 /* Default to unknown PHY */
915 sc->phyid = EPIC_UNKN_PHY;
917 /* Lookup selected PHY */
918 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
919 miisc = LIST_NEXT(miisc, mii_list)) {
920 if (IFM_INST(media) == miisc->mii_inst) {
926 /* Identify selected PHY */
928 int id1, id2, model, oui;
930 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
931 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
933 oui = MII_OUI(id1, id2);
934 model = MII_MODEL(id2);
936 case MII_OUI_QUALSEMI:
937 if (model == MII_MODEL_QUALSEMI_QS6612)
938 sc->phyid = EPIC_QS6612_PHY;
940 case MII_OUI_xxALTIMA:
941 if (model == MII_MODEL_xxALTIMA_AC101)
942 sc->phyid = EPIC_AC101_PHY;
944 case MII_OUI_xxLEVEL1:
945 if (model == MII_MODEL_xxLEVEL1_LXT970)
946 sc->phyid = EPIC_LXT970_PHY;
953 * Do PHY specific card setup
956 /* Call this, to isolate all not selected PHYs and
961 /* Do our own setup */
963 case EPIC_QS6612_PHY:
966 /* We have to powerup fiber tranceivers */
967 if (IFM_SUBTYPE(media) == IFM_100_FX)
968 sc->miicfg |= MIICFG_694_ENABLE;
970 sc->miicfg &= ~MIICFG_694_ENABLE;
971 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
974 case EPIC_LXT970_PHY:
975 /* We have to powerup fiber tranceivers */
976 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
977 if (IFM_SUBTYPE(media) == IFM_100_FX)
978 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
980 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
981 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
985 /* Select serial PHY, (10base2/BNC usually) */
986 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
987 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
989 /* There is no driver to fill this */
990 mii->mii_media_active = media;
991 mii->mii_media_status = 0;
993 /* We need to call this manualy as i wasn't called
996 epic_miibus_statchg(sc->dev);
1000 device_printf(sc->dev, "ERROR! Unknown PHY selected\n");
1008 * Report current media status.
1011 epic_ifmedia_sts(ifp, ifmr)
1013 struct ifmediareq *ifmr;
1016 struct mii_data *mii;
1017 struct ifmedia *ifm;
1020 mii = device_get_softc(sc->miibus);
1021 ifm = &mii->mii_media;
1023 /* Nothing should be selected if interface is down */
1024 if ((ifp->if_flags & IFF_UP) == 0) {
1025 ifmr->ifm_active = IFM_NONE;
1026 ifmr->ifm_status = 0;
1031 /* Call underlying pollstat, if not serial PHY */
1032 if (sc->phyid != EPIC_SERIAL)
1035 /* Simply copy media info */
1036 ifmr->ifm_active = mii->mii_media_active;
1037 ifmr->ifm_status = mii->mii_media_status;
1043 * Callback routine, called on media change.
1046 epic_miibus_statchg(dev)
1050 struct mii_data *mii;
1053 sc = device_get_softc(dev);
1054 mii = device_get_softc(sc->miibus);
1055 media = mii->mii_media_active;
1057 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1059 /* If we are in full-duplex mode or loopback operation,
1060 * we need to decouple receiver and transmitter.
1062 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1063 sc->txcon |= TXCON_FULL_DUPLEX;
1065 /* On some cards we need manualy set fullduplex led */
1066 if (sc->cardid == SMC9432FTX ||
1067 sc->cardid == SMC9432FTX_SC) {
1068 if (IFM_OPTIONS(media) & IFM_FDX)
1069 sc->miicfg |= MIICFG_694_ENABLE;
1071 sc->miicfg &= ~MIICFG_694_ENABLE;
1073 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1076 /* Update baudrate */
1077 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1078 IFM_SUBTYPE(media) == IFM_100_FX)
1079 sc->sc_if.if_baudrate = 100000000;
1081 sc->sc_if.if_baudrate = 10000000;
1083 epic_stop_activity(sc);
1084 epic_set_tx_mode(sc);
1085 epic_start_activity(sc);
1091 epic_miibus_mediainit(dev)
1095 struct mii_data *mii;
1096 struct ifmedia *ifm;
1099 sc = device_get_softc(dev);
1100 mii = device_get_softc(sc->miibus);
1101 ifm = &mii->mii_media;
1103 /* Add Serial Media Interface if present, this applies to
1106 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1107 /* Store its instance */
1108 sc->serinst = mii->mii_instance++;
1110 /* Add as 10base2/BNC media */
1111 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1112 ifmedia_add(ifm, media, 0, NULL);
1114 /* Report to user */
1115 device_printf(sc->dev, "serial PHY detected (10Base2/BNC)\n");
1122 * Reset chip, allocate rings, and update media.
1128 struct ifnet *ifp = &sc->sc_if;
1133 /* If interface is already running, then we need not do anything */
1134 if (ifp->if_flags & IFF_RUNNING) {
1139 /* Soft reset the chip (we have to power up card before) */
1140 CSR_WRITE_4(sc, GENCTL, 0);
1141 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1144 * Reset takes 15 pci ticks which depends on PCI bus speed.
1145 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1150 CSR_WRITE_4(sc, GENCTL, 0);
1152 /* Workaround for Application Note 7-15 */
1153 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1155 /* Initialize rings */
1156 if (epic_init_rings(sc)) {
1157 device_printf(sc->dev, "failed to init rings\n");
1162 /* Give rings to EPIC */
1163 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1164 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1166 /* Put node address to EPIC */
1167 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1168 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1169 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1171 /* Set tx mode, includeing transmit threshold */
1172 epic_set_tx_mode(sc);
1174 /* Compute and set RXCON. */
1175 epic_set_rx_mode(sc);
1177 /* Set multicast table */
1178 epic_set_mc_table(sc);
1180 /* Enable interrupts by setting the interrupt mask. */
1181 CSR_WRITE_4(sc, INTMASK,
1182 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1183 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1186 /* Acknowledge all pending interrupts */
1187 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1189 /* Enable interrupts, set for PCI read multiple and etc */
1190 CSR_WRITE_4(sc, GENCTL,
1191 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1192 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1194 /* Mark interface running ... */
1195 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1196 else ifp->if_flags &= ~IFF_RUNNING;
1199 ifp->if_flags &= ~IFF_OACTIVE;
1201 /* Start Rx process */
1202 epic_start_activity(sc);
1204 /* Set appropriate media */
1205 epic_ifmedia_upd(ifp);
1207 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
1215 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1219 epic_set_rx_mode(sc)
1222 u_int32_t flags = sc->sc_if.if_flags;
1223 u_int32_t rxcon = RXCON_DEFAULT;
1225 #if defined(EPIC_EARLY_RX)
1226 rxcon |= RXCON_EARLY_RX;
1229 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1231 CSR_WRITE_4(sc, RXCON, rxcon);
1237 * Synopsis: Set transmit control register. Chip must be in idle state to
1241 epic_set_tx_mode(sc)
1244 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1245 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1247 CSR_WRITE_4(sc, TXCON, sc->txcon);
1251 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1252 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1253 * individual frames, multicast filter must be manually programmed)
1255 * Note: EPIC must be in idle state.
1258 epic_set_mc_table(sc)
1261 struct ifnet *ifp = &sc->sc_if;
1262 struct ifmultiaddr *ifma;
1263 u_int16_t filter[4];
1266 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1267 CSR_WRITE_4(sc, MC0, 0xFFFF);
1268 CSR_WRITE_4(sc, MC1, 0xFFFF);
1269 CSR_WRITE_4(sc, MC2, 0xFFFF);
1270 CSR_WRITE_4(sc, MC3, 0xFFFF);
1280 #if defined(__DragonFly__) || __FreeBSD_version < 500000
1281 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1283 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1285 if (ifma->ifma_addr->sa_family != AF_LINK)
1287 h = epic_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1288 filter[h >> 4] |= 1 << (h & 0xF);
1291 CSR_WRITE_4(sc, MC0, filter[0]);
1292 CSR_WRITE_4(sc, MC1, filter[1]);
1293 CSR_WRITE_4(sc, MC2, filter[2]);
1294 CSR_WRITE_4(sc, MC3, filter[3]);
1300 * Synopsis: calculate EPIC's hash of multicast address.
1306 u_int32_t crc, carry;
1310 /* Compute CRC for the address value. */
1311 crc = 0xFFFFFFFF; /* initial value */
1313 for (i = 0; i < 6; i++) {
1315 for (j = 0; j < 8; j++) {
1316 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1320 crc = (crc ^ 0x04c11db6) | carry;
1324 return ((crc >> 26) & 0x3F);
1329 * Synopsis: Start receive process and transmit one, if they need.
1332 epic_start_activity(sc)
1335 /* Start rx process */
1336 CSR_WRITE_4(sc, COMMAND,
1337 COMMAND_RXQUEUED | COMMAND_START_RX |
1338 (sc->pending_txs?COMMAND_TXQUEUED:0));
1342 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1343 * packet needs to be queued to stop Tx DMA.
1346 epic_stop_activity(sc)
1351 /* Stop Tx and Rx DMA */
1352 CSR_WRITE_4(sc, COMMAND,
1353 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1355 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1356 for (i=0; i<0x1000; i++) {
1357 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1358 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1363 /* Catch all finished packets */
1367 status = CSR_READ_4(sc, INTSTAT);
1369 if ((status & INTSTAT_RXIDLE) == 0)
1370 device_printf(sc->dev, "ERROR! Can't stop Rx DMA\n");
1372 if ((status & INTSTAT_TXIDLE) == 0)
1373 device_printf(sc->dev, "ERROR! Can't stop Tx DMA\n");
1376 * May need to queue one more packet if TQE, this is rare
1377 * but existing case.
1379 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1380 (void) epic_queue_last_packet(sc);
1385 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1386 * a packet from current descriptor will be copied to internal RAM. We
1387 * compose a dummy packet here and queue it for transmission.
1389 * XXX the packet will then be actually sent over network...
1392 epic_queue_last_packet(sc)
1395 struct epic_tx_desc *desc;
1396 struct epic_frag_list *flist;
1397 struct epic_tx_buffer *buf;
1401 device_printf(sc->dev, "queue last packet\n");
1403 desc = sc->tx_desc + sc->cur_tx;
1404 flist = sc->tx_flist + sc->cur_tx;
1405 buf = sc->tx_buffer + sc->cur_tx;
1407 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1410 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
1415 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1416 flist->frag[0].fraglen = m0->m_len;
1417 m0->m_pkthdr.len = m0->m_len;
1418 m0->m_pkthdr.rcvif = &sc->sc_if;
1419 bzero(mtod(m0,caddr_t), m0->m_len);
1421 /* Fill fragments list */
1422 flist->frag[0].fraglen = m0->m_len;
1423 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1424 flist->numfrags = 1;
1426 /* Fill in descriptor */
1429 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1430 desc->control = 0x01;
1431 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1432 desc->status = 0x8000;
1434 /* Launch transmition */
1435 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1437 /* Wait Tx DMA to stop (for how long??? XXX) */
1438 for (i=0; i<1000; i++) {
1439 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1444 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1445 device_printf(sc->dev, "ERROR! can't stop Tx DMA (2)\n");
1453 * Synopsis: Shut down board and deallocates rings.
1463 sc->sc_if.if_timer = 0;
1465 callout_stop(&sc->tx_stat_timer);
1467 /* Disable interrupts */
1468 CSR_WRITE_4(sc, INTMASK, 0);
1469 CSR_WRITE_4(sc, GENCTL, 0);
1471 /* Try to stop Rx and TX processes */
1472 epic_stop_activity(sc);
1475 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1478 /* Make chip go to bed */
1479 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1481 /* Free memory allocated for rings */
1482 epic_free_rings(sc);
1484 /* Mark as stoped */
1485 sc->sc_if.if_flags &= ~IFF_RUNNING;
1492 * Synopsis: This function should free all memory allocated for rings.
1500 for (i=0; i<RX_RING_SIZE; i++) {
1501 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1502 struct epic_rx_desc *desc = sc->rx_desc + i;
1505 desc->buflength = 0;
1508 if (buf->mbuf) m_freem(buf->mbuf);
1512 for (i=0; i<TX_RING_SIZE; i++) {
1513 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1514 struct epic_tx_desc *desc = sc->tx_desc + i;
1517 desc->buflength = 0;
1520 if (buf->mbuf) m_freem(buf->mbuf);
1526 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1527 * Point Tx descs to fragment lists. Check that all descs and fraglists
1528 * are bounded and aligned properly.
1536 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1538 for (i = 0; i < RX_RING_SIZE; i++) {
1539 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1540 struct epic_rx_desc *desc = sc->rx_desc + i;
1542 desc->status = 0; /* Owned by driver */
1543 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1545 if ((desc->next & 3) ||
1546 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1547 epic_free_rings(sc);
1551 EPIC_MGETCLUSTER(buf->mbuf);
1552 if (NULL == buf->mbuf) {
1553 epic_free_rings(sc);
1556 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1558 desc->buflength = MCLBYTES; /* Max RX buffer length */
1559 desc->status = 0x8000; /* Set owner bit to NIC */
1562 for (i = 0; i < TX_RING_SIZE; i++) {
1563 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1564 struct epic_tx_desc *desc = sc->tx_desc + i;
1567 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1569 if ((desc->next & 3) ||
1570 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1571 epic_free_rings(sc);
1576 desc->bufaddr = vtophys(sc->tx_flist + i);
1578 if ((desc->bufaddr & 3) ||
1579 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1580 epic_free_rings(sc);
1589 * EEPROM operation functions
1592 epic_write_eepromreg(sc, val)
1598 CSR_WRITE_1(sc, EECTL, val);
1600 for (i=0; i<0xFF; i++)
1601 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1607 epic_read_eepromreg(sc)
1610 return CSR_READ_1(sc, EECTL);
1614 epic_eeprom_clock(sc, val)
1618 epic_write_eepromreg(sc, val);
1619 epic_write_eepromreg(sc, (val | 0x4));
1620 epic_write_eepromreg(sc, val);
1622 return epic_read_eepromreg(sc);
1626 epic_output_eepromw(sc, val)
1632 for (i = 0xF; i >= 0; i--) {
1634 epic_eeprom_clock(sc, 0x0B);
1636 epic_eeprom_clock(sc, 0x03);
1641 epic_input_eepromw(sc)
1644 u_int16_t retval = 0;
1647 for (i = 0xF; i >= 0; i--) {
1648 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1656 epic_read_eeprom(sc, loc)
1663 epic_write_eepromreg(sc, 3);
1665 if (epic_read_eepromreg(sc) & 0x40)
1666 read_cmd = (loc & 0x3F) | 0x180;
1668 read_cmd = (loc & 0xFF) | 0x600;
1670 epic_output_eepromw(sc, read_cmd);
1672 dataval = epic_input_eepromw(sc);
1674 epic_write_eepromreg(sc, 1);
1680 * Here goes MII read/write routines
1683 epic_read_phy_reg(sc, phy, reg)
1689 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1691 for (i = 0; i < 0x100; i++) {
1692 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1696 return (CSR_READ_4(sc, MIIDATA));
1700 epic_write_phy_reg(sc, phy, reg, val)
1706 CSR_WRITE_4(sc, MIIDATA, val);
1707 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1709 for(i=0;i<0x100;i++) {
1710 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1718 epic_miibus_readreg(dev, phy, reg)
1724 sc = device_get_softc(dev);
1726 return (PHY_READ_2(sc, phy, reg));
1730 epic_miibus_writereg(dev, phy, reg, data)
1736 sc = device_get_softc(dev);
1738 PHY_WRITE_2(sc, phy, reg, data);