sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35 #include <linux/workqueue.h>
  36
  37 extern struct drm_i915_private *i915_mch_dev;
  38
  39 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  40 {
  41         /*
  42          * The dri breadcrumb update races against the drm master disappearing.
  43          * Instead of trying to fix this (this is by far not the only ums issue)
  44          * just don't do the update in kms mode.
  45          */
  46         if (drm_core_check_feature(dev, DRIVER_MODESET))
  47                 return;
  48
  49         /* XXX: don't do it at all actually */
  50         return;
  51 }
  52
  53 static void i915_write_hws_pga(struct drm_device *dev)
  54 {
  55         drm_i915_private_t *dev_priv = dev->dev_private;
  56         u32 addr;
  57
  58         addr = dev_priv->status_page_dmah->busaddr;
  59         if (INTEL_INFO(dev)->gen >= 4)
  60                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  61         I915_WRITE(HWS_PGA, addr);
  62 }
  63
  64 /**
  65  * Sets up the hardware status page for devices that need a physical address
  66  * in the register.
  67  */
  68 static int i915_init_phys_hws(struct drm_device *dev)
  69 {
  70         drm_i915_private_t *dev_priv = dev->dev_private;
  71         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  72
  73         /*
  74          * Program Hardware Status Page
  75          * XXXKIB Keep 4GB limit for allocation for now.  This method
  76          * of allocation is used on <= 965 hardware, that has several
  77          * erratas regarding the use of physical memory > 4 GB.
  78          */
  79         DRM_UNLOCK(dev);
  80         dev_priv->status_page_dmah =
  81                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  82         DRM_LOCK(dev);
  83         if (!dev_priv->status_page_dmah) {
  84                 DRM_ERROR("Can not allocate hardware status page\n");
  85                 return -ENOMEM;
  86         }
  87         ring->status_page.page_addr = dev_priv->hw_status_page =
  88             dev_priv->status_page_dmah->vaddr;
  89         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  90
  91         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  92
  93         i915_write_hws_pga(dev);
  94         DRM_DEBUG("Enabled hardware status page, phys %jx\n",
  95             (uintmax_t)dev_priv->dma_status_page);
  96         return 0;
  97 }
  98
  99 /**
 100  * Frees the hardware status page, whether it's a physical address or a virtual
 101  * address set up by the X Server.
 102  */
 103 static void i915_free_hws(struct drm_device *dev)
 104 {
 105         drm_i915_private_t *dev_priv = dev->dev_private;
 106         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 107
 108         if (dev_priv->status_page_dmah) {
 109                 drm_pci_free(dev, dev_priv->status_page_dmah);
 110                 dev_priv->status_page_dmah = NULL;
 111         }
 112
 113         if (dev_priv->status_gfx_addr) {
 114                 dev_priv->status_gfx_addr = 0;
 115                 ring->status_page.gfx_addr = 0;
 116                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 117         }
 118
 119         /* Need to rewrite hardware status page */
 120         I915_WRITE(HWS_PGA, 0x1ffff000);
 121 }
 122
 123 void i915_kernel_lost_context(struct drm_device * dev)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 127
 128         /*
 129          * We should never lose context on the ring with modesetting
 130          * as we don't expose it to userspace
 131          */
 132         if (drm_core_check_feature(dev, DRIVER_MODESET))
 133                 return;
 134
 135         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 136         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 137         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 138         if (ring->space < 0)
 139                 ring->space += ring->size;
 140
 141 #if 1
 142         KIB_NOTYET();
 143 #else
 144         if (!dev->primary->master)
 145                 return;
 146 #endif
 147
 148         if (ring->head == ring->tail && dev_priv->sarea_priv)
 149                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 150 }
 151
 152 static int i915_dma_cleanup(struct drm_device * dev)
 153 {
 154         drm_i915_private_t *dev_priv = dev->dev_private;
 155         int i;
 156
 157
 158         /* Make sure interrupts are disabled here because the uninstall ioctl
 159          * may not have been called from userspace and after dev_private
 160          * is freed, it's too late.
 161          */
 162         if (dev->irq_enabled)
 163                 drm_irq_uninstall(dev);
 164
 165         DRM_LOCK(dev);
 166         for (i = 0; i < I915_NUM_RINGS; i++)
 167                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 168         DRM_UNLOCK(dev);
 169
 170         /* Clear the HWS virtual address at teardown */
 171         if (I915_NEED_GFX_HWS(dev))
 172                 i915_free_hws(dev);
 173
 174         return 0;
 175 }
 176
 177 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 178 {
 179         drm_i915_private_t *dev_priv = dev->dev_private;
 180         int ret;
 181
 182         dev_priv->sarea = drm_getsarea(dev);
 183         if (!dev_priv->sarea) {
 184                 DRM_ERROR("can not find sarea!\n");
 185                 i915_dma_cleanup(dev);
 186                 return -EINVAL;
 187         }
 188
 189         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 190             ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
 191
 192         if (init->ring_size != 0) {
 193                 if (LP_RING(dev_priv)->obj != NULL) {
 194                         i915_dma_cleanup(dev);
 195                         DRM_ERROR("Client tried to initialize ringbuffer in "
 196                                   "GEM mode\n");
 197                         return -EINVAL;
 198                 }
 199
 200                 ret = intel_render_ring_init_dri(dev,
 201                                                  init->ring_start,
 202                                                  init->ring_size);
 203                 if (ret) {
 204                         i915_dma_cleanup(dev);
 205                         return ret;
 206                 }
 207         }
 208
 209         dev_priv->cpp = init->cpp;
 210         dev_priv->back_offset = init->back_offset;
 211         dev_priv->front_offset = init->front_offset;
 212         dev_priv->current_page = 0;
 213         dev_priv->sarea_priv->pf_current_page = 0;
 214
 215         /* Allow hardware batchbuffers unless told otherwise.
 216          */
 217         dev_priv->dri1.allow_batchbuffer = 1;
 218
 219         return 0;
 220 }
 221
 222 static int i915_dma_resume(struct drm_device * dev)
 223 {
 224         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 225         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 226
 227         DRM_DEBUG("\n");
 228
 229         if (ring->virtual_start == NULL) {
 230                 DRM_ERROR("can not ioremap virtual address for"
 231                           " ring buffer\n");
 232                 return -ENOMEM;
 233         }
 234
 235         /* Program Hardware Status Page */
 236         if (!ring->status_page.page_addr) {
 237                 DRM_ERROR("Can not find hardware status page\n");
 238                 return -EINVAL;
 239         }
 240         DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
 241         if (ring->status_page.gfx_addr != 0)
 242                 intel_ring_setup_status_page(ring);
 243         else
 244                 i915_write_hws_pga(dev);
 245
 246         DRM_DEBUG("Enabled hardware status page\n");
 247
 248         return 0;
 249 }
 250
 251 static int i915_dma_init(struct drm_device *dev, void *data,
 252                          struct drm_file *file_priv)
 253 {
 254         drm_i915_init_t *init = data;
 255         int retcode = 0;
 256
 257         switch (init->func) {
 258         case I915_INIT_DMA:
 259                 retcode = i915_initialize(dev, init);
 260                 break;
 261         case I915_CLEANUP_DMA:
 262                 retcode = i915_dma_cleanup(dev);
 263                 break;
 264         case I915_RESUME_DMA:
 265                 retcode = i915_dma_resume(dev);
 266                 break;
 267         default:
 268                 retcode = -EINVAL;
 269                 break;
 270         }
 271
 272         return retcode;
 273 }
 274
 275 /* Implement basically the same security restrictions as hardware does
 276  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 277  *
 278  * Most of the calculations below involve calculating the size of a
 279  * particular instruction.  It's important to get the size right as
 280  * that tells us where the next instruction to check is.  Any illegal
 281  * instruction detected will be given a size of zero, which is a
 282  * signal to abort the rest of the buffer.
 283  */
 284 static int do_validate_cmd(int cmd)
 285 {
 286         switch (((cmd >> 29) & 0x7)) {
 287         case 0x0:
 288                 switch ((cmd >> 23) & 0x3f) {
 289                 case 0x0:
 290                         return 1;       /* MI_NOOP */
 291                 case 0x4:
 292                         return 1;       /* MI_FLUSH */
 293                 default:
 294                         return 0;       /* disallow everything else */
 295                 }
 296                 break;
 297         case 0x1:
 298                 return 0;       /* reserved */
 299         case 0x2:
 300                 return (cmd & 0xff) + 2;        /* 2d commands */
 301         case 0x3:
 302                 if (((cmd >> 24) & 0x1f) <= 0x18)
 303                         return 1;
 304
 305                 switch ((cmd >> 24) & 0x1f) {
 306                 case 0x1c:
 307                         return 1;
 308                 case 0x1d:
 309                         switch ((cmd >> 16) & 0xff) {
 310                         case 0x3:
 311                                 return (cmd & 0x1f) + 2;
 312                         case 0x4:
 313                                 return (cmd & 0xf) + 2;
 314                         default:
 315                                 return (cmd & 0xffff) + 2;
 316                         }
 317                 case 0x1e:
 318                         if (cmd & (1 << 23))
 319                                 return (cmd & 0xffff) + 1;
 320                         else
 321                                 return 1;
 322                 case 0x1f:
 323                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 324                                 return (cmd & 0x1ffff) + 2;
 325                         else if (cmd & (1 << 17))       /* indirect random */
 326                                 if ((cmd & 0xffff) == 0)
 327                                         return 0;       /* unknown length, too hard */
 328                                 else
 329                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 330                         else
 331                                 return 2;       /* indirect sequential */
 332                 default:
 333                         return 0;
 334                 }
 335         default:
 336                 return 0;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int validate_cmd(int cmd)
 343 {
 344         int ret = do_validate_cmd(cmd);
 345
 346 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 347
 348         return ret;
 349 }
 350
 351 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 352                           int dwords)
 353 {
 354         drm_i915_private_t *dev_priv = dev->dev_private;
 355         int i, ret;
 356
 357         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 358                 return -EINVAL;
 359
 360         ret = BEGIN_LP_RING((dwords+1)&~1);
 361         if (ret)
 362                 return ret;
 363
 364         for (i = 0; i < dwords;) {
 365                 int cmd, sz;
 366
 367                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 368                         return -EINVAL;
 369
 370                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 371                         return -EINVAL;
 372
 373                 OUT_RING(cmd);
 374
 375                 while (++i, --sz) {
 376                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 377                                                          sizeof(cmd))) {
 378                                 return -EINVAL;
 379                         }
 380                         OUT_RING(cmd);
 381                 }
 382         }
 383
 384         if (dwords & 1)
 385                 OUT_RING(0);
 386
 387         ADVANCE_LP_RING();
 388
 389         return 0;
 390 }
 391
 392 int i915_emit_box(struct drm_device * dev,
 393                   struct drm_clip_rect *boxes,
 394                   int i, int DR1, int DR4)
 395 {
 396         struct drm_clip_rect box;
 397
 398         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 399                 return -EFAULT;
 400         }
 401
 402         return (i915_emit_box_p(dev, &box, DR1, DR4));
 403 }
 404
 405 int
 406 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
 407     int DR1, int DR4)
 408 {
 409         drm_i915_private_t *dev_priv = dev->dev_private;
 410         int ret;
 411
 412         if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
 413             box->x2 <= 0) {
 414                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 415                           box->x1, box->y1, box->x2, box->y2);
 416                 return -EINVAL;
 417         }
 418
 419         if (INTEL_INFO(dev)->gen >= 4) {
 420                 ret = BEGIN_LP_RING(4);
 421                 if (ret != 0)
 422                         return (ret);
 423
 424                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 425                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 426                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 427                 OUT_RING(DR4);
 428         } else {
 429                 ret = BEGIN_LP_RING(6);
 430                 if (ret != 0)
 431                         return (ret);
 432
 433                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 434                 OUT_RING(DR1);
 435                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 436                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 437                 OUT_RING(DR4);
 438                 OUT_RING(0);
 439         }
 440         ADVANCE_LP_RING();
 441
 442         return 0;
 443 }
 444
 445 /* XXX: Emitting the counter should really be moved to part of the IRQ
 446  * emit. For now, do it in both places:
 447  */
 448
 449 static void i915_emit_breadcrumb(struct drm_device *dev)
 450 {
 451         drm_i915_private_t *dev_priv = dev->dev_private;
 452
 453         dev_priv->dri1.counter++;
 454         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 455                 dev_priv->dri1.counter = 0;
 456         if (dev_priv->sarea_priv)
 457                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 458
 459         if (BEGIN_LP_RING(4) == 0) {
 460                 OUT_RING(MI_STORE_DWORD_INDEX);
 461                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 462                 OUT_RING(dev_priv->dri1.counter);
 463                 OUT_RING(0);
 464                 ADVANCE_LP_RING();
 465         }
 466 }
 467
 468 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 469     drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
 470 {
 471         int nbox = cmd->num_cliprects;
 472         int i = 0, count, ret;
 473
 474         if (cmd->sz & 0x3) {
 475                 DRM_ERROR("alignment\n");
 476                 return -EINVAL;
 477         }
 478
 479         i915_kernel_lost_context(dev);
 480
 481         count = nbox ? nbox : 1;
 482
 483         for (i = 0; i < count; i++) {
 484                 if (i < nbox) {
 485                         ret = i915_emit_box_p(dev, &cmd->cliprects[i],
 486                             cmd->DR1, cmd->DR4);
 487                         if (ret)
 488                                 return ret;
 489                 }
 490
 491                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 492                 if (ret)
 493                         return ret;
 494         }
 495
 496         i915_emit_breadcrumb(dev);
 497         return 0;
 498 }
 499
 500 static int
 501 i915_dispatch_batchbuffer(struct drm_device * dev,
 502     drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
 503 {
 504         drm_i915_private_t *dev_priv = dev->dev_private;
 505         int nbox = batch->num_cliprects;
 506         int i, count, ret;
 507
 508         if ((batch->start | batch->used) & 0x7) {
 509                 DRM_ERROR("alignment\n");
 510                 return -EINVAL;
 511         }
 512
 513         i915_kernel_lost_context(dev);
 514
 515         count = nbox ? nbox : 1;
 516
 517         for (i = 0; i < count; i++) {
 518                 if (i < nbox) {
 519                         int ret = i915_emit_box_p(dev, &cliprects[i],
 520                             batch->DR1, batch->DR4);
 521                         if (ret)
 522                                 return ret;
 523                 }
 524
 525                 if (!IS_I830(dev) && !IS_845G(dev)) {
 526                         ret = BEGIN_LP_RING(2);
 527                         if (ret != 0)
 528                                 return (ret);
 529
 530                         if (INTEL_INFO(dev)->gen >= 4) {
 531                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
 532                                     MI_BATCH_NON_SECURE_I965);
 533                                 OUT_RING(batch->start);
 534                         } else {
 535                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 536                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 537                         }
 538                 } else {
 539                         ret = BEGIN_LP_RING(4);
 540                         if (ret != 0)
 541                                 return (ret);
 542
 543                         OUT_RING(MI_BATCH_BUFFER);
 544                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 545                         OUT_RING(batch->start + batch->used - 4);
 546                         OUT_RING(0);
 547                 }
 548                 ADVANCE_LP_RING();
 549         }
 550
 551         i915_emit_breadcrumb(dev);
 552
 553         return 0;
 554 }
 555
 556 static int i915_dispatch_flip(struct drm_device * dev)
 557 {
 558         drm_i915_private_t *dev_priv = dev->dev_private;
 559         int ret;
 560
 561         if (!dev_priv->sarea_priv)
 562                 return -EINVAL;
 563
 564         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 565                           __func__,
 566                          dev_priv->dri1.current_page,
 567                          dev_priv->sarea_priv->pf_current_page);
 568
 569         i915_kernel_lost_context(dev);
 570
 571         ret = BEGIN_LP_RING(10);
 572         if (ret)
 573                 return ret;
 574
 575         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 576         OUT_RING(0);
 577
 578         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 579         OUT_RING(0);
 580         if (dev_priv->dri1.current_page == 0) {
 581                 OUT_RING(dev_priv->dri1.back_offset);
 582                 dev_priv->dri1.current_page = 1;
 583         } else {
 584                 OUT_RING(dev_priv->dri1.front_offset);
 585                 dev_priv->dri1.current_page = 0;
 586         }
 587         OUT_RING(0);
 588
 589         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 590         OUT_RING(0);
 591
 592         ADVANCE_LP_RING();
 593
 594         dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 595
 596         if (BEGIN_LP_RING(4) == 0) {
 597                 OUT_RING(MI_STORE_DWORD_INDEX);
 598                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 599                 OUT_RING(dev_priv->dri1.counter);
 600                 OUT_RING(0);
 601                 ADVANCE_LP_RING();
 602         }
 603
 604         dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 605         return 0;
 606 }
 607
 608 static int i915_quiescent(struct drm_device *dev)
 609 {
 610         i915_kernel_lost_context(dev);
 611         return intel_ring_idle(LP_RING(dev->dev_private));
 612 }
 613
 614 static int
 615 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 616 {
 617         int ret;
 618
 619         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 620
 621         DRM_LOCK(dev);
 622         ret = i915_quiescent(dev);
 623         DRM_UNLOCK(dev);
 624
 625         return (ret);
 626 }
 627
 628 static int i915_batchbuffer(struct drm_device *dev, void *data,
 629                             struct drm_file *file_priv)
 630 {
 631         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 632         drm_i915_sarea_t *sarea_priv;
 633         drm_i915_batchbuffer_t *batch = data;
 634         struct drm_clip_rect *cliprects;
 635         size_t cliplen;
 636         int ret;
 637
 638         if (!dev_priv->dri1.allow_batchbuffer) {
 639                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 640                 return -EINVAL;
 641         }
 642
 643         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 644                   batch->start, batch->used, batch->num_cliprects);
 645
 646         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 647
 648         cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
 649         if (batch->num_cliprects < 0)
 650                 return -EFAULT;
 651         if (batch->num_cliprects != 0) {
 652                 cliprects = kmalloc(batch->num_cliprects *
 653                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 654                     M_WAITOK | M_ZERO);
 655
 656                 ret = -copyin(batch->cliprects, cliprects,
 657                     batch->num_cliprects * sizeof(struct drm_clip_rect));
 658                 if (ret != 0) {
 659                         ret = -EFAULT;
 660                         goto fail_free;
 661                 }
 662         } else
 663                 cliprects = NULL;
 664
 665         DRM_LOCK(dev);
 666         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 667         DRM_UNLOCK(dev);
 668
 669         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 670         if (sarea_priv)
 671                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 672
 673 fail_free:
 674         drm_free(cliprects, DRM_MEM_DMA);
 675         return ret;
 676 }
 677
 678 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 679                           struct drm_file *file_priv)
 680 {
 681         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 682         drm_i915_sarea_t *sarea_priv;
 683         drm_i915_cmdbuffer_t *cmdbuf = data;
 684         struct drm_clip_rect *cliprects = NULL;
 685         void *batch_data;
 686         int ret;
 687
 688         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 689                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 690
 691         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 692
 693         if (cmdbuf->num_cliprects < 0)
 694                 return -EINVAL;
 695
 696         batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
 697
 698         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
 699         if (ret != 0) {
 700                 ret = -EFAULT;
 701                 goto fail_batch_free;
 702         }
 703
 704         if (cmdbuf->num_cliprects) {
 705                 cliprects = kmalloc(cmdbuf->num_cliprects *
 706                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 707                     M_WAITOK | M_ZERO);
 708                 ret = -copyin(cmdbuf->cliprects, cliprects,
 709                     cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
 710
 711                 if (ret != 0) {
 712                         ret = -EFAULT;
 713                         goto fail_clip_free;
 714                 }
 715         }
 716
 717         DRM_LOCK(dev);
 718         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 719         DRM_UNLOCK(dev);
 720         if (ret) {
 721                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 722                 goto fail_clip_free;
 723         }
 724
 725         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 726         if (sarea_priv)
 727                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 728
 729 fail_clip_free:
 730         drm_free(cliprects, DRM_MEM_DMA);
 731 fail_batch_free:
 732         drm_free(batch_data, DRM_MEM_DMA);
 733         return ret;
 734 }
 735
 736 static int i915_emit_irq(struct drm_device * dev)
 737 {
 738         drm_i915_private_t *dev_priv = dev->dev_private;
 739 #if 0
 740         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 741 #endif
 742
 743         i915_kernel_lost_context(dev);
 744
 745         DRM_DEBUG_DRIVER("\n");
 746
 747         dev_priv->dri1.counter++;
 748         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 749                 dev_priv->dri1.counter = 1;
 750         if (dev_priv->sarea_priv)
 751                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 752
 753         if (BEGIN_LP_RING(4) == 0) {
 754                 OUT_RING(MI_STORE_DWORD_INDEX);
 755                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 756                 OUT_RING(dev_priv->dri1.counter);
 757                 OUT_RING(MI_USER_INTERRUPT);
 758                 ADVANCE_LP_RING();
 759         }
 760
 761         return dev_priv->dri1.counter;
 762 }
 763
 764 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 765 {
 766         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 767 #if 0
 768         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 769 #endif
 770         int ret = 0;
 771         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 772
 773         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 774                   READ_BREADCRUMB(dev_priv));
 775
 776 #if 0
 777         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 778                 if (master_priv->sarea_priv)
 779                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 780                 return 0;
 781         }
 782
 783         if (master_priv->sarea_priv)
 784                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 785 #else
 786         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 787                 if (dev_priv->sarea_priv) {
 788                         dev_priv->sarea_priv->last_dispatch =
 789                                 READ_BREADCRUMB(dev_priv);
 790                 }
 791                 return 0;
 792         }
 793
 794         if (dev_priv->sarea_priv)
 795                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 796 #endif
 797
 798         if (ring->irq_get(ring)) {
 799                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 800                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 801                 ring->irq_put(ring);
 802         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 803                 ret = -EBUSY;
 804
 805         if (ret == -EBUSY) {
 806                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 807                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 808         }
 809
 810         return ret;
 811 }
 812
 813 /* Needs the lock as it touches the ring.
 814  */
 815 int i915_irq_emit(struct drm_device *dev, void *data,
 816                          struct drm_file *file_priv)
 817 {
 818         drm_i915_private_t *dev_priv = dev->dev_private;
 819         drm_i915_irq_emit_t *emit = data;
 820         int result;
 821
 822         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 823                 DRM_ERROR("called with no initialization\n");
 824                 return -EINVAL;
 825         }
 826
 827         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 828
 829         DRM_LOCK(dev);
 830         result = i915_emit_irq(dev);
 831         DRM_UNLOCK(dev);
 832
 833         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 834                 DRM_ERROR("copy_to_user\n");
 835                 return -EFAULT;
 836         }
 837
 838         return 0;
 839 }
 840
 841 /* Doesn't need the hardware lock.
 842  */
 843 int i915_irq_wait(struct drm_device *dev, void *data,
 844                          struct drm_file *file_priv)
 845 {
 846         drm_i915_private_t *dev_priv = dev->dev_private;
 847         drm_i915_irq_wait_t *irqwait = data;
 848
 849         if (!dev_priv) {
 850                 DRM_ERROR("called with no initialization\n");
 851                 return -EINVAL;
 852         }
 853
 854         return i915_wait_irq(dev, irqwait->irq_seq);
 855 }
 856
 857 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 858                          struct drm_file *file_priv)
 859 {
 860         drm_i915_private_t *dev_priv = dev->dev_private;
 861         drm_i915_vblank_pipe_t *pipe = data;
 862
 863         if (drm_core_check_feature(dev, DRIVER_MODESET))
 864                 return -ENODEV;
 865
 866         if (!dev_priv) {
 867                 DRM_ERROR("called with no initialization\n");
 868                 return -EINVAL;
 869         }
 870
 871         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 872
 873         return 0;
 874 }
 875
 876 /**
 877  * Schedule buffer swap at given vertical blank.
 878  */
 879 static int i915_vblank_swap(struct drm_device *dev, void *data,
 880                      struct drm_file *file_priv)
 881 {
 882         /* The delayed swap mechanism was fundamentally racy, and has been
 883          * removed.  The model was that the client requested a delayed flip/swap
 884          * from the kernel, then waited for vblank before continuing to perform
 885          * rendering.  The problem was that the kernel might wake the client
 886          * up before it dispatched the vblank swap (since the lock has to be
 887          * held while touching the ringbuffer), in which case the client would
 888          * clear and start the next frame before the swap occurred, and
 889          * flicker would occur in addition to likely missing the vblank.
 890          *
 891          * In the absence of this ioctl, userland falls back to a correct path
 892          * of waiting for a vblank, then dispatching the swap on its own.
 893          * Context switching to userland and back is plenty fast enough for
 894          * meeting the requirements of vblank swapping.
 895          */
 896         return -EINVAL;
 897 }
 898
 899 static int i915_flip_bufs(struct drm_device *dev, void *data,
 900                           struct drm_file *file_priv)
 901 {
 902         int ret;
 903
 904         DRM_DEBUG("%s\n", __func__);
 905
 906         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 907
 908         DRM_LOCK(dev);
 909         ret = i915_dispatch_flip(dev);
 910         DRM_UNLOCK(dev);
 911
 912         return ret;
 913 }
 914
 915 static int i915_getparam(struct drm_device *dev, void *data,
 916                          struct drm_file *file_priv)
 917 {
 918         drm_i915_private_t *dev_priv = dev->dev_private;
 919         drm_i915_getparam_t *param = data;
 920         int value;
 921
 922         if (!dev_priv) {
 923                 DRM_ERROR("called with no initialization\n");
 924                 return -EINVAL;
 925         }
 926
 927         switch (param->param) {
 928         case I915_PARAM_IRQ_ACTIVE:
 929                 value = dev->irq_enabled ? 1 : 0;
 930                 break;
 931         case I915_PARAM_ALLOW_BATCHBUFFER:
 932                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 933                 break;
 934         case I915_PARAM_LAST_DISPATCH:
 935                 value = READ_BREADCRUMB(dev_priv);
 936                 break;
 937         case I915_PARAM_CHIPSET_ID:
 938                 value = dev->pci_device;
 939                 break;
 940         case I915_PARAM_HAS_GEM:
 941                 value = 1;
 942                 break;
 943         case I915_PARAM_NUM_FENCES_AVAIL:
 944                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 945                 break;
 946         case I915_PARAM_HAS_OVERLAY:
 947                 value = dev_priv->overlay ? 1 : 0;
 948                 break;
 949         case I915_PARAM_HAS_PAGEFLIPPING:
 950                 value = 1;
 951                 break;
 952         case I915_PARAM_HAS_EXECBUF2:
 953                 /* depends on GEM */
 954                 value = 1;
 955                 break;
 956         case I915_PARAM_HAS_BSD:
 957                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 958                 break;
 959         case I915_PARAM_HAS_BLT:
 960                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 961                 break;
 962         case I915_PARAM_HAS_RELAXED_FENCING:
 963                 value = 1;
 964                 break;
 965         case I915_PARAM_HAS_COHERENT_RINGS:
 966                 value = 1;
 967                 break;
 968         case I915_PARAM_HAS_EXEC_CONSTANTS:
 969                 value = INTEL_INFO(dev)->gen >= 4;
 970                 break;
 971         case I915_PARAM_HAS_RELAXED_DELTA:
 972                 value = 1;
 973                 break;
 974         case I915_PARAM_HAS_GEN7_SOL_RESET:
 975                 value = 1;
 976                 break;
 977         case I915_PARAM_HAS_LLC:
 978                 value = HAS_LLC(dev);
 979                 break;
 980         case I915_PARAM_HAS_ALIASING_PPGTT:
 981                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 982                 break;
 983         case I915_PARAM_HAS_PINNED_BATCHES:
 984                 value = 1;
 985                 break;
 986         default:
 987                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 988                                  param->param);
 989                 return -EINVAL;
 990         }
 991
 992         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 993                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 994                 return -EFAULT;
 995         }
 996
 997         return 0;
 998 }
 999
1000 static int i915_setparam(struct drm_device *dev, void *data,
1001                          struct drm_file *file_priv)
1002 {
1003         drm_i915_private_t *dev_priv = dev->dev_private;
1004         drm_i915_setparam_t *param = data;
1005
1006         if (!dev_priv) {
1007                 DRM_ERROR("called with no initialization\n");
1008                 return -EINVAL;
1009         }
1010
1011         switch (param->param) {
1012         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1013                 break;
1014         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1015                 break;
1016         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1017                 dev_priv->dri1.allow_batchbuffer = param->value;
1018                 break;
1019         case I915_SETPARAM_NUM_USED_FENCES:
1020                 if (param->value > dev_priv->num_fence_regs ||
1021                     param->value < 0)
1022                         return -EINVAL;
1023                 /* Userspace can use first N regs */
1024                 dev_priv->fence_reg_start = param->value;
1025                 break;
1026         default:
1027                 DRM_DEBUG("unknown parameter %d\n", param->param);
1028                 return -EINVAL;
1029         }
1030
1031         return 0;
1032 }
1033
1034 static int i915_set_status_page(struct drm_device *dev, void *data,
1035                                 struct drm_file *file_priv)
1036 {
1037         drm_i915_private_t *dev_priv = dev->dev_private;
1038         drm_i915_hws_addr_t *hws = data;
1039         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1040
1041         if (!I915_NEED_GFX_HWS(dev))
1042                 return -EINVAL;
1043
1044         if (!dev_priv) {
1045                 DRM_ERROR("called with no initialization\n");
1046                 return -EINVAL;
1047         }
1048
1049         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1050         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1051                 DRM_ERROR("tried to set status page when mode setting active\n");
1052                 return 0;
1053         }
1054
1055         ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
1056             hws->addr & (0x1ffff<<12);
1057
1058         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1059         dev_priv->hws_map.size = 4*1024;
1060         dev_priv->hws_map.type = 0;
1061         dev_priv->hws_map.flags = 0;
1062         dev_priv->hws_map.mtrr = 0;
1063
1064         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
1065         if (dev_priv->hws_map.virtual == NULL) {
1066                 i915_dma_cleanup(dev);
1067                 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
1068                 DRM_ERROR("can not ioremap virtual address for"
1069                                 " G33 hw status page\n");
1070                 return -ENOMEM;
1071         }
1072         ring->status_page.page_addr = dev_priv->hw_status_page =
1073             dev_priv->hws_map.virtual;
1074
1075         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1076         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1077         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
1078                         dev_priv->status_gfx_addr);
1079         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1080         return 0;
1081 }
1082
1083 static int i915_load_modeset_init(struct drm_device *dev)
1084 {
1085         struct drm_i915_private *dev_priv = dev->dev_private;
1086         int ret;
1087
1088         ret = intel_parse_bios(dev);
1089         if (ret)
1090                 DRM_INFO("failed to find VBIOS tables\n");
1091
1092 #if 0
1093         /* If we have > 1 VGA cards, then we need to arbitrate access
1094          * to the common VGA resources.
1095          *
1096          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1097          * then we do not take part in VGA arbitration and the
1098          * vga_client_register() fails with -ENODEV.
1099          */
1100         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1101         if (ret && ret != -ENODEV)
1102                 goto out;
1103
1104         intel_register_dsm_handler();
1105
1106         ret = vga_switcheroo_register_client(dev->pdev,
1107                                              i915_switcheroo_set_state,
1108                                              NULL,
1109                                              i915_switcheroo_can_switch);
1110         if (ret)
1111                 goto cleanup_vga_client;
1112
1113         /* Initialise stolen first so that we may reserve preallocated
1114          * objects for the BIOS to KMS transition.
1115          */
1116         ret = i915_gem_init_stolen(dev);
1117         if (ret)
1118                 goto cleanup_vga_switcheroo;
1119 #endif
1120
1121         intel_modeset_init(dev);
1122
1123         ret = i915_gem_init(dev);
1124         if (ret)
1125                 goto cleanup_gem_stolen;
1126
1127         intel_modeset_gem_init(dev);
1128
1129         ret = drm_irq_install(dev);
1130         if (ret)
1131                 goto cleanup_gem;
1132
1133         /* Always safe in the mode setting case. */
1134         /* FIXME: do pre/post-mode set stuff in core KMS code */
1135         dev->vblank_disable_allowed = 1;
1136
1137         ret = intel_fbdev_init(dev);
1138         if (ret)
1139                 goto cleanup_irq;
1140
1141         drm_kms_helper_poll_init(dev);
1142
1143         /* We're off and running w/KMS */
1144         dev_priv->mm.suspended = 0;
1145
1146         return 0;
1147
1148 cleanup_irq:
1149         drm_irq_uninstall(dev);
1150 cleanup_gem:
1151         DRM_LOCK(dev);
1152         i915_gem_cleanup_ringbuffer(dev);
1153         DRM_UNLOCK(dev);
1154         i915_gem_cleanup_aliasing_ppgtt(dev);
1155 cleanup_gem_stolen:
1156 #if 0
1157         i915_gem_cleanup_stolen(dev);
1158 cleanup_vga_switcheroo:
1159         vga_switcheroo_unregister_client(dev->pdev);
1160 cleanup_vga_client:
1161         vga_client_register(dev->pdev, NULL, NULL, NULL);
1162 out:
1163 #endif
1164         return ret;
1165 }
1166
1167 static int
1168 i915_get_bridge_dev(struct drm_device *dev)
1169 {
1170         struct drm_i915_private *dev_priv;
1171
1172         dev_priv = dev->dev_private;
1173
1174         dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1175         if (dev_priv->bridge_dev == NULL) {
1176                 DRM_ERROR("bridge device not found\n");
1177                 return (-1);
1178         }
1179         return (0);
1180 }
1181
1182 #define MCHBAR_I915 0x44
1183 #define MCHBAR_I965 0x48
1184 #define MCHBAR_SIZE (4*4096)
1185
1186 #define DEVEN_REG 0x54
1187 #define   DEVEN_MCHBAR_EN (1 << 28)
1188
1189 /* Allocate space for the MCH regs if needed, return nonzero on error */
1190 static int
1191 intel_alloc_mchbar_resource(struct drm_device *dev)
1192 {
1193         drm_i915_private_t *dev_priv;
1194         device_t vga;
1195         int reg;
1196         u32 temp_lo, temp_hi;
1197         u64 mchbar_addr, temp;
1198
1199         dev_priv = dev->dev_private;
1200         reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1201
1202         if (INTEL_INFO(dev)->gen >= 4)
1203                 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1204         else
1205                 temp_hi = 0;
1206         temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1207         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1208
1209         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1210 #ifdef XXX_CONFIG_PNP
1211         if (mchbar_addr &&
1212             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1213                 return 0;
1214 #endif
1215
1216         /* Get some space for it */
1217         vga = device_get_parent(dev->dev);
1218         dev_priv->mch_res_rid = 0x100;
1219         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1220             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1221             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1222         if (dev_priv->mch_res == NULL) {
1223                 DRM_ERROR("failed mchbar resource alloc\n");
1224                 return (-ENOMEM);
1225         }
1226
1227         if (INTEL_INFO(dev)->gen >= 4) {
1228                 temp = rman_get_start(dev_priv->mch_res);
1229                 temp >>= 32;
1230                 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1231         }
1232         pci_write_config(dev_priv->bridge_dev, reg,
1233             rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1234         return (0);
1235 }
1236
1237 static void
1238 intel_setup_mchbar(struct drm_device *dev)
1239 {
1240         drm_i915_private_t *dev_priv;
1241         int mchbar_reg;
1242         u32 temp;
1243         bool enabled;
1244
1245         dev_priv = dev->dev_private;
1246         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1247
1248         dev_priv->mchbar_need_disable = false;
1249
1250         if (IS_I915G(dev) || IS_I915GM(dev)) {
1251                 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1252                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1253         } else {
1254                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1255                 enabled = temp & 1;
1256         }
1257
1258         /* If it's already enabled, don't have to do anything */
1259         if (enabled) {
1260                 DRM_DEBUG("mchbar already enabled\n");
1261                 return;
1262         }
1263
1264         if (intel_alloc_mchbar_resource(dev))
1265                 return;
1266
1267         dev_priv->mchbar_need_disable = true;
1268
1269         /* Space is allocated or reserved, so enable it. */
1270         if (IS_I915G(dev) || IS_I915GM(dev)) {
1271                 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1272                     temp | DEVEN_MCHBAR_EN, 4);
1273         } else {
1274                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1275                 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1276         }
1277 }
1278
1279 static void
1280 intel_teardown_mchbar(struct drm_device *dev)
1281 {
1282         drm_i915_private_t *dev_priv;
1283         device_t vga;
1284         int mchbar_reg;
1285         u32 temp;
1286
1287         dev_priv = dev->dev_private;
1288         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1289
1290         if (dev_priv->mchbar_need_disable) {
1291                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1292                         temp = pci_read_config(dev_priv->bridge_dev,
1293                             DEVEN_REG, 4);
1294                         temp &= ~DEVEN_MCHBAR_EN;
1295                         pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1296                             temp, 4);
1297                 } else {
1298                         temp = pci_read_config(dev_priv->bridge_dev,
1299                             mchbar_reg, 4);
1300                         temp &= ~1;
1301                         pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1302                             temp, 4);
1303                 }
1304         }
1305
1306         if (dev_priv->mch_res != NULL) {
1307                 vga = device_get_parent(dev->dev);
1308                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1309                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1310                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1311                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1312                 dev_priv->mch_res = NULL;
1313         }
1314 }
1315
1316 /**
1317  * i915_driver_load - setup chip and create an initial config
1318  * @dev: DRM device
1319  * @flags: startup flags
1320  *
1321  * The driver load routine has to do several things:
1322  *   - drive output discovery via intel_modeset_init()
1323  *   - initialize the memory manager
1324  *   - allocate initial config memory
1325  *   - setup the DRM framebuffer with the allocated memory
1326  */
1327 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1328 {
1329         struct drm_i915_private *dev_priv = dev->dev_private;
1330         unsigned long base, size;
1331         int mmio_bar, ret;
1332
1333         ret = 0;
1334
1335         /* i915 has 4 more counters */
1336         dev->counters += 4;
1337         dev->types[6] = _DRM_STAT_IRQ;
1338         dev->types[7] = _DRM_STAT_PRIMARY;
1339         dev->types[8] = _DRM_STAT_SECONDARY;
1340         dev->types[9] = _DRM_STAT_DMA;
1341
1342         dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1343             M_ZERO | M_WAITOK);
1344         if (dev_priv == NULL)
1345                 return -ENOMEM;
1346
1347         dev->dev_private = (void *)dev_priv;
1348         dev_priv->dev = dev;
1349         dev_priv->info = i915_get_device_id(dev->pci_device);
1350
1351         if (i915_get_bridge_dev(dev)) {
1352                 drm_free(dev_priv, DRM_MEM_DRIVER);
1353                 return (-EIO);
1354         }
1355         dev_priv->mm.gtt = intel_gtt_get();
1356
1357         /* Add register map (needed for suspend/resume) */
1358         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1359         base = drm_get_resource_start(dev, mmio_bar);
1360         size = drm_get_resource_len(dev, mmio_bar);
1361
1362         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1363             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1364
1365         /* The i915 workqueue is primarily used for batched retirement of
1366          * requests (and thus managing bo) once the task has been completed
1367          * by the GPU. i915_gem_retire_requests() is called directly when we
1368          * need high-priority retirement, such as waiting for an explicit
1369          * bo.
1370          *
1371          * It is also used for periodic low-priority events, such as
1372          * idle-timers and recording error state.
1373          *
1374          * All tasks on the workqueue are expected to acquire the dev mutex
1375          * so there is no point in running more than one instance of the
1376          * workqueue at any time.  Use an ordered one.
1377          */
1378         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1379         if (dev_priv->wq == NULL) {
1380                 DRM_ERROR("Failed to create our workqueue.\n");
1381                 ret = -ENOMEM;
1382                 goto out_mtrrfree;
1383         }
1384
1385         /* This must be called before any calls to HAS_PCH_* */
1386         intel_detect_pch(dev);
1387
1388         intel_irq_init(dev);
1389         intel_gt_init(dev);
1390
1391         /* Try to make sure MCHBAR is enabled before poking at it */
1392         intel_setup_mchbar(dev);
1393         intel_setup_gmbus(dev);
1394         intel_opregion_setup(dev);
1395
1396         intel_setup_bios(dev);
1397
1398         i915_gem_load(dev);
1399
1400         /* On the 945G/GM, the chipset reports the MSI capability on the
1401          * integrated graphics even though the support isn't actually there
1402          * according to the published specs.  It doesn't appear to function
1403          * correctly in testing on 945G.
1404          * This may be a side effect of MSI having been made available for PEG
1405          * and the registers being closely associated.
1406          *
1407          * According to chipset errata, on the 965GM, MSI interrupts may
1408          * be lost or delayed, but we use them anyways to avoid
1409          * stuck interrupts on some machines.
1410          */
1411
1412         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1413         lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1414         spin_init(&dev_priv->rps.lock);
1415         spin_init(&dev_priv->dpio_lock);
1416
1417         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1418
1419         /* Init HWS */
1420         if (!I915_NEED_GFX_HWS(dev)) {
1421                 ret = i915_init_phys_hws(dev);
1422                 if (ret != 0) {
1423                         drm_rmmap(dev, dev_priv->mmio_map);
1424                         drm_free(dev_priv, DRM_MEM_DRIVER);
1425                         return ret;
1426                 }
1427         }
1428
1429         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1430                 dev_priv->num_pipe = 3;
1431         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1432                 dev_priv->num_pipe = 2;
1433         else
1434                 dev_priv->num_pipe = 1;
1435
1436         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1437         if (ret)
1438                 goto out_gem_unload;
1439
1440         /* Start out suspended */
1441         dev_priv->mm.suspended = 1;
1442
1443         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1444                 ret = i915_load_modeset_init(dev);
1445                 if (ret < 0) {
1446                         DRM_ERROR("failed to init modeset\n");
1447                         goto out_gem_unload;
1448                 }
1449         }
1450
1451         /* Must be done after probing outputs */
1452         intel_opregion_init(dev);
1453
1454         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1455                     (unsigned long) dev);
1456
1457         if (IS_GEN5(dev)) {
1458                 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1459                 i915_mch_dev = dev_priv;
1460                 dev_priv->mchdev_lock = &mchdev_lock;
1461                 lockmgr(&mchdev_lock, LK_RELEASE);
1462         }
1463
1464         return 0;
1465
1466 out_gem_unload:
1467         intel_teardown_gmbus(dev);
1468         intel_teardown_mchbar(dev);
1469         destroy_workqueue(dev_priv->wq);
1470 out_mtrrfree:
1471         return ret;
1472 }
1473
1474 int i915_driver_unload(struct drm_device *dev)
1475 {
1476         struct drm_i915_private *dev_priv = dev->dev_private;
1477         int ret;
1478
1479         intel_gpu_ips_teardown();
1480
1481         DRM_LOCK(dev);
1482         ret = i915_gpu_idle(dev);
1483         if (ret)
1484                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1485         i915_gem_retire_requests(dev);
1486         DRM_UNLOCK(dev);
1487
1488         /* Cancel the retire work handler, which should be idle now. */
1489         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1490
1491         i915_free_hws(dev);
1492
1493         intel_teardown_mchbar(dev);
1494
1495         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1496                 intel_fbdev_fini(dev);
1497                 intel_modeset_cleanup(dev);
1498         }
1499
1500         /* Free error state after interrupts are fully disabled. */
1501         del_timer_sync(&dev_priv->hangcheck_timer);
1502         cancel_work_sync(&dev_priv->error_work);
1503         i915_destroy_error_state(dev);
1504
1505         intel_opregion_fini(dev);
1506
1507         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1508                 /* Flush any outstanding unpin_work. */
1509                 flush_workqueue(dev_priv->wq);
1510
1511                 DRM_LOCK(dev);
1512                 i915_gem_free_all_phys_object(dev);
1513                 i915_gem_cleanup_ringbuffer(dev);
1514                 DRM_UNLOCK(dev);
1515                 i915_gem_cleanup_aliasing_ppgtt(dev);
1516                 drm_mm_takedown(&dev_priv->mm.stolen);
1517
1518                 intel_cleanup_overlay(dev);
1519
1520                 if (!I915_NEED_GFX_HWS(dev))
1521                         i915_free_hws(dev);
1522         }
1523
1524         i915_gem_unload(dev);
1525
1526         bus_generic_detach(dev->dev);
1527         drm_rmmap(dev, dev_priv->mmio_map);
1528         intel_teardown_gmbus(dev);
1529
1530         destroy_workqueue(dev_priv->wq);
1531
1532         drm_free(dev->dev_private, DRM_MEM_DRIVER);
1533
1534         return 0;
1535 }
1536
1537 int
1538 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1539 {
1540         struct drm_i915_file_private *i915_file_priv;
1541
1542         i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1543             M_WAITOK | M_ZERO);
1544
1545         spin_init(&i915_file_priv->mm.lock);
1546         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1547         file_priv->driver_priv = i915_file_priv;
1548
1549         return (0);
1550 }
1551
1552 void
1553 i915_driver_lastclose(struct drm_device * dev)
1554 {
1555         drm_i915_private_t *dev_priv = dev->dev_private;
1556
1557         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1558 #if 1
1559                 KIB_NOTYET();
1560 #else
1561                 drm_fb_helper_restore();
1562                 vga_switcheroo_process_delayed_switch();
1563 #endif
1564                 return;
1565         }
1566         i915_gem_lastclose(dev);
1567         i915_dma_cleanup(dev);
1568 }
1569
1570 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1571 {
1572
1573         i915_gem_release(dev, file_priv);
1574 }
1575
1576 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1577 {
1578         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1579
1580         spin_uninit(&i915_file_priv->mm.lock);
1581         drm_free(i915_file_priv, DRM_MEM_FILES);
1582 }
1583
1584 struct drm_ioctl_desc i915_ioctls[] = {
1585         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1586         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1587         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1588         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1589         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1590         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1591         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1592         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1593         DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1594         DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1595         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1596         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1597         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1598         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1599         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1600         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1601         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1602         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1603         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1604         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1605         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1606         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1607         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1608         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1609         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1610         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1611         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1612         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1613         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1614         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1615         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1616         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1617         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1618         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1619         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1620         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1621         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1622         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1623         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1624         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1625         DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1626         DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1627 };
1628
1629 struct drm_driver i915_driver_info = {
1630         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1631             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1632             DRIVER_GEM /*| DRIVER_MODESET*/,
1633
1634         .buf_priv_size  = sizeof(drm_i915_private_t),
1635         .load           = i915_driver_load,
1636         .open           = i915_driver_open,
1637         .unload         = i915_driver_unload,
1638         .preclose       = i915_driver_preclose,
1639         .lastclose      = i915_driver_lastclose,
1640         .postclose      = i915_driver_postclose,
1641         .device_is_agp  = i915_driver_device_is_agp,
1642         .gem_init_object = i915_gem_init_object,
1643         .gem_free_object = i915_gem_free_object,
1644         .gem_pager_ops  = &i915_gem_pager_ops,
1645         .dumb_create    = i915_gem_dumb_create,
1646         .dumb_map_offset = i915_gem_mmap_gtt,
1647         .dumb_destroy   = i915_gem_dumb_destroy,
1648         .sysctl_init    = i915_sysctl_init,
1649         .sysctl_cleanup = i915_sysctl_cleanup,
1650
1651         .ioctls         = i915_ioctls,
1652         .max_ioctl      = DRM_ARRAY_SIZE(i915_ioctls),
1653
1654         .name           = DRIVER_NAME,
1655         .desc           = DRIVER_DESC,
1656         .date           = DRIVER_DATE,
1657         .major          = DRIVER_MAJOR,
1658         .minor          = DRIVER_MINOR,
1659         .patchlevel     = DRIVER_PATCHLEVEL,
1660 };
1661
1662 /**
1663  * Determine if the device really is AGP or not.
1664  *
1665  * All Intel graphics chipsets are treated as AGP, even if they are really
1666  * built-in.
1667  *
1668  * \param dev   The device to be tested.
1669  *
1670  * \returns
1671  * A value of 1 is always retured to indictate every i9x5 is AGP.
1672  */
1673 int i915_driver_device_is_agp(struct drm_device * dev)
1674 {
1675         return 1;
1676 }