2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
37 #include "opt_polling.h"
39 #include <sys/param.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/interrupt.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
48 #include <sys/serialize.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
51 #include <sys/sysctl.h>
54 #include <net/ethernet.h>
56 #include <net/if_arp.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
60 #include <net/ifq_var.h>
61 #include <net/vlan/if_vlan_var.h>
62 #include <net/vlan/if_vlan_ether.h>
64 #include <dev/netif/mii_layer/mii.h>
65 #include <dev/netif/mii_layer/miivar.h>
66 #include <dev/netif/mii_layer/brgphyreg.h>
68 #include <bus/pci/pcidevs.h>
69 #include <bus/pci/pcireg.h>
70 #include <bus/pci/pcivar.h>
72 #include <dev/netif/bge/if_bgereg.h>
73 #include <dev/netif/bnx/if_bnxvar.h>
75 /* "device miibus" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
78 #define BNX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
80 static const struct bnx_type {
85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
86 "Broadcom BCM5717 Gigabit Ethernet" },
87 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
88 "Broadcom BCM5718 Gigabit Ethernet" },
89 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
90 "Broadcom BCM5719 Gigabit Ethernet" },
91 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
92 "Broadcom BCM5720 Gigabit Ethernet" },
94 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
95 "Broadcom BCM57761 Gigabit Ethernet" },
96 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
97 "Broadcom BCM57762 Gigabit Ethernet" },
98 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
99 "Broadcom BCM57765 Gigabit Ethernet" },
100 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
101 "Broadcom BCM57766 Gigabit Ethernet" },
102 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
103 "Broadcom BCM57781 Gigabit Ethernet" },
104 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
105 "Broadcom BCM57782 Gigabit Ethernet" },
106 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
107 "Broadcom BCM57785 Gigabit Ethernet" },
108 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
109 "Broadcom BCM57786 Gigabit Ethernet" },
110 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
111 "Broadcom BCM57791 Fast Ethernet" },
112 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
113 "Broadcom BCM57795 Fast Ethernet" },
118 #define BNX_IS_JUMBO_CAPABLE(sc) ((sc)->bnx_flags & BNX_FLAG_JUMBO)
119 #define BNX_IS_5717_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
120 #define BNX_IS_57765_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
121 #define BNX_IS_57765_FAMILY(sc) \
122 ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
124 typedef int (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
126 static int bnx_probe(device_t);
127 static int bnx_attach(device_t);
128 static int bnx_detach(device_t);
129 static void bnx_shutdown(device_t);
130 static int bnx_suspend(device_t);
131 static int bnx_resume(device_t);
132 static int bnx_miibus_readreg(device_t, int, int);
133 static int bnx_miibus_writereg(device_t, int, int, int);
134 static void bnx_miibus_statchg(device_t);
136 #ifdef DEVICE_POLLING
137 static void bnx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
139 static void bnx_intr_legacy(void *);
140 static void bnx_msi(void *);
141 static void bnx_msi_oneshot(void *);
142 static void bnx_intr(struct bnx_softc *);
143 static void bnx_enable_intr(struct bnx_softc *);
144 static void bnx_disable_intr(struct bnx_softc *);
145 static void bnx_txeof(struct bnx_softc *, uint16_t);
146 static void bnx_rxeof(struct bnx_softc *, uint16_t);
148 static void bnx_start(struct ifnet *);
149 static int bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
150 static void bnx_init(void *);
151 static void bnx_stop(struct bnx_softc *);
152 static void bnx_watchdog(struct ifnet *);
153 static int bnx_ifmedia_upd(struct ifnet *);
154 static void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
155 static void bnx_tick(void *);
157 static int bnx_alloc_jumbo_mem(struct bnx_softc *);
158 static void bnx_free_jumbo_mem(struct bnx_softc *);
159 static struct bnx_jslot
160 *bnx_jalloc(struct bnx_softc *);
161 static void bnx_jfree(void *);
162 static void bnx_jref(void *);
163 static int bnx_newbuf_std(struct bnx_softc *, int, int);
164 static int bnx_newbuf_jumbo(struct bnx_softc *, int, int);
165 static void bnx_setup_rxdesc_std(struct bnx_softc *, int);
166 static void bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
167 static int bnx_init_rx_ring_std(struct bnx_softc *);
168 static void bnx_free_rx_ring_std(struct bnx_softc *);
169 static int bnx_init_rx_ring_jumbo(struct bnx_softc *);
170 static void bnx_free_rx_ring_jumbo(struct bnx_softc *);
171 static void bnx_free_tx_ring(struct bnx_softc *);
172 static int bnx_init_tx_ring(struct bnx_softc *);
173 static int bnx_dma_alloc(struct bnx_softc *);
174 static void bnx_dma_free(struct bnx_softc *);
175 static int bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
176 bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
177 static void bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
179 bnx_defrag_shortdma(struct mbuf *);
180 static int bnx_encap(struct bnx_softc *, struct mbuf **, uint32_t *);
182 static void bnx_reset(struct bnx_softc *);
183 static int bnx_chipinit(struct bnx_softc *);
184 static int bnx_blockinit(struct bnx_softc *);
185 static void bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
186 static void bnx_enable_msi(struct bnx_softc *sc);
187 static void bnx_setmulti(struct bnx_softc *);
188 static void bnx_setpromisc(struct bnx_softc *);
189 static void bnx_stats_update_regs(struct bnx_softc *);
190 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
192 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
193 static void bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
195 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
197 static void bnx_writereg_ind(struct bnx_softc *, uint32_t, uint32_t);
198 static void bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
199 static void bnx_writembx(struct bnx_softc *, int, int);
200 static uint8_t bnx_nvram_getbyte(struct bnx_softc *, int, uint8_t *);
201 static int bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
202 static uint8_t bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
203 static int bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
205 static void bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
206 static void bnx_copper_link_upd(struct bnx_softc *, uint32_t);
207 static void bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
208 static void bnx_link_poll(struct bnx_softc *);
210 static int bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
211 static int bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
212 static int bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
213 static int bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
215 static void bnx_coal_change(struct bnx_softc *);
216 static int bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
217 static int bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
218 static int bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
219 static int bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
220 static int bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
221 static int bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
222 static int bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
225 static int bnx_msi_enable = 1;
226 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
228 static device_method_t bnx_methods[] = {
229 /* Device interface */
230 DEVMETHOD(device_probe, bnx_probe),
231 DEVMETHOD(device_attach, bnx_attach),
232 DEVMETHOD(device_detach, bnx_detach),
233 DEVMETHOD(device_shutdown, bnx_shutdown),
234 DEVMETHOD(device_suspend, bnx_suspend),
235 DEVMETHOD(device_resume, bnx_resume),
238 DEVMETHOD(bus_print_child, bus_generic_print_child),
239 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
242 DEVMETHOD(miibus_readreg, bnx_miibus_readreg),
243 DEVMETHOD(miibus_writereg, bnx_miibus_writereg),
244 DEVMETHOD(miibus_statchg, bnx_miibus_statchg),
249 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
250 static devclass_t bnx_devclass;
252 DECLARE_DUMMY_MODULE(if_bnx);
253 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
254 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
257 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
259 device_t dev = sc->bnx_dev;
262 if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
263 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
266 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
267 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
268 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
273 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
275 device_t dev = sc->bnx_dev;
277 if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
278 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
281 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
282 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
283 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
288 bnx_readreg_ind(struct bnx_softc *sc, uin32_t off)
290 device_t dev = sc->bnx_dev;
292 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
293 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
298 bnx_writereg_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
300 device_t dev = sc->bnx_dev;
302 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
303 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
307 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
309 CSR_WRITE_4(sc, off, val);
313 bnx_writembx(struct bnx_softc *sc, int off, int val)
315 if (sc->bnx_asicrev == BGE_ASICREV_BCM5906)
316 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
318 CSR_WRITE_4(sc, off, val);
322 bnx_nvram_getbyte(struct bnx_softc *sc, int addr, uint8_t *dest)
324 uint32_t access, byte = 0;
328 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
329 for (i = 0; i < 8000; i++) {
330 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
338 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
339 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
341 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
342 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
343 for (i = 0; i < BNX_TIMEOUT * 10; i++) {
345 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
351 if (i == BNX_TIMEOUT * 10) {
352 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
357 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
359 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
361 /* Disable access. */
362 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
365 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
366 CSR_READ_4(sc, BGE_NVRAM_SWARB);
372 * Read a sequence of bytes from NVRAM.
375 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
380 if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
383 for (i = 0; i < cnt; i++) {
384 err = bnx_nvram_getbyte(sc, off + i, &byte);
390 return (err ? 1 : 0);
394 * Read a byte of data stored in the EEPROM at address 'addr.' The
395 * BCM570x supports both the traditional bitbang interface and an
396 * auto access interface for reading the EEPROM. We use the auto
400 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
406 * Enable use of auto EEPROM access so we can avoid
407 * having to use the bitbang method.
409 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
411 /* Reset the EEPROM, load the clock period. */
412 CSR_WRITE_4(sc, BGE_EE_ADDR,
413 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
416 /* Issue the read EEPROM command. */
417 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
419 /* Wait for completion */
420 for(i = 0; i < BNX_TIMEOUT * 10; i++) {
422 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
426 if (i == BNX_TIMEOUT) {
427 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
432 byte = CSR_READ_4(sc, BGE_EE_DATA);
434 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
440 * Read a sequence of bytes from the EEPROM.
443 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
449 for (byte = 0, err = 0, i = 0; i < len; i++) {
450 err = bnx_eeprom_getbyte(sc, off + i, &byte);
460 bnx_miibus_readreg(device_t dev, int phy, int reg)
462 struct bnx_softc *sc = device_get_softc(dev);
466 KASSERT(phy == sc->bnx_phyno,
467 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
469 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
470 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
471 CSR_WRITE_4(sc, BGE_MI_MODE,
472 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
476 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
477 BGE_MIPHY(phy) | BGE_MIREG(reg));
479 /* Poll for the PHY register access to complete. */
480 for (i = 0; i < BNX_TIMEOUT; i++) {
482 val = CSR_READ_4(sc, BGE_MI_COMM);
483 if ((val & BGE_MICOMM_BUSY) == 0) {
485 val = CSR_READ_4(sc, BGE_MI_COMM);
489 if (i == BNX_TIMEOUT) {
490 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
491 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
495 /* Restore the autopoll bit if necessary. */
496 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
497 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
501 if (val & BGE_MICOMM_READFAIL)
504 return (val & 0xFFFF);
508 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
510 struct bnx_softc *sc = device_get_softc(dev);
513 KASSERT(phy == sc->bnx_phyno,
514 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
516 if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
517 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
520 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
521 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
522 CSR_WRITE_4(sc, BGE_MI_MODE,
523 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
527 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
528 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
530 for (i = 0; i < BNX_TIMEOUT; i++) {
532 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
534 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
538 if (i == BNX_TIMEOUT) {
539 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
540 "(phy %d, reg %d, val %d)\n", phy, reg, val);
543 /* Restore the autopoll bit if necessary. */
544 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
545 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
553 bnx_miibus_statchg(device_t dev)
555 struct bnx_softc *sc;
556 struct mii_data *mii;
558 sc = device_get_softc(dev);
559 mii = device_get_softc(sc->bnx_miibus);
561 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
562 (IFM_ACTIVE | IFM_AVALID)) {
563 switch (IFM_SUBTYPE(mii->mii_media_active)) {
571 if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
583 if (sc->bnx_link == 0)
586 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
587 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
588 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
589 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
591 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
594 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
595 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
597 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
602 * Memory management for jumbo frames.
605 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
607 struct ifnet *ifp = &sc->arpcom.ac_if;
608 struct bnx_jslot *entry;
614 * Create tag for jumbo mbufs.
615 * This is really a bit of a kludge. We allocate a special
616 * jumbo buffer pool which (thanks to the way our DMA
617 * memory allocation works) will consist of contiguous
618 * pages. This means that even though a jumbo buffer might
619 * be larger than a page size, we don't really need to
620 * map it into more than one DMA segment. However, the
621 * default mbuf tag will result in multi-segment mappings,
622 * so we have to create a special jumbo mbuf tag that
623 * lets us get away with mapping the jumbo buffers as
624 * a single segment. I think eventually the driver should
625 * be changed so that it uses ordinary mbufs and cluster
626 * buffers, i.e. jumbo frames can span multiple DMA
627 * descriptors. But that's a project for another day.
631 * Create DMA stuffs for jumbo RX ring.
633 error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
634 &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
635 &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
636 (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
637 &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
639 if_printf(ifp, "could not create jumbo RX ring\n");
644 * Create DMA stuffs for jumbo buffer block.
646 error = bnx_dma_block_alloc(sc, BNX_JMEM,
647 &sc->bnx_cdata.bnx_jumbo_tag,
648 &sc->bnx_cdata.bnx_jumbo_map,
649 (void **)&sc->bnx_ldata.bnx_jumbo_buf,
652 if_printf(ifp, "could not create jumbo buffer\n");
656 SLIST_INIT(&sc->bnx_jfree_listhead);
659 * Now divide it up into 9K pieces and save the addresses
660 * in an array. Note that we play an evil trick here by using
661 * the first few bytes in the buffer to hold the the address
662 * of the softc structure for this interface. This is because
663 * bnx_jfree() needs it, but it is called by the mbuf management
664 * code which will not pass it to us explicitly.
666 for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
667 entry = &sc->bnx_cdata.bnx_jslots[i];
669 entry->bnx_buf = ptr;
670 entry->bnx_paddr = paddr;
671 entry->bnx_inuse = 0;
673 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
682 bnx_free_jumbo_mem(struct bnx_softc *sc)
684 /* Destroy jumbo RX ring. */
685 bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
686 sc->bnx_cdata.bnx_rx_jumbo_ring_map,
687 sc->bnx_ldata.bnx_rx_jumbo_ring);
689 /* Destroy jumbo buffer block. */
690 bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
691 sc->bnx_cdata.bnx_jumbo_map,
692 sc->bnx_ldata.bnx_jumbo_buf);
696 * Allocate a jumbo buffer.
698 static struct bnx_jslot *
699 bnx_jalloc(struct bnx_softc *sc)
701 struct bnx_jslot *entry;
703 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
704 entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
706 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
707 entry->bnx_inuse = 1;
709 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
711 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
716 * Adjust usage count on a jumbo buffer.
721 struct bnx_jslot *entry = (struct bnx_jslot *)arg;
722 struct bnx_softc *sc = entry->bnx_sc;
725 panic("bnx_jref: can't find softc pointer!");
727 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
728 panic("bnx_jref: asked to reference buffer "
729 "that we don't manage!");
730 } else if (entry->bnx_inuse == 0) {
731 panic("bnx_jref: buffer already free!");
733 atomic_add_int(&entry->bnx_inuse, 1);
738 * Release a jumbo buffer.
743 struct bnx_jslot *entry = (struct bnx_jslot *)arg;
744 struct bnx_softc *sc = entry->bnx_sc;
747 panic("bnx_jfree: can't find softc pointer!");
749 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
750 panic("bnx_jfree: asked to free buffer that we don't manage!");
751 } else if (entry->bnx_inuse == 0) {
752 panic("bnx_jfree: buffer already free!");
755 * Possible MP race to 0, use the serializer. The atomic insn
756 * is still needed for races against bnx_jref().
758 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
759 atomic_subtract_int(&entry->bnx_inuse, 1);
760 if (entry->bnx_inuse == 0) {
761 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
764 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
770 * Intialize a standard receive ring descriptor.
773 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
775 struct mbuf *m_new = NULL;
776 bus_dma_segment_t seg;
780 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
783 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
784 m_adj(m_new, ETHER_ALIGN);
786 error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
787 sc->bnx_cdata.bnx_rx_tmpmap, m_new,
788 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
795 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
796 sc->bnx_cdata.bnx_rx_std_dmamap[i],
797 BUS_DMASYNC_POSTREAD);
798 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
799 sc->bnx_cdata.bnx_rx_std_dmamap[i]);
802 map = sc->bnx_cdata.bnx_rx_tmpmap;
803 sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
804 sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
806 sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
807 sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
809 bnx_setup_rxdesc_std(sc, i);
814 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
816 struct bnx_rxchain *rc;
819 rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
820 r = &sc->bnx_ldata.bnx_rx_std_ring[i];
822 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
823 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
824 r->bge_len = rc->bnx_mbuf->m_len;
826 r->bge_flags = BGE_RXBDFLAG_END;
830 * Initialize a jumbo receive ring descriptor. This allocates
831 * a jumbo buffer from the pool managed internally by the driver.
834 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
836 struct mbuf *m_new = NULL;
837 struct bnx_jslot *buf;
840 /* Allocate the mbuf. */
841 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
845 /* Allocate the jumbo buffer */
846 buf = bnx_jalloc(sc);
852 /* Attach the buffer to the mbuf. */
853 m_new->m_ext.ext_arg = buf;
854 m_new->m_ext.ext_buf = buf->bnx_buf;
855 m_new->m_ext.ext_free = bnx_jfree;
856 m_new->m_ext.ext_ref = bnx_jref;
857 m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
859 m_new->m_flags |= M_EXT;
861 m_new->m_data = m_new->m_ext.ext_buf;
862 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
864 paddr = buf->bnx_paddr;
865 m_adj(m_new, ETHER_ALIGN);
866 paddr += ETHER_ALIGN;
868 /* Save necessary information */
869 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
870 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
872 /* Set up the descriptor. */
873 bnx_setup_rxdesc_jumbo(sc, i);
878 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
881 struct bnx_rxchain *rc;
883 r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
884 rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
886 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
887 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
888 r->bge_len = rc->bnx_mbuf->m_len;
890 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
894 bnx_init_rx_ring_std(struct bnx_softc *sc)
898 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
899 error = bnx_newbuf_std(sc, i, 1);
904 sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
905 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
911 bnx_free_rx_ring_std(struct bnx_softc *sc)
915 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
916 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
918 if (rc->bnx_mbuf != NULL) {
919 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
920 sc->bnx_cdata.bnx_rx_std_dmamap[i]);
921 m_freem(rc->bnx_mbuf);
924 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
925 sizeof(struct bge_rx_bd));
930 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
935 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
936 error = bnx_newbuf_jumbo(sc, i, 1);
941 sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
943 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
944 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
945 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
947 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
953 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
957 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
958 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
960 if (rc->bnx_mbuf != NULL) {
961 m_freem(rc->bnx_mbuf);
964 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
965 sizeof(struct bge_rx_bd));
970 bnx_free_tx_ring(struct bnx_softc *sc)
974 for (i = 0; i < BGE_TX_RING_CNT; i++) {
975 if (sc->bnx_cdata.bnx_tx_chain[i] != NULL) {
976 bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
977 sc->bnx_cdata.bnx_tx_dmamap[i]);
978 m_freem(sc->bnx_cdata.bnx_tx_chain[i]);
979 sc->bnx_cdata.bnx_tx_chain[i] = NULL;
981 bzero(&sc->bnx_ldata.bnx_tx_ring[i],
982 sizeof(struct bge_tx_bd));
987 bnx_init_tx_ring(struct bnx_softc *sc)
990 sc->bnx_tx_saved_considx = 0;
991 sc->bnx_tx_prodidx = 0;
993 /* Initialize transmit producer index for host-memory send ring. */
994 bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bnx_tx_prodidx);
995 bnx_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1001 bnx_setmulti(struct bnx_softc *sc)
1004 struct ifmultiaddr *ifma;
1005 uint32_t hashes[4] = { 0, 0, 0, 0 };
1008 ifp = &sc->arpcom.ac_if;
1010 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1011 for (i = 0; i < 4; i++)
1012 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1016 /* First, zot all the existing filters. */
1017 for (i = 0; i < 4; i++)
1018 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1020 /* Now program new ones. */
1021 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1022 if (ifma->ifma_addr->sa_family != AF_LINK)
1025 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1026 ETHER_ADDR_LEN) & 0x7f;
1027 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1030 for (i = 0; i < 4; i++)
1031 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1035 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1036 * self-test results.
1039 bnx_chipinit(struct bnx_softc *sc)
1041 uint32_t dma_rw_ctl, mode_ctl;
1044 /* Set endian type before we access any non-PCI registers. */
1045 pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1046 BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1048 /* Clear the MAC control register */
1049 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1052 * Clear the MAC statistics block in the NIC's
1055 for (i = BGE_STATS_BLOCK;
1056 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1057 BNX_MEMWIN_WRITE(sc, i, 0);
1059 for (i = BGE_STATUS_BLOCK;
1060 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1061 BNX_MEMWIN_WRITE(sc, i, 0);
1063 if (BNX_IS_57765_FAMILY(sc)) {
1066 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1067 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1068 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1070 /* Access the lower 1K of PL PCI-E block registers. */
1071 CSR_WRITE_4(sc, BGE_MODE_CTL,
1072 val | BGE_MODECTL_PCIE_PL_SEL);
1074 val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1075 val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1076 CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1078 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1080 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1081 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1082 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1084 /* Access the lower 1K of DL PCI-E block registers. */
1085 CSR_WRITE_4(sc, BGE_MODE_CTL,
1086 val | BGE_MODECTL_PCIE_DL_SEL);
1088 val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1089 val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1090 val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1091 CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1093 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1096 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1097 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1098 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1099 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1103 * Set up the PCI DMA control register.
1105 dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1107 * Disable 32bytes cache alignment for DMA write to host memory
1110 * 64bytes cache alignment for DMA write to host memory is still
1113 dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1114 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1115 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1117 * Enable HW workaround for controllers that misinterpret
1118 * a status tag update and leave interrupts permanently
1121 if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1122 !BNX_IS_57765_FAMILY(sc))
1123 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1125 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1128 pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1131 * Set up general mode register.
1133 mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1134 BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1135 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1138 * Disable memory write invalidate. Apparently it is not supported
1139 * properly by these devices. Also ensure that INTx isn't disabled,
1140 * as these chips need it even when using MSI.
1142 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1143 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1145 /* Set the timer prescaler (always 66Mhz) */
1146 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1148 if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1149 DELAY(40); /* XXX */
1151 /* Put PHY into ready state */
1152 BNX_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1153 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1161 bnx_blockinit(struct bnx_softc *sc)
1163 struct bge_rcb *rcb;
1170 * Initialize the memory window pointer register so that
1171 * we can access the first 32K of internal NIC RAM. This will
1172 * allow us to set up the TX send ring RCBs and the RX return
1173 * ring RCBs, plus other things which live in NIC memory.
1175 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1177 /* Configure mbuf pool watermarks */
1178 if (BNX_IS_57765_PLUS(sc)) {
1179 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1180 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1181 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1182 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1184 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1185 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1187 } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1188 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1189 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1190 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1192 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1193 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1194 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1197 /* Configure DMA resource watermarks */
1198 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1199 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1201 /* Enable buffer manager */
1202 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1204 * Change the arbitration algorithm of TXMBUF read request to
1205 * round-robin instead of priority based for BCM5719. When
1206 * TXFIFO is almost empty, RDMA will hold its request until
1207 * TXFIFO is not almost empty.
1209 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1210 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1211 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1212 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1213 sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1214 val |= BGE_BMANMODE_LOMBUF_ATTN;
1215 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1217 /* Poll for buffer manager start indication */
1218 for (i = 0; i < BNX_TIMEOUT; i++) {
1219 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1224 if (i == BNX_TIMEOUT) {
1225 if_printf(&sc->arpcom.ac_if,
1226 "buffer manager failed to start\n");
1230 /* Enable flow-through queues */
1231 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1232 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1234 /* Wait until queue initialization is complete */
1235 for (i = 0; i < BNX_TIMEOUT; i++) {
1236 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1241 if (i == BNX_TIMEOUT) {
1242 if_printf(&sc->arpcom.ac_if,
1243 "flow-through queue init failed\n");
1248 * Summary of rings supported by the controller:
1250 * Standard Receive Producer Ring
1251 * - This ring is used to feed receive buffers for "standard"
1252 * sized frames (typically 1536 bytes) to the controller.
1254 * Jumbo Receive Producer Ring
1255 * - This ring is used to feed receive buffers for jumbo sized
1256 * frames (i.e. anything bigger than the "standard" frames)
1257 * to the controller.
1259 * Mini Receive Producer Ring
1260 * - This ring is used to feed receive buffers for "mini"
1261 * sized frames to the controller.
1262 * - This feature required external memory for the controller
1263 * but was never used in a production system. Should always
1266 * Receive Return Ring
1267 * - After the controller has placed an incoming frame into a
1268 * receive buffer that buffer is moved into a receive return
1269 * ring. The driver is then responsible to passing the
1270 * buffer up to the stack. Many versions of the controller
1271 * support multiple RR rings.
1274 * - This ring is used for outgoing frames. Many versions of
1275 * the controller support multiple send rings.
1278 /* Initialize the standard receive producer ring control block. */
1279 rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1280 rcb->bge_hostaddr.bge_addr_lo =
1281 BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1282 rcb->bge_hostaddr.bge_addr_hi =
1283 BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1284 if (BNX_IS_57765_PLUS(sc)) {
1286 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1287 * Bits 15-2 : Maximum RX frame size
1288 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
1291 rcb->bge_maxlen_flags =
1292 BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1295 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1296 * Bits 15-2 : Reserved (should be 0)
1297 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1300 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1302 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1303 sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1304 sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1305 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1307 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1308 /* Write the standard receive producer ring control block. */
1309 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1310 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1311 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1312 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1313 /* Reset the standard receive producer ring producer index. */
1314 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1317 * Initialize the jumbo RX producer ring control
1318 * block. We set the 'ring disabled' bit in the
1319 * flags field until we're actually ready to start
1320 * using this ring (i.e. once we set the MTU
1321 * high enough to require it).
1323 if (BNX_IS_JUMBO_CAPABLE(sc)) {
1324 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1325 /* Get the jumbo receive producer ring RCB parameters. */
1326 rcb->bge_hostaddr.bge_addr_lo =
1327 BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1328 rcb->bge_hostaddr.bge_addr_hi =
1329 BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1330 rcb->bge_maxlen_flags =
1331 BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1332 BGE_RCB_FLAG_RING_DISABLED);
1333 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1334 sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1335 sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1336 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1338 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1339 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1340 rcb->bge_hostaddr.bge_addr_hi);
1341 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1342 rcb->bge_hostaddr.bge_addr_lo);
1343 /* Program the jumbo receive producer ring RCB parameters. */
1344 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1345 rcb->bge_maxlen_flags);
1346 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1347 /* Reset the jumbo receive producer ring producer index. */
1348 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1351 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1352 if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
1353 (sc->bnx_chipid == BGE_CHIPID_BCM5906_A0 ||
1354 sc->bnx_chipid == BGE_CHIPID_BCM5906_A1 ||
1355 sc->bnx_chipid == BGE_CHIPID_BCM5906_A2)) {
1356 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1357 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1361 * The BD ring replenish thresholds control how often the
1362 * hardware fetches new BD's from the producer rings in host
1363 * memory. Setting the value too low on a busy system can
1364 * starve the hardware and recue the throughpout.
1366 * Set the BD ring replentish thresholds. The recommended
1367 * values are 1/8th the number of descriptors allocated to
1371 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1372 if (BNX_IS_JUMBO_CAPABLE(sc)) {
1373 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1374 BGE_JUMBO_RX_RING_CNT/8);
1376 if (BNX_IS_57765_PLUS(sc)) {
1377 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1378 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1382 * Disable all send rings by setting the 'ring disabled' bit
1383 * in the flags field of all the TX send ring control blocks,
1384 * located in NIC memory.
1386 if (BNX_IS_5717_PLUS(sc))
1388 else if (BNX_IS_57765_FAMILY(sc))
1392 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1393 for (i = 0; i < limit; i++) {
1394 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1395 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1396 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1397 vrcb += sizeof(struct bge_rcb);
1400 /* Configure send ring RCB 0 (we use only the first ring) */
1401 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1402 BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_tx_ring_paddr);
1403 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1404 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1405 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1406 sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1407 sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1408 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1410 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1411 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1413 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1414 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1417 * Disable all receive return rings by setting the
1418 * 'ring disabled' bit in the flags field of all the receive
1419 * return ring control blocks, located in NIC memory.
1421 if (BNX_IS_5717_PLUS(sc)) {
1422 /* Should be 17, use 16 until we get an SRAM map. */
1424 } else if (BNX_IS_57765_FAMILY(sc)) {
1429 /* Disable all receive return rings. */
1430 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1431 for (i = 0; i < limit; i++) {
1432 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1433 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1434 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1435 BGE_RCB_FLAG_RING_DISABLED);
1436 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1437 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1438 (i * (sizeof(uint64_t))), 0);
1439 vrcb += sizeof(struct bge_rcb);
1443 * Set up receive return ring 0. Note that the NIC address
1444 * for RX return rings is 0x0. The return rings live entirely
1445 * within the host, so the nicaddr field in the RCB isn't used.
1447 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1448 BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1449 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1450 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1451 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1452 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1453 BGE_RCB_MAXLEN_FLAGS(sc->bnx_return_ring_cnt, 0));
1455 /* Set random backoff seed for TX */
1456 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1457 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1458 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1459 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1460 BGE_TX_BACKOFF_SEED_MASK);
1462 /* Set inter-packet gap */
1464 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1465 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1466 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1468 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1471 * Specify which ring to use for packets that don't match
1474 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1477 * Configure number of RX lists. One interrupt distribution
1478 * list, sixteen active lists, one bad frames class.
1480 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1482 /* Inialize RX list placement stats mask. */
1483 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1484 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1486 /* Disable host coalescing until we get it set up */
1487 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1489 /* Poll to make sure it's shut down. */
1490 for (i = 0; i < BNX_TIMEOUT; i++) {
1491 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1496 if (i == BNX_TIMEOUT) {
1497 if_printf(&sc->arpcom.ac_if,
1498 "host coalescing engine failed to idle\n");
1502 /* Set up host coalescing defaults */
1503 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1504 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1505 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1506 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1507 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1508 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1510 /* Set up address of status block */
1511 bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1512 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1513 BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1514 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1515 BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1517 /* Set up status block partail update size. */
1518 val = BGE_STATBLKSZ_32BYTE;
1521 * Does not seem to have visible effect in both
1522 * bulk data (1472B UDP datagram) and tiny data
1523 * (18B UDP datagram) TX tests.
1525 val |= BGE_HCCMODE_CLRTICK_TX;
1527 /* Turn on host coalescing state machine */
1528 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1530 /* Turn on RX BD completion state machine and enable attentions */
1531 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1532 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1534 /* Turn on RX list placement state machine */
1535 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1537 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1538 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1539 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1540 BGE_MACMODE_FRMHDR_DMA_ENB;
1542 if (sc->bnx_flags & BNX_FLAG_TBI)
1543 val |= BGE_PORTMODE_TBI;
1544 else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1545 val |= BGE_PORTMODE_GMII;
1547 val |= BGE_PORTMODE_MII;
1549 /* Turn on DMA, clear stats */
1550 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1552 /* Set misc. local control, enable interrupts on attentions */
1553 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1556 /* Assert GPIO pins for PHY reset */
1557 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1558 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1559 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1560 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1563 /* Turn on write DMA state machine */
1564 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1565 /* Enable host coalescing bug fix. */
1566 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1567 if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1568 /* Request larger DMA burst size to get better performance. */
1569 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1571 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1574 if (BNX_IS_57765_PLUS(sc)) {
1577 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1579 * Adjust tx margin to prevent TX data corruption and
1580 * fix internal FIFO overflow.
1582 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1583 sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1584 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1585 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1586 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1587 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1588 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1589 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1592 * Enable fix for read DMA FIFO overruns.
1593 * The fix is to limit the number of RX BDs
1594 * the hardware would fetch at a fime.
1596 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1597 dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1600 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1601 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1602 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1603 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1604 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1605 } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1607 * Allow 4KB burst length reads for non-LSO frames.
1608 * Enable 512B burst length reads for buffer descriptors.
1610 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1611 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1612 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1613 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1616 /* Turn on read DMA state machine */
1617 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1618 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1619 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1620 if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1621 sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1622 sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1623 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1624 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1625 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1627 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1628 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1629 BGE_RDMAMODE_H2BNC_VLAN_DET;
1631 * Allow multiple outstanding read requests from
1632 * non-LSO read DMA engine.
1634 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1636 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1637 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1640 /* Turn on RX data completion state machine */
1641 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1643 /* Turn on RX BD initiator state machine */
1644 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1646 /* Turn on RX data and RX BD initiator state machine */
1647 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1649 /* Turn on send BD completion state machine */
1650 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1652 /* Turn on send data completion state machine */
1653 val = BGE_SDCMODE_ENABLE;
1654 if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1655 val |= BGE_SDCMODE_CDELAY;
1656 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1658 /* Turn on send data initiator state machine */
1659 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1661 /* Turn on send BD initiator state machine */
1662 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1664 /* Turn on send BD selector state machine */
1665 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1667 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1668 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1669 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1671 /* ack/clear link change events */
1672 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1673 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1674 BGE_MACSTAT_LINK_CHANGED);
1675 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1678 * Enable attention when the link has changed state for
1679 * devices that use auto polling.
1681 if (sc->bnx_flags & BNX_FLAG_TBI) {
1682 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1684 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1685 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1691 * Clear any pending link state attention.
1692 * Otherwise some link state change events may be lost until attention
1693 * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1694 * It's not necessary on newer BCM chips - perhaps enabling link
1695 * state change attentions implies clearing pending attention.
1697 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1698 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1699 BGE_MACSTAT_LINK_CHANGED);
1701 /* Enable link state change attentions. */
1702 BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1708 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1709 * against our list and return its name if we find a match. Note
1710 * that since the Broadcom controller contains VPD support, we
1711 * can get the device name string from the controller itself instead
1712 * of the compiled-in string. This is a little slow, but it guarantees
1713 * we'll always announce the right product name.
1716 bnx_probe(device_t dev)
1718 const struct bnx_type *t;
1719 uint16_t product, vendor;
1721 if (!pci_is_pcie(dev))
1724 product = pci_get_device(dev);
1725 vendor = pci_get_vendor(dev);
1727 for (t = bnx_devs; t->bnx_name != NULL; t++) {
1728 if (vendor == t->bnx_vid && product == t->bnx_did)
1731 if (t->bnx_name == NULL)
1734 device_set_desc(dev, t->bnx_name);
1739 bnx_attach(device_t dev)
1742 struct bnx_softc *sc;
1743 uint32_t hwcfg = 0, misccfg;
1744 int error = 0, rid, capmask;
1745 uint8_t ether_addr[ETHER_ADDR_LEN];
1746 uint16_t product, vendor;
1747 driver_intr_t *intr_func;
1748 uintptr_t mii_priv = 0;
1751 sc = device_get_softc(dev);
1753 callout_init(&sc->bnx_stat_timer);
1754 lwkt_serialize_init(&sc->bnx_jslot_serializer);
1756 product = pci_get_device(dev);
1757 vendor = pci_get_vendor(dev);
1759 #ifndef BURN_BRIDGES
1760 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1763 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1764 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1766 device_printf(dev, "chip is in D%d power mode "
1767 "-- setting to D0\n", pci_get_powerstate(dev));
1769 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1771 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1772 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1774 #endif /* !BURN_BRIDGE */
1777 * Map control/status registers.
1779 pci_enable_busmaster(dev);
1782 sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1785 if (sc->bnx_res == NULL) {
1786 device_printf(dev, "couldn't map memory\n");
1790 sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1791 sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1793 /* Save various chip information */
1795 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1796 BGE_PCIMISCCTL_ASICREV_SHIFT;
1797 if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1798 /* All chips having dedicated ASICREV register have CPMU */
1799 sc->bnx_flags |= BNX_FLAG_CPMU;
1802 case PCI_PRODUCT_BROADCOM_BCM5717:
1803 case PCI_PRODUCT_BROADCOM_BCM5718:
1804 case PCI_PRODUCT_BROADCOM_BCM5719:
1805 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1806 sc->bnx_chipid = pci_read_config(dev,
1807 BGE_PCI_GEN2_PRODID_ASICREV, 4);
1810 case PCI_PRODUCT_BROADCOM_BCM57761:
1811 case PCI_PRODUCT_BROADCOM_BCM57762:
1812 case PCI_PRODUCT_BROADCOM_BCM57765:
1813 case PCI_PRODUCT_BROADCOM_BCM57766:
1814 case PCI_PRODUCT_BROADCOM_BCM57781:
1815 case PCI_PRODUCT_BROADCOM_BCM57782:
1816 case PCI_PRODUCT_BROADCOM_BCM57785:
1817 case PCI_PRODUCT_BROADCOM_BCM57786:
1818 case PCI_PRODUCT_BROADCOM_BCM57791:
1819 case PCI_PRODUCT_BROADCOM_BCM57795:
1820 sc->bnx_chipid = pci_read_config(dev,
1821 BGE_PCI_GEN15_PRODID_ASICREV, 4);
1825 sc->bnx_chipid = pci_read_config(dev,
1826 BGE_PCI_PRODID_ASICREV, 4);
1830 sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1831 sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1833 switch (sc->bnx_asicrev) {
1834 case BGE_ASICREV_BCM5717:
1835 case BGE_ASICREV_BCM5719:
1836 case BGE_ASICREV_BCM5720:
1837 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1840 case BGE_ASICREV_BCM57765:
1841 case BGE_ASICREV_BCM57766:
1842 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1845 sc->bnx_flags |= BNX_FLAG_SHORTDMA;
1847 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
1849 sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1850 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1851 sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1852 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1854 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1855 device_printf(dev, "CHIP ID 0x%08x; "
1856 "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1857 sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1860 * Set various PHY quirk flags.
1863 capmask = MII_CAPMASK_DEFAULT;
1864 if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1865 product == PCI_PRODUCT_BROADCOM_BCM57795) {
1867 capmask &= ~BMSR_EXTSTAT;
1870 mii_priv |= BRGPHY_FLAG_WIRESPEED;
1873 * Allocate interrupt
1875 sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1878 sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1880 if (sc->bnx_irq == NULL) {
1881 device_printf(dev, "couldn't map interrupt\n");
1886 if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1887 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1891 /* Initialize if_name earlier, so if_printf could be used */
1892 ifp = &sc->arpcom.ac_if;
1893 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1895 /* Try to reset the chip. */
1898 if (bnx_chipinit(sc)) {
1899 device_printf(dev, "chip initialization failed\n");
1905 * Get station address
1907 error = bnx_get_eaddr(sc, ether_addr);
1909 device_printf(dev, "failed to read station address\n");
1913 if (BNX_IS_57765_PLUS(sc)) {
1914 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT;
1916 /* 5705/5750 limits RX return ring to 512 entries. */
1917 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1920 error = bnx_dma_alloc(sc);
1924 /* Set default tuneable values. */
1925 sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1926 sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1927 sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1928 sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1929 sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_DEF;
1930 sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_DEF;
1932 /* Set up ifnet structure */
1934 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1935 ifp->if_ioctl = bnx_ioctl;
1936 ifp->if_start = bnx_start;
1937 #ifdef DEVICE_POLLING
1938 ifp->if_poll = bnx_poll;
1940 ifp->if_watchdog = bnx_watchdog;
1941 ifp->if_init = bnx_init;
1942 ifp->if_mtu = ETHERMTU;
1943 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1944 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1945 ifq_set_ready(&ifp->if_snd);
1947 ifp->if_capabilities |= IFCAP_HWCSUM;
1948 ifp->if_hwassist = BNX_CSUM_FEATURES;
1949 ifp->if_capenable = ifp->if_capabilities;
1952 * Figure out what sort of media we have by checking the
1953 * hardware config word in the first 32k of NIC internal memory,
1954 * or fall back to examining the EEPROM if necessary.
1955 * Note: on some BCM5700 cards, this value appears to be unset.
1956 * If that's the case, we have to rely on identifying the NIC
1957 * by its PCI subsystem ID, as we do below for the SysKonnect
1960 if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1961 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1963 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1965 device_printf(dev, "failed to read EEPROM\n");
1969 hwcfg = ntohl(hwcfg);
1972 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1973 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1974 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1975 sc->bnx_flags |= BNX_FLAG_TBI;
1978 if (sc->bnx_flags & BNX_FLAG_CPMU)
1979 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1981 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1983 /* Setup link status update stuffs */
1984 if (sc->bnx_flags & BNX_FLAG_TBI) {
1985 sc->bnx_link_upd = bnx_tbi_link_upd;
1986 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1987 } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1988 sc->bnx_link_upd = bnx_autopoll_link_upd;
1989 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1991 sc->bnx_link_upd = bnx_copper_link_upd;
1992 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1995 /* Set default PHY address */
1999 * PHY address mapping for various devices.
2001 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2002 * ---------+-------+-------+-------+-------+
2003 * BCM57XX | 1 | X | X | X |
2004 * BCM5704 | 1 | X | 1 | X |
2005 * BCM5717 | 1 | 8 | 2 | 9 |
2006 * BCM5719 | 1 | 8 | 2 | 9 |
2007 * BCM5720 | 1 | 8 | 2 | 9 |
2009 * Other addresses may respond but they are not
2010 * IEEE compliant PHYs and should be ignored.
2012 if (BNX_IS_5717_PLUS(sc)) {
2015 f = pci_get_function(dev);
2016 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2017 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2018 BGE_SGDIGSTS_IS_SERDES)
2019 sc->bnx_phyno = f + 8;
2021 sc->bnx_phyno = f + 1;
2023 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2024 BGE_CPMU_PHY_STRAP_IS_SERDES)
2025 sc->bnx_phyno = f + 8;
2027 sc->bnx_phyno = f + 1;
2031 if (sc->bnx_flags & BNX_FLAG_TBI) {
2032 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2033 bnx_ifmedia_upd, bnx_ifmedia_sts);
2034 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2035 ifmedia_add(&sc->bnx_ifmedia,
2036 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2037 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2038 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2039 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2041 struct mii_probe_args mii_args;
2043 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2044 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2045 mii_args.mii_capmask = capmask;
2046 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2047 mii_args.mii_priv = mii_priv;
2049 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2051 device_printf(dev, "MII without any PHY!\n");
2057 * Create sysctl nodes.
2059 sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2060 sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2061 SYSCTL_STATIC_CHILDREN(_hw),
2063 device_get_nameunit(dev),
2065 if (sc->bnx_sysctl_tree == NULL) {
2066 device_printf(dev, "can't add sysctl node\n");
2071 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2072 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2073 OID_AUTO, "rx_coal_ticks",
2074 CTLTYPE_INT | CTLFLAG_RW,
2075 sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2076 "Receive coalescing ticks (usec).");
2077 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2078 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2079 OID_AUTO, "tx_coal_ticks",
2080 CTLTYPE_INT | CTLFLAG_RW,
2081 sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2082 "Transmit coalescing ticks (usec).");
2083 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2084 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2085 OID_AUTO, "rx_coal_bds",
2086 CTLTYPE_INT | CTLFLAG_RW,
2087 sc, 0, bnx_sysctl_rx_coal_bds, "I",
2088 "Receive max coalesced BD count.");
2089 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2090 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2091 OID_AUTO, "tx_coal_bds",
2092 CTLTYPE_INT | CTLFLAG_RW,
2093 sc, 0, bnx_sysctl_tx_coal_bds, "I",
2094 "Transmit max coalesced BD count.");
2096 * A common design characteristic for many Broadcom
2097 * client controllers is that they only support a
2098 * single outstanding DMA read operation on the PCIe
2099 * bus. This means that it will take twice as long to
2100 * fetch a TX frame that is split into header and
2101 * payload buffers as it does to fetch a single,
2102 * contiguous TX frame (2 reads vs. 1 read). For these
2103 * controllers, coalescing buffers to reduce the number
2104 * of memory reads is effective way to get maximum
2105 * performance(about 940Mbps). Without collapsing TX
2106 * buffers the maximum TCP bulk transfer performance
2107 * is about 850Mbps. However forcing coalescing mbufs
2108 * consumes a lot of CPU cycles, so leave it off by
2111 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2112 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2113 "force_defrag", CTLFLAG_RW, &sc->bnx_force_defrag, 0,
2114 "Force defragment on TX path");
2116 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2117 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2118 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2119 sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2120 "Receive max coalesced BD count during interrupt.");
2121 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2122 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2123 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2124 sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2125 "Transmit max coalesced BD count during interrupt.");
2128 * Call MI attach routine.
2130 ether_ifattach(ifp, ether_addr, NULL);
2132 if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2133 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2134 intr_func = bnx_msi_oneshot;
2136 device_printf(dev, "oneshot MSI\n");
2138 intr_func = bnx_msi;
2141 intr_func = bnx_intr_legacy;
2143 error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2144 &sc->bnx_intrhand, ifp->if_serializer);
2146 ether_ifdetach(ifp);
2147 device_printf(dev, "couldn't set up irq\n");
2151 ifp->if_cpuid = rman_get_cpuid(sc->bnx_irq);
2152 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2161 bnx_detach(device_t dev)
2163 struct bnx_softc *sc = device_get_softc(dev);
2165 if (device_is_attached(dev)) {
2166 struct ifnet *ifp = &sc->arpcom.ac_if;
2168 lwkt_serialize_enter(ifp->if_serializer);
2171 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2172 lwkt_serialize_exit(ifp->if_serializer);
2174 ether_ifdetach(ifp);
2177 if (sc->bnx_flags & BNX_FLAG_TBI)
2178 ifmedia_removeall(&sc->bnx_ifmedia);
2180 device_delete_child(dev, sc->bnx_miibus);
2181 bus_generic_detach(dev);
2183 if (sc->bnx_irq != NULL) {
2184 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2187 if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2188 pci_release_msi(dev);
2190 if (sc->bnx_res != NULL) {
2191 bus_release_resource(dev, SYS_RES_MEMORY,
2192 BGE_PCI_BAR0, sc->bnx_res);
2195 if (sc->bnx_sysctl_tree != NULL)
2196 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2204 bnx_reset(struct bnx_softc *sc)
2207 uint32_t cachesize, command, pcistate, reset;
2208 void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2214 if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
2215 write_op = bnx_writemem_direct;
2217 write_op = bnx_writereg_ind;
2219 /* Save some important PCI state. */
2220 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2221 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2222 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2224 pci_write_config(dev, BGE_PCI_MISC_CTL,
2225 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2226 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2227 BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2229 /* Disable fastboot on controllers that support it. */
2231 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2232 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2235 * Write the magic number to SRAM at offset 0xB50.
2236 * When firmware finishes its initialization it will
2237 * write ~BGE_MAGIC_NUMBER to the same location.
2239 bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2241 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2243 /* XXX: Broadcom Linux driver. */
2244 /* Force PCI-E 1.0a mode */
2245 if (!BNX_IS_57765_PLUS(sc) &&
2246 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2247 (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2248 BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2249 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2250 BGE_PCIE_PHY_TSTCTL_PSCRAM);
2252 if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2253 /* Prevent PCIE link training during global reset */
2254 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2259 * Set GPHY Power Down Override to leave GPHY
2260 * powered up in D0 uninitialized.
2262 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2263 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2265 /* Issue global reset */
2266 write_op(sc, BGE_MISC_CFG, reset);
2268 if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2269 uint32_t status, ctrl;
2271 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2272 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2273 status | BGE_VCPU_STATUS_DRV_RESET);
2274 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2275 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2276 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2281 /* XXX: Broadcom Linux driver. */
2282 if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2285 DELAY(500000); /* wait for link training to complete */
2286 v = pci_read_config(dev, 0xc4, 4);
2287 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2290 devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2292 /* Disable no snoop and disable relaxed ordering. */
2293 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2295 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2296 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2297 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2298 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2301 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2304 /* Clear error status. */
2305 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2306 PCIEM_DEVSTS_CORR_ERR |
2307 PCIEM_DEVSTS_NFATAL_ERR |
2308 PCIEM_DEVSTS_FATAL_ERR |
2309 PCIEM_DEVSTS_UNSUPP_REQ, 2);
2311 /* Reset some of the PCI state that got zapped by reset */
2312 pci_write_config(dev, BGE_PCI_MISC_CTL,
2313 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2314 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2315 BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2316 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2317 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2318 write_op(sc, BGE_MISC_CFG, (65 << 1));
2320 /* Enable memory arbiter */
2321 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2323 if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2324 for (i = 0; i < BNX_TIMEOUT; i++) {
2325 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2326 if (val & BGE_VCPU_STATUS_INIT_DONE)
2330 if (i == BNX_TIMEOUT) {
2331 if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2336 * Poll until we see the 1's complement of the magic number.
2337 * This indicates that the firmware initialization
2340 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2341 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2342 if (val == ~BGE_MAGIC_NUMBER)
2346 if (i == BNX_FIRMWARE_TIMEOUT) {
2347 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2348 "timed out, found 0x%08x\n", val);
2351 /* BCM57765 A0 needs additional time before accessing. */
2352 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2357 * XXX Wait for the value of the PCISTATE register to
2358 * return to its original pre-reset state. This is a
2359 * fairly good indicator of reset completion. If we don't
2360 * wait for the reset to fully complete, trying to read
2361 * from the device's non-PCI registers may yield garbage
2364 for (i = 0; i < BNX_TIMEOUT; i++) {
2365 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2370 /* Fix up byte swapping */
2371 CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2373 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2376 * The 5704 in TBI mode apparently needs some special
2377 * adjustment to insure the SERDES drive level is set
2380 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2381 (sc->bnx_flags & BNX_FLAG_TBI)) {
2384 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2385 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2386 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2389 /* XXX: Broadcom Linux driver. */
2390 if (!BNX_IS_57765_PLUS(sc)) {
2393 /* Enable Data FIFO protection. */
2394 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2395 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2400 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2401 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2402 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2407 * Frame reception handling. This is called if there's a frame
2408 * on the receive return list.
2410 * Note: we have to be able to handle two possibilities here:
2411 * 1) the frame is from the jumbo recieve ring
2412 * 2) the frame is from the standard receive ring
2416 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod)
2419 int stdcnt = 0, jumbocnt = 0;
2421 ifp = &sc->arpcom.ac_if;
2423 while (sc->bnx_rx_saved_considx != rx_prod) {
2424 struct bge_rx_bd *cur_rx;
2426 struct mbuf *m = NULL;
2427 uint16_t vlan_tag = 0;
2431 &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2433 rxidx = cur_rx->bge_idx;
2434 BNX_INC(sc->bnx_rx_saved_considx, sc->bnx_return_ring_cnt);
2436 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2438 vlan_tag = cur_rx->bge_vlan_tag;
2441 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2442 BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2445 if (rxidx != sc->bnx_jumbo) {
2447 if_printf(ifp, "sw jumbo index(%d) "
2448 "and hw jumbo index(%d) mismatch, drop!\n",
2449 sc->bnx_jumbo, rxidx);
2450 bnx_setup_rxdesc_jumbo(sc, rxidx);
2454 m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2455 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2457 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2460 if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2462 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2466 BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2469 if (rxidx != sc->bnx_std) {
2471 if_printf(ifp, "sw std index(%d) "
2472 "and hw std index(%d) mismatch, drop!\n",
2473 sc->bnx_std, rxidx);
2474 bnx_setup_rxdesc_std(sc, rxidx);
2478 m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2479 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2481 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2484 if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2486 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2492 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2493 m->m_pkthdr.rcvif = ifp;
2495 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2496 (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2497 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2498 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2499 if ((cur_rx->bge_error_flag &
2500 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2501 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2503 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2504 m->m_pkthdr.csum_data =
2505 cur_rx->bge_tcp_udp_csum;
2506 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2512 * If we received a packet with a vlan tag, pass it
2513 * to vlan_input() instead of ether_input().
2516 m->m_flags |= M_VLANTAG;
2517 m->m_pkthdr.ether_vlantag = vlan_tag;
2518 have_tag = vlan_tag = 0;
2520 ifp->if_input(ifp, m);
2523 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2525 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2527 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2531 bnx_txeof(struct bnx_softc *sc, uint16_t tx_cons)
2533 struct bge_tx_bd *cur_tx = NULL;
2536 ifp = &sc->arpcom.ac_if;
2539 * Go through our tx ring and free mbufs for those
2540 * frames that have been sent.
2542 while (sc->bnx_tx_saved_considx != tx_cons) {
2545 idx = sc->bnx_tx_saved_considx;
2546 cur_tx = &sc->bnx_ldata.bnx_tx_ring[idx];
2547 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2549 if (sc->bnx_cdata.bnx_tx_chain[idx] != NULL) {
2550 bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
2551 sc->bnx_cdata.bnx_tx_dmamap[idx]);
2552 m_freem(sc->bnx_cdata.bnx_tx_chain[idx]);
2553 sc->bnx_cdata.bnx_tx_chain[idx] = NULL;
2556 BNX_INC(sc->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2559 if (cur_tx != NULL &&
2560 (BGE_TX_RING_CNT - sc->bnx_txcnt) >=
2561 (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2562 ifp->if_flags &= ~IFF_OACTIVE;
2564 if (sc->bnx_txcnt == 0)
2567 if (!ifq_is_empty(&ifp->if_snd))
2571 #ifdef DEVICE_POLLING
2574 bnx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2576 struct bnx_softc *sc = ifp->if_softc;
2577 struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2578 uint16_t rx_prod, tx_cons;
2582 bnx_disable_intr(sc);
2584 case POLL_DEREGISTER:
2585 bnx_enable_intr(sc);
2587 case POLL_AND_CHECK_STATUS:
2589 * Process link state changes.
2594 sc->bnx_status_tag = sblk->bge_status_tag;
2596 * Use a load fence to ensure that status_tag
2597 * is saved before rx_prod and tx_cons.
2601 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2602 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2603 if (ifp->if_flags & IFF_RUNNING) {
2604 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2605 if (sc->bnx_rx_saved_considx != rx_prod)
2606 bnx_rxeof(sc, rx_prod);
2608 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2609 if (sc->bnx_tx_saved_considx != tx_cons)
2610 bnx_txeof(sc, tx_cons);
2619 bnx_intr_legacy(void *xsc)
2621 struct bnx_softc *sc = xsc;
2622 struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2624 if (sc->bnx_status_tag == sblk->bge_status_tag) {
2627 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2628 if (val & BGE_PCISTAT_INTR_NOTACT)
2634 * Interrupt will have to be disabled if tagged status
2635 * is used, else interrupt will always be asserted on
2636 * certain chips (at least on BCM5750 AX/BX).
2638 bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2646 struct bnx_softc *sc = xsc;
2648 /* Disable interrupt first */
2649 bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2654 bnx_msi_oneshot(void *xsc)
2660 bnx_intr(struct bnx_softc *sc)
2662 struct ifnet *ifp = &sc->arpcom.ac_if;
2663 struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2664 uint16_t rx_prod, tx_cons;
2667 sc->bnx_status_tag = sblk->bge_status_tag;
2669 * Use a load fence to ensure that status_tag is saved
2670 * before rx_prod, tx_cons and status.
2674 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2675 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2676 status = sblk->bge_status;
2678 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2681 if (ifp->if_flags & IFF_RUNNING) {
2682 if (sc->bnx_rx_saved_considx != rx_prod)
2683 bnx_rxeof(sc, rx_prod);
2685 if (sc->bnx_tx_saved_considx != tx_cons)
2686 bnx_txeof(sc, tx_cons);
2689 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2691 if (sc->bnx_coal_chg)
2692 bnx_coal_change(sc);
2698 struct bnx_softc *sc = xsc;
2699 struct ifnet *ifp = &sc->arpcom.ac_if;
2701 lwkt_serialize_enter(ifp->if_serializer);
2703 bnx_stats_update_regs(sc);
2705 if (sc->bnx_flags & BNX_FLAG_TBI) {
2707 * Since in TBI mode auto-polling can't be used we should poll
2708 * link status manually. Here we register pending link event
2709 * and trigger interrupt.
2712 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2713 } else if (!sc->bnx_link) {
2714 mii_tick(device_get_softc(sc->bnx_miibus));
2717 callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2719 lwkt_serialize_exit(ifp->if_serializer);
2723 bnx_stats_update_regs(struct bnx_softc *sc)
2725 struct ifnet *ifp = &sc->arpcom.ac_if;
2726 struct bge_mac_stats_regs stats;
2730 s = (uint32_t *)&stats;
2731 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2732 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2736 ifp->if_collisions +=
2737 (stats.dot3StatsSingleCollisionFrames +
2738 stats.dot3StatsMultipleCollisionFrames +
2739 stats.dot3StatsExcessiveCollisions +
2740 stats.dot3StatsLateCollisions) -
2745 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2746 * pointers to descriptors.
2749 bnx_encap(struct bnx_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2751 struct bge_tx_bd *d = NULL;
2752 uint16_t csum_flags = 0;
2753 bus_dma_segment_t segs[BNX_NSEG_NEW];
2755 int error, maxsegs, nsegs, idx, i;
2756 struct mbuf *m_head = *m_head0, *m_new;
2758 if (m_head->m_pkthdr.csum_flags) {
2759 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2760 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2761 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2762 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2763 if (m_head->m_flags & M_LASTFRAG)
2764 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2765 else if (m_head->m_flags & M_FRAG)
2766 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2770 map = sc->bnx_cdata.bnx_tx_dmamap[idx];
2772 maxsegs = (BGE_TX_RING_CNT - sc->bnx_txcnt) - BNX_NSEG_RSVD;
2773 KASSERT(maxsegs >= BNX_NSEG_SPARE,
2774 ("not enough segments %d", maxsegs));
2776 if (maxsegs > BNX_NSEG_NEW)
2777 maxsegs = BNX_NSEG_NEW;
2780 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2781 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2782 * but when such padded frames employ the bge IP/TCP checksum
2783 * offload, the hardware checksum assist gives incorrect results
2784 * (possibly from incorporating its own padding into the UDP/TCP
2785 * checksum; who knows). If we pad such runts with zeros, the
2786 * onboard checksum comes out correct.
2788 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2789 m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2790 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2795 if ((sc->bnx_flags & BNX_FLAG_SHORTDMA) && m_head->m_next != NULL) {
2796 m_new = bnx_defrag_shortdma(m_head);
2797 if (m_new == NULL) {
2801 *m_head0 = m_head = m_new;
2803 if (sc->bnx_force_defrag && m_head->m_next != NULL) {
2805 * Forcefully defragment mbuf chain to overcome hardware
2806 * limitation which only support a single outstanding
2807 * DMA read operation. If it fails, keep moving on using
2808 * the original mbuf chain.
2810 m_new = m_defrag(m_head, MB_DONTWAIT);
2812 *m_head0 = m_head = m_new;
2815 error = bus_dmamap_load_mbuf_defrag(sc->bnx_cdata.bnx_tx_mtag, map,
2816 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2821 bus_dmamap_sync(sc->bnx_cdata.bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2823 for (i = 0; ; i++) {
2824 d = &sc->bnx_ldata.bnx_tx_ring[idx];
2826 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2827 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2828 d->bge_len = segs[i].ds_len;
2829 d->bge_flags = csum_flags;
2833 BNX_INC(idx, BGE_TX_RING_CNT);
2835 /* Mark the last segment as end of packet... */
2836 d->bge_flags |= BGE_TXBDFLAG_END;
2838 /* Set vlan tag to the first segment of the packet. */
2839 d = &sc->bnx_ldata.bnx_tx_ring[*txidx];
2840 if (m_head->m_flags & M_VLANTAG) {
2841 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2842 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2844 d->bge_vlan_tag = 0;
2848 * Insure that the map for this transmission is placed at
2849 * the array index of the last descriptor in this chain.
2851 sc->bnx_cdata.bnx_tx_dmamap[*txidx] = sc->bnx_cdata.bnx_tx_dmamap[idx];
2852 sc->bnx_cdata.bnx_tx_dmamap[idx] = map;
2853 sc->bnx_cdata.bnx_tx_chain[idx] = m_head;
2854 sc->bnx_txcnt += nsegs;
2856 BNX_INC(idx, BGE_TX_RING_CNT);
2867 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2868 * to the mbuf data regions directly in the transmit descriptors.
2871 bnx_start(struct ifnet *ifp)
2873 struct bnx_softc *sc = ifp->if_softc;
2874 struct mbuf *m_head = NULL;
2878 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2881 prodidx = sc->bnx_tx_prodidx;
2884 while (sc->bnx_cdata.bnx_tx_chain[prodidx] == NULL) {
2885 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2891 * The code inside the if() block is never reached since we
2892 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2893 * requests to checksum TCP/UDP in a fragmented packet.
2896 * safety overkill. If this is a fragmented packet chain
2897 * with delayed TCP/UDP checksums, then only encapsulate
2898 * it if we have enough descriptors to handle the entire
2900 * (paranoia -- may not actually be needed)
2902 if ((m_head->m_flags & M_FIRSTFRAG) &&
2903 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2904 if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
2905 m_head->m_pkthdr.csum_data + BNX_NSEG_RSVD) {
2906 ifp->if_flags |= IFF_OACTIVE;
2907 ifq_prepend(&ifp->if_snd, m_head);
2913 * Sanity check: avoid coming within BGE_NSEG_RSVD
2914 * descriptors of the end of the ring. Also make
2915 * sure there are BGE_NSEG_SPARE descriptors for
2916 * jumbo buffers' defragmentation.
2918 if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
2919 (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2920 ifp->if_flags |= IFF_OACTIVE;
2921 ifq_prepend(&ifp->if_snd, m_head);
2926 * Pack the data into the transmit ring. If we
2927 * don't have room, set the OACTIVE flag and wait
2928 * for the NIC to drain the ring.
2930 if (bnx_encap(sc, &m_head, &prodidx)) {
2931 ifp->if_flags |= IFF_OACTIVE;
2937 ETHER_BPF_MTAP(ifp, m_head);
2944 bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2946 sc->bnx_tx_prodidx = prodidx;
2949 * Set a timeout in case the chip goes out to lunch.
2957 struct bnx_softc *sc = xsc;
2958 struct ifnet *ifp = &sc->arpcom.ac_if;
2962 ASSERT_SERIALIZED(ifp->if_serializer);
2964 /* Cancel pending I/O and flush buffers. */
2970 * Init the various state machines, ring
2971 * control blocks and firmware.
2973 if (bnx_blockinit(sc)) {
2974 if_printf(ifp, "initialization failure\n");
2980 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2981 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2983 /* Load our MAC address. */
2984 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2985 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2986 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2988 /* Enable or disable promiscuous mode as needed. */
2991 /* Program multicast filter. */
2995 if (bnx_init_rx_ring_std(sc)) {
2996 if_printf(ifp, "RX ring initialization failed\n");
3001 /* Init jumbo RX ring. */
3002 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3003 if (bnx_init_rx_ring_jumbo(sc)) {
3004 if_printf(ifp, "Jumbo RX ring initialization failed\n");
3010 /* Init our RX return ring index */
3011 sc->bnx_rx_saved_considx = 0;
3014 bnx_init_tx_ring(sc);
3016 /* Enable TX MAC state machine lockup fix. */
3017 mode = CSR_READ_4(sc, BGE_TX_MODE);
3018 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3019 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
3020 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3021 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3022 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3024 /* Turn on transmitter */
3025 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3027 /* Turn on receiver */
3028 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3031 * Set the number of good frames to receive after RX MBUF
3032 * Low Watermark has been reached. After the RX MAC receives
3033 * this number of frames, it will drop subsequent incoming
3034 * frames until the MBUF High Watermark is reached.
3036 if (BNX_IS_57765_FAMILY(sc))
3037 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3039 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3041 if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3043 if_printf(ifp, "MSI_MODE: %#x\n",
3044 CSR_READ_4(sc, BGE_MSI_MODE));
3048 /* Tell firmware we're alive. */
3049 BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3051 /* Enable host interrupts if polling(4) is not enabled. */
3052 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3053 #ifdef DEVICE_POLLING
3054 if (ifp->if_flags & IFF_POLLING)
3055 bnx_disable_intr(sc);
3058 bnx_enable_intr(sc);
3060 bnx_ifmedia_upd(ifp);
3062 ifp->if_flags |= IFF_RUNNING;
3063 ifp->if_flags &= ~IFF_OACTIVE;
3065 callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
3069 * Set media options.
3072 bnx_ifmedia_upd(struct ifnet *ifp)
3074 struct bnx_softc *sc = ifp->if_softc;
3076 /* If this is a 1000baseX NIC, enable the TBI port. */
3077 if (sc->bnx_flags & BNX_FLAG_TBI) {
3078 struct ifmedia *ifm = &sc->bnx_ifmedia;
3080 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3083 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3088 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3089 BNX_CLRBIT(sc, BGE_MAC_MODE,
3090 BGE_MACMODE_HALF_DUPLEX);
3092 BNX_SETBIT(sc, BGE_MAC_MODE,
3093 BGE_MACMODE_HALF_DUPLEX);
3100 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3104 if (mii->mii_instance) {
3105 struct mii_softc *miisc;
3107 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3108 mii_phy_reset(miisc);
3113 * Force an interrupt so that we will call bnx_link_upd
3114 * if needed and clear any pending link state attention.
3115 * Without this we are not getting any further interrupts
3116 * for link state changes and thus will not UP the link and
3117 * not be able to send in bnx_start. The only way to get
3118 * things working was to receive a packet and get an RX
3121 * bnx_tick should help for fiber cards and we might not
3122 * need to do this here if BNX_FLAG_TBI is set but as
3123 * we poll for fiber anyway it should not harm.
3125 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3131 * Report current media status.
3134 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3136 struct bnx_softc *sc = ifp->if_softc;
3138 if (sc->bnx_flags & BNX_FLAG_TBI) {
3139 ifmr->ifm_status = IFM_AVALID;
3140 ifmr->ifm_active = IFM_ETHER;
3141 if (CSR_READ_4(sc, BGE_MAC_STS) &
3142 BGE_MACSTAT_TBI_PCS_SYNCHED) {
3143 ifmr->ifm_status |= IFM_ACTIVE;
3145 ifmr->ifm_active |= IFM_NONE;
3149 ifmr->ifm_active |= IFM_1000_SX;
3150 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3151 ifmr->ifm_active |= IFM_HDX;
3153 ifmr->ifm_active |= IFM_FDX;
3155 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3158 ifmr->ifm_active = mii->mii_media_active;
3159 ifmr->ifm_status = mii->mii_media_status;
3164 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3166 struct bnx_softc *sc = ifp->if_softc;
3167 struct ifreq *ifr = (struct ifreq *)data;
3168 int mask, error = 0;
3170 ASSERT_SERIALIZED(ifp->if_serializer);
3174 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3175 (BNX_IS_JUMBO_CAPABLE(sc) &&
3176 ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3178 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3179 ifp->if_mtu = ifr->ifr_mtu;
3180 if (ifp->if_flags & IFF_RUNNING)
3185 if (ifp->if_flags & IFF_UP) {
3186 if (ifp->if_flags & IFF_RUNNING) {
3187 mask = ifp->if_flags ^ sc->bnx_if_flags;
3190 * If only the state of the PROMISC flag
3191 * changed, then just use the 'set promisc
3192 * mode' command instead of reinitializing
3193 * the entire NIC. Doing a full re-init
3194 * means reloading the firmware and waiting
3195 * for it to start up, which may take a
3196 * second or two. Similarly for ALLMULTI.
3198 if (mask & IFF_PROMISC)
3200 if (mask & IFF_ALLMULTI)
3205 } else if (ifp->if_flags & IFF_RUNNING) {
3208 sc->bnx_if_flags = ifp->if_flags;
3212 if (ifp->if_flags & IFF_RUNNING)
3217 if (sc->bnx_flags & BNX_FLAG_TBI) {
3218 error = ifmedia_ioctl(ifp, ifr,
3219 &sc->bnx_ifmedia, command);
3221 struct mii_data *mii;
3223 mii = device_get_softc(sc->bnx_miibus);
3224 error = ifmedia_ioctl(ifp, ifr,
3225 &mii->mii_media, command);
3229 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3230 if (mask & IFCAP_HWCSUM) {
3231 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3232 if (IFCAP_HWCSUM & ifp->if_capenable)
3233 ifp->if_hwassist = BNX_CSUM_FEATURES;
3235 ifp->if_hwassist = 0;
3239 error = ether_ioctl(ifp, command, data);
3246 bnx_watchdog(struct ifnet *ifp)
3248 struct bnx_softc *sc = ifp->if_softc;
3250 if_printf(ifp, "watchdog timeout -- resetting\n");
3256 if (!ifq_is_empty(&ifp->if_snd))
3261 * Stop the adapter and free any mbufs allocated to the
3265 bnx_stop(struct bnx_softc *sc)
3267 struct ifnet *ifp = &sc->arpcom.ac_if;
3269 ASSERT_SERIALIZED(ifp->if_serializer);
3271 callout_stop(&sc->bnx_stat_timer);
3274 * Disable all of the receiver blocks
3276 bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3277 bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3278 bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3279 bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3280 bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3281 bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3284 * Disable all of the transmit blocks
3286 bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3287 bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3288 bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3289 bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3290 bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3291 bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3294 * Shut down all of the memory managers and related
3297 bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3298 bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3299 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3300 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3302 /* Disable host interrupts. */
3303 bnx_disable_intr(sc);
3306 * Tell firmware we're shutting down.
3308 BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3310 /* Free the RX lists. */
3311 bnx_free_rx_ring_std(sc);
3313 /* Free jumbo RX list. */
3314 if (BNX_IS_JUMBO_CAPABLE(sc))
3315 bnx_free_rx_ring_jumbo(sc);
3317 /* Free TX buffers. */
3318 bnx_free_tx_ring(sc);
3320 sc->bnx_status_tag = 0;
3322 sc->bnx_coal_chg = 0;
3324 sc->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
3326 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3331 * Stop all chip I/O so that the kernel's probe routines don't
3332 * get confused by errant DMAs when rebooting.
3335 bnx_shutdown(device_t dev)
3337 struct bnx_softc *sc = device_get_softc(dev);
3338 struct ifnet *ifp = &sc->arpcom.ac_if;
3340 lwkt_serialize_enter(ifp->if_serializer);
3343 lwkt_serialize_exit(ifp->if_serializer);
3347 bnx_suspend(device_t dev)
3349 struct bnx_softc *sc = device_get_softc(dev);
3350 struct ifnet *ifp = &sc->arpcom.ac_if;
3352 lwkt_serialize_enter(ifp->if_serializer);
3354 lwkt_serialize_exit(ifp->if_serializer);
3360 bnx_resume(device_t dev)
3362 struct bnx_softc *sc = device_get_softc(dev);
3363 struct ifnet *ifp = &sc->arpcom.ac_if;
3365 lwkt_serialize_enter(ifp->if_serializer);
3367 if (ifp->if_flags & IFF_UP) {
3370 if (!ifq_is_empty(&ifp->if_snd))
3374 lwkt_serialize_exit(ifp->if_serializer);
3380 bnx_setpromisc(struct bnx_softc *sc)
3382 struct ifnet *ifp = &sc->arpcom.ac_if;
3384 if (ifp->if_flags & IFF_PROMISC)
3385 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3387 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3391 bnx_dma_free(struct bnx_softc *sc)
3395 /* Destroy RX mbuf DMA stuffs. */
3396 if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3397 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3398 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3399 sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3401 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3402 sc->bnx_cdata.bnx_rx_tmpmap);
3403 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3406 /* Destroy TX mbuf DMA stuffs. */
3407 if (sc->bnx_cdata.bnx_tx_mtag != NULL) {
3408 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3409 bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3410 sc->bnx_cdata.bnx_tx_dmamap[i]);
3412 bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3415 /* Destroy standard RX ring */
3416 bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3417 sc->bnx_cdata.bnx_rx_std_ring_map,
3418 sc->bnx_ldata.bnx_rx_std_ring);
3420 if (BNX_IS_JUMBO_CAPABLE(sc))
3421 bnx_free_jumbo_mem(sc);
3423 /* Destroy RX return ring */
3424 bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3425 sc->bnx_cdata.bnx_rx_return_ring_map,
3426 sc->bnx_ldata.bnx_rx_return_ring);
3428 /* Destroy TX ring */
3429 bnx_dma_block_free(sc->bnx_cdata.bnx_tx_ring_tag,
3430 sc->bnx_cdata.bnx_tx_ring_map,
3431 sc->bnx_ldata.bnx_tx_ring);
3433 /* Destroy status block */
3434 bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3435 sc->bnx_cdata.bnx_status_map,
3436 sc->bnx_ldata.bnx_status_block);
3438 /* Destroy the parent tag */
3439 if (sc->bnx_cdata.bnx_parent_tag != NULL)
3440 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3444 bnx_dma_alloc(struct bnx_softc *sc)
3446 struct ifnet *ifp = &sc->arpcom.ac_if;
3450 * Allocate the parent bus DMA tag appropriate for PCI.
3452 * All of the NetExtreme/NetLink controllers have 4GB boundary
3454 * Whenever an address crosses a multiple of the 4GB boundary
3455 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3456 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3457 * state machine will lockup and cause the device to hang.
3459 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3460 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3462 BUS_SPACE_MAXSIZE_32BIT, 0,
3463 BUS_SPACE_MAXSIZE_32BIT,
3464 0, &sc->bnx_cdata.bnx_parent_tag);
3466 if_printf(ifp, "could not allocate parent dma tag\n");
3471 * Create DMA tag and maps for RX mbufs.
3473 error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3474 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3475 NULL, NULL, MCLBYTES, 1, MCLBYTES,
3476 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3477 &sc->bnx_cdata.bnx_rx_mtag);
3479 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3483 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3484 BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3486 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3487 sc->bnx_cdata.bnx_rx_mtag = NULL;
3491 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3492 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3494 &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3498 for (j = 0; j < i; ++j) {
3499 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3500 sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3502 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3503 sc->bnx_cdata.bnx_rx_mtag = NULL;
3505 if_printf(ifp, "could not create DMA map for RX\n");
3511 * Create DMA tag and maps for TX mbufs.
3513 error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3514 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3516 BNX_JUMBO_FRAMELEN, BNX_NSEG_NEW, MCLBYTES,
3517 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3519 &sc->bnx_cdata.bnx_tx_mtag);
3521 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3525 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3526 error = bus_dmamap_create(sc->bnx_cdata.bnx_tx_mtag,
3527 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3528 &sc->bnx_cdata.bnx_tx_dmamap[i]);
3532 for (j = 0; j < i; ++j) {
3533 bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3534 sc->bnx_cdata.bnx_tx_dmamap[j]);
3536 bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3537 sc->bnx_cdata.bnx_tx_mtag = NULL;
3539 if_printf(ifp, "could not create DMA map for TX\n");
3545 * Create DMA stuffs for standard RX ring.
3547 error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3548 &sc->bnx_cdata.bnx_rx_std_ring_tag,
3549 &sc->bnx_cdata.bnx_rx_std_ring_map,
3550 (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3551 &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3553 if_printf(ifp, "could not create std RX ring\n");
3558 * Create jumbo buffer pool.
3560 if (BNX_IS_JUMBO_CAPABLE(sc)) {
3561 error = bnx_alloc_jumbo_mem(sc);
3563 if_printf(ifp, "could not create jumbo buffer pool\n");
3569 * Create DMA stuffs for RX return ring.
3571 error = bnx_dma_block_alloc(sc,
3572 BGE_RX_RTN_RING_SZ(sc->bnx_return_ring_cnt),
3573 &sc->bnx_cdata.bnx_rx_return_ring_tag,
3574 &sc->bnx_cdata.bnx_rx_return_ring_map,
3575 (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3576 &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3578 if_printf(ifp, "could not create RX ret ring\n");
3583 * Create DMA stuffs for TX ring.
3585 error = bnx_dma_block_alloc(sc, BGE_TX_RING_SZ,
3586 &sc->bnx_cdata.bnx_tx_ring_tag,
3587 &sc->bnx_cdata.bnx_tx_ring_map,
3588 (void *)&sc->bnx_ldata.bnx_tx_ring,
3589 &sc->bnx_ldata.bnx_tx_ring_paddr);
3591 if_printf(ifp, "could not create TX ring\n");
3596 * Create DMA stuffs for status block.
3598 error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3599 &sc->bnx_cdata.bnx_status_tag,
3600 &sc->bnx_cdata.bnx_status_map,
3601 (void *)&sc->bnx_ldata.bnx_status_block,
3602 &sc->bnx_ldata.bnx_status_block_paddr);
3604 if_printf(ifp, "could not create status block\n");
3612 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3613 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3618 error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3619 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3620 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3624 *tag = dmem.dmem_tag;
3625 *map = dmem.dmem_map;
3626 *addr = dmem.dmem_addr;
3627 *paddr = dmem.dmem_busaddr;
3633 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3636 bus_dmamap_unload(tag, map);
3637 bus_dmamem_free(tag, addr, map);
3638 bus_dma_tag_destroy(tag);
3643 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3645 struct ifnet *ifp = &sc->arpcom.ac_if;
3647 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3650 * Sometimes PCS encoding errors are detected in
3651 * TBI mode (on fiber NICs), and for some reason
3652 * the chip will signal them as link changes.
3653 * If we get a link change event, but the 'PCS
3654 * encoding error' bit in the MAC status register
3655 * is set, don't bother doing a link check.
3656 * This avoids spurious "gigabit link up" messages
3657 * that sometimes appear on fiber NICs during
3658 * periods of heavy traffic.
3660 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3661 if (!sc->bnx_link) {
3663 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3664 BNX_CLRBIT(sc, BGE_MAC_MODE,
3665 BGE_MACMODE_TBI_SEND_CFGS);
3667 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3670 if_printf(ifp, "link UP\n");
3672 ifp->if_link_state = LINK_STATE_UP;
3673 if_link_state_change(ifp);
3675 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3680 if_printf(ifp, "link DOWN\n");
3682 ifp->if_link_state = LINK_STATE_DOWN;
3683 if_link_state_change(ifp);
3687 #undef PCS_ENCODE_ERR
3689 /* Clear the attention. */
3690 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3691 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3692 BGE_MACSTAT_LINK_CHANGED);
3696 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3698 struct ifnet *ifp = &sc->arpcom.ac_if;
3699 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3702 bnx_miibus_statchg(sc->bnx_dev);
3706 if_printf(ifp, "link UP\n");
3708 if_printf(ifp, "link DOWN\n");
3711 /* Clear the attention. */
3712 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3713 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3714 BGE_MACSTAT_LINK_CHANGED);
3718 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3720 struct ifnet *ifp = &sc->arpcom.ac_if;
3721 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3725 if (!sc->bnx_link &&
3726 (mii->mii_media_status & IFM_ACTIVE) &&
3727 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3730 if_printf(ifp, "link UP\n");
3731 } else if (sc->bnx_link &&
3732 (!(mii->mii_media_status & IFM_ACTIVE) ||
3733 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3736 if_printf(ifp, "link DOWN\n");
3739 /* Clear the attention. */
3740 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3741 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3742 BGE_MACSTAT_LINK_CHANGED);
3746 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3748 struct bnx_softc *sc = arg1;
3750 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3751 &sc->bnx_rx_coal_ticks,
3752 BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3753 BNX_RX_COAL_TICKS_CHG);
3757 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3759 struct bnx_softc *sc = arg1;
3761 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3762 &sc->bnx_tx_coal_ticks,
3763 BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3764 BNX_TX_COAL_TICKS_CHG);
3768 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3770 struct bnx_softc *sc = arg1;
3772 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3773 &sc->bnx_rx_coal_bds,
3774 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3775 BNX_RX_COAL_BDS_CHG);
3779 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3781 struct bnx_softc *sc = arg1;
3783 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3784 &sc->bnx_tx_coal_bds,
3785 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3786 BNX_TX_COAL_BDS_CHG);
3790 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3792 struct bnx_softc *sc = arg1;
3794 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3795 &sc->bnx_rx_coal_bds_int,
3796 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3797 BNX_RX_COAL_BDS_INT_CHG);
3801 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3803 struct bnx_softc *sc = arg1;
3805 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3806 &sc->bnx_tx_coal_bds_int,
3807 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3808 BNX_TX_COAL_BDS_INT_CHG);
3812 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3813 int coal_min, int coal_max, uint32_t coal_chg_mask)
3815 struct bnx_softc *sc = arg1;
3816 struct ifnet *ifp = &sc->arpcom.ac_if;
3819 lwkt_serialize_enter(ifp->if_serializer);
3822 error = sysctl_handle_int(oidp, &v, 0, req);
3823 if (!error && req->newptr != NULL) {
3824 if (v < coal_min || v > coal_max) {
3828 sc->bnx_coal_chg |= coal_chg_mask;
3832 lwkt_serialize_exit(ifp->if_serializer);
3837 bnx_coal_change(struct bnx_softc *sc)
3839 struct ifnet *ifp = &sc->arpcom.ac_if;
3842 ASSERT_SERIALIZED(ifp->if_serializer);
3844 if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3845 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3846 sc->bnx_rx_coal_ticks);
3848 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3851 if_printf(ifp, "rx_coal_ticks -> %u\n",
3852 sc->bnx_rx_coal_ticks);
3856 if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3857 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3858 sc->bnx_tx_coal_ticks);
3860 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3863 if_printf(ifp, "tx_coal_ticks -> %u\n",
3864 sc->bnx_tx_coal_ticks);
3868 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3869 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3870 sc->bnx_rx_coal_bds);
3872 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3875 if_printf(ifp, "rx_coal_bds -> %u\n",
3876 sc->bnx_rx_coal_bds);
3880 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3881 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3882 sc->bnx_tx_coal_bds);
3884 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3887 if_printf(ifp, "tx_max_coal_bds -> %u\n",
3888 sc->bnx_tx_coal_bds);
3892 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3893 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3894 sc->bnx_rx_coal_bds_int);
3896 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3899 if_printf(ifp, "rx_coal_bds_int -> %u\n",
3900 sc->bnx_rx_coal_bds_int);
3904 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3905 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3906 sc->bnx_tx_coal_bds_int);
3908 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3911 if_printf(ifp, "tx_coal_bds_int -> %u\n",
3912 sc->bnx_tx_coal_bds_int);
3916 sc->bnx_coal_chg = 0;
3920 bnx_enable_intr(struct bnx_softc *sc)
3922 struct ifnet *ifp = &sc->arpcom.ac_if;
3924 lwkt_serialize_handler_enable(ifp->if_serializer);
3929 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3930 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3931 /* XXX Linux driver */
3932 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3936 * Unmask the interrupt when we stop polling.
3938 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3939 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3942 * Trigger another interrupt, since above writing
3943 * to interrupt mailbox0 may acknowledge pending
3946 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3950 bnx_disable_intr(struct bnx_softc *sc)
3952 struct ifnet *ifp = &sc->arpcom.ac_if;
3955 * Mask the interrupt when we start polling.
3957 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3958 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3961 * Acknowledge possible asserted interrupt.
3963 bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3965 lwkt_serialize_handler_disable(ifp->if_serializer);
3969 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
3974 mac_addr = bnx_readmem_ind(sc, 0x0c14);
3975 if ((mac_addr >> 16) == 0x484b) {
3976 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3977 ether_addr[1] = (uint8_t)mac_addr;
3978 mac_addr = bnx_readmem_ind(sc, 0x0c18);
3979 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3980 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3981 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3982 ether_addr[5] = (uint8_t)mac_addr;
3989 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
3991 int mac_offset = BGE_EE_MAC_OFFSET;
3993 if (BNX_IS_5717_PLUS(sc)) {
3996 f = pci_get_function(sc->bnx_dev);
3998 mac_offset = BGE_EE_MAC_OFFSET_5717;
4000 mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4001 } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
4002 mac_offset = BGE_EE_MAC_OFFSET_5906;
4005 return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4009 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4011 if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4014 return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4019 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4021 static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4022 /* NOTE: Order is critical */
4024 bnx_get_eaddr_nvram,
4025 bnx_get_eaddr_eeprom,
4028 const bnx_eaddr_fcn_t *func;
4030 for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4031 if ((*func)(sc, eaddr) == 0)
4034 return (*func == NULL ? ENXIO : 0);
4038 * NOTE: 'm' is not freed upon failure
4041 bnx_defrag_shortdma(struct mbuf *m)
4047 * If device receive two back-to-back send BDs with less than
4048 * or equal to 8 total bytes then the device may hang. The two
4049 * back-to-back send BDs must in the same frame for this failure
4050 * to occur. Scan mbuf chains and see whether two back-to-back
4051 * send BDs are there. If this is the case, allocate new mbuf
4052 * and copy the frame to workaround the silicon bug.
4054 for (n = m, found = 0; n != NULL; n = n->m_next) {
4065 n = m_defrag(m, MB_DONTWAIT);
4072 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4076 BNX_CLRBIT(sc, reg, bit);
4077 for (i = 0; i < BNX_TIMEOUT; i++) {
4078 if ((CSR_READ_4(sc, reg) & bit) == 0)
4085 bnx_link_poll(struct bnx_softc *sc)
4089 status = CSR_READ_4(sc, BGE_MAC_STS);
4090 if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4091 sc->bnx_link_evt = 0;
4092 sc->bnx_link_upd(sc, status);
4097 bnx_enable_msi(struct bnx_softc *sc)
4101 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4102 msi_mode |= BGE_MSIMODE_ENABLE;
4103 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4106 * 5718-PG105-R says that "one shot" mode
4107 * does not work if MSI is used, however,
4108 * it obviously works.
4110 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4112 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4116 bnx_dma_swap_options(struct bnx_softc *sc)
4118 uint32_t dma_options;
4120 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4121 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4122 #if BYTE_ORDER == BIG_ENDIAN
4123 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4125 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
4126 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4127 BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4128 BGE_MODECTL_HTX2B_ENABLE;