sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_polling.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124
 125         /* required last entry */
 126         IGB_DEVICE_NULL
 127 };
 128
 129 static int      igb_probe(device_t);
 130 static int      igb_attach(device_t);
 131 static int      igb_detach(device_t);
 132 static int      igb_shutdown(device_t);
 133 static int      igb_suspend(device_t);
 134 static int      igb_resume(device_t);
 135
 136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 137 static void     igb_setup_ifp(struct igb_softc *);
 138 static int      igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
 139 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
 140 static void     igb_add_sysctl(struct igb_softc *);
 141 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 142 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 143
 144 static void     igb_vf_init_stats(struct igb_softc *);
 145 static void     igb_reset(struct igb_softc *);
 146 static void     igb_update_stats_counters(struct igb_softc *);
 147 static void     igb_update_vf_stats_counters(struct igb_softc *);
 148 static void     igb_update_link_status(struct igb_softc *);
 149 static void     igb_init_tx_unit(struct igb_softc *);
 150 static void     igb_init_rx_unit(struct igb_softc *);
 151
 152 static void     igb_set_vlan(struct igb_softc *);
 153 static void     igb_set_multi(struct igb_softc *);
 154 static void     igb_set_promisc(struct igb_softc *);
 155 static void     igb_disable_promisc(struct igb_softc *);
 156
 157 static int      igb_alloc_rings(struct igb_softc *);
 158 static void     igb_free_rings(struct igb_softc *);
 159 static int      igb_create_tx_ring(struct igb_tx_ring *);
 160 static int      igb_create_rx_ring(struct igb_rx_ring *);
 161 static void     igb_free_tx_ring(struct igb_tx_ring *);
 162 static void     igb_free_rx_ring(struct igb_rx_ring *);
 163 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 164 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 165 static void     igb_init_tx_ring(struct igb_tx_ring *);
 166 static int      igb_init_rx_ring(struct igb_rx_ring *);
 167 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 168 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
 169
 170 static void     igb_stop(struct igb_softc *);
 171 static void     igb_init(void *);
 172 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 173 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 174 static int      igb_media_change(struct ifnet *);
 175 static void     igb_timer(void *);
 176 static void     igb_watchdog(struct ifnet *);
 177 static void     igb_start(struct ifnet *);
 178 #ifdef DEVICE_POLLING
 179 static void     igb_poll(struct ifnet *, enum poll_cmd, int);
 180 #endif
 181 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 182 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 183 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 184 #ifdef INVARIANTS
 185 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 186                     boolean_t);
 187 #endif
 188
 189 static void     igb_intr(void *);
 190 static void     igb_shared_intr(void *);
 191 static void     igb_rxeof(struct igb_rx_ring *, int);
 192 static void     igb_txeof(struct igb_tx_ring *);
 193 static void     igb_set_eitr(struct igb_softc *);
 194 static void     igb_enable_intr(struct igb_softc *);
 195 static void     igb_disable_intr(struct igb_softc *);
 196 static void     igb_init_unshared_intr(struct igb_softc *);
 197 static void     igb_init_intr(struct igb_softc *);
 198 static int      igb_setup_intr(struct igb_softc *);
 199 static void     igb_setup_tx_intr(struct igb_tx_ring *, int *, int);
 200 static void     igb_setup_rx_intr(struct igb_rx_ring *, int *, int);
 201 static void     igb_set_intr_mask(struct igb_softc *);
 202 static int      igb_alloc_intr(struct igb_softc *);
 203 static void     igb_free_intr(struct igb_softc *);
 204
 205 /* Management and WOL Support */
 206 static void     igb_get_mgmt(struct igb_softc *);
 207 static void     igb_rel_mgmt(struct igb_softc *);
 208 static void     igb_get_hw_control(struct igb_softc *);
 209 static void     igb_rel_hw_control(struct igb_softc *);
 210 static void     igb_enable_wol(device_t);
 211
 212 static device_method_t igb_methods[] = {
 213         /* Device interface */
 214         DEVMETHOD(device_probe,         igb_probe),
 215         DEVMETHOD(device_attach,        igb_attach),
 216         DEVMETHOD(device_detach,        igb_detach),
 217         DEVMETHOD(device_shutdown,      igb_shutdown),
 218         DEVMETHOD(device_suspend,       igb_suspend),
 219         DEVMETHOD(device_resume,        igb_resume),
 220         { 0, 0 }
 221 };
 222
 223 static driver_t igb_driver = {
 224         "igb",
 225         igb_methods,
 226         sizeof(struct igb_softc),
 227 };
 228
 229 static devclass_t igb_devclass;
 230
 231 DECLARE_DUMMY_MODULE(if_igb);
 232 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 233 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 234
 235 static int      igb_rxd = IGB_DEFAULT_RXD;
 236 static int      igb_txd = IGB_DEFAULT_TXD;
 237 static int      igb_rxr = 0;
 238 static int      igb_msi_enable = 1;
 239 static int      igb_msix_enable = 1;
 240 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 241 static int      igb_fc_setting = e1000_fc_full;
 242
 243 /*
 244  * DMA Coalescing, only for i350 - default to off,
 245  * this feature is for power savings
 246  */
 247 static int      igb_dma_coalesce = 0;
 248
 249 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 250 TUNABLE_INT("hw.igb.txd", &igb_txd);
 251 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 252 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 253 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 254 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 255
 256 /* i350 specific */
 257 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 258 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 259
 260 static __inline void
 261 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 262 {
 263         /* Ignore Checksum bit is set */
 264         if (staterr & E1000_RXD_STAT_IXSM)
 265                 return;
 266
 267         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 268             E1000_RXD_STAT_IPCS)
 269                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 270
 271         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 272                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 273                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 274                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 275                         mp->m_pkthdr.csum_data = htons(0xffff);
 276                 }
 277         }
 278 }
 279
 280 static __inline struct pktinfo *
 281 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 282     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 283 {
 284         switch (hashtype) {
 285         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 286                 pi->pi_netisr = NETISR_IP;
 287                 pi->pi_flags = 0;
 288                 pi->pi_l3proto = IPPROTO_TCP;
 289                 break;
 290
 291         case E1000_RXDADV_RSSTYPE_IPV4:
 292                 if (staterr & E1000_RXD_STAT_IXSM)
 293                         return NULL;
 294
 295                 if ((staterr &
 296                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 297                     E1000_RXD_STAT_TCPCS) {
 298                         pi->pi_netisr = NETISR_IP;
 299                         pi->pi_flags = 0;
 300                         pi->pi_l3proto = IPPROTO_UDP;
 301                         break;
 302                 }
 303                 /* FALL THROUGH */
 304         default:
 305                 return NULL;
 306         }
 307
 308         m->m_flags |= M_HASH;
 309         m->m_pkthdr.hash = toeplitz_hash(hash);
 310         return pi;
 311 }
 312
 313 static int
 314 igb_probe(device_t dev)
 315 {
 316         const struct igb_device *d;
 317         uint16_t vid, did;
 318
 319         vid = pci_get_vendor(dev);
 320         did = pci_get_device(dev);
 321
 322         for (d = igb_devices; d->desc != NULL; ++d) {
 323                 if (vid == d->vid && did == d->did) {
 324                         device_set_desc(dev, d->desc);
 325                         return 0;
 326                 }
 327         }
 328         return ENXIO;
 329 }
 330
 331 static int
 332 igb_attach(device_t dev)
 333 {
 334         struct igb_softc *sc = device_get_softc(dev);
 335         uint16_t eeprom_data;
 336         int error = 0, i, j, ring_max;
 337
 338 #ifdef notyet
 339         /* SYSCTL stuff */
 340         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 341             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 342             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 343             igb_sysctl_nvm_info, "I", "NVM Information");
 344
 345         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 346             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 347             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
 348             &igb_enable_aim, 1, "Interrupt Moderation");
 349
 350         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 351             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 352             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 353             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 354 #endif
 355
 356         callout_init_mp(&sc->timer);
 357
 358         sc->dev = sc->osdep.dev = dev;
 359
 360         /*
 361          * Determine hardware and mac type
 362          */
 363         sc->hw.vendor_id = pci_get_vendor(dev);
 364         sc->hw.device_id = pci_get_device(dev);
 365         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 366         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 367         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 368
 369         if (e1000_set_mac_type(&sc->hw))
 370                 return ENXIO;
 371
 372         /* Are we a VF device? */
 373         if (sc->hw.mac.type == e1000_vfadapt ||
 374             sc->hw.mac.type == e1000_vfadapt_i350)
 375                 sc->vf_ifp = 1;
 376         else
 377                 sc->vf_ifp = 0;
 378
 379         /*
 380          * Configure total supported RX/TX ring count
 381          */
 382         switch (sc->hw.mac.type) {
 383         case e1000_82575:
 384                 ring_max = IGB_MAX_RING_82575;
 385                 break;
 386         case e1000_82580:
 387                 ring_max = IGB_MAX_RING_82580;
 388                 break;
 389         case e1000_i350:
 390                 ring_max = IGB_MAX_RING_I350;
 391                 break;
 392         case e1000_82576:
 393                 ring_max = IGB_MAX_RING_82576;
 394                 break;
 395         default:
 396                 ring_max = IGB_MIN_RING;
 397                 break;
 398         }
 399         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 400         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 401 #ifdef IGB_RSS_DEBUG
 402         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 403 #endif
 404         sc->rx_ring_inuse = sc->rx_ring_cnt;
 405         sc->tx_ring_cnt = 1; /* XXX */
 406
 407         /* Enable bus mastering */
 408         pci_enable_busmaster(dev);
 409
 410         /*
 411          * Allocate IO memory
 412          */
 413         sc->mem_rid = PCIR_BAR(0);
 414         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 415             RF_ACTIVE);
 416         if (sc->mem_res == NULL) {
 417                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 418                 error = ENXIO;
 419                 goto failed;
 420         }
 421         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 422         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 423
 424         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 425
 426         /* Save PCI command register for Shared Code */
 427         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 428         sc->hw.back = &sc->osdep;
 429
 430         sc->intr_rate = IGB_INTR_RATE;
 431
 432         /* Do Shared Code initialization */
 433         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 434                 device_printf(dev, "Setup of Shared code failed\n");
 435                 error = ENXIO;
 436                 goto failed;
 437         }
 438
 439         e1000_get_bus_info(&sc->hw);
 440
 441         sc->hw.mac.autoneg = DO_AUTO_NEG;
 442         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 443         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 444
 445         /* Copper options */
 446         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 447                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 448                 sc->hw.phy.disable_polarity_correction = FALSE;
 449                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 450         }
 451
 452         /* Set the frame limits assuming  standard ethernet sized frames. */
 453         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 454
 455         /* Allocate RX/TX rings */
 456         error = igb_alloc_rings(sc);
 457         if (error)
 458                 goto failed;
 459
 460         /* Allocate interrupt */
 461         error = igb_alloc_intr(sc);
 462         if (error)
 463                 goto failed;
 464
 465         /*
 466          * Setup serializers
 467          */
 468         lwkt_serialize_init(&sc->main_serialize);
 469         i = 0;
 470         sc->serializes[i++] = &sc->main_serialize;
 471
 472         sc->tx_serialize = i;
 473         for (j = 0; j < sc->tx_ring_cnt; ++j)
 474                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
 475
 476         sc->rx_serialize = i;
 477         for (j = 0; j < sc->rx_ring_cnt; ++j)
 478                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
 479
 480         sc->serialize_cnt = i;
 481         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
 482
 483         /* Allocate the appropriate stats memory */
 484         if (sc->vf_ifp) {
 485                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 486                     M_WAITOK | M_ZERO);
 487                 igb_vf_init_stats(sc);
 488         } else {
 489                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 490                     M_WAITOK | M_ZERO);
 491         }
 492
 493         /* Allocate multicast array memory. */
 494         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 495             M_DEVBUF, M_WAITOK);
 496
 497         /* Some adapter-specific advanced features */
 498         if (sc->hw.mac.type >= e1000_i350) {
 499 #ifdef notyet
 500                 igb_set_sysctl_value(adapter, "dma_coalesce",
 501                     "configure dma coalesce",
 502                     &adapter->dma_coalesce, igb_dma_coalesce);
 503                 igb_set_sysctl_value(adapter, "eee_disabled",
 504                     "enable Energy Efficient Ethernet",
 505                     &adapter->hw.dev_spec._82575.eee_disable,
 506                     igb_eee_disabled);
 507 #else
 508                 sc->dma_coalesce = igb_dma_coalesce;
 509                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 510 #endif
 511                 e1000_set_eee_i350(&sc->hw);
 512         }
 513
 514         /*
 515          * Start from a known state, this is important in reading the nvm and
 516          * mac from that.
 517          */
 518         e1000_reset_hw(&sc->hw);
 519
 520         /* Make sure we have a good EEPROM before we read from it */
 521         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 522                 /*
 523                  * Some PCI-E parts fail the first check due to
 524                  * the link being in sleep state, call it again,
 525                  * if it fails a second time its a real issue.
 526                  */
 527                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 528                         device_printf(dev,
 529                             "The EEPROM Checksum Is Not Valid\n");
 530                         error = EIO;
 531                         goto failed;
 532                 }
 533         }
 534
 535         /* Copy the permanent MAC address out of the EEPROM */
 536         if (e1000_read_mac_addr(&sc->hw) < 0) {
 537                 device_printf(dev, "EEPROM read error while reading MAC"
 538                     " address\n");
 539                 error = EIO;
 540                 goto failed;
 541         }
 542         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 543                 device_printf(dev, "Invalid MAC address\n");
 544                 error = EIO;
 545                 goto failed;
 546         }
 547
 548 #ifdef notyet
 549         /*
 550         ** Configure Interrupts
 551         */
 552         if ((adapter->msix > 1) && (igb_enable_msix))
 553                 error = igb_allocate_msix(adapter);
 554         else /* MSI or Legacy */
 555                 error = igb_allocate_legacy(adapter);
 556         if (error)
 557                 goto err_late;
 558 #endif
 559
 560         /* Setup OS specific network interface */
 561         igb_setup_ifp(sc);
 562
 563         /* Add sysctl tree, must after igb_setup_ifp() */
 564         igb_add_sysctl(sc);
 565
 566         /* Now get a good starting state */
 567         igb_reset(sc);
 568
 569         /* Initialize statistics */
 570         igb_update_stats_counters(sc);
 571
 572         sc->hw.mac.get_link_status = 1;
 573         igb_update_link_status(sc);
 574
 575         /* Indicate SOL/IDER usage */
 576         if (e1000_check_reset_block(&sc->hw)) {
 577                 device_printf(dev,
 578                     "PHY reset is blocked due to SOL/IDER session.\n");
 579         }
 580
 581         /* Determine if we have to control management hardware */
 582         if (e1000_enable_mng_pass_thru(&sc->hw))
 583                 sc->flags |= IGB_FLAG_HAS_MGMT;
 584
 585         /*
 586          * Setup Wake-on-Lan
 587          */
 588         /* APME bit in EEPROM is mapped to WUC.APME */
 589         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 590         if (eeprom_data)
 591                 sc->wol = E1000_WUFC_MAG;
 592         /* XXX disable WOL */
 593         sc->wol = 0;
 594
 595 #ifdef notyet
 596         /* Register for VLAN events */
 597         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 598              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 599         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 600              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 601 #endif
 602
 603 #ifdef notyet
 604         igb_add_hw_stats(adapter);
 605 #endif
 606
 607         error = igb_setup_intr(sc);
 608         if (error) {
 609                 ether_ifdetach(&sc->arpcom.ac_if);
 610                 goto failed;
 611         }
 612         return 0;
 613
 614 failed:
 615         igb_detach(dev);
 616         return error;
 617 }
 618
 619 static int
 620 igb_detach(device_t dev)
 621 {
 622         struct igb_softc *sc = device_get_softc(dev);
 623
 624         if (device_is_attached(dev)) {
 625                 struct ifnet *ifp = &sc->arpcom.ac_if;
 626
 627                 ifnet_serialize_all(ifp);
 628
 629                 igb_stop(sc);
 630
 631                 e1000_phy_hw_reset(&sc->hw);
 632
 633                 /* Give control back to firmware */
 634                 igb_rel_mgmt(sc);
 635                 igb_rel_hw_control(sc);
 636
 637                 if (sc->wol) {
 638                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 639                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 640                         igb_enable_wol(dev);
 641                 }
 642
 643                 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
 644
 645                 ifnet_deserialize_all(ifp);
 646
 647                 ether_ifdetach(ifp);
 648         } else if (sc->mem_res != NULL) {
 649                 igb_rel_hw_control(sc);
 650         }
 651         bus_generic_detach(dev);
 652
 653         igb_free_intr(sc);
 654
 655         if (sc->mem_res != NULL) {
 656                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 657                     sc->mem_res);
 658         }
 659
 660         igb_free_rings(sc);
 661
 662         if (sc->mta != NULL)
 663                 kfree(sc->mta, M_DEVBUF);
 664         if (sc->stats != NULL)
 665                 kfree(sc->stats, M_DEVBUF);
 666
 667         if (sc->sysctl_tree != NULL)
 668                 sysctl_ctx_free(&sc->sysctl_ctx);
 669
 670         return 0;
 671 }
 672
 673 static int
 674 igb_shutdown(device_t dev)
 675 {
 676         return igb_suspend(dev);
 677 }
 678
 679 static int
 680 igb_suspend(device_t dev)
 681 {
 682         struct igb_softc *sc = device_get_softc(dev);
 683         struct ifnet *ifp = &sc->arpcom.ac_if;
 684
 685         ifnet_serialize_all(ifp);
 686
 687         igb_stop(sc);
 688
 689         igb_rel_mgmt(sc);
 690         igb_rel_hw_control(sc);
 691
 692         if (sc->wol) {
 693                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 694                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 695                 igb_enable_wol(dev);
 696         }
 697
 698         ifnet_deserialize_all(ifp);
 699
 700         return bus_generic_suspend(dev);
 701 }
 702
 703 static int
 704 igb_resume(device_t dev)
 705 {
 706         struct igb_softc *sc = device_get_softc(dev);
 707         struct ifnet *ifp = &sc->arpcom.ac_if;
 708
 709         ifnet_serialize_all(ifp);
 710
 711         igb_init(sc);
 712         igb_get_mgmt(sc);
 713
 714         if_devstart(ifp);
 715
 716         ifnet_deserialize_all(ifp);
 717
 718         return bus_generic_resume(dev);
 719 }
 720
 721 static int
 722 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 723 {
 724         struct igb_softc *sc = ifp->if_softc;
 725         struct ifreq *ifr = (struct ifreq *)data;
 726         int max_frame_size, mask, reinit;
 727         int error = 0;
 728
 729         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 730
 731         switch (command) {
 732         case SIOCSIFMTU:
 733                 max_frame_size = 9234;
 734                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 735                     ETHER_CRC_LEN) {
 736                         error = EINVAL;
 737                         break;
 738                 }
 739
 740                 ifp->if_mtu = ifr->ifr_mtu;
 741                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 742                     ETHER_CRC_LEN;
 743
 744                 if (ifp->if_flags & IFF_RUNNING)
 745                         igb_init(sc);
 746                 break;
 747
 748         case SIOCSIFFLAGS:
 749                 if (ifp->if_flags & IFF_UP) {
 750                         if (ifp->if_flags & IFF_RUNNING) {
 751                                 if ((ifp->if_flags ^ sc->if_flags) &
 752                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 753                                         igb_disable_promisc(sc);
 754                                         igb_set_promisc(sc);
 755                                 }
 756                         } else {
 757                                 igb_init(sc);
 758                         }
 759                 } else if (ifp->if_flags & IFF_RUNNING) {
 760                         igb_stop(sc);
 761                 }
 762                 sc->if_flags = ifp->if_flags;
 763                 break;
 764
 765         case SIOCADDMULTI:
 766         case SIOCDELMULTI:
 767                 if (ifp->if_flags & IFF_RUNNING) {
 768                         igb_disable_intr(sc);
 769                         igb_set_multi(sc);
 770 #ifdef DEVICE_POLLING
 771                         if (!(ifp->if_flags & IFF_POLLING))
 772 #endif
 773                                 igb_enable_intr(sc);
 774                 }
 775                 break;
 776
 777         case SIOCSIFMEDIA:
 778                 /*
 779                  * As the speed/duplex settings are being
 780                  * changed, we need toreset the PHY.
 781                  */
 782                 sc->hw.phy.reset_disable = FALSE;
 783
 784                 /* Check SOL/IDER usage */
 785                 if (e1000_check_reset_block(&sc->hw)) {
 786                         if_printf(ifp, "Media change is "
 787                             "blocked due to SOL/IDER session.\n");
 788                         break;
 789                 }
 790                 /* FALL THROUGH */
 791
 792         case SIOCGIFMEDIA:
 793                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 794                 break;
 795
 796         case SIOCSIFCAP:
 797                 reinit = 0;
 798                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 799                 if (mask & IFCAP_HWCSUM) {
 800                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
 801                         reinit = 1;
 802                 }
 803                 if (mask & IFCAP_VLAN_HWTAGGING) {
 804                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 805                         reinit = 1;
 806                 }
 807                 if (mask & IFCAP_RSS)
 808                         ifp->if_capenable ^= IFCAP_RSS;
 809                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 810                         igb_init(sc);
 811                 break;
 812
 813         default:
 814                 error = ether_ioctl(ifp, command, data);
 815                 break;
 816         }
 817         return error;
 818 }
 819
 820 static void
 821 igb_init(void *xsc)
 822 {
 823         struct igb_softc *sc = xsc;
 824         struct ifnet *ifp = &sc->arpcom.ac_if;
 825         int i;
 826
 827         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 828
 829         igb_stop(sc);
 830
 831         /* Get the latest mac address, User can use a LAA */
 832         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 833
 834         /* Put the address into the Receive Address Array */
 835         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 836
 837         igb_reset(sc);
 838         igb_update_link_status(sc);
 839
 840         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 841
 842         /* Set hardware offload abilities */
 843         if (ifp->if_capenable & IFCAP_TXCSUM)
 844                 ifp->if_hwassist = IGB_CSUM_FEATURES;
 845         else
 846                 ifp->if_hwassist = 0;
 847
 848         /* Configure for OS presence */
 849         igb_get_mgmt(sc);
 850
 851         if (IGB_ENABLE_HWRSS(sc)) {
 852                 if (sc->intr_type != PCI_INTR_TYPE_MSIX
 853 #ifdef DEVICE_POLLING
 854                     || (ifp->if_flags & IFF_POLLING)
 855 #endif
 856                     ) {
 857                         sc->rx_ring_inuse = IGB_MIN_RING_RSS;
 858                         if (bootverbose) {
 859                                 if_printf(ifp, "RX rings %d/%d\n",
 860                                     sc->rx_ring_inuse, sc->rx_ring_cnt);
 861                         }
 862                 }
 863         }
 864
 865         /* Prepare transmit descriptors and buffers */
 866         for (i = 0; i < sc->tx_ring_cnt; ++i)
 867                 igb_init_tx_ring(&sc->tx_rings[i]);
 868         igb_init_tx_unit(sc);
 869
 870         /* Setup Multicast table */
 871         igb_set_multi(sc);
 872
 873 #if 0
 874         /*
 875          * Figure out the desired mbuf pool
 876          * for doing jumbo/packetsplit
 877          */
 878         if (adapter->max_frame_size <= 2048)
 879                 adapter->rx_mbuf_sz = MCLBYTES;
 880         else if (adapter->max_frame_size <= 4096)
 881                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 882         else
 883                 adapter->rx_mbuf_sz = MJUM9BYTES;
 884 #endif
 885
 886         /* Initialize interrupt */
 887         igb_init_intr(sc);
 888
 889         /* Prepare receive descriptors and buffers */
 890         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 891                 int error;
 892
 893                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 894                 if (error) {
 895                         if_printf(ifp, "Could not setup receive structures\n");
 896                         igb_stop(sc);
 897                         return;
 898                 }
 899         }
 900         igb_init_rx_unit(sc);
 901
 902         /* Enable VLAN support */
 903         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 904                 igb_set_vlan(sc);
 905
 906         /* Don't lose promiscuous settings */
 907         igb_set_promisc(sc);
 908
 909         ifp->if_flags |= IFF_RUNNING;
 910         ifp->if_flags &= ~IFF_OACTIVE;
 911
 912         callout_reset(&sc->timer, hz, igb_timer, sc);
 913         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 914
 915 #if 0
 916         if (adapter->msix > 1) /* Set up queue routing */
 917                 igb_configure_queues(adapter);
 918 #endif
 919
 920         /* this clears any pending interrupts */
 921         E1000_READ_REG(&sc->hw, E1000_ICR);
 922 #ifdef DEVICE_POLLING
 923         /*
 924          * Only enable interrupts if we are not polling, make sure
 925          * they are off otherwise.
 926          */
 927         if (ifp->if_flags & IFF_POLLING)
 928                 igb_disable_intr(sc);
 929         else
 930 #endif /* DEVICE_POLLING */
 931         {
 932                 igb_enable_intr(sc);
 933                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
 934         }
 935
 936         /* Set Energy Efficient Ethernet */
 937         e1000_set_eee_i350(&sc->hw);
 938
 939         /* Don't reset the phy next time init gets called */
 940         sc->hw.phy.reset_disable = TRUE;
 941 }
 942
 943 static void
 944 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 945 {
 946         struct igb_softc *sc = ifp->if_softc;
 947         u_char fiber_type = IFM_1000_SX;
 948
 949         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 950
 951         igb_update_link_status(sc);
 952
 953         ifmr->ifm_status = IFM_AVALID;
 954         ifmr->ifm_active = IFM_ETHER;
 955
 956         if (!sc->link_active)
 957                 return;
 958
 959         ifmr->ifm_status |= IFM_ACTIVE;
 960
 961         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
 962             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
 963                 ifmr->ifm_active |= fiber_type | IFM_FDX;
 964         } else {
 965                 switch (sc->link_speed) {
 966                 case 10:
 967                         ifmr->ifm_active |= IFM_10_T;
 968                         break;
 969
 970                 case 100:
 971                         ifmr->ifm_active |= IFM_100_TX;
 972                         break;
 973
 974                 case 1000:
 975                         ifmr->ifm_active |= IFM_1000_T;
 976                         break;
 977                 }
 978                 if (sc->link_duplex == FULL_DUPLEX)
 979                         ifmr->ifm_active |= IFM_FDX;
 980                 else
 981                         ifmr->ifm_active |= IFM_HDX;
 982         }
 983 }
 984
 985 static int
 986 igb_media_change(struct ifnet *ifp)
 987 {
 988         struct igb_softc *sc = ifp->if_softc;
 989         struct ifmedia *ifm = &sc->media;
 990
 991         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 992
 993         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 994                 return EINVAL;
 995
 996         switch (IFM_SUBTYPE(ifm->ifm_media)) {
 997         case IFM_AUTO:
 998                 sc->hw.mac.autoneg = DO_AUTO_NEG;
 999                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1000                 break;
1001
1002         case IFM_1000_LX:
1003         case IFM_1000_SX:
1004         case IFM_1000_T:
1005                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1006                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1007                 break;
1008
1009         case IFM_100_TX:
1010                 sc->hw.mac.autoneg = FALSE;
1011                 sc->hw.phy.autoneg_advertised = 0;
1012                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1013                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1014                 else
1015                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1016                 break;
1017
1018         case IFM_10_T:
1019                 sc->hw.mac.autoneg = FALSE;
1020                 sc->hw.phy.autoneg_advertised = 0;
1021                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1022                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1023                 else
1024                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1025                 break;
1026
1027         default:
1028                 if_printf(ifp, "Unsupported media type\n");
1029                 break;
1030         }
1031
1032         igb_init(sc);
1033
1034         return 0;
1035 }
1036
1037 static void
1038 igb_set_promisc(struct igb_softc *sc)
1039 {
1040         struct ifnet *ifp = &sc->arpcom.ac_if;
1041         struct e1000_hw *hw = &sc->hw;
1042         uint32_t reg;
1043
1044         if (sc->vf_ifp) {
1045                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1046                 return;
1047         }
1048
1049         reg = E1000_READ_REG(hw, E1000_RCTL);
1050         if (ifp->if_flags & IFF_PROMISC) {
1051                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1052                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1053         } else if (ifp->if_flags & IFF_ALLMULTI) {
1054                 reg |= E1000_RCTL_MPE;
1055                 reg &= ~E1000_RCTL_UPE;
1056                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1057         }
1058 }
1059
1060 static void
1061 igb_disable_promisc(struct igb_softc *sc)
1062 {
1063         struct e1000_hw *hw = &sc->hw;
1064         uint32_t reg;
1065
1066         if (sc->vf_ifp) {
1067                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1068                 return;
1069         }
1070         reg = E1000_READ_REG(hw, E1000_RCTL);
1071         reg &= ~E1000_RCTL_UPE;
1072         reg &= ~E1000_RCTL_MPE;
1073         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1074 }
1075
1076 static void
1077 igb_set_multi(struct igb_softc *sc)
1078 {
1079         struct ifnet *ifp = &sc->arpcom.ac_if;
1080         struct ifmultiaddr *ifma;
1081         uint32_t reg_rctl = 0;
1082         uint8_t *mta;
1083         int mcnt = 0;
1084
1085         mta = sc->mta;
1086         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1087
1088         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1089                 if (ifma->ifma_addr->sa_family != AF_LINK)
1090                         continue;
1091
1092                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1093                         break;
1094
1095                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1096                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1097                 mcnt++;
1098         }
1099
1100         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1101                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1102                 reg_rctl |= E1000_RCTL_MPE;
1103                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1104         } else {
1105                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1106         }
1107 }
1108
1109 static void
1110 igb_timer(void *xsc)
1111 {
1112         struct igb_softc *sc = xsc;
1113
1114         lwkt_serialize_enter(&sc->main_serialize);
1115
1116         igb_update_link_status(sc);
1117         igb_update_stats_counters(sc);
1118
1119         callout_reset(&sc->timer, hz, igb_timer, sc);
1120
1121         lwkt_serialize_exit(&sc->main_serialize);
1122 }
1123
1124 static void
1125 igb_update_link_status(struct igb_softc *sc)
1126 {
1127         struct ifnet *ifp = &sc->arpcom.ac_if;
1128         struct e1000_hw *hw = &sc->hw;
1129         uint32_t link_check, thstat, ctrl;
1130
1131         link_check = thstat = ctrl = 0;
1132
1133         /* Get the cached link value or read for real */
1134         switch (hw->phy.media_type) {
1135         case e1000_media_type_copper:
1136                 if (hw->mac.get_link_status) {
1137                         /* Do the work to read phy */
1138                         e1000_check_for_link(hw);
1139                         link_check = !hw->mac.get_link_status;
1140                 } else {
1141                         link_check = TRUE;
1142                 }
1143                 break;
1144
1145         case e1000_media_type_fiber:
1146                 e1000_check_for_link(hw);
1147                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1148                 break;
1149
1150         case e1000_media_type_internal_serdes:
1151                 e1000_check_for_link(hw);
1152                 link_check = hw->mac.serdes_has_link;
1153                 break;
1154
1155         /* VF device is type_unknown */
1156         case e1000_media_type_unknown:
1157                 e1000_check_for_link(hw);
1158                 link_check = !hw->mac.get_link_status;
1159                 /* Fall thru */
1160         default:
1161                 break;
1162         }
1163
1164         /* Check for thermal downshift or shutdown */
1165         if (hw->mac.type == e1000_i350) {
1166                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1167                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1168         }
1169
1170         /* Now we check if a transition has happened */
1171         if (link_check && sc->link_active == 0) {
1172                 e1000_get_speed_and_duplex(hw,
1173                     &sc->link_speed, &sc->link_duplex);
1174                 if (bootverbose) {
1175                         if_printf(ifp, "Link is up %d Mbps %s\n",
1176                             sc->link_speed,
1177                             sc->link_duplex == FULL_DUPLEX ?
1178                             "Full Duplex" : "Half Duplex");
1179                 }
1180                 sc->link_active = 1;
1181
1182                 ifp->if_baudrate = sc->link_speed * 1000000;
1183                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1184                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1185                         if_printf(ifp, "Link: thermal downshift\n");
1186                 /* This can sleep */
1187                 ifp->if_link_state = LINK_STATE_UP;
1188                 if_link_state_change(ifp);
1189         } else if (!link_check && sc->link_active == 1) {
1190                 ifp->if_baudrate = sc->link_speed = 0;
1191                 sc->link_duplex = 0;
1192                 if (bootverbose)
1193                         if_printf(ifp, "Link is Down\n");
1194                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1195                     (thstat & E1000_THSTAT_PWR_DOWN))
1196                         if_printf(ifp, "Link: thermal shutdown\n");
1197                 sc->link_active = 0;
1198                 /* This can sleep */
1199                 ifp->if_link_state = LINK_STATE_DOWN;
1200                 if_link_state_change(ifp);
1201         }
1202 }
1203
1204 static void
1205 igb_stop(struct igb_softc *sc)
1206 {
1207         struct ifnet *ifp = &sc->arpcom.ac_if;
1208         int i;
1209
1210         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1211
1212         igb_disable_intr(sc);
1213
1214         callout_stop(&sc->timer);
1215
1216         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1217         ifp->if_timer = 0;
1218
1219         e1000_reset_hw(&sc->hw);
1220         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1221
1222         e1000_led_off(&sc->hw);
1223         e1000_cleanup_led(&sc->hw);
1224
1225         for (i = 0; i < sc->tx_ring_cnt; ++i)
1226                 igb_free_tx_ring(&sc->tx_rings[i]);
1227         for (i = 0; i < sc->rx_ring_cnt; ++i)
1228                 igb_free_rx_ring(&sc->rx_rings[i]);
1229 }
1230
1231 static void
1232 igb_reset(struct igb_softc *sc)
1233 {
1234         struct ifnet *ifp = &sc->arpcom.ac_if;
1235         struct e1000_hw *hw = &sc->hw;
1236         struct e1000_fc_info *fc = &hw->fc;
1237         uint32_t pba = 0;
1238         uint16_t hwm;
1239
1240         /* Let the firmware know the OS is in control */
1241         igb_get_hw_control(sc);
1242
1243         /*
1244          * Packet Buffer Allocation (PBA)
1245          * Writing PBA sets the receive portion of the buffer
1246          * the remainder is used for the transmit buffer.
1247          */
1248         switch (hw->mac.type) {
1249         case e1000_82575:
1250                 pba = E1000_PBA_32K;
1251                 break;
1252
1253         case e1000_82576:
1254         case e1000_vfadapt:
1255                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1256                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1257                 break;
1258
1259         case e1000_82580:
1260         case e1000_i350:
1261         case e1000_vfadapt_i350:
1262                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1263                 pba = e1000_rxpbs_adjust_82580(pba);
1264                 break;
1265                 /* XXX pba = E1000_PBA_35K; */
1266
1267         default:
1268                 break;
1269         }
1270
1271         /* Special needs in case of Jumbo frames */
1272         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1273                 uint32_t tx_space, min_tx, min_rx;
1274
1275                 pba = E1000_READ_REG(hw, E1000_PBA);
1276                 tx_space = pba >> 16;
1277                 pba &= 0xffff;
1278
1279                 min_tx = (sc->max_frame_size +
1280                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1281                 min_tx = roundup2(min_tx, 1024);
1282                 min_tx >>= 10;
1283                 min_rx = sc->max_frame_size;
1284                 min_rx = roundup2(min_rx, 1024);
1285                 min_rx >>= 10;
1286                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1287                         pba = pba - (min_tx - tx_space);
1288                         /*
1289                          * if short on rx space, rx wins
1290                          * and must trump tx adjustment
1291                          */
1292                         if (pba < min_rx)
1293                                 pba = min_rx;
1294                 }
1295                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1296         }
1297
1298         /*
1299          * These parameters control the automatic generation (Tx) and
1300          * response (Rx) to Ethernet PAUSE frames.
1301          * - High water mark should allow for at least two frames to be
1302          *   received after sending an XOFF.
1303          * - Low water mark works best when it is very near the high water mark.
1304          *   This allows the receiver to restart by sending XON when it has
1305          *   drained a bit.
1306          */
1307         hwm = min(((pba << 10) * 9 / 10),
1308             ((pba << 10) - 2 * sc->max_frame_size));
1309
1310         if (hw->mac.type < e1000_82576) {
1311                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1312                 fc->low_water = fc->high_water - 8;
1313         } else {
1314                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1315                 fc->low_water = fc->high_water - 16;
1316         }
1317         fc->pause_time = IGB_FC_PAUSE_TIME;
1318         fc->send_xon = TRUE;
1319
1320         /* Issue a global reset */
1321         e1000_reset_hw(hw);
1322         E1000_WRITE_REG(hw, E1000_WUC, 0);
1323
1324         if (e1000_init_hw(hw) < 0)
1325                 if_printf(ifp, "Hardware Initialization Failed\n");
1326
1327         /* Setup DMA Coalescing */
1328         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1329                 uint32_t reg;
1330
1331                 hwm = (pba - 4) << 10;
1332                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1333                     & E1000_DMACR_DMACTHR_MASK;
1334
1335                 /* transition to L0x or L1 if available..*/
1336                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1337
1338                 /* timer = +-1000 usec in 32usec intervals */
1339                 reg |= (1000 >> 5);
1340                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1341
1342                 /* No lower threshold */
1343                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1344
1345                 /* set hwm to PBA -  2 * max frame size */
1346                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1347
1348                 /* Set the interval before transition */
1349                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1350                 reg |= 0x800000FF; /* 255 usec */
1351                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1352
1353                 /* free space in tx packet buffer to wake from DMA coal */
1354                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1355                     (20480 - (2 * sc->max_frame_size)) >> 6);
1356
1357                 /* make low power state decision controlled by DMA coal */
1358                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1359                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1360                     reg | E1000_PCIEMISC_LX_DECISION);
1361                 if_printf(ifp, "DMA Coalescing enabled\n");
1362         }
1363
1364         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1365         e1000_get_phy_info(hw);
1366         e1000_check_for_link(hw);
1367 }
1368
1369 static void
1370 igb_setup_ifp(struct igb_softc *sc)
1371 {
1372         struct ifnet *ifp = &sc->arpcom.ac_if;
1373
1374         if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1375         ifp->if_softc = sc;
1376         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1377         ifp->if_init =  igb_init;
1378         ifp->if_ioctl = igb_ioctl;
1379         ifp->if_start = igb_start;
1380         ifp->if_serialize = igb_serialize;
1381         ifp->if_deserialize = igb_deserialize;
1382         ifp->if_tryserialize = igb_tryserialize;
1383 #ifdef INVARIANTS
1384         ifp->if_serialize_assert = igb_serialize_assert;
1385 #endif
1386 #ifdef DEVICE_POLLING
1387         ifp->if_poll = igb_poll;
1388 #endif
1389         ifp->if_watchdog = igb_watchdog;
1390
1391         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1392         ifq_set_ready(&ifp->if_snd);
1393
1394         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1395
1396         ifp->if_capabilities =
1397             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1398         if (IGB_ENABLE_HWRSS(sc))
1399                 ifp->if_capabilities |= IFCAP_RSS;
1400         ifp->if_capenable = ifp->if_capabilities;
1401         ifp->if_hwassist = IGB_CSUM_FEATURES;
1402
1403         /*
1404          * Tell the upper layer(s) we support long frames
1405          */
1406         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1407
1408         /*
1409          * Specify the media types supported by this adapter and register
1410          * callbacks to update media and link information
1411          */
1412         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1413         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1414             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1415                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1416                     0, NULL);
1417                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1418         } else {
1419                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1420                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1421                     0, NULL);
1422                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1423                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1424                     0, NULL);
1425                 if (sc->hw.phy.type != e1000_phy_ife) {
1426                         ifmedia_add(&sc->media,
1427                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1428                         ifmedia_add(&sc->media,
1429                             IFM_ETHER | IFM_1000_T, 0, NULL);
1430                 }
1431         }
1432         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1433         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1434 }
1435
1436 static void
1437 igb_add_sysctl(struct igb_softc *sc)
1438 {
1439 #ifdef IGB_RSS_DEBUG
1440         char rx_pkt[32];
1441         int i;
1442 #endif
1443
1444         sysctl_ctx_init(&sc->sysctl_ctx);
1445         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1446             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1447             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1448         if (sc->sysctl_tree == NULL) {
1449                 device_printf(sc->dev, "can't add sysctl node\n");
1450                 return;
1451         }
1452
1453         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1454             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1455         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1456             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1457             "# of RX rings used");
1458         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1459             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1460             "# of RX descs");
1461         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1462             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1463             "# of TX descs");
1464
1465         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1466             OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1467             sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1468
1469         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1470             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1471             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1472             "# of segments per TX interrupt");
1473
1474 #ifdef IGB_RSS_DEBUG
1475         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1476             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1477             "RSS debug level");
1478         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1479                 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
1480                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1481                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, rx_pkt,
1482                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1483         }
1484 #endif
1485 }
1486
1487 static int
1488 igb_alloc_rings(struct igb_softc *sc)
1489 {
1490         int error, i;
1491
1492         /*
1493          * Create top level busdma tag
1494          */
1495         error = bus_dma_tag_create(NULL, 1, 0,
1496             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1497             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1498             &sc->parent_tag);
1499         if (error) {
1500                 device_printf(sc->dev, "could not create top level DMA tag\n");
1501                 return error;
1502         }
1503
1504         /*
1505          * Allocate TX descriptor rings and buffers
1506          */
1507         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1508             M_DEVBUF, M_WAITOK | M_ZERO);
1509         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1510                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1511
1512                 /* Set up some basics */
1513                 txr->sc = sc;
1514                 txr->me = i;
1515                 lwkt_serialize_init(&txr->tx_serialize);
1516
1517                 error = igb_create_tx_ring(txr);
1518                 if (error)
1519                         return error;
1520         }
1521
1522         /*
1523          * Allocate RX descriptor rings and buffers
1524          */
1525         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1526             M_DEVBUF, M_WAITOK | M_ZERO);
1527         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1528                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1529
1530                 /* Set up some basics */
1531                 rxr->sc = sc;
1532                 rxr->me = i;
1533                 lwkt_serialize_init(&rxr->rx_serialize);
1534
1535                 error = igb_create_rx_ring(rxr);
1536                 if (error)
1537                         return error;
1538         }
1539
1540         return 0;
1541 }
1542
1543 static void
1544 igb_free_rings(struct igb_softc *sc)
1545 {
1546         int i;
1547
1548         if (sc->tx_rings != NULL) {
1549                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1550                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1551
1552                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1553                 }
1554                 kfree(sc->tx_rings, M_DEVBUF);
1555         }
1556
1557         if (sc->rx_rings != NULL) {
1558                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1559                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1560
1561                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1562                 }
1563                 kfree(sc->rx_rings, M_DEVBUF);
1564         }
1565 }
1566
1567 static int
1568 igb_create_tx_ring(struct igb_tx_ring *txr)
1569 {
1570         int tsize, error, i;
1571
1572         /*
1573          * Validate number of transmit descriptors. It must not exceed
1574          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1575          */
1576         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1577             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1578                 device_printf(txr->sc->dev,
1579                     "Using %d TX descriptors instead of %d!\n",
1580                     IGB_DEFAULT_TXD, igb_txd);
1581                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1582         } else {
1583                 txr->num_tx_desc = igb_txd;
1584         }
1585
1586         /*
1587          * Allocate TX descriptor ring
1588          */
1589         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1590             IGB_DBA_ALIGN);
1591         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1592             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1593             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1594         if (txr->txdma.dma_vaddr == NULL) {
1595                 device_printf(txr->sc->dev,
1596                     "Unable to allocate TX Descriptor memory\n");
1597                 return ENOMEM;
1598         }
1599         txr->tx_base = txr->txdma.dma_vaddr;
1600         bzero(txr->tx_base, tsize);
1601
1602         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1603             M_DEVBUF, M_WAITOK | M_ZERO);
1604
1605         /*
1606          * Allocate TX head write-back buffer
1607          */
1608         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1609             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1610             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1611         if (txr->tx_hdr == NULL) {
1612                 device_printf(txr->sc->dev,
1613                     "Unable to allocate TX head write-back buffer\n");
1614                 return ENOMEM;
1615         }
1616
1617         /*
1618          * Create DMA tag for TX buffers
1619          */
1620         error = bus_dma_tag_create(txr->sc->parent_tag,
1621             1, 0,               /* alignment, bounds */
1622             BUS_SPACE_MAXADDR,  /* lowaddr */
1623             BUS_SPACE_MAXADDR,  /* highaddr */
1624             NULL, NULL,         /* filter, filterarg */
1625             IGB_TSO_SIZE,       /* maxsize */
1626             IGB_MAX_SCATTER,    /* nsegments */
1627             PAGE_SIZE,          /* maxsegsize */
1628             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1629             BUS_DMA_ONEBPAGE,   /* flags */
1630             &txr->tx_tag);
1631         if (error) {
1632                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1633                 kfree(txr->tx_buf, M_DEVBUF);
1634                 txr->tx_buf = NULL;
1635                 return error;
1636         }
1637
1638         /*
1639          * Create DMA maps for TX buffers
1640          */
1641         for (i = 0; i < txr->num_tx_desc; ++i) {
1642                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1643
1644                 error = bus_dmamap_create(txr->tx_tag,
1645                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1646                 if (error) {
1647                         device_printf(txr->sc->dev,
1648                             "Unable to create TX DMA map\n");
1649                         igb_destroy_tx_ring(txr, i);
1650                         return error;
1651                 }
1652         }
1653
1654         /*
1655          * Initialize various watermark
1656          */
1657         txr->spare_desc = IGB_TX_SPARE;
1658         txr->intr_nsegs = txr->num_tx_desc / 16;
1659         txr->oact_hi_desc = txr->num_tx_desc / 2;
1660         txr->oact_lo_desc = txr->num_tx_desc / 8;
1661         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1662                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1663         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1664                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1665
1666         return 0;
1667 }
1668
1669 static void
1670 igb_free_tx_ring(struct igb_tx_ring *txr)
1671 {
1672         int i;
1673
1674         for (i = 0; i < txr->num_tx_desc; ++i) {
1675                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1676
1677                 if (txbuf->m_head != NULL) {
1678                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1679                         m_freem(txbuf->m_head);
1680                         txbuf->m_head = NULL;
1681                 }
1682         }
1683 }
1684
1685 static void
1686 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1687 {
1688         int i;
1689
1690         if (txr->txdma.dma_vaddr != NULL) {
1691                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1692                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1693                     txr->txdma.dma_map);
1694                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1695                 txr->txdma.dma_vaddr = NULL;
1696         }
1697
1698         if (txr->tx_hdr != NULL) {
1699                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1700                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1701                     txr->tx_hdr_dmap);
1702                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1703                 txr->tx_hdr = NULL;
1704         }
1705
1706         if (txr->tx_buf == NULL)
1707                 return;
1708
1709         for (i = 0; i < ndesc; ++i) {
1710                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1711
1712                 KKASSERT(txbuf->m_head == NULL);
1713                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1714         }
1715         bus_dma_tag_destroy(txr->tx_tag);
1716
1717         kfree(txr->tx_buf, M_DEVBUF);
1718         txr->tx_buf = NULL;
1719 }
1720
1721 static void
1722 igb_init_tx_ring(struct igb_tx_ring *txr)
1723 {
1724         /* Clear the old descriptor contents */
1725         bzero(txr->tx_base,
1726             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1727
1728         /* Clear TX head write-back buffer */
1729         *(txr->tx_hdr) = 0;
1730
1731         /* Reset indices */
1732         txr->next_avail_desc = 0;
1733         txr->next_to_clean = 0;
1734         txr->tx_nsegs = 0;
1735
1736         /* Set number of descriptors available */
1737         txr->tx_avail = txr->num_tx_desc;
1738 }
1739
1740 static void
1741 igb_init_tx_unit(struct igb_softc *sc)
1742 {
1743         struct e1000_hw *hw = &sc->hw;
1744         uint32_t tctl;
1745         int i;
1746
1747         /* Setup the Tx Descriptor Rings */
1748         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1749                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1750                 uint64_t bus_addr = txr->txdma.dma_paddr;
1751                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1752                 uint32_t txdctl = 0;
1753                 uint32_t dca_txctrl;
1754
1755                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1756                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1757                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1758                     (uint32_t)(bus_addr >> 32));
1759                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1760                     (uint32_t)bus_addr);
1761
1762                 /* Setup the HW Tx Head and Tail descriptor pointers */
1763                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1764                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1765
1766                 txdctl |= IGB_TX_PTHRESH;
1767                 txdctl |= IGB_TX_HTHRESH << 8;
1768                 txdctl |= IGB_TX_WTHRESH << 16;
1769                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1770                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1771
1772                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1773                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1774                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1775
1776                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1777                     (uint32_t)(hdr_paddr >> 32));
1778                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1779                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1780         }
1781
1782         if (sc->vf_ifp)
1783                 return;
1784
1785         e1000_config_collision_dist(hw);
1786
1787         /* Program the Transmit Control Register */
1788         tctl = E1000_READ_REG(hw, E1000_TCTL);
1789         tctl &= ~E1000_TCTL_CT;
1790         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1791             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1792
1793         /* This write will effectively turn on the transmit unit. */
1794         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1795 }
1796
1797 static boolean_t
1798 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1799 {
1800         struct e1000_adv_tx_context_desc *TXD;
1801         struct igb_tx_buf *txbuf;
1802         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1803         struct ether_vlan_header *eh;
1804         struct ip *ip = NULL;
1805         int ehdrlen, ctxd, ip_hlen = 0;
1806         uint16_t etype, vlantag = 0;
1807         boolean_t offload = TRUE;
1808
1809         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1810                 offload = FALSE;
1811
1812         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1813         ctxd = txr->next_avail_desc;
1814         txbuf = &txr->tx_buf[ctxd];
1815         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1816
1817         /*
1818          * In advanced descriptors the vlan tag must
1819          * be placed into the context descriptor, thus
1820          * we need to be here just for that setup.
1821          */
1822         if (mp->m_flags & M_VLANTAG) {
1823                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1824                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1825         } else if (!offload) {
1826                 return FALSE;
1827         }
1828
1829         /*
1830          * Determine where frame payload starts.
1831          * Jump over vlan headers if already present,
1832          * helpful for QinQ too.
1833          */
1834         KASSERT(mp->m_len >= ETHER_HDR_LEN,
1835             ("igb_txctx_pullup is not called (eh)?\n"));
1836         eh = mtod(mp, struct ether_vlan_header *);
1837         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1838                 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1839                     ("igb_txctx_pullup is not called (evh)?\n"));
1840                 etype = ntohs(eh->evl_proto);
1841                 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1842         } else {
1843                 etype = ntohs(eh->evl_encap_proto);
1844                 ehdrlen = ETHER_HDR_LEN;
1845         }
1846
1847         /* Set the ether header length */
1848         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1849
1850         switch (etype) {
1851         case ETHERTYPE_IP:
1852                 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1853                     ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1854
1855                 /* NOTE: We could only safely access ip.ip_vhl part */
1856                 ip = (struct ip *)(mp->m_data + ehdrlen);
1857                 ip_hlen = ip->ip_hl << 2;
1858
1859                 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1860                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1861                 break;
1862
1863 #ifdef notyet
1864         case ETHERTYPE_IPV6:
1865                 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1866                 ip_hlen = sizeof(struct ip6_hdr);
1867                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1868                 break;
1869 #endif
1870
1871         default:
1872                 offload = FALSE;
1873                 break;
1874         }
1875
1876         vlan_macip_lens |= ip_hlen;
1877         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1878
1879         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1880                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1881         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1882                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1883
1884         /* 82575 needs the queue index added */
1885         if (txr->sc->hw.mac.type == e1000_82575)
1886                 mss_l4len_idx = txr->me << 4;
1887
1888         /* Now copy bits into descriptor */
1889         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1890         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1891         TXD->seqnum_seed = htole32(0);
1892         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1893
1894         txbuf->m_head = NULL;
1895
1896         /* We've consumed the first desc, adjust counters */
1897         if (++ctxd == txr->num_tx_desc)
1898                 ctxd = 0;
1899         txr->next_avail_desc = ctxd;
1900         --txr->tx_avail;
1901
1902         return offload;
1903 }
1904
1905 static void
1906 igb_txeof(struct igb_tx_ring *txr)
1907 {
1908         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1909         int first, hdr, avail;
1910
1911         if (txr->tx_avail == txr->num_tx_desc)
1912                 return;
1913
1914         first = txr->next_to_clean;
1915         hdr = *(txr->tx_hdr);
1916
1917         if (first == hdr)
1918                 return;
1919
1920         avail = txr->tx_avail;
1921         while (first != hdr) {
1922                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1923
1924                 ++avail;
1925                 if (txbuf->m_head) {
1926                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1927                         m_freem(txbuf->m_head);
1928                         txbuf->m_head = NULL;
1929                         ++ifp->if_opackets;
1930                 }
1931                 if (++first == txr->num_tx_desc)
1932                         first = 0;
1933         }
1934         txr->next_to_clean = first;
1935         txr->tx_avail = avail;
1936
1937         /*
1938          * If we have a minimum free, clear IFF_OACTIVE
1939          * to tell the stack that it is OK to send packets.
1940          */
1941         if (IGB_IS_NOT_OACTIVE(txr)) {
1942                 ifp->if_flags &= ~IFF_OACTIVE;
1943
1944                 /*
1945                  * We have enough TX descriptors, turn off
1946                  * the watchdog.  We allow small amount of
1947                  * packets (roughly intr_nsegs) pending on
1948                  * the transmit ring.
1949                  */
1950                 ifp->if_timer = 0;
1951         }
1952 }
1953
1954 static int
1955 igb_create_rx_ring(struct igb_rx_ring *rxr)
1956 {
1957         int rsize, i, error;
1958
1959         /*
1960          * Validate number of receive descriptors. It must not exceed
1961          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1962          */
1963         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1964             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1965                 device_printf(rxr->sc->dev,
1966                     "Using %d RX descriptors instead of %d!\n",
1967                     IGB_DEFAULT_RXD, igb_rxd);
1968                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1969         } else {
1970                 rxr->num_rx_desc = igb_rxd;
1971         }
1972
1973         /*
1974          * Allocate RX descriptor ring
1975          */
1976         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1977             IGB_DBA_ALIGN);
1978         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1979             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1980             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1981             &rxr->rxdma.dma_paddr);
1982         if (rxr->rxdma.dma_vaddr == NULL) {
1983                 device_printf(rxr->sc->dev,
1984                     "Unable to allocate RxDescriptor memory\n");
1985                 return ENOMEM;
1986         }
1987         rxr->rx_base = rxr->rxdma.dma_vaddr;
1988         bzero(rxr->rx_base, rsize);
1989
1990         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
1991             M_DEVBUF, M_WAITOK | M_ZERO);
1992
1993         /*
1994          * Create DMA tag for RX buffers
1995          */
1996         error = bus_dma_tag_create(rxr->sc->parent_tag,
1997             1, 0,               /* alignment, bounds */
1998             BUS_SPACE_MAXADDR,  /* lowaddr */
1999             BUS_SPACE_MAXADDR,  /* highaddr */
2000             NULL, NULL,         /* filter, filterarg */
2001             MCLBYTES,           /* maxsize */
2002             1,                  /* nsegments */
2003             MCLBYTES,           /* maxsegsize */
2004             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2005             &rxr->rx_tag);
2006         if (error) {
2007                 device_printf(rxr->sc->dev,
2008                     "Unable to create RX payload DMA tag\n");
2009                 kfree(rxr->rx_buf, M_DEVBUF);
2010                 rxr->rx_buf = NULL;
2011                 return error;
2012         }
2013
2014         /*
2015          * Create spare DMA map for RX buffers
2016          */
2017         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2018             &rxr->rx_sparemap);
2019         if (error) {
2020                 device_printf(rxr->sc->dev,
2021                     "Unable to create spare RX DMA maps\n");
2022                 bus_dma_tag_destroy(rxr->rx_tag);
2023                 kfree(rxr->rx_buf, M_DEVBUF);
2024                 rxr->rx_buf = NULL;
2025                 return error;
2026         }
2027
2028         /*
2029          * Create DMA maps for RX buffers
2030          */
2031         for (i = 0; i < rxr->num_rx_desc; i++) {
2032                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2033
2034                 error = bus_dmamap_create(rxr->rx_tag,
2035                     BUS_DMA_WAITOK, &rxbuf->map);
2036                 if (error) {
2037                         device_printf(rxr->sc->dev,
2038                             "Unable to create RX DMA maps\n");
2039                         igb_destroy_rx_ring(rxr, i);
2040                         return error;
2041                 }
2042         }
2043         return 0;
2044 }
2045
2046 static void
2047 igb_free_rx_ring(struct igb_rx_ring *rxr)
2048 {
2049         int i;
2050
2051         for (i = 0; i < rxr->num_rx_desc; ++i) {
2052                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2053
2054                 if (rxbuf->m_head != NULL) {
2055                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2056                         m_freem(rxbuf->m_head);
2057                         rxbuf->m_head = NULL;
2058                 }
2059         }
2060
2061         if (rxr->fmp != NULL)
2062                 m_freem(rxr->fmp);
2063         rxr->fmp = NULL;
2064         rxr->lmp = NULL;
2065 }
2066
2067 static void
2068 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2069 {
2070         int i;
2071
2072         if (rxr->rxdma.dma_vaddr != NULL) {
2073                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2074                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2075                     rxr->rxdma.dma_map);
2076                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2077                 rxr->rxdma.dma_vaddr = NULL;
2078         }
2079
2080         if (rxr->rx_buf == NULL)
2081                 return;
2082
2083         for (i = 0; i < ndesc; ++i) {
2084                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2085
2086                 KKASSERT(rxbuf->m_head == NULL);
2087                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2088         }
2089         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2090         bus_dma_tag_destroy(rxr->rx_tag);
2091
2092         kfree(rxr->rx_buf, M_DEVBUF);
2093         rxr->rx_buf = NULL;
2094 }
2095
2096 static void
2097 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2098 {
2099         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2100         rxd->wb.upper.status_error = 0;
2101 }
2102
2103 static int
2104 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2105 {
2106         struct mbuf *m;
2107         bus_dma_segment_t seg;
2108         bus_dmamap_t map;
2109         struct igb_rx_buf *rxbuf;
2110         int error, nseg;
2111
2112         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2113         if (m == NULL) {
2114                 if (wait) {
2115                         if_printf(&rxr->sc->arpcom.ac_if,
2116                             "Unable to allocate RX mbuf\n");
2117                 }
2118                 return ENOBUFS;
2119         }
2120         m->m_len = m->m_pkthdr.len = MCLBYTES;
2121
2122         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2123                 m_adj(m, ETHER_ALIGN);
2124
2125         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2126             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2127         if (error) {
2128                 m_freem(m);
2129                 if (wait) {
2130                         if_printf(&rxr->sc->arpcom.ac_if,
2131                             "Unable to load RX mbuf\n");
2132                 }
2133                 return error;
2134         }
2135
2136         rxbuf = &rxr->rx_buf[i];
2137         if (rxbuf->m_head != NULL)
2138                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2139
2140         map = rxbuf->map;
2141         rxbuf->map = rxr->rx_sparemap;
2142         rxr->rx_sparemap = map;
2143
2144         rxbuf->m_head = m;
2145         rxbuf->paddr = seg.ds_addr;
2146
2147         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2148         return 0;
2149 }
2150
2151 static int
2152 igb_init_rx_ring(struct igb_rx_ring *rxr)
2153 {
2154         int i;
2155
2156         /* Clear the ring contents */
2157         bzero(rxr->rx_base,
2158             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2159
2160         /* Now replenish the ring mbufs */
2161         for (i = 0; i < rxr->num_rx_desc; ++i) {
2162                 int error;
2163
2164                 error = igb_newbuf(rxr, i, TRUE);
2165                 if (error)
2166                         return error;
2167         }
2168
2169         /* Setup our descriptor indices */
2170         rxr->next_to_check = 0;
2171
2172         rxr->fmp = NULL;
2173         rxr->lmp = NULL;
2174         rxr->discard = FALSE;
2175
2176         return 0;
2177 }
2178
2179 static void
2180 igb_init_rx_unit(struct igb_softc *sc)
2181 {
2182         struct ifnet *ifp = &sc->arpcom.ac_if;
2183         struct e1000_hw *hw = &sc->hw;
2184         uint32_t rctl, rxcsum, srrctl = 0;
2185         int i;
2186
2187         /*
2188          * Make sure receives are disabled while setting
2189          * up the descriptor ring
2190          */
2191         rctl = E1000_READ_REG(hw, E1000_RCTL);
2192         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2193
2194 #if 0
2195         /*
2196         ** Set up for header split
2197         */
2198         if (igb_header_split) {
2199                 /* Use a standard mbuf for the header */
2200                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2201                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2202         } else
2203 #endif
2204                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2205
2206         /*
2207         ** Set up for jumbo frames
2208         */
2209         if (ifp->if_mtu > ETHERMTU) {
2210                 rctl |= E1000_RCTL_LPE;
2211 #if 0
2212                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2213                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2214                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2215                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2216                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2217                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2218                 }
2219                 /* Set maximum packet len */
2220                 psize = adapter->max_frame_size;
2221                 /* are we on a vlan? */
2222                 if (adapter->ifp->if_vlantrunk != NULL)
2223                         psize += VLAN_TAG_SIZE;
2224                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2225 #else
2226                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2227                 rctl |= E1000_RCTL_SZ_2048;
2228 #endif
2229         } else {
2230                 rctl &= ~E1000_RCTL_LPE;
2231                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2232                 rctl |= E1000_RCTL_SZ_2048;
2233         }
2234
2235         /* Setup the Base and Length of the Rx Descriptor Rings */
2236         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2237                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2238                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2239                 uint32_t rxdctl;
2240
2241                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2242                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2243                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2244                     (uint32_t)(bus_addr >> 32));
2245                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2246                     (uint32_t)bus_addr);
2247                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2248                 /* Enable this Queue */
2249                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2250                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2251                 rxdctl &= 0xFFF00000;
2252                 rxdctl |= IGB_RX_PTHRESH;
2253                 rxdctl |= IGB_RX_HTHRESH << 8;
2254                 rxdctl |= IGB_RX_WTHRESH << 16;
2255                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2256         }
2257
2258         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2259         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2260
2261         /*
2262          * Receive Checksum Offload for TCP and UDP
2263          *
2264          * Checksum offloading is also enabled if multiple receive
2265          * queue is to be supported, since we need it to figure out
2266          * fragments.
2267          */
2268         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2269                 /*
2270                  * NOTE:
2271                  * PCSD must be enabled to enable multiple
2272                  * receive queues.
2273                  */
2274                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2275                     E1000_RXCSUM_PCSD;
2276         } else {
2277                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2278                     E1000_RXCSUM_PCSD);
2279         }
2280         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2281
2282         if (IGB_ENABLE_HWRSS(sc)) {
2283                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2284                 uint32_t reta_shift;
2285                 int j, r;
2286
2287                 /*
2288                  * NOTE:
2289                  * When we reach here, RSS has already been disabled
2290                  * in igb_stop(), so we could safely configure RSS key
2291                  * and redirect table.
2292                  */
2293
2294                 /*
2295                  * Configure RSS key
2296                  */
2297                 toeplitz_get_key(key, sizeof(key));
2298                 for (i = 0; i < IGB_NRSSRK; ++i) {
2299                         uint32_t rssrk;
2300
2301                         rssrk = IGB_RSSRK_VAL(key, i);
2302                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2303
2304                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2305                 }
2306
2307                 /*
2308                  * Configure RSS redirect table in following fashion:
2309                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2310                  */
2311                 reta_shift = IGB_RETA_SHIFT;
2312                 if (hw->mac.type == e1000_82575)
2313                         reta_shift = IGB_RETA_SHIFT_82575;
2314
2315                 r = 0;
2316                 for (j = 0; j < IGB_NRETA; ++j) {
2317                         uint32_t reta = 0;
2318
2319                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2320                                 uint32_t q;
2321
2322                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2323                                 reta |= q << (8 * i);
2324                                 ++r;
2325                         }
2326                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2327                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2328                 }
2329
2330                 /*
2331                  * Enable multiple receive queues.
2332                  * Enable IPv4 RSS standard hash functions.
2333                  * Disable RSS interrupt on 82575
2334                  */
2335                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2336                                 E1000_MRQC_ENABLE_RSS_4Q |
2337                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2338                                 E1000_MRQC_RSS_FIELD_IPV4);
2339         }
2340
2341         /* Setup the Receive Control Register */
2342         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2343         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2344             E1000_RCTL_RDMTS_HALF |
2345             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2346         /* Strip CRC bytes. */
2347         rctl |= E1000_RCTL_SECRC;
2348         /* Make sure VLAN Filters are off */
2349         rctl &= ~E1000_RCTL_VFE;
2350         /* Don't store bad packets */
2351         rctl &= ~E1000_RCTL_SBP;
2352
2353         /* Enable Receives */
2354         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2355
2356         /*
2357          * Setup the HW Rx Head and Tail Descriptor Pointers
2358          *   - needs to be after enable
2359          */
2360         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2361                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2362
2363                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2364                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2365         }
2366 }
2367
2368 static void
2369 igb_rxeof(struct igb_rx_ring *rxr, int count)
2370 {
2371         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2372         union e1000_adv_rx_desc *cur;
2373         uint32_t staterr;
2374         int i;
2375
2376         i = rxr->next_to_check;
2377         cur = &rxr->rx_base[i];
2378         staterr = le32toh(cur->wb.upper.status_error);
2379
2380         if ((staterr & E1000_RXD_STAT_DD) == 0)
2381                 return;
2382
2383         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2384                 struct pktinfo *pi = NULL, pi0;
2385                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2386                 struct mbuf *m = NULL;
2387                 boolean_t eop;
2388
2389                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2390                 if (eop)
2391                         --count;
2392
2393                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2394                     !rxr->discard) {
2395                         struct mbuf *mp = rxbuf->m_head;
2396                         uint32_t hash, hashtype;
2397                         uint16_t vlan;
2398                         int len;
2399
2400                         len = le16toh(cur->wb.upper.length);
2401                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2402                             (staterr & E1000_RXDEXT_STATERR_LB))
2403                                 vlan = be16toh(cur->wb.upper.vlan);
2404                         else
2405                                 vlan = le16toh(cur->wb.upper.vlan);
2406
2407                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2408                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2409                             E1000_RXDADV_RSSTYPE_MASK;
2410
2411                         IGB_RSS_DPRINTF(rxr->sc, 10,
2412                             "ring%d, hash 0x%08x, hashtype %u\n",
2413                             rxr->me, hash, hashtype);
2414
2415                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2416                             BUS_DMASYNC_POSTREAD);
2417
2418                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2419                                 ifp->if_iqdrops++;
2420                                 goto discard;
2421                         }
2422
2423                         mp->m_len = len;
2424                         if (rxr->fmp == NULL) {
2425                                 mp->m_pkthdr.len = len;
2426                                 rxr->fmp = mp;
2427                                 rxr->lmp = mp;
2428                         } else {
2429                                 rxr->lmp->m_next = mp;
2430                                 rxr->lmp = rxr->lmp->m_next;
2431                                 rxr->fmp->m_pkthdr.len += len;
2432                         }
2433
2434                         if (eop) {
2435                                 m = rxr->fmp;
2436                                 rxr->fmp = NULL;
2437                                 rxr->lmp = NULL;
2438
2439                                 m->m_pkthdr.rcvif = ifp;
2440                                 ifp->if_ipackets++;
2441
2442                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2443                                         igb_rxcsum(staterr, m);
2444
2445                                 if (staterr & E1000_RXD_STAT_VP) {
2446                                         m->m_pkthdr.ether_vlantag = vlan;
2447                                         m->m_flags |= M_VLANTAG;
2448                                 }
2449
2450                                 if (ifp->if_capenable & IFCAP_RSS) {
2451                                         pi = igb_rssinfo(m, &pi0,
2452                                             hash, hashtype, staterr);
2453                                 }
2454 #ifdef IGB_RSS_DEBUG
2455                                 rxr->rx_packets++;
2456 #endif
2457                         }
2458                 } else {
2459                         ifp->if_ierrors++;
2460 discard:
2461                         igb_setup_rxdesc(cur, rxbuf);
2462                         if (!eop)
2463                                 rxr->discard = TRUE;
2464                         else
2465                                 rxr->discard = FALSE;
2466                         if (rxr->fmp != NULL) {
2467                                 m_freem(rxr->fmp);
2468                                 rxr->fmp = NULL;
2469                                 rxr->lmp = NULL;
2470                         }
2471                         m = NULL;
2472                 }
2473
2474                 if (m != NULL)
2475                         ether_input_pkt(ifp, m, pi);
2476
2477                 /* Advance our pointers to the next descriptor. */
2478                 if (++i == rxr->num_rx_desc)
2479                         i = 0;
2480
2481                 cur = &rxr->rx_base[i];
2482                 staterr = le32toh(cur->wb.upper.status_error);
2483         }
2484         rxr->next_to_check = i;
2485
2486         if (--i < 0)
2487                 i = rxr->num_rx_desc - 1;
2488         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2489 }
2490
2491
2492 static void
2493 igb_set_vlan(struct igb_softc *sc)
2494 {
2495         struct e1000_hw *hw = &sc->hw;
2496         uint32_t reg;
2497 #if 0
2498         struct ifnet *ifp = sc->arpcom.ac_if;
2499 #endif
2500
2501         if (sc->vf_ifp) {
2502                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2503                 return;
2504         }
2505
2506         reg = E1000_READ_REG(hw, E1000_CTRL);
2507         reg |= E1000_CTRL_VME;
2508         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2509
2510 #if 0
2511         /* Enable the Filter Table */
2512         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2513                 reg = E1000_READ_REG(hw, E1000_RCTL);
2514                 reg &= ~E1000_RCTL_CFIEN;
2515                 reg |= E1000_RCTL_VFE;
2516                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2517         }
2518 #endif
2519
2520         /* Update the frame size */
2521         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2522             sc->max_frame_size + VLAN_TAG_SIZE);
2523
2524 #if 0
2525         /* Don't bother with table if no vlans */
2526         if ((adapter->num_vlans == 0) ||
2527             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2528                 return;
2529         /*
2530         ** A soft reset zero's out the VFTA, so
2531         ** we need to repopulate it now.
2532         */
2533         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2534                 if (adapter->shadow_vfta[i] != 0) {
2535                         if (adapter->vf_ifp)
2536                                 e1000_vfta_set_vf(hw,
2537                                     adapter->shadow_vfta[i], TRUE);
2538                         else
2539                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2540                                  i, adapter->shadow_vfta[i]);
2541                 }
2542 #endif
2543 }
2544
2545 static void
2546 igb_enable_intr(struct igb_softc *sc)
2547 {
2548         lwkt_serialize_handler_enable(&sc->main_serialize);
2549
2550         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2551                 /* XXX MSI-X should use sc->intr_mask */
2552                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2553                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2554                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2555                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2556         } else {
2557                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2558         }
2559         E1000_WRITE_FLUSH(&sc->hw);
2560 }
2561
2562 static void
2563 igb_disable_intr(struct igb_softc *sc)
2564 {
2565         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2566                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2567                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2568         }
2569         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2570         E1000_WRITE_FLUSH(&sc->hw);
2571
2572         lwkt_serialize_handler_disable(&sc->main_serialize);
2573 }
2574
2575 /*
2576  * Bit of a misnomer, what this really means is
2577  * to enable OS management of the system... aka
2578  * to disable special hardware management features
2579  */
2580 static void
2581 igb_get_mgmt(struct igb_softc *sc)
2582 {
2583         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2584                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2585                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2586
2587                 /* disable hardware interception of ARP */
2588                 manc &= ~E1000_MANC_ARP_EN;
2589
2590                 /* enable receiving management packets to the host */
2591                 manc |= E1000_MANC_EN_MNG2HOST;
2592                 manc2h |= 1 << 5; /* Mng Port 623 */
2593                 manc2h |= 1 << 6; /* Mng Port 664 */
2594                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2595                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2596         }
2597 }
2598
2599 /*
2600  * Give control back to hardware management controller
2601  * if there is one.
2602  */
2603 static void
2604 igb_rel_mgmt(struct igb_softc *sc)
2605 {
2606         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2607                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2608
2609                 /* Re-enable hardware interception of ARP */
2610                 manc |= E1000_MANC_ARP_EN;
2611                 manc &= ~E1000_MANC_EN_MNG2HOST;
2612
2613                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2614         }
2615 }
2616
2617 /*
2618  * Sets CTRL_EXT:DRV_LOAD bit.
2619  *
2620  * For ASF and Pass Through versions of f/w this means that
2621  * the driver is loaded.
2622  */
2623 static void
2624 igb_get_hw_control(struct igb_softc *sc)
2625 {
2626         uint32_t ctrl_ext;
2627
2628         if (sc->vf_ifp)
2629                 return;
2630
2631         /* Let firmware know the driver has taken over */
2632         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2633         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2634             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2635 }
2636
2637 /*
2638  * Resets CTRL_EXT:DRV_LOAD bit.
2639  *
2640  * For ASF and Pass Through versions of f/w this means that the
2641  * driver is no longer loaded.
2642  */
2643 static void
2644 igb_rel_hw_control(struct igb_softc *sc)
2645 {
2646         uint32_t ctrl_ext;
2647
2648         if (sc->vf_ifp)
2649                 return;
2650
2651         /* Let firmware taken over control of h/w */
2652         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2653         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2654             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2655 }
2656
2657 static int
2658 igb_is_valid_ether_addr(const uint8_t *addr)
2659 {
2660         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2661
2662         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2663                 return FALSE;
2664         return TRUE;
2665 }
2666
2667 /*
2668  * Enable PCI Wake On Lan capability
2669  */
2670 static void
2671 igb_enable_wol(device_t dev)
2672 {
2673         uint16_t cap, status;
2674         uint8_t id;
2675
2676         /* First find the capabilities pointer*/
2677         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2678
2679         /* Read the PM Capabilities */
2680         id = pci_read_config(dev, cap, 1);
2681         if (id != PCIY_PMG)     /* Something wrong */
2682                 return;
2683
2684         /*
2685          * OK, we have the power capabilities,
2686          * so now get the status register
2687          */
2688         cap += PCIR_POWER_STATUS;
2689         status = pci_read_config(dev, cap, 2);
2690         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2691         pci_write_config(dev, cap, status, 2);
2692 }
2693
2694 static void
2695 igb_update_stats_counters(struct igb_softc *sc)
2696 {
2697         struct e1000_hw *hw = &sc->hw;
2698         struct e1000_hw_stats *stats;
2699         struct ifnet *ifp = &sc->arpcom.ac_if;
2700
2701         /*
2702          * The virtual function adapter has only a
2703          * small controlled set of stats, do only
2704          * those and return.
2705          */
2706         if (sc->vf_ifp) {
2707                 igb_update_vf_stats_counters(sc);
2708                 return;
2709         }
2710         stats = sc->stats;
2711
2712         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2713             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2714                 stats->symerrs +=
2715                     E1000_READ_REG(hw,E1000_SYMERRS);
2716                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2717         }
2718
2719         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2720         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2721         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2722         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2723
2724         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2725         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2726         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2727         stats->dc += E1000_READ_REG(hw, E1000_DC);
2728         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2729         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2730         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2731
2732         /*
2733          * For watchdog management we need to know if we have been
2734          * paused during the last interval, so capture that here.
2735          */
2736         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2737         stats->xoffrxc += sc->pause_frames;
2738         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2739         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2740         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2741         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2742         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2743         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2744         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2745         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2746         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2747         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2748         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2749         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2750
2751         /* For the 64-bit byte counters the low dword must be read first. */
2752         /* Both registers clear on the read of the high dword */
2753
2754         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2755             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2756         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2757             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2758
2759         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2760         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2761         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2762         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2763         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2764
2765         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2766         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2767
2768         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2769         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2770         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2771         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2772         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2773         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2774         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2775         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2776         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2777         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2778
2779         /* Interrupt Counts */
2780
2781         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2782         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2783         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2784         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2785         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2786         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2787         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2788         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2789         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2790
2791         /* Host to Card Statistics */
2792
2793         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2794         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2795         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2796         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2797         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2798         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2799         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2800         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2801             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2802         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2803             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2804         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2805         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2806         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2807
2808         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2809         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2810         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2811         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2812         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2813         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2814
2815         ifp->if_collisions = stats->colc;
2816
2817         /* Rx Errors */
2818         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2819             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2820
2821         /* Tx Errors */
2822         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2823
2824         /* Driver specific counters */
2825         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2826         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2827         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2828         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2829         sc->packet_buf_alloc_tx =
2830             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2831         sc->packet_buf_alloc_rx =
2832             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2833 }
2834
2835 static void
2836 igb_vf_init_stats(struct igb_softc *sc)
2837 {
2838         struct e1000_hw *hw = &sc->hw;
2839         struct e1000_vf_stats *stats;
2840
2841         stats = sc->stats;
2842         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2843         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2844         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2845         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2846         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2847 }
2848
2849 static void
2850 igb_update_vf_stats_counters(struct igb_softc *sc)
2851 {
2852         struct e1000_hw *hw = &sc->hw;
2853         struct e1000_vf_stats *stats;
2854
2855         if (sc->link_speed == 0)
2856                 return;
2857
2858         stats = sc->stats;
2859         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2860         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2861         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2862         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2863         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2864 }
2865
2866 #ifdef DEVICE_POLLING
2867
2868 static void
2869 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2870 {
2871         struct igb_softc *sc = ifp->if_softc;
2872         uint32_t reg_icr;
2873
2874         ASSERT_SERIALIZED(&sc->main_serialize);
2875
2876         switch (cmd) {
2877         case POLL_REGISTER:
2878                 igb_disable_intr(sc);
2879                 break;
2880
2881         case POLL_DEREGISTER:
2882                 igb_enable_intr(sc);
2883                 break;
2884
2885         case POLL_AND_CHECK_STATUS:
2886                 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2887                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2888                         sc->hw.mac.get_link_status = 1;
2889                         igb_update_link_status(sc);
2890                 }
2891                 /* FALL THROUGH */
2892         case POLL_ONLY:
2893                 if (ifp->if_flags & IFF_RUNNING) {
2894                         struct igb_tx_ring *txr;
2895                         int i;
2896
2897                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2898                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2899
2900                                 lwkt_serialize_enter(&rxr->rx_serialize);
2901                                 igb_rxeof(rxr, count);
2902                                 lwkt_serialize_exit(&rxr->rx_serialize);
2903                         }
2904
2905                         txr = &sc->tx_rings[0];
2906                         lwkt_serialize_enter(&txr->tx_serialize);
2907                         igb_txeof(txr);
2908                         if (!ifq_is_empty(&ifp->if_snd))
2909                                 if_devstart(ifp);
2910                         lwkt_serialize_exit(&txr->tx_serialize);
2911                 }
2912                 break;
2913         }
2914 }
2915
2916 #endif /* DEVICE_POLLING */
2917
2918 static void
2919 igb_intr(void *xsc)
2920 {
2921         struct igb_softc *sc = xsc;
2922         struct ifnet *ifp = &sc->arpcom.ac_if;
2923         uint32_t eicr;
2924
2925         ASSERT_SERIALIZED(&sc->main_serialize);
2926
2927         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2928
2929         if (eicr == 0)
2930                 return;
2931
2932         if (ifp->if_flags & IFF_RUNNING) {
2933                 struct igb_tx_ring *txr;
2934                 int i;
2935
2936                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2937                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2938
2939                         if (eicr & rxr->rx_intr_mask) {
2940                                 lwkt_serialize_enter(&rxr->rx_serialize);
2941                                 igb_rxeof(rxr, -1);
2942                                 lwkt_serialize_exit(&rxr->rx_serialize);
2943                         }
2944                 }
2945
2946                 txr = &sc->tx_rings[0];
2947                 if (eicr & txr->tx_intr_mask) {
2948                         lwkt_serialize_enter(&txr->tx_serialize);
2949                         igb_txeof(txr);
2950                         if (!ifq_is_empty(&ifp->if_snd))
2951                                 if_devstart(ifp);
2952                         lwkt_serialize_exit(&txr->tx_serialize);
2953                 }
2954         }
2955
2956         if (eicr & E1000_EICR_OTHER) {
2957                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2958
2959                 /* Link status change */
2960                 if (icr & E1000_ICR_LSC) {
2961                         sc->hw.mac.get_link_status = 1;
2962                         igb_update_link_status(sc);
2963                 }
2964         }
2965
2966         /*
2967          * Reading EICR has the side effect to clear interrupt mask,
2968          * so all interrupts need to be enabled here.
2969          */
2970         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2971 }
2972
2973 static void
2974 igb_shared_intr(void *xsc)
2975 {
2976         struct igb_softc *sc = xsc;
2977         struct ifnet *ifp = &sc->arpcom.ac_if;
2978         uint32_t reg_icr;
2979
2980         ASSERT_SERIALIZED(&sc->main_serialize);
2981
2982         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2983
2984         /* Hot eject?  */
2985         if (reg_icr == 0xffffffff)
2986                 return;
2987
2988         /* Definitely not our interrupt.  */
2989         if (reg_icr == 0x0)
2990                 return;
2991
2992         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
2993                 return;
2994
2995         if (ifp->if_flags & IFF_RUNNING) {
2996                 if (reg_icr &
2997                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
2998                         int i;
2999
3000                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3001                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3002
3003                                 lwkt_serialize_enter(&rxr->rx_serialize);
3004                                 igb_rxeof(rxr, -1);
3005                                 lwkt_serialize_exit(&rxr->rx_serialize);
3006                         }
3007                 }
3008
3009                 if (reg_icr & E1000_ICR_TXDW) {
3010                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3011
3012                         lwkt_serialize_enter(&txr->tx_serialize);
3013                         igb_txeof(txr);
3014                         if (!ifq_is_empty(&ifp->if_snd))
3015                                 if_devstart(ifp);
3016                         lwkt_serialize_exit(&txr->tx_serialize);
3017                 }
3018         }
3019
3020         /* Link status change */
3021         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3022                 sc->hw.mac.get_link_status = 1;
3023                 igb_update_link_status(sc);
3024         }
3025
3026         if (reg_icr & E1000_ICR_RXO)
3027                 sc->rx_overruns++;
3028 }
3029
3030 static int
3031 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
3032 {
3033         struct mbuf *m = *m0;
3034         struct ether_header *eh;
3035         int len;
3036
3037         txr->ctx_try_pullup++;
3038
3039         len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
3040
3041         if (__predict_false(!M_WRITABLE(m))) {
3042                 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3043                         txr->ctx_drop1++;
3044                         m_freem(m);
3045                         *m0 = NULL;
3046                         return ENOBUFS;
3047                 }
3048                 eh = mtod(m, struct ether_header *);
3049
3050                 if (eh->ether_type == htons(ETHERTYPE_VLAN))
3051                         len += EVL_ENCAPLEN;
3052
3053                 if (m->m_len < len) {
3054                         txr->ctx_drop2++;
3055                         m_freem(m);
3056                         *m0 = NULL;
3057                         return ENOBUFS;
3058                 }
3059                 return 0;
3060         }
3061
3062         if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3063                 txr->ctx_pullup1++;
3064                 m = m_pullup(m, ETHER_HDR_LEN);
3065                 if (m == NULL) {
3066                         txr->ctx_pullup1_failed++;
3067                         *m0 = NULL;
3068                         return ENOBUFS;
3069                 }
3070                 *m0 = m;
3071         }
3072         eh = mtod(m, struct ether_header *);
3073
3074         if (eh->ether_type == htons(ETHERTYPE_VLAN))
3075                 len += EVL_ENCAPLEN;
3076
3077         if (m->m_len < len) {
3078                 txr->ctx_pullup2++;
3079                 m = m_pullup(m, len);
3080                 if (m == NULL) {
3081                         txr->ctx_pullup2_failed++;
3082                         *m0 = NULL;
3083                         return ENOBUFS;
3084                 }
3085                 *m0 = m;
3086         }
3087         return 0;
3088 }
3089
3090 static int
3091 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3092 {
3093         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3094         bus_dmamap_t map;
3095         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3096         union e1000_adv_tx_desc *txd = NULL;
3097         struct mbuf *m_head = *m_headp;
3098         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3099         int maxsegs, nsegs, i, j, error, last = 0;
3100         uint32_t hdrlen = 0;
3101
3102         if (m_head->m_len < IGB_TXCSUM_MINHL &&
3103             ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
3104              (m_head->m_flags & M_VLANTAG))) {
3105                 /*
3106                  * Make sure that ethernet header and ip.ip_hl are in
3107                  * contiguous memory, since if TXCSUM or VLANTAG is
3108                  * enabled, later TX context descriptor's setup need
3109                  * to access ip.ip_hl.
3110                  */
3111                 error = igb_txctx_pullup(txr, m_headp);
3112                 if (error) {
3113                         KKASSERT(*m_headp == NULL);
3114                         return error;
3115                 }
3116                 m_head = *m_headp;
3117         }
3118
3119         /* Set basic descriptor constants */
3120         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3121         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3122         if (m_head->m_flags & M_VLANTAG)
3123                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3124
3125         /*
3126          * Map the packet for DMA.
3127          */
3128         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3129         tx_buf_mapped = tx_buf;
3130         map = tx_buf->map;
3131
3132         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3133         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3134         if (maxsegs > IGB_MAX_SCATTER)
3135                 maxsegs = IGB_MAX_SCATTER;
3136
3137         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3138             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3139         if (error) {
3140                 if (error == ENOBUFS)
3141                         txr->sc->mbuf_defrag_failed++;
3142                 else
3143                         txr->sc->no_tx_dma_setup++;
3144
3145                 m_freem(*m_headp);
3146                 *m_headp = NULL;
3147                 return error;
3148         }
3149         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3150
3151         m_head = *m_headp;
3152
3153 #if 0
3154         /*
3155          * Set up the context descriptor:
3156          * used when any hardware offload is done.
3157          * This includes CSUM, VLAN, and TSO. It
3158          * will use the first descriptor.
3159          */
3160         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3161                 if (igb_tso_setup(txr, m_head, &hdrlen)) {
3162                         cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3163                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3164                         olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3165                 } else
3166                         return (ENXIO);
3167         } else if (igb_tx_ctx_setup(txr, m_head))
3168                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3169 #else
3170         if (igb_txctx(txr, m_head)) {
3171                 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3172                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3173                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3174                 txr->tx_nsegs++;
3175         }
3176 #endif
3177
3178         txr->tx_nsegs += nsegs;
3179         if (txr->tx_nsegs >= txr->intr_nsegs) {
3180                 /*
3181                  * Report Status (RS) is turned on every intr_nsegs
3182                  * descriptors (roughly).
3183                  */
3184                 txr->tx_nsegs = 0;
3185                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3186         }
3187
3188         /* Calculate payload length */
3189         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3190             << E1000_ADVTXD_PAYLEN_SHIFT);
3191
3192         /* 82575 needs the queue index added */
3193         if (txr->sc->hw.mac.type == e1000_82575)
3194                 olinfo_status |= txr->me << 4;
3195
3196         /* Set up our transmit descriptors */
3197         i = txr->next_avail_desc;
3198         for (j = 0; j < nsegs; j++) {
3199                 bus_size_t seg_len;
3200                 bus_addr_t seg_addr;
3201
3202                 tx_buf = &txr->tx_buf[i];
3203                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3204                 seg_addr = segs[j].ds_addr;
3205                 seg_len = segs[j].ds_len;
3206
3207                 txd->read.buffer_addr = htole64(seg_addr);
3208                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3209                 txd->read.olinfo_status = htole32(olinfo_status);
3210                 last = i;
3211                 if (++i == txr->num_tx_desc)
3212                         i = 0;
3213                 tx_buf->m_head = NULL;
3214         }
3215
3216         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3217         txr->next_avail_desc = i;
3218         txr->tx_avail -= nsegs;
3219
3220         tx_buf->m_head = m_head;
3221         tx_buf_mapped->map = tx_buf->map;
3222         tx_buf->map = map;
3223
3224         /*
3225          * Last Descriptor of Packet needs End Of Packet (EOP)
3226          */
3227         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3228
3229         /*
3230          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3231          * that this frame is available to transmit.
3232          */
3233         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3234         ++txr->tx_packets;
3235
3236         return 0;
3237 }
3238
3239 static void
3240 igb_start(struct ifnet *ifp)
3241 {
3242         struct igb_softc *sc = ifp->if_softc;
3243         struct igb_tx_ring *txr = &sc->tx_rings[0];
3244         struct mbuf *m_head;
3245
3246         ASSERT_SERIALIZED(&txr->tx_serialize);
3247
3248         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3249                 return;
3250
3251         if (!sc->link_active) {
3252                 ifq_purge(&ifp->if_snd);
3253                 return;
3254         }
3255
3256         if (!IGB_IS_NOT_OACTIVE(txr))
3257                 igb_txeof(txr);
3258
3259         while (!ifq_is_empty(&ifp->if_snd)) {
3260                 if (IGB_IS_OACTIVE(txr)) {
3261                         ifp->if_flags |= IFF_OACTIVE;
3262                         /* Set watchdog on */
3263                         ifp->if_timer = 5;
3264                         break;
3265                 }
3266
3267                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3268                 if (m_head == NULL)
3269                         break;
3270
3271                 if (igb_encap(txr, &m_head)) {
3272                         ifp->if_oerrors++;
3273                         continue;
3274                 }
3275
3276                 /* Send a copy of the frame to the BPF listener */
3277                 ETHER_BPF_MTAP(ifp, m_head);
3278         }
3279 }
3280
3281 static void
3282 igb_watchdog(struct ifnet *ifp)
3283 {
3284         struct igb_softc *sc = ifp->if_softc;
3285         struct igb_tx_ring *txr = &sc->tx_rings[0];
3286
3287         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3288
3289         /*
3290          * If flow control has paused us since last checking
3291          * it invalidates the watchdog timing, so dont run it.
3292          */
3293         if (sc->pause_frames) {
3294                 sc->pause_frames = 0;
3295                 ifp->if_timer = 5;
3296                 return;
3297         }
3298
3299         if_printf(ifp, "Watchdog timeout -- resetting\n");
3300         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3301             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3302             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3303         if_printf(ifp, "TX(%d) desc avail = %d, "
3304             "Next TX to Clean = %d\n",
3305             txr->me, txr->tx_avail, txr->next_to_clean);
3306
3307         ifp->if_oerrors++;
3308         sc->watchdog_events++;
3309
3310         igb_init(sc);
3311         if (!ifq_is_empty(&ifp->if_snd))
3312                 if_devstart(ifp);
3313 }
3314
3315 static void
3316 igb_set_eitr(struct igb_softc *sc)
3317 {
3318         uint32_t itr = 0;
3319
3320         if (sc->intr_rate > 0) {
3321                 if (sc->hw.mac.type == e1000_82575) {
3322                         itr = 1000000000 / 256 / sc->intr_rate;
3323                         /*
3324                          * NOTE:
3325                          * Document is wrong on the 2 bits left shift
3326                          */
3327                 } else {
3328                         itr = 1000000 / sc->intr_rate;
3329                         itr <<= 2;
3330                 }
3331                 itr &= 0x7FFC;
3332         }
3333         if (sc->hw.mac.type == e1000_82575)
3334                 itr |= itr << 16;
3335         else
3336                 itr |= E1000_EITR_CNT_IGNR;
3337         E1000_WRITE_REG(&sc->hw, E1000_EITR(0), itr);
3338 }
3339
3340 static int
3341 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3342 {
3343         struct igb_softc *sc = (void *)arg1;
3344         struct ifnet *ifp = &sc->arpcom.ac_if;
3345         int error, intr_rate;
3346
3347         intr_rate = sc->intr_rate;
3348         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3349         if (error || req->newptr == NULL)
3350                 return error;
3351         if (intr_rate < 0)
3352                 return EINVAL;
3353
3354         ifnet_serialize_all(ifp);
3355
3356         sc->intr_rate = intr_rate;
3357         if (ifp->if_flags & IFF_RUNNING)
3358                 igb_set_eitr(sc);
3359
3360         ifnet_deserialize_all(ifp);
3361
3362         if (bootverbose)
3363                 if_printf(ifp, "Interrupt rate set to %d/sec\n", sc->intr_rate);
3364         return 0;
3365 }
3366
3367 static int
3368 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3369 {
3370         struct igb_softc *sc = (void *)arg1;
3371         struct ifnet *ifp = &sc->arpcom.ac_if;
3372         struct igb_tx_ring *txr = &sc->tx_rings[0];
3373         int error, nsegs;
3374
3375         nsegs = txr->intr_nsegs;
3376         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3377         if (error || req->newptr == NULL)
3378                 return error;
3379         if (nsegs <= 0)
3380                 return EINVAL;
3381
3382         ifnet_serialize_all(ifp);
3383
3384         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3385             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3386                 error = EINVAL;
3387         } else {
3388                 error = 0;
3389                 txr->intr_nsegs = nsegs;
3390         }
3391
3392         ifnet_deserialize_all(ifp);
3393
3394         return error;
3395 }
3396
3397 static void
3398 igb_init_intr(struct igb_softc *sc)
3399 {
3400         igb_set_intr_mask(sc);
3401         if (sc->flags & IGB_FLAG_SHARED_INTR)
3402                 igb_set_eitr(sc);
3403         else
3404                 igb_init_unshared_intr(sc);
3405 }
3406
3407 static void
3408 igb_init_unshared_intr(struct igb_softc *sc)
3409 {
3410         struct e1000_hw *hw = &sc->hw;
3411         const struct igb_rx_ring *rxr;
3412         const struct igb_tx_ring *txr;
3413         uint32_t ivar, index;
3414         int i;
3415
3416         /*
3417          * Enable extended mode
3418          */
3419         if (sc->hw.mac.type != e1000_82575) {
3420                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_NSICR);
3421         } else {
3422                 uint32_t tmp;
3423
3424                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3425                 tmp |= E1000_CTRL_EXT_IRCA;
3426                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3427         }
3428
3429         /*
3430          * Map TX/RX interrupts to EICR
3431          */
3432         switch (sc->hw.mac.type) {
3433         case e1000_82580:
3434         case e1000_i350:
3435         case e1000_vfadapt:
3436         case e1000_vfadapt_i350:
3437                 /* RX entries */
3438                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3439                         rxr = &sc->rx_rings[i];
3440
3441                         index = i >> 1;
3442                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3443
3444                         if (i & 1) {
3445                                 ivar &= 0xff00ffff;
3446                                 ivar |=
3447                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3448                         } else {
3449                                 ivar &= 0xffffff00;
3450                                 ivar |=
3451                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3452                         }
3453                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3454                 }
3455                 /* TX entries */
3456                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3457                         txr = &sc->tx_rings[i];
3458
3459                         index = i >> 1;
3460                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3461
3462                         if (i & 1) {
3463                                 ivar &= 0x00ffffff;
3464                                 ivar |=
3465                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3466                         } else {
3467                                 ivar &= 0xffff00ff;
3468                                 ivar |=
3469                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3470                         }
3471                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3472                 }
3473                 /* Clear unused IVAR_MISC */
3474                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3475                 break;
3476
3477         case e1000_82576:
3478                 /* RX entries */
3479                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3480                         rxr = &sc->rx_rings[i];
3481
3482                         index = i & 0x7; /* Each IVAR has two entries */
3483                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3484
3485                         if (i < 8) {
3486                                 ivar &= 0xffffff00;
3487                                 ivar |=
3488                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3489                         } else {
3490                                 ivar &= 0xff00ffff;
3491                                 ivar |=
3492                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3493                         }
3494                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3495                 }
3496                 /* TX entries */
3497                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3498                         txr = &sc->tx_rings[i];
3499
3500                         index = i & 0x7; /* Each IVAR has two entries */
3501                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3502
3503                         if (i < 8) {
3504                                 ivar &= 0xffff00ff;
3505                                 ivar |=
3506                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3507                         } else {
3508                                 ivar &= 0x00ffffff;
3509                                 ivar |=
3510                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3511                         }
3512                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3513                 }
3514                 /* Clear unused IVAR_MISC */
3515                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3516                 break;
3517
3518         case e1000_82575:
3519                 /*
3520                  * Enable necessary interrupt bits.
3521                  *
3522                  * The name of the register is confusing; in addition to
3523                  * configuring the first vector of MSI-X, it also configures
3524                  * which bits of EICR could be set by the hardware even when
3525                  * MSI or line interrupt is used; it thus controls interrupt
3526                  * generation.  It MUST be configured explicitly; the default
3527                  * value mentioned in the datasheet is wrong: RX queue0 and
3528                  * TX queue0 are NOT enabled by default.
3529                  */
3530                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3531                 break;
3532
3533         default:
3534                 break;
3535         }
3536
3537         /*
3538          * Configure interrupt moderation
3539          */
3540         igb_set_eitr(sc);
3541 }
3542
3543 static int
3544 igb_setup_intr(struct igb_softc *sc)
3545 {
3546         struct ifnet *ifp = &sc->arpcom.ac_if;
3547         int error, i, intr_bit, intr_bitmax;
3548
3549         /*
3550          * Setup interrupt mask
3551          */
3552         switch (sc->hw.mac.type) {
3553         case e1000_82575:
3554                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3555                 break;
3556         case e1000_82580:
3557                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3558                 break;
3559         case e1000_i350:
3560                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3561                 break;
3562         case e1000_82576:
3563                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3564                 break;
3565         default:
3566                 intr_bitmax = IGB_MIN_TXRXINT;
3567                 break;
3568         }
3569         intr_bit = 0;
3570         for (i = 0; i < sc->tx_ring_cnt; ++i)
3571                 igb_setup_tx_intr(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3572         for (i = 0; i < sc->rx_ring_cnt; ++i)
3573                 igb_setup_rx_intr(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3574
3575         igb_set_intr_mask(sc);
3576
3577         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3578                 int unshared;
3579
3580                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3581                 if (!unshared) {
3582                         sc->flags |= IGB_FLAG_SHARED_INTR;
3583                         if (bootverbose)
3584                                 device_printf(sc->dev, "IRQ shared\n");
3585                 } else if (bootverbose) {
3586                         device_printf(sc->dev, "IRQ unshared\n");
3587                 }
3588         }
3589
3590         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3591             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_shared_intr : igb_intr,
3592             sc, &sc->intr_tag, &sc->main_serialize);
3593         if (error) {
3594                 device_printf(sc->dev, "Failed to register interrupt handler");
3595                 return error;
3596         }
3597
3598         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3599         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3600
3601         return 0;
3602 }
3603
3604 static void
3605 igb_setup_tx_intr(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3606 {
3607         if (txr->sc->hw.mac.type == e1000_82575) {
3608                 txr->tx_intr_bit = 0;   /* unused */
3609                 switch (txr->me) {
3610                 case 0:
3611                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3612                         break;
3613                 case 1:
3614                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3615                         break;
3616                 case 2:
3617                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3618                         break;
3619                 case 3:
3620                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3621                         break;
3622                 default:
3623                         panic("unsupported # of TX ring, %d\n", txr->me);
3624                 }
3625         } else {
3626                 int intr_bit = *intr_bit0;
3627
3628                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3629                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3630
3631                 *intr_bit0 = intr_bit + 1;
3632         }
3633 }
3634
3635 static void
3636 igb_setup_rx_intr(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3637 {
3638         if (rxr->sc->hw.mac.type == e1000_82575) {
3639                 rxr->rx_intr_bit = 0;   /* unused */
3640                 switch (rxr->me) {
3641                 case 0:
3642                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3643                         break;
3644                 case 1:
3645                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3646                         break;
3647                 case 2:
3648                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3649                         break;
3650                 case 3:
3651                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3652                         break;
3653                 default:
3654                         panic("unsupported # of RX ring, %d\n", rxr->me);
3655                 }
3656         } else {
3657                 int intr_bit = *intr_bit0;
3658
3659                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3660                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3661
3662                 *intr_bit0 = intr_bit + 1;
3663         }
3664 }
3665
3666 static void
3667 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3668 {
3669         struct igb_softc *sc = ifp->if_softc;
3670
3671         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3672             sc->tx_serialize, sc->rx_serialize, slz);
3673 }
3674
3675 static void
3676 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3677 {
3678         struct igb_softc *sc = ifp->if_softc;
3679
3680         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3681             sc->tx_serialize, sc->rx_serialize, slz);
3682 }
3683
3684 static int
3685 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3686 {
3687         struct igb_softc *sc = ifp->if_softc;
3688
3689         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3690             sc->tx_serialize, sc->rx_serialize, slz);
3691 }
3692
3693 #ifdef INVARIANTS
3694
3695 static void
3696 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3697     boolean_t serialized)
3698 {
3699         struct igb_softc *sc = ifp->if_softc;
3700
3701         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3702             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3703 }
3704
3705 #endif  /* INVARIANTS */
3706
3707 static void
3708 igb_set_intr_mask(struct igb_softc *sc)
3709 {
3710         int i;
3711
3712         sc->intr_mask = E1000_EICR_OTHER;
3713         for (i = 0; i < sc->rx_ring_inuse; ++i)
3714                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3715         for (i = 0; i < sc->tx_ring_cnt; ++i)
3716                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3717         if (bootverbose) {
3718                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3719                     sc->intr_mask);
3720         }
3721 }
3722
3723 static int
3724 igb_alloc_intr(struct igb_softc *sc)
3725 {
3726         u_int intr_flags;
3727
3728         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3729             &sc->intr_rid, &intr_flags);
3730
3731         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3732             &sc->intr_rid, intr_flags);
3733         if (sc->intr_res == NULL) {
3734                 device_printf(sc->dev, "Unable to allocate bus resource: "
3735                     "interrupt\n");
3736                 return ENXIO;
3737         }
3738         return 0;
3739 }
3740
3741 static void
3742 igb_free_intr(struct igb_softc *sc)
3743 {
3744         if (sc->intr_res != NULL) {
3745                 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3746                     sc->intr_res);
3747         }
3748         if (sc->intr_type == PCI_INTR_TYPE_MSI)
3749                 pci_release_msi(sc->dev);
3750 }