1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
31 #include <drm/i915_drm.h>
33 #include "intel_drv.h"
34 #include "intel_ringbuffer.h"
35 #include <linux/workqueue.h>
37 extern struct drm_i915_private *i915_mch_dev;
39 extern void i915_pineview_get_mem_freq(struct drm_device *dev);
40 extern void i915_ironlake_get_mem_freq(struct drm_device *dev);
41 static int i915_driver_unload_int(struct drm_device *dev, bool locked);
43 void i915_update_dri1_breadcrumb(struct drm_device *dev)
46 * The dri breadcrumb update races against the drm master disappearing.
47 * Instead of trying to fix this (this is by far not the only ums issue)
48 * just don't do the update in kms mode.
50 if (drm_core_check_feature(dev, DRIVER_MODESET))
53 /* XXX: don't do it at all actually */
57 static void i915_write_hws_pga(struct drm_device *dev)
59 drm_i915_private_t *dev_priv = dev->dev_private;
62 addr = dev_priv->status_page_dmah->busaddr;
63 if (INTEL_INFO(dev)->gen >= 4)
64 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
65 I915_WRITE(HWS_PGA, addr);
69 * Sets up the hardware status page for devices that need a physical address
72 static int i915_init_phys_hws(struct drm_device *dev)
74 drm_i915_private_t *dev_priv = dev->dev_private;
75 struct intel_ring_buffer *ring = LP_RING(dev_priv);
78 * Program Hardware Status Page
79 * XXXKIB Keep 4GB limit for allocation for now. This method
80 * of allocation is used on <= 965 hardware, that has several
81 * erratas regarding the use of physical memory > 4 GB.
84 dev_priv->status_page_dmah =
85 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
87 if (!dev_priv->status_page_dmah) {
88 DRM_ERROR("Can not allocate hardware status page\n");
91 ring->status_page.page_addr = dev_priv->hw_status_page =
92 dev_priv->status_page_dmah->vaddr;
93 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
95 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
97 i915_write_hws_pga(dev);
98 DRM_DEBUG("Enabled hardware status page, phys %jx\n",
99 (uintmax_t)dev_priv->dma_status_page);
104 * Frees the hardware status page, whether it's a physical address or a virtual
105 * address set up by the X Server.
107 static void i915_free_hws(struct drm_device *dev)
109 drm_i915_private_t *dev_priv = dev->dev_private;
110 struct intel_ring_buffer *ring = LP_RING(dev_priv);
112 if (dev_priv->status_page_dmah) {
113 drm_pci_free(dev, dev_priv->status_page_dmah);
114 dev_priv->status_page_dmah = NULL;
117 if (dev_priv->status_gfx_addr) {
118 dev_priv->status_gfx_addr = 0;
119 ring->status_page.gfx_addr = 0;
120 drm_core_ioremapfree(&dev_priv->hws_map, dev);
123 /* Need to rewrite hardware status page */
124 I915_WRITE(HWS_PGA, 0x1ffff000);
127 void i915_kernel_lost_context(struct drm_device * dev)
129 drm_i915_private_t *dev_priv = dev->dev_private;
130 struct intel_ring_buffer *ring = LP_RING(dev_priv);
133 * We should never lose context on the ring with modesetting
134 * as we don't expose it to userspace
136 if (drm_core_check_feature(dev, DRIVER_MODESET))
139 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
140 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
141 ring->space = ring->head - (ring->tail + 8);
143 ring->space += ring->size;
148 if (!dev->primary->master)
152 if (ring->head == ring->tail && dev_priv->sarea_priv)
153 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
156 static int i915_dma_cleanup(struct drm_device * dev)
158 drm_i915_private_t *dev_priv = dev->dev_private;
162 /* Make sure interrupts are disabled here because the uninstall ioctl
163 * may not have been called from userspace and after dev_private
164 * is freed, it's too late.
166 if (dev->irq_enabled)
167 drm_irq_uninstall(dev);
169 for (i = 0; i < I915_NUM_RINGS; i++)
170 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
172 /* Clear the HWS virtual address at teardown */
173 if (I915_NEED_GFX_HWS(dev))
179 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
181 drm_i915_private_t *dev_priv = dev->dev_private;
184 dev_priv->sarea = drm_getsarea(dev);
185 if (!dev_priv->sarea) {
186 DRM_ERROR("can not find sarea!\n");
187 i915_dma_cleanup(dev);
191 dev_priv->sarea_priv = (drm_i915_sarea_t *)
192 ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
194 if (init->ring_size != 0) {
195 if (LP_RING(dev_priv)->obj != NULL) {
196 i915_dma_cleanup(dev);
197 DRM_ERROR("Client tried to initialize ringbuffer in "
202 ret = intel_render_ring_init_dri(dev,
206 i915_dma_cleanup(dev);
211 dev_priv->cpp = init->cpp;
212 dev_priv->back_offset = init->back_offset;
213 dev_priv->front_offset = init->front_offset;
214 dev_priv->current_page = 0;
215 dev_priv->sarea_priv->pf_current_page = 0;
217 /* Allow hardware batchbuffers unless told otherwise.
219 dev_priv->allow_batchbuffer = 1;
224 static int i915_dma_resume(struct drm_device * dev)
226 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
227 struct intel_ring_buffer *ring = LP_RING(dev_priv);
231 if (ring->map.handle == NULL) {
232 DRM_ERROR("can not ioremap virtual address for"
237 /* Program Hardware Status Page */
238 if (!ring->status_page.page_addr) {
239 DRM_ERROR("Can not find hardware status page\n");
242 DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
243 if (ring->status_page.gfx_addr != 0)
244 intel_ring_setup_status_page(ring);
246 i915_write_hws_pga(dev);
248 DRM_DEBUG("Enabled hardware status page\n");
253 static int i915_dma_init(struct drm_device *dev, void *data,
254 struct drm_file *file_priv)
256 drm_i915_init_t *init = data;
259 switch (init->func) {
261 retcode = i915_initialize(dev, init);
263 case I915_CLEANUP_DMA:
264 retcode = i915_dma_cleanup(dev);
266 case I915_RESUME_DMA:
267 retcode = i915_dma_resume(dev);
277 /* Implement basically the same security restrictions as hardware does
278 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
280 * Most of the calculations below involve calculating the size of a
281 * particular instruction. It's important to get the size right as
282 * that tells us where the next instruction to check is. Any illegal
283 * instruction detected will be given a size of zero, which is a
284 * signal to abort the rest of the buffer.
286 static int do_validate_cmd(int cmd)
288 switch (((cmd >> 29) & 0x7)) {
290 switch ((cmd >> 23) & 0x3f) {
292 return 1; /* MI_NOOP */
294 return 1; /* MI_FLUSH */
296 return 0; /* disallow everything else */
300 return 0; /* reserved */
302 return (cmd & 0xff) + 2; /* 2d commands */
304 if (((cmd >> 24) & 0x1f) <= 0x18)
307 switch ((cmd >> 24) & 0x1f) {
311 switch ((cmd >> 16) & 0xff) {
313 return (cmd & 0x1f) + 2;
315 return (cmd & 0xf) + 2;
317 return (cmd & 0xffff) + 2;
321 return (cmd & 0xffff) + 1;
325 if ((cmd & (1 << 23)) == 0) /* inline vertices */
326 return (cmd & 0x1ffff) + 2;
327 else if (cmd & (1 << 17)) /* indirect random */
328 if ((cmd & 0xffff) == 0)
329 return 0; /* unknown length, too hard */
331 return (((cmd & 0xffff) + 1) / 2) + 1;
333 return 2; /* indirect sequential */
344 static int validate_cmd(int cmd)
346 int ret = do_validate_cmd(cmd);
348 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
353 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
356 drm_i915_private_t *dev_priv = dev->dev_private;
359 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
362 ret = BEGIN_LP_RING((dwords+1)&~1);
366 for (i = 0; i < dwords;) {
369 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
372 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
378 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
394 int i915_emit_box(struct drm_device * dev,
395 struct drm_clip_rect *boxes,
396 int i, int DR1, int DR4)
398 struct drm_clip_rect box;
400 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
404 return (i915_emit_box_p(dev, &box, DR1, DR4));
408 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
411 drm_i915_private_t *dev_priv = dev->dev_private;
414 if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
416 DRM_ERROR("Bad box %d,%d..%d,%d\n",
417 box->x1, box->y1, box->x2, box->y2);
421 if (INTEL_INFO(dev)->gen >= 4) {
422 ret = BEGIN_LP_RING(4);
426 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
427 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
428 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
431 ret = BEGIN_LP_RING(6);
435 OUT_RING(GFX_OP_DRAWRECT_INFO);
437 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
438 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
447 /* XXX: Emitting the counter should really be moved to part of the IRQ
448 * emit. For now, do it in both places:
451 static void i915_emit_breadcrumb(struct drm_device *dev)
453 drm_i915_private_t *dev_priv = dev->dev_private;
455 if (++dev_priv->counter > 0x7FFFFFFFUL)
456 dev_priv->counter = 0;
457 if (dev_priv->sarea_priv)
458 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
460 if (BEGIN_LP_RING(4) == 0) {
461 OUT_RING(MI_STORE_DWORD_INDEX);
462 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
463 OUT_RING(dev_priv->counter);
469 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
470 drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
472 int nbox = cmd->num_cliprects;
473 int i = 0, count, ret;
476 DRM_ERROR("alignment\n");
480 i915_kernel_lost_context(dev);
482 count = nbox ? nbox : 1;
484 for (i = 0; i < count; i++) {
486 ret = i915_emit_box_p(dev, &cmd->cliprects[i],
492 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
497 i915_emit_breadcrumb(dev);
502 i915_dispatch_batchbuffer(struct drm_device * dev,
503 drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
505 drm_i915_private_t *dev_priv = dev->dev_private;
506 int nbox = batch->num_cliprects;
509 if ((batch->start | batch->used) & 0x7) {
510 DRM_ERROR("alignment\n");
514 i915_kernel_lost_context(dev);
516 count = nbox ? nbox : 1;
518 for (i = 0; i < count; i++) {
520 int ret = i915_emit_box_p(dev, &cliprects[i],
521 batch->DR1, batch->DR4);
526 if (!IS_I830(dev) && !IS_845G(dev)) {
527 ret = BEGIN_LP_RING(2);
531 if (INTEL_INFO(dev)->gen >= 4) {
532 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
533 MI_BATCH_NON_SECURE_I965);
534 OUT_RING(batch->start);
536 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
537 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
540 ret = BEGIN_LP_RING(4);
544 OUT_RING(MI_BATCH_BUFFER);
545 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
546 OUT_RING(batch->start + batch->used - 4);
552 i915_emit_breadcrumb(dev);
557 static int i915_dispatch_flip(struct drm_device * dev)
559 drm_i915_private_t *dev_priv = dev->dev_private;
562 if (!dev_priv->sarea_priv)
565 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
567 dev_priv->current_page,
568 dev_priv->sarea_priv->pf_current_page);
570 i915_kernel_lost_context(dev);
572 ret = BEGIN_LP_RING(10);
575 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
578 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
580 if (dev_priv->current_page == 0) {
581 OUT_RING(dev_priv->back_offset);
582 dev_priv->current_page = 1;
584 OUT_RING(dev_priv->front_offset);
585 dev_priv->current_page = 0;
589 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
594 if (++dev_priv->counter > 0x7FFFFFFFUL)
595 dev_priv->counter = 0;
596 if (dev_priv->sarea_priv)
597 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
599 if (BEGIN_LP_RING(4) == 0) {
600 OUT_RING(MI_STORE_DWORD_INDEX);
601 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
602 OUT_RING(dev_priv->counter);
607 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
612 i915_quiescent(struct drm_device *dev)
614 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
616 i915_kernel_lost_context(dev);
617 return (intel_wait_ring_idle(ring));
621 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
625 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
628 ret = i915_quiescent(dev);
634 static int i915_batchbuffer(struct drm_device *dev, void *data,
635 struct drm_file *file_priv)
637 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
638 drm_i915_sarea_t *sarea_priv;
639 drm_i915_batchbuffer_t *batch = data;
640 struct drm_clip_rect *cliprects;
644 if (!dev_priv->allow_batchbuffer) {
645 DRM_ERROR("Batchbuffer ioctl disabled\n");
650 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
651 batch->start, batch->used, batch->num_cliprects);
653 cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
654 if (batch->num_cliprects < 0)
656 if (batch->num_cliprects != 0) {
657 cliprects = kmalloc(batch->num_cliprects *
658 sizeof(struct drm_clip_rect), DRM_MEM_DMA,
661 ret = -copyin(batch->cliprects, cliprects,
662 batch->num_cliprects * sizeof(struct drm_clip_rect));
671 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
672 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
674 sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
676 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
679 drm_free(cliprects, DRM_MEM_DMA);
683 static int i915_cmdbuffer(struct drm_device *dev, void *data,
684 struct drm_file *file_priv)
686 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
687 drm_i915_sarea_t *sarea_priv;
688 drm_i915_cmdbuffer_t *cmdbuf = data;
689 struct drm_clip_rect *cliprects = NULL;
693 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
694 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
696 if (cmdbuf->num_cliprects < 0)
701 batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
703 ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
706 goto fail_batch_free;
709 if (cmdbuf->num_cliprects) {
710 cliprects = kmalloc(cmdbuf->num_cliprects *
711 sizeof(struct drm_clip_rect), DRM_MEM_DMA,
713 ret = -copyin(cmdbuf->cliprects, cliprects,
714 cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
722 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
723 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
725 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
729 sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
731 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
734 drm_free(cliprects, DRM_MEM_DMA);
736 drm_free(batch_data, DRM_MEM_DMA);
740 static int i915_emit_irq(struct drm_device * dev)
742 drm_i915_private_t *dev_priv = dev->dev_private;
744 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
747 i915_kernel_lost_context(dev);
749 DRM_DEBUG("i915: emit_irq\n");
752 if (dev_priv->counter > 0x7FFFFFFFUL)
753 dev_priv->counter = 1;
755 if (master_priv->sarea_priv)
756 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
758 if (dev_priv->sarea_priv)
759 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
762 if (BEGIN_LP_RING(4) == 0) {
763 OUT_RING(MI_STORE_DWORD_INDEX);
764 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
765 OUT_RING(dev_priv->counter);
766 OUT_RING(MI_USER_INTERRUPT);
770 return dev_priv->counter;
773 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
775 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
777 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
780 struct intel_ring_buffer *ring = LP_RING(dev_priv);
782 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
783 READ_BREADCRUMB(dev_priv));
786 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
787 if (master_priv->sarea_priv)
788 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
792 if (master_priv->sarea_priv)
793 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
795 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
796 if (dev_priv->sarea_priv) {
797 dev_priv->sarea_priv->last_dispatch =
798 READ_BREADCRUMB(dev_priv);
803 if (dev_priv->sarea_priv)
804 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
808 lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
809 if (ring->irq_get(ring)) {
811 while (ret == 0 && READ_BREADCRUMB(dev_priv) < irq_nr) {
812 ret = -lksleep(ring, &ring->irq_lock, PCATCH,
816 lockmgr(&ring->irq_lock, LK_RELEASE);
819 lockmgr(&ring->irq_lock, LK_RELEASE);
820 if (_intel_wait_for(dev, READ_BREADCRUMB(dev_priv) >= irq_nr,
826 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
827 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
833 /* Needs the lock as it touches the ring.
835 int i915_irq_emit(struct drm_device *dev, void *data,
836 struct drm_file *file_priv)
838 drm_i915_private_t *dev_priv = dev->dev_private;
839 drm_i915_irq_emit_t *emit = data;
842 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
843 DRM_ERROR("called with no initialization\n");
847 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
850 result = i915_emit_irq(dev);
853 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
854 DRM_ERROR("copy_to_user\n");
861 /* Doesn't need the hardware lock.
863 int i915_irq_wait(struct drm_device *dev, void *data,
864 struct drm_file *file_priv)
866 drm_i915_private_t *dev_priv = dev->dev_private;
867 drm_i915_irq_wait_t *irqwait = data;
870 DRM_ERROR("called with no initialization\n");
874 return i915_wait_irq(dev, irqwait->irq_seq);
877 static int i915_flip_bufs(struct drm_device *dev, void *data,
878 struct drm_file *file_priv)
882 DRM_DEBUG("%s\n", __func__);
884 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
886 ret = i915_dispatch_flip(dev);
891 static int i915_getparam(struct drm_device *dev, void *data,
892 struct drm_file *file_priv)
894 drm_i915_private_t *dev_priv = dev->dev_private;
895 drm_i915_getparam_t *param = data;
899 DRM_ERROR("called with no initialization\n");
903 switch (param->param) {
904 case I915_PARAM_IRQ_ACTIVE:
905 value = dev->irq_enabled ? 1 : 0;
907 case I915_PARAM_ALLOW_BATCHBUFFER:
908 value = dev_priv->allow_batchbuffer ? 1 : 0;
910 case I915_PARAM_LAST_DISPATCH:
911 value = READ_BREADCRUMB(dev_priv);
913 case I915_PARAM_CHIPSET_ID:
914 value = dev->pci_device;
916 case I915_PARAM_HAS_GEM:
919 case I915_PARAM_NUM_FENCES_AVAIL:
920 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
922 case I915_PARAM_HAS_OVERLAY:
923 value = dev_priv->overlay ? 1 : 0;
925 case I915_PARAM_HAS_PAGEFLIPPING:
928 case I915_PARAM_HAS_EXECBUF2:
931 case I915_PARAM_HAS_BSD:
932 value = HAS_BSD(dev);
934 case I915_PARAM_HAS_BLT:
935 value = HAS_BLT(dev);
937 case I915_PARAM_HAS_RELAXED_FENCING:
940 case I915_PARAM_HAS_COHERENT_RINGS:
943 case I915_PARAM_HAS_EXEC_CONSTANTS:
944 value = INTEL_INFO(dev)->gen >= 4;
946 case I915_PARAM_HAS_RELAXED_DELTA:
949 case I915_PARAM_HAS_GEN7_SOL_RESET:
952 case I915_PARAM_HAS_LLC:
953 value = HAS_LLC(dev);
956 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
961 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
962 DRM_ERROR("DRM_COPY_TO_USER failed\n");
969 static int i915_setparam(struct drm_device *dev, void *data,
970 struct drm_file *file_priv)
972 drm_i915_private_t *dev_priv = dev->dev_private;
973 drm_i915_setparam_t *param = data;
976 DRM_ERROR("called with no initialization\n");
980 switch (param->param) {
981 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
983 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
984 dev_priv->tex_lru_log_granularity = param->value;
986 case I915_SETPARAM_ALLOW_BATCHBUFFER:
987 dev_priv->allow_batchbuffer = param->value;
989 case I915_SETPARAM_NUM_USED_FENCES:
990 if (param->value > dev_priv->num_fence_regs ||
993 /* Userspace can use first N regs */
994 dev_priv->fence_reg_start = param->value;
997 DRM_DEBUG("unknown parameter %d\n", param->param);
1004 static int i915_set_status_page(struct drm_device *dev, void *data,
1005 struct drm_file *file_priv)
1007 drm_i915_private_t *dev_priv = dev->dev_private;
1008 drm_i915_hws_addr_t *hws = data;
1009 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1011 if (!I915_NEED_GFX_HWS(dev))
1015 DRM_ERROR("called with no initialization\n");
1019 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1020 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1021 DRM_ERROR("tried to set status page when mode setting active\n");
1025 ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
1026 hws->addr & (0x1ffff<<12);
1028 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1029 dev_priv->hws_map.size = 4*1024;
1030 dev_priv->hws_map.type = 0;
1031 dev_priv->hws_map.flags = 0;
1032 dev_priv->hws_map.mtrr = 0;
1034 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
1035 if (dev_priv->hws_map.virtual == NULL) {
1036 i915_dma_cleanup(dev);
1037 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
1038 DRM_ERROR("can not ioremap virtual address for"
1039 " G33 hw status page\n");
1042 ring->status_page.page_addr = dev_priv->hw_status_page =
1043 dev_priv->hws_map.virtual;
1045 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1046 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1047 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
1048 dev_priv->status_gfx_addr);
1049 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1054 intel_enable_ppgtt(struct drm_device *dev)
1056 if (i915_enable_ppgtt >= 0)
1057 return i915_enable_ppgtt;
1059 /* Disable ppgtt on SNB if VT-d is on. */
1060 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
1067 i915_load_gem_init(struct drm_device *dev)
1069 struct drm_i915_private *dev_priv = dev->dev_private;
1070 unsigned long prealloc_size, gtt_size, mappable_size;
1073 prealloc_size = dev_priv->mm.gtt->stolen_size;
1074 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1075 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1077 /* Basic memrange allocator for stolen space */
1078 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1081 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
1082 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
1083 * aperture accordingly when using aliasing ppgtt. */
1084 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
1085 /* For paranoia keep the guard page in between. */
1086 gtt_size -= PAGE_SIZE;
1088 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
1090 ret = i915_gem_init_aliasing_ppgtt(dev);
1096 /* Let GEM Manage all of the aperture.
1098 * However, leave one page at the end still bound to the scratch
1099 * page. There are a number of places where the hardware
1100 * apparently prefetches past the end of the object, and we've
1101 * seen multiple hangs with the GPU head pointer stuck in a
1102 * batchbuffer bound at the last page of the aperture. One page
1103 * should be enough to keep any prefetching inside of the
1106 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1109 ret = i915_gem_init_hw(dev);
1112 i915_gem_cleanup_aliasing_ppgtt(dev);
1117 /* Try to set up FBC with a reasonable compressed buffer size */
1118 if (I915_HAS_FBC(dev) && i915_powersave) {
1121 /* Leave 1M for line length buffer & misc. */
1123 /* Try to get a 32M buffer... */
1124 if (prealloc_size > (36*1024*1024))
1125 cfb_size = 32*1024*1024;
1126 else /* fall back to 7/8 of the stolen space */
1127 cfb_size = prealloc_size * 7 / 8;
1128 i915_setup_compression(dev, cfb_size);
1132 /* Allow hardware batchbuffers unless told otherwise. */
1133 dev_priv->allow_batchbuffer = 1;
1138 i915_load_modeset_init(struct drm_device *dev)
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1143 ret = intel_parse_bios(dev);
1145 DRM_INFO("failed to find VBIOS tables\n");
1148 intel_register_dsm_handler();
1151 /* IIR "flip pending" bit means done if this bit is set */
1152 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1153 dev_priv->flip_pending_is_done = true;
1155 intel_modeset_init(dev);
1157 ret = i915_load_gem_init(dev);
1161 intel_modeset_gem_init(dev);
1163 ret = drm_irq_install(dev);
1167 dev->vblank_disable_allowed = 1;
1169 ret = intel_fbdev_init(dev);
1173 drm_kms_helper_poll_init(dev);
1175 /* We're off and running w/KMS */
1176 dev_priv->mm.suspended = 0;
1182 i915_gem_cleanup_ringbuffer(dev);
1184 i915_gem_cleanup_aliasing_ppgtt(dev);
1189 i915_get_bridge_dev(struct drm_device *dev)
1191 struct drm_i915_private *dev_priv;
1193 dev_priv = dev->dev_private;
1195 dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1196 if (dev_priv->bridge_dev == NULL) {
1197 DRM_ERROR("bridge device not found\n");
1203 #define MCHBAR_I915 0x44
1204 #define MCHBAR_I965 0x48
1205 #define MCHBAR_SIZE (4*4096)
1207 #define DEVEN_REG 0x54
1208 #define DEVEN_MCHBAR_EN (1 << 28)
1210 /* Allocate space for the MCH regs if needed, return nonzero on error */
1212 intel_alloc_mchbar_resource(struct drm_device *dev)
1214 drm_i915_private_t *dev_priv;
1217 u32 temp_lo, temp_hi;
1218 u64 mchbar_addr, temp;
1220 dev_priv = dev->dev_private;
1221 reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1223 if (INTEL_INFO(dev)->gen >= 4)
1224 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1227 temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1228 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1230 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1231 #ifdef XXX_CONFIG_PNP
1233 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1237 /* Get some space for it */
1238 vga = device_get_parent(dev->dev);
1239 dev_priv->mch_res_rid = 0x100;
1240 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1241 dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1242 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1243 if (dev_priv->mch_res == NULL) {
1244 DRM_ERROR("failed mchbar resource alloc\n");
1248 if (INTEL_INFO(dev)->gen >= 4) {
1249 temp = rman_get_start(dev_priv->mch_res);
1251 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1253 pci_write_config(dev_priv->bridge_dev, reg,
1254 rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1259 intel_setup_mchbar(struct drm_device *dev)
1261 drm_i915_private_t *dev_priv;
1266 dev_priv = dev->dev_private;
1267 mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1269 dev_priv->mchbar_need_disable = false;
1271 if (IS_I915G(dev) || IS_I915GM(dev)) {
1272 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1273 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1275 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1279 /* If it's already enabled, don't have to do anything */
1281 DRM_DEBUG("mchbar already enabled\n");
1285 if (intel_alloc_mchbar_resource(dev))
1288 dev_priv->mchbar_need_disable = true;
1290 /* Space is allocated or reserved, so enable it. */
1291 if (IS_I915G(dev) || IS_I915GM(dev)) {
1292 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1293 temp | DEVEN_MCHBAR_EN, 4);
1295 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1296 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1301 intel_teardown_mchbar(struct drm_device *dev)
1303 drm_i915_private_t *dev_priv;
1308 dev_priv = dev->dev_private;
1309 mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1311 if (dev_priv->mchbar_need_disable) {
1312 if (IS_I915G(dev) || IS_I915GM(dev)) {
1313 temp = pci_read_config(dev_priv->bridge_dev,
1315 temp &= ~DEVEN_MCHBAR_EN;
1316 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1319 temp = pci_read_config(dev_priv->bridge_dev,
1322 pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1327 if (dev_priv->mch_res != NULL) {
1328 vga = device_get_parent(dev->dev);
1329 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1330 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1331 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1332 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1333 dev_priv->mch_res = NULL;
1338 * i915_driver_load - setup chip and create an initial config
1340 * @flags: startup flags
1342 * The driver load routine has to do several things:
1343 * - drive output discovery via intel_modeset_init()
1344 * - initialize the memory manager
1345 * - allocate initial config memory
1346 * - setup the DRM framebuffer with the allocated memory
1348 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1350 struct drm_i915_private *dev_priv = dev->dev_private;
1351 unsigned long base, size;
1356 /* i915 has 4 more counters */
1358 dev->types[6] = _DRM_STAT_IRQ;
1359 dev->types[7] = _DRM_STAT_PRIMARY;
1360 dev->types[8] = _DRM_STAT_SECONDARY;
1361 dev->types[9] = _DRM_STAT_DMA;
1363 dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1365 if (dev_priv == NULL)
1368 dev->dev_private = (void *)dev_priv;
1369 dev_priv->dev = dev;
1370 dev_priv->info = i915_get_device_id(dev->pci_device);
1372 if (i915_get_bridge_dev(dev)) {
1373 drm_free(dev_priv, DRM_MEM_DRIVER);
1376 dev_priv->mm.gtt = intel_gtt_get();
1378 /* Add register map (needed for suspend/resume) */
1379 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1380 base = drm_get_resource_start(dev, mmio_bar);
1381 size = drm_get_resource_len(dev, mmio_bar);
1383 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1384 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1386 /* The i915 workqueue is primarily used for batched retirement of
1387 * requests (and thus managing bo) once the task has been completed
1388 * by the GPU. i915_gem_retire_requests() is called directly when we
1389 * need high-priority retirement, such as waiting for an explicit
1392 * It is also used for periodic low-priority events, such as
1393 * idle-timers and recording error state.
1395 * All tasks on the workqueue are expected to acquire the dev mutex
1396 * so there is no point in running more than one instance of the
1397 * workqueue at any time. Use an ordered one.
1399 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1400 if (dev_priv->wq == NULL) {
1401 DRM_ERROR("Failed to create our workqueue.\n");
1406 intel_irq_init(dev);
1409 /* Try to make sure MCHBAR is enabled before poking at it */
1410 intel_setup_mchbar(dev);
1411 intel_setup_gmbus(dev);
1412 intel_opregion_setup(dev);
1414 intel_setup_bios(dev);
1418 /* On the 945G/GM, the chipset reports the MSI capability on the
1419 * integrated graphics even though the support isn't actually there
1420 * according to the published specs. It doesn't appear to function
1421 * correctly in testing on 945G.
1422 * This may be a side effect of MSI having been made available for PEG
1423 * and the registers being closely associated.
1425 * According to chipset errata, on the 965GM, MSI interrupts may
1426 * be lost or delayed, but we use them anyways to avoid
1427 * stuck interrupts on some machines.
1430 lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1431 lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1432 spin_init(&dev_priv->rps.lock);
1433 lockinit(&dev_priv->error_completion_lock, "915cmp", 0, LK_CANRECURSE);
1435 lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1438 if (!I915_NEED_GFX_HWS(dev)) {
1439 ret = i915_init_phys_hws(dev);
1441 drm_rmmap(dev, dev_priv->mmio_map);
1442 drm_free(dev_priv, DRM_MEM_DRIVER);
1447 if (IS_PINEVIEW(dev))
1448 i915_pineview_get_mem_freq(dev);
1449 else if (IS_GEN5(dev))
1450 i915_ironlake_get_mem_freq(dev);
1452 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1453 dev_priv->num_pipe = 3;
1454 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1455 dev_priv->num_pipe = 2;
1457 dev_priv->num_pipe = 1;
1459 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1461 goto out_gem_unload;
1463 /* Start out suspended */
1464 dev_priv->mm.suspended = 1;
1466 intel_detect_pch(dev);
1468 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1469 ret = i915_load_modeset_init(dev);
1471 DRM_ERROR("failed to init modeset\n");
1472 goto out_gem_unload;
1476 intel_opregion_init(dev);
1478 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1479 (unsigned long) dev);
1482 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1483 i915_mch_dev = dev_priv;
1484 dev_priv->mchdev_lock = &mchdev_lock;
1485 lockmgr(&mchdev_lock, LK_RELEASE);
1492 (void) i915_driver_unload_int(dev, true);
1499 i915_driver_unload_int(struct drm_device *dev, bool locked)
1501 struct drm_i915_private *dev_priv = dev->dev_private;
1506 ret = i915_gpu_idle(dev, true);
1508 DRM_ERROR("failed to idle hardware: %d\n", ret);
1514 intel_teardown_mchbar(dev);
1518 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1519 intel_fbdev_fini(dev);
1520 intel_modeset_cleanup(dev);
1523 /* Free error state after interrupts are fully disabled. */
1524 del_timer_sync(&dev_priv->hangcheck_timer);
1526 i915_destroy_error_state(dev);
1528 intel_opregion_fini(dev);
1533 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1536 i915_gem_free_all_phys_object(dev);
1537 i915_gem_cleanup_ringbuffer(dev);
1540 i915_gem_cleanup_aliasing_ppgtt(dev);
1544 if (I915_HAS_FBC(dev) && i915_powersave)
1545 i915_cleanup_compression(dev);
1547 drm_mm_takedown(&dev_priv->mm.stolen);
1549 intel_cleanup_overlay(dev);
1551 if (!I915_NEED_GFX_HWS(dev))
1555 i915_gem_unload(dev);
1557 lockuninit(&dev_priv->irq_lock);
1559 if (dev_priv->wq != NULL)
1560 destroy_workqueue(dev_priv->wq);
1562 bus_generic_detach(dev->dev);
1563 drm_rmmap(dev, dev_priv->mmio_map);
1564 intel_teardown_gmbus(dev);
1566 lockuninit(&dev_priv->error_lock);
1567 lockuninit(&dev_priv->error_completion_lock);
1568 drm_free(dev->dev_private, DRM_MEM_DRIVER);
1574 i915_driver_unload(struct drm_device *dev)
1577 return (i915_driver_unload_int(dev, true));
1581 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1583 struct drm_i915_file_private *i915_file_priv;
1585 i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1588 spin_init(&i915_file_priv->mm.lock);
1589 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1590 file_priv->driver_priv = i915_file_priv;
1596 i915_driver_lastclose(struct drm_device * dev)
1598 drm_i915_private_t *dev_priv = dev->dev_private;
1600 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1604 drm_fb_helper_restore();
1605 vga_switcheroo_process_delayed_switch();
1609 i915_gem_lastclose(dev);
1610 i915_dma_cleanup(dev);
1613 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1616 i915_gem_release(dev, file_priv);
1619 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1621 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1623 spin_uninit(&i915_file_priv->mm.lock);
1624 drm_free(i915_file_priv, DRM_MEM_FILES);
1627 struct drm_ioctl_desc i915_ioctls[] = {
1628 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1629 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1630 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1631 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1632 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1633 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1634 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1635 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1636 DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1637 DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1638 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1639 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1640 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1641 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1642 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1643 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1644 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1645 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1646 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1647 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1648 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1649 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1650 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1651 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1652 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1653 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1654 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1655 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1656 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1657 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1658 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1659 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1660 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1661 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1662 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1663 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1664 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1665 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1666 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1667 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1668 DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1669 DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1672 struct drm_driver i915_driver_info = {
1673 .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1674 DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1675 DRIVER_GEM /*| DRIVER_MODESET*/,
1677 .buf_priv_size = sizeof(drm_i915_private_t),
1678 .load = i915_driver_load,
1679 .open = i915_driver_open,
1680 .unload = i915_driver_unload,
1681 .preclose = i915_driver_preclose,
1682 .lastclose = i915_driver_lastclose,
1683 .postclose = i915_driver_postclose,
1684 .device_is_agp = i915_driver_device_is_agp,
1685 .gem_init_object = i915_gem_init_object,
1686 .gem_free_object = i915_gem_free_object,
1687 .gem_pager_ops = &i915_gem_pager_ops,
1688 .dumb_create = i915_gem_dumb_create,
1689 .dumb_map_offset = i915_gem_mmap_gtt,
1690 .dumb_destroy = i915_gem_dumb_destroy,
1691 .sysctl_init = i915_sysctl_init,
1692 .sysctl_cleanup = i915_sysctl_cleanup,
1694 .ioctls = i915_ioctls,
1695 .max_ioctl = DRM_ARRAY_SIZE(i915_ioctls),
1697 .name = DRIVER_NAME,
1698 .desc = DRIVER_DESC,
1699 .date = DRIVER_DATE,
1700 .major = DRIVER_MAJOR,
1701 .minor = DRIVER_MINOR,
1702 .patchlevel = DRIVER_PATCHLEVEL,
1706 * Determine if the device really is AGP or not.
1708 * All Intel graphics chipsets are treated as AGP, even if they are really
1711 * \param dev The device to be tested.
1714 * A value of 1 is always retured to indictate every i9x5 is AGP.
1716 int i915_driver_device_is_agp(struct drm_device * dev)