2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
30 #include "opt_polling.h"
33 #include <sys/param.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
37 #include <sys/interrupt.h>
38 #include <sys/malloc.h>
41 #include <sys/serialize.h>
42 #include <sys/serialize2.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
47 #include <net/ethernet.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/ifq_var.h>
54 #include <net/toeplitz.h>
55 #include <net/toeplitz2.h>
56 #include <net/vlan/if_vlan_var.h>
57 #include <net/vlan/if_vlan_ether.h>
59 #include <netinet/in.h>
61 #include <dev/netif/mii_layer/miivar.h>
62 #include <dev/netif/mii_layer/jmphyreg.h>
64 #include <bus/pci/pcireg.h>
65 #include <bus/pci/pcivar.h>
66 #include <bus/pci/pcidevs.h>
68 #include <dev/netif/jme/if_jmereg.h>
69 #include <dev/netif/jme/if_jmevar.h>
71 #include "miibus_if.h"
73 #define JME_TX_SERIALIZE 1
74 #define JME_RX_SERIALIZE 2
76 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
79 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
81 if ((sc)->jme_rss_debug >= (lvl)) \
82 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
84 #else /* !JME_RSS_DEBUG */
85 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
86 #endif /* JME_RSS_DEBUG */
88 static int jme_probe(device_t);
89 static int jme_attach(device_t);
90 static int jme_detach(device_t);
91 static int jme_shutdown(device_t);
92 static int jme_suspend(device_t);
93 static int jme_resume(device_t);
95 static int jme_miibus_readreg(device_t, int, int);
96 static int jme_miibus_writereg(device_t, int, int, int);
97 static void jme_miibus_statchg(device_t);
99 static void jme_init(void *);
100 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
101 static void jme_start(struct ifnet *);
102 static void jme_watchdog(struct ifnet *);
103 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
104 static int jme_mediachange(struct ifnet *);
105 #ifdef DEVICE_POLLING
106 static void jme_poll(struct ifnet *, enum poll_cmd, int);
108 static void jme_serialize(struct ifnet *, enum ifnet_serialize);
109 static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
110 static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
112 static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
116 static void jme_intr(void *);
117 static void jme_msix_tx(void *);
118 static void jme_msix_rx(void *);
119 static void jme_txeof(struct jme_softc *);
120 static void jme_rxeof(struct jme_rxdata *, int);
121 static void jme_rx_intr(struct jme_softc *, uint32_t);
123 static int jme_msix_setup(device_t);
124 static void jme_msix_teardown(device_t, int);
125 static int jme_intr_setup(device_t);
126 static void jme_intr_teardown(device_t);
127 static void jme_msix_try_alloc(device_t);
128 static void jme_msix_free(device_t);
129 static int jme_intr_alloc(device_t);
130 static void jme_intr_free(device_t);
131 static int jme_dma_alloc(struct jme_softc *);
132 static void jme_dma_free(struct jme_softc *);
133 static int jme_init_rx_ring(struct jme_rxdata *);
134 static void jme_init_tx_ring(struct jme_softc *);
135 static void jme_init_ssb(struct jme_softc *);
136 static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
137 static int jme_encap(struct jme_softc *, struct mbuf **);
138 static void jme_rxpkt(struct jme_rxdata *);
139 static int jme_rxring_dma_alloc(struct jme_rxdata *);
140 static int jme_rxbuf_dma_alloc(struct jme_rxdata *);
141 static int jme_rxbuf_dma_filter(void *, bus_addr_t);
143 static void jme_tick(void *);
144 static void jme_stop(struct jme_softc *);
145 static void jme_reset(struct jme_softc *);
146 static void jme_set_msinum(struct jme_softc *);
147 static void jme_set_vlan(struct jme_softc *);
148 static void jme_set_filter(struct jme_softc *);
149 static void jme_stop_tx(struct jme_softc *);
150 static void jme_stop_rx(struct jme_softc *);
151 static void jme_mac_config(struct jme_softc *);
152 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
153 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
154 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
156 static void jme_setwol(struct jme_softc *);
157 static void jme_setlinkspeed(struct jme_softc *);
159 static void jme_set_tx_coal(struct jme_softc *);
160 static void jme_set_rx_coal(struct jme_softc *);
161 static void jme_enable_rss(struct jme_softc *);
162 static void jme_disable_rss(struct jme_softc *);
164 static void jme_sysctl_node(struct jme_softc *);
165 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
166 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
167 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
168 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
171 * Devices supported by this driver.
173 static const struct jme_dev {
174 uint16_t jme_vendorid;
175 uint16_t jme_deviceid;
177 const char *jme_name;
179 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
181 "JMicron Inc, JMC250 Gigabit Ethernet" },
182 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
184 "JMicron Inc, JMC260 Fast Ethernet" },
188 static device_method_t jme_methods[] = {
189 /* Device interface. */
190 DEVMETHOD(device_probe, jme_probe),
191 DEVMETHOD(device_attach, jme_attach),
192 DEVMETHOD(device_detach, jme_detach),
193 DEVMETHOD(device_shutdown, jme_shutdown),
194 DEVMETHOD(device_suspend, jme_suspend),
195 DEVMETHOD(device_resume, jme_resume),
198 DEVMETHOD(bus_print_child, bus_generic_print_child),
199 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
202 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
203 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
204 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
209 static driver_t jme_driver = {
212 sizeof(struct jme_softc)
215 static devclass_t jme_devclass;
217 DECLARE_DUMMY_MODULE(if_jme);
218 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
219 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
220 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
222 static const struct {
226 } jme_rx_status[JME_NRXRING_MAX] = {
227 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
228 INTR_RXQ0_DESC_EMPTY },
229 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
230 INTR_RXQ1_DESC_EMPTY },
231 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
232 INTR_RXQ2_DESC_EMPTY },
233 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
234 INTR_RXQ3_DESC_EMPTY }
237 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
238 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
239 static int jme_rx_ring_count = 0;
240 static int jme_msi_enable = 1;
241 static int jme_msix_enable = 1;
243 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
244 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
245 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
246 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
247 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
250 jme_setup_rxdesc(struct jme_rxdesc *rxd)
252 struct jme_desc *desc;
255 desc->buflen = htole32(MCLBYTES);
256 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
257 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
258 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
262 * Read a PHY register on the MII of the JMC250.
265 jme_miibus_readreg(device_t dev, int phy, int reg)
267 struct jme_softc *sc = device_get_softc(dev);
271 /* For FPGA version, PHY address 0 should be ignored. */
272 if (sc->jme_caps & JME_CAP_FPGA) {
276 if (sc->jme_phyaddr != phy)
280 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
281 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
283 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
285 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
289 device_printf(sc->jme_dev, "phy read timeout: "
290 "phy %d, reg %d\n", phy, reg);
294 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
298 * Write a PHY register on the MII of the JMC250.
301 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
303 struct jme_softc *sc = device_get_softc(dev);
306 /* For FPGA version, PHY address 0 should be ignored. */
307 if (sc->jme_caps & JME_CAP_FPGA) {
311 if (sc->jme_phyaddr != phy)
315 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
316 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
317 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
319 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
321 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
325 device_printf(sc->jme_dev, "phy write timeout: "
326 "phy %d, reg %d\n", phy, reg);
333 * Callback from MII layer when media changes.
336 jme_miibus_statchg(device_t dev)
338 struct jme_softc *sc = device_get_softc(dev);
339 struct ifnet *ifp = &sc->arpcom.ac_if;
340 struct mii_data *mii;
341 struct jme_txdesc *txd;
345 ASSERT_IFNET_SERIALIZED_ALL(ifp);
347 if ((ifp->if_flags & IFF_RUNNING) == 0)
350 mii = device_get_softc(sc->jme_miibus);
352 sc->jme_flags &= ~JME_FLAG_LINK;
353 if ((mii->mii_media_status & IFM_AVALID) != 0) {
354 switch (IFM_SUBTYPE(mii->mii_media_active)) {
357 sc->jme_flags |= JME_FLAG_LINK;
360 if (sc->jme_caps & JME_CAP_FASTETH)
362 sc->jme_flags |= JME_FLAG_LINK;
370 * Disabling Rx/Tx MACs have a side-effect of resetting
371 * JME_TXNDA/JME_RXNDA register to the first address of
372 * Tx/Rx descriptor address. So driver should reset its
373 * internal procucer/consumer pointer and reclaim any
374 * allocated resources. Note, just saving the value of
375 * JME_TXNDA and JME_RXNDA registers before stopping MAC
376 * and restoring JME_TXNDA/JME_RXNDA register is not
377 * sufficient to make sure correct MAC state because
378 * stopping MAC operation can take a while and hardware
379 * might have updated JME_TXNDA/JME_RXNDA registers
380 * during the stop operation.
383 /* Disable interrupts */
384 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
387 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
389 callout_stop(&sc->jme_tick_ch);
391 /* Stop receiver/transmitter. */
395 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
396 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
398 jme_rxeof(rdata, -1);
399 if (rdata->jme_rxhead != NULL)
400 m_freem(rdata->jme_rxhead);
401 JME_RXCHAIN_RESET(rdata);
404 * Reuse configured Rx descriptors and reset
405 * procuder/consumer index.
407 rdata->jme_rx_cons = 0;
409 if (JME_ENABLE_HWRSS(sc))
415 if (sc->jme_cdata.jme_tx_cnt != 0) {
416 /* Remove queued packets for transmit. */
417 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
418 txd = &sc->jme_cdata.jme_txdesc[i];
419 if (txd->tx_m != NULL) {
421 sc->jme_cdata.jme_tx_tag,
430 jme_init_tx_ring(sc);
432 /* Initialize shadow status block. */
435 /* Program MAC with resolved speed/duplex/flow-control. */
436 if (sc->jme_flags & JME_FLAG_LINK) {
439 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
441 /* Set Tx ring address to the hardware. */
442 paddr = sc->jme_cdata.jme_tx_ring_paddr;
443 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
444 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
446 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
447 CSR_WRITE_4(sc, JME_RXCSR,
448 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
450 /* Set Rx ring address to the hardware. */
451 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
452 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
453 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
456 /* Restart receiver/transmitter. */
457 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
459 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
462 ifp->if_flags |= IFF_RUNNING;
463 ifp->if_flags &= ~IFF_OACTIVE;
464 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
466 #ifdef DEVICE_POLLING
467 if (!(ifp->if_flags & IFF_POLLING))
469 /* Reenable interrupts. */
470 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
474 * Get the current interface media status.
477 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
479 struct jme_softc *sc = ifp->if_softc;
480 struct mii_data *mii = device_get_softc(sc->jme_miibus);
482 ASSERT_IFNET_SERIALIZED_ALL(ifp);
485 ifmr->ifm_status = mii->mii_media_status;
486 ifmr->ifm_active = mii->mii_media_active;
490 * Set hardware to newly-selected media.
493 jme_mediachange(struct ifnet *ifp)
495 struct jme_softc *sc = ifp->if_softc;
496 struct mii_data *mii = device_get_softc(sc->jme_miibus);
499 ASSERT_IFNET_SERIALIZED_ALL(ifp);
501 if (mii->mii_instance != 0) {
502 struct mii_softc *miisc;
504 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
505 mii_phy_reset(miisc);
507 error = mii_mediachg(mii);
513 jme_probe(device_t dev)
515 const struct jme_dev *sp;
518 vid = pci_get_vendor(dev);
519 did = pci_get_device(dev);
520 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
521 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
522 struct jme_softc *sc = device_get_softc(dev);
524 sc->jme_caps = sp->jme_caps;
525 device_set_desc(dev, sp->jme_name);
533 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
539 for (i = JME_TIMEOUT; i > 0; i--) {
540 reg = CSR_READ_4(sc, JME_SMBCSR);
541 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
547 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
551 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
552 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
553 for (i = JME_TIMEOUT; i > 0; i--) {
555 reg = CSR_READ_4(sc, JME_SMBINTF);
556 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
561 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
565 reg = CSR_READ_4(sc, JME_SMBINTF);
566 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
572 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
574 uint8_t fup, reg, val;
579 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
580 fup != JME_EEPROM_SIG0)
582 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
583 fup != JME_EEPROM_SIG1)
587 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
589 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
590 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
591 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
593 if (reg >= JME_PAR0 &&
594 reg < JME_PAR0 + ETHER_ADDR_LEN) {
595 if (jme_eeprom_read_byte(sc, offset + 2,
598 eaddr[reg - JME_PAR0] = val;
602 /* Check for the end of EEPROM descriptor. */
603 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
605 /* Try next eeprom descriptor. */
606 offset += JME_EEPROM_DESC_BYTES;
607 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
609 if (match == ETHER_ADDR_LEN)
616 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
620 /* Read station address. */
621 par0 = CSR_READ_4(sc, JME_PAR0);
622 par1 = CSR_READ_4(sc, JME_PAR1);
624 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
625 device_printf(sc->jme_dev,
626 "generating fake ethernet address.\n");
627 par0 = karc4random();
628 /* Set OUI to JMicron. */
632 eaddr[3] = (par0 >> 16) & 0xff;
633 eaddr[4] = (par0 >> 8) & 0xff;
634 eaddr[5] = par0 & 0xff;
636 eaddr[0] = (par0 >> 0) & 0xFF;
637 eaddr[1] = (par0 >> 8) & 0xFF;
638 eaddr[2] = (par0 >> 16) & 0xFF;
639 eaddr[3] = (par0 >> 24) & 0xFF;
640 eaddr[4] = (par1 >> 0) & 0xFF;
641 eaddr[5] = (par1 >> 8) & 0xFF;
646 jme_attach(device_t dev)
648 struct jme_softc *sc = device_get_softc(dev);
649 struct ifnet *ifp = &sc->arpcom.ac_if;
652 uint8_t pcie_ptr, rev;
653 int error = 0, i, j, rx_desc_cnt;
654 uint8_t eaddr[ETHER_ADDR_LEN];
656 lwkt_serialize_init(&sc->jme_serialize);
657 lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
658 for (i = 0; i < JME_NRXRING_MAX; ++i) {
660 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
663 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
665 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
666 if (rx_desc_cnt > JME_NDESC_MAX)
667 rx_desc_cnt = JME_NDESC_MAX;
669 sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
671 sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
673 if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
674 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
679 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
681 sc->jme_cdata.jme_rx_ring_cnt =
682 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
685 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
687 KKASSERT(i == JME_TX_SERIALIZE);
688 sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
690 KKASSERT(i == JME_RX_SERIALIZE);
691 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
692 sc->jme_serialize_arr[i++] =
693 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
695 KKASSERT(i <= JME_NSERIALIZE);
696 sc->jme_serialize_cnt = i;
698 sc->jme_cdata.jme_sc = sc;
699 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
700 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
703 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
704 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
705 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
706 rdata->jme_rx_idx = i;
707 rdata->jme_rx_desc_cnt = rx_desc_cnt;
711 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
713 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
715 callout_init(&sc->jme_tick_ch);
718 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
721 irq = pci_read_config(dev, PCIR_INTLINE, 4);
722 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
724 device_printf(dev, "chip is in D%d power mode "
725 "-- setting to D0\n", pci_get_powerstate(dev));
727 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
729 pci_write_config(dev, PCIR_INTLINE, irq, 4);
730 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
732 #endif /* !BURN_BRIDGE */
734 /* Enable bus mastering */
735 pci_enable_busmaster(dev);
740 * JMC250 supports both memory mapped and I/O register space
741 * access. Because I/O register access should use different
742 * BARs to access registers it's waste of time to use I/O
743 * register spce access. JMC250 uses 16K to map entire memory
746 sc->jme_mem_rid = JME_PCIR_BAR;
747 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
748 &sc->jme_mem_rid, RF_ACTIVE);
749 if (sc->jme_mem_res == NULL) {
750 device_printf(dev, "can't allocate IO memory\n");
753 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
754 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
759 error = jme_intr_alloc(dev);
766 reg = CSR_READ_4(sc, JME_CHIPMODE);
767 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
769 sc->jme_caps |= JME_CAP_FPGA;
771 device_printf(dev, "FPGA revision: 0x%04x\n",
772 (reg & CHIPMODE_FPGA_REV_MASK) >>
773 CHIPMODE_FPGA_REV_SHIFT);
777 /* NOTE: FM revision is put in the upper 4 bits */
778 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
779 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
781 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
783 did = pci_get_device(dev);
785 case PCI_PRODUCT_JMICRON_JMC250:
786 if (rev == JME_REV1_A2)
787 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
790 case PCI_PRODUCT_JMICRON_JMC260:
792 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
796 panic("unknown device id 0x%04x", did);
798 if (rev >= JME_REV2) {
799 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
800 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
801 GHC_TXMAC_CLKSRC_1000;
804 /* Reset the ethernet controller. */
807 /* Map MSI/MSI-X vectors */
810 /* Get station address. */
811 reg = CSR_READ_4(sc, JME_SMBCSR);
812 if (reg & SMBCSR_EEPROM_PRESENT)
813 error = jme_eeprom_macaddr(sc, eaddr);
814 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
815 if (error != 0 && (bootverbose)) {
816 device_printf(dev, "ethernet hardware address "
817 "not found in EEPROM.\n");
819 jme_reg_macaddr(sc, eaddr);
824 * Integrated JR0211 has fixed PHY address whereas FPGA version
825 * requires PHY probing to get correct PHY address.
827 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
828 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
829 GPREG0_PHY_ADDR_MASK;
831 device_printf(dev, "PHY is at address %d.\n",
838 /* Set max allowable DMA size. */
839 pcie_ptr = pci_get_pciecap_ptr(dev);
843 sc->jme_caps |= JME_CAP_PCIE;
844 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
846 device_printf(dev, "Read request size : %d bytes.\n",
847 128 << ((ctrl >> 12) & 0x07));
848 device_printf(dev, "TLP payload size : %d bytes.\n",
849 128 << ((ctrl >> 5) & 0x07));
851 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
852 case PCIEM_DEVCTL_MAX_READRQ_128:
853 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
855 case PCIEM_DEVCTL_MAX_READRQ_256:
856 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
859 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
862 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
864 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
865 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
869 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
870 sc->jme_caps |= JME_CAP_PMCAP;
878 /* Allocate DMA stuffs */
879 error = jme_dma_alloc(sc);
884 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
885 ifp->if_init = jme_init;
886 ifp->if_ioctl = jme_ioctl;
887 ifp->if_start = jme_start;
888 #ifdef DEVICE_POLLING
889 ifp->if_poll = jme_poll;
891 ifp->if_watchdog = jme_watchdog;
892 ifp->if_serialize = jme_serialize;
893 ifp->if_deserialize = jme_deserialize;
894 ifp->if_tryserialize = jme_tryserialize;
896 ifp->if_serialize_assert = jme_serialize_assert;
898 ifq_set_maxlen(&ifp->if_snd,
899 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
900 ifq_set_ready(&ifp->if_snd);
902 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
903 ifp->if_capabilities = IFCAP_HWCSUM |
905 IFCAP_VLAN_HWTAGGING;
906 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
907 ifp->if_capabilities |= IFCAP_RSS;
908 ifp->if_capenable = ifp->if_capabilities;
911 * Disable TXCSUM by default to improve bulk data
912 * transmit performance (+20Mbps improvement).
914 ifp->if_capenable &= ~IFCAP_TXCSUM;
916 if (ifp->if_capenable & IFCAP_TXCSUM)
917 ifp->if_hwassist = JME_CSUM_FEATURES;
919 /* Set up MII bus. */
920 error = mii_phy_probe(dev, &sc->jme_miibus,
921 jme_mediachange, jme_mediastatus);
923 device_printf(dev, "no PHY found!\n");
928 * Save PHYADDR for FPGA mode PHY.
930 if (sc->jme_caps & JME_CAP_FPGA) {
931 struct mii_data *mii = device_get_softc(sc->jme_miibus);
933 if (mii->mii_instance != 0) {
934 struct mii_softc *miisc;
936 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
937 if (miisc->mii_phy != 0) {
938 sc->jme_phyaddr = miisc->mii_phy;
942 if (sc->jme_phyaddr != 0) {
943 device_printf(sc->jme_dev,
944 "FPGA PHY is at %d\n", sc->jme_phyaddr);
946 jme_miibus_writereg(dev, sc->jme_phyaddr,
947 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
949 /* XXX should we clear JME_WA_EXTFIFO */
954 ether_ifattach(ifp, eaddr, NULL);
956 /* Tell the upper layer(s) we support long frames. */
957 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
959 error = jme_intr_setup(dev);
972 jme_detach(device_t dev)
974 struct jme_softc *sc = device_get_softc(dev);
976 if (device_is_attached(dev)) {
977 struct ifnet *ifp = &sc->arpcom.ac_if;
979 ifnet_serialize_all(ifp);
981 jme_intr_teardown(dev);
982 ifnet_deserialize_all(ifp);
987 if (sc->jme_sysctl_tree != NULL)
988 sysctl_ctx_free(&sc->jme_sysctl_ctx);
990 if (sc->jme_miibus != NULL)
991 device_delete_child(dev, sc->jme_miibus);
992 bus_generic_detach(dev);
996 if (sc->jme_mem_res != NULL) {
997 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
1007 jme_sysctl_node(struct jme_softc *sc)
1010 #ifdef JME_RSS_DEBUG
1014 sysctl_ctx_init(&sc->jme_sysctl_ctx);
1015 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1016 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1017 device_get_nameunit(sc->jme_dev),
1019 if (sc->jme_sysctl_tree == NULL) {
1020 device_printf(sc->jme_dev, "can't add sysctl node\n");
1024 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1025 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1026 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1027 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1029 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1030 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1031 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1032 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1034 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1035 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1036 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1037 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1039 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1040 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1041 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1042 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1044 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1045 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1046 "rx_desc_count", CTLFLAG_RD,
1047 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1048 0, "RX desc count");
1049 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1050 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1051 "tx_desc_count", CTLFLAG_RD,
1052 &sc->jme_cdata.jme_tx_desc_cnt,
1053 0, "TX desc count");
1054 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1055 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1056 "rx_ring_count", CTLFLAG_RD,
1057 &sc->jme_cdata.jme_rx_ring_cnt,
1058 0, "RX ring count");
1059 #ifdef JME_RSS_DEBUG
1060 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1061 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1062 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1063 0, "RSS debug level");
1064 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1065 char rx_ring_pkt[32];
1067 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1068 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1069 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1070 rx_ring_pkt, CTLFLAG_RW,
1071 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1076 * Set default coalesce valves
1078 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1079 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1080 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1081 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1084 * Adjust coalesce valves, in case that the number of TX/RX
1085 * descs are set to small values by users.
1087 * NOTE: coal_max will not be zero, since number of descs
1088 * must aligned by JME_NDESC_ALIGN (16 currently)
1090 coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6;
1091 if (coal_max < sc->jme_tx_coal_pkt)
1092 sc->jme_tx_coal_pkt = coal_max;
1094 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
1095 if (coal_max < sc->jme_rx_coal_pkt)
1096 sc->jme_rx_coal_pkt = coal_max;
1100 jme_dma_alloc(struct jme_softc *sc)
1102 struct jme_txdesc *txd;
1104 int error, i, asize;
1106 sc->jme_cdata.jme_txdesc =
1107 kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1108 M_DEVBUF, M_WAITOK | M_ZERO);
1109 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1110 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1113 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1114 M_DEVBUF, M_WAITOK | M_ZERO);
1117 /* Create parent ring tag. */
1118 error = bus_dma_tag_create(NULL,/* parent */
1119 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1120 sc->jme_lowaddr, /* lowaddr */
1121 BUS_SPACE_MAXADDR, /* highaddr */
1122 NULL, NULL, /* filter, filterarg */
1123 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1125 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1127 &sc->jme_cdata.jme_ring_tag);
1129 device_printf(sc->jme_dev,
1130 "could not create parent ring DMA tag.\n");
1135 * Create DMA stuffs for TX ring
1137 asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
1138 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1139 JME_TX_RING_ALIGN, 0,
1140 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1141 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1143 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1146 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1147 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1148 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1149 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1152 * Create DMA stuffs for RX rings
1154 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1155 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1160 /* Create parent buffer tag. */
1161 error = bus_dma_tag_create(NULL,/* parent */
1162 1, 0, /* algnmnt, boundary */
1163 sc->jme_lowaddr, /* lowaddr */
1164 BUS_SPACE_MAXADDR, /* highaddr */
1165 NULL, NULL, /* filter, filterarg */
1166 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1168 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1170 &sc->jme_cdata.jme_buffer_tag);
1172 device_printf(sc->jme_dev,
1173 "could not create parent buffer DMA tag.\n");
1178 * Create DMA stuffs for shadow status block
1180 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1181 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1182 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1183 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1185 device_printf(sc->jme_dev,
1186 "could not create shadow status block.\n");
1189 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1190 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1191 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1192 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1195 * Create DMA stuffs for TX buffers
1198 /* Create tag for Tx buffers. */
1199 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1200 1, 0, /* algnmnt, boundary */
1201 BUS_SPACE_MAXADDR, /* lowaddr */
1202 BUS_SPACE_MAXADDR, /* highaddr */
1203 NULL, NULL, /* filter, filterarg */
1204 JME_JUMBO_FRAMELEN, /* maxsize */
1205 JME_MAXTXSEGS, /* nsegments */
1206 JME_MAXSEGSIZE, /* maxsegsize */
1207 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1208 &sc->jme_cdata.jme_tx_tag);
1210 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1214 /* Create DMA maps for Tx buffers. */
1215 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1216 txd = &sc->jme_cdata.jme_txdesc[i];
1217 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1218 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1223 device_printf(sc->jme_dev,
1224 "could not create %dth Tx dmamap.\n", i);
1226 for (j = 0; j < i; ++j) {
1227 txd = &sc->jme_cdata.jme_txdesc[j];
1228 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1231 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1232 sc->jme_cdata.jme_tx_tag = NULL;
1238 * Create DMA stuffs for RX buffers
1240 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1241 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1249 jme_dma_free(struct jme_softc *sc)
1251 struct jme_txdesc *txd;
1252 struct jme_rxdesc *rxd;
1253 struct jme_rxdata *rdata;
1257 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1258 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1259 sc->jme_cdata.jme_tx_ring_map);
1260 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1261 sc->jme_cdata.jme_tx_ring,
1262 sc->jme_cdata.jme_tx_ring_map);
1263 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1264 sc->jme_cdata.jme_tx_ring_tag = NULL;
1268 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1269 rdata = &sc->jme_cdata.jme_rx_data[r];
1270 if (rdata->jme_rx_ring_tag != NULL) {
1271 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1272 rdata->jme_rx_ring_map);
1273 bus_dmamem_free(rdata->jme_rx_ring_tag,
1275 rdata->jme_rx_ring_map);
1276 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1277 rdata->jme_rx_ring_tag = NULL;
1282 if (sc->jme_cdata.jme_tx_tag != NULL) {
1283 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1284 txd = &sc->jme_cdata.jme_txdesc[i];
1285 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1288 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1289 sc->jme_cdata.jme_tx_tag = NULL;
1293 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1294 rdata = &sc->jme_cdata.jme_rx_data[r];
1295 if (rdata->jme_rx_tag != NULL) {
1296 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1297 rxd = &rdata->jme_rxdesc[i];
1298 bus_dmamap_destroy(rdata->jme_rx_tag,
1301 bus_dmamap_destroy(rdata->jme_rx_tag,
1302 rdata->jme_rx_sparemap);
1303 bus_dma_tag_destroy(rdata->jme_rx_tag);
1304 rdata->jme_rx_tag = NULL;
1308 /* Shadow status block. */
1309 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1310 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1311 sc->jme_cdata.jme_ssb_map);
1312 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1313 sc->jme_cdata.jme_ssb_block,
1314 sc->jme_cdata.jme_ssb_map);
1315 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1316 sc->jme_cdata.jme_ssb_tag = NULL;
1319 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1320 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1321 sc->jme_cdata.jme_buffer_tag = NULL;
1323 if (sc->jme_cdata.jme_ring_tag != NULL) {
1324 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1325 sc->jme_cdata.jme_ring_tag = NULL;
1328 if (sc->jme_cdata.jme_txdesc != NULL) {
1329 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1330 sc->jme_cdata.jme_txdesc = NULL;
1332 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1333 rdata = &sc->jme_cdata.jme_rx_data[r];
1334 if (rdata->jme_rxdesc != NULL) {
1335 kfree(rdata->jme_rxdesc, M_DEVBUF);
1336 rdata->jme_rxdesc = NULL;
1342 * Make sure the interface is stopped at reboot time.
1345 jme_shutdown(device_t dev)
1347 return jme_suspend(dev);
1352 * Unlike other ethernet controllers, JMC250 requires
1353 * explicit resetting link speed to 10/100Mbps as gigabit
1354 * link will cunsume more power than 375mA.
1355 * Note, we reset the link speed to 10/100Mbps with
1356 * auto-negotiation but we don't know whether that operation
1357 * would succeed or not as we have no control after powering
1358 * off. If the renegotiation fail WOL may not work. Running
1359 * at 1Gbps draws more power than 375mA at 3.3V which is
1360 * specified in PCI specification and that would result in
1361 * complete shutdowning power to ethernet controller.
1364 * Save current negotiated media speed/duplex/flow-control
1365 * to softc and restore the same link again after resuming.
1366 * PHY handling such as power down/resetting to 100Mbps
1367 * may be better handled in suspend method in phy driver.
1370 jme_setlinkspeed(struct jme_softc *sc)
1372 struct mii_data *mii;
1375 JME_LOCK_ASSERT(sc);
1377 mii = device_get_softc(sc->jme_miibus);
1380 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1381 switch IFM_SUBTYPE(mii->mii_media_active) {
1391 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1392 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1393 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1394 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1395 BMCR_AUTOEN | BMCR_STARTNEG);
1398 /* Poll link state until jme(4) get a 10/100 link. */
1399 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1401 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1402 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1412 pause("jmelnk", hz);
1415 if (i == MII_ANEGTICKS_GIGE)
1416 device_printf(sc->jme_dev, "establishing link failed, "
1417 "WOL may not work!");
1420 * No link, force MAC to have 100Mbps, full-duplex link.
1421 * This is the last resort and may/may not work.
1423 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1424 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1429 jme_setwol(struct jme_softc *sc)
1431 struct ifnet *ifp = &sc->arpcom.ac_if;
1436 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1437 /* No PME capability, PHY power down. */
1438 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1439 MII_BMCR, BMCR_PDOWN);
1443 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1444 pmcs = CSR_READ_4(sc, JME_PMCS);
1445 pmcs &= ~PMCS_WOL_ENB_MASK;
1446 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1447 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1448 /* Enable PME message. */
1449 gpr |= GPREG0_PME_ENB;
1450 /* For gigabit controllers, reset link speed to 10/100. */
1451 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1452 jme_setlinkspeed(sc);
1455 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1456 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1459 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1460 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1461 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1462 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1463 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1464 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1465 /* No WOL, PHY power down. */
1466 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1467 MII_BMCR, BMCR_PDOWN);
1473 jme_suspend(device_t dev)
1475 struct jme_softc *sc = device_get_softc(dev);
1476 struct ifnet *ifp = &sc->arpcom.ac_if;
1478 ifnet_serialize_all(ifp);
1483 ifnet_deserialize_all(ifp);
1489 jme_resume(device_t dev)
1491 struct jme_softc *sc = device_get_softc(dev);
1492 struct ifnet *ifp = &sc->arpcom.ac_if;
1497 ifnet_serialize_all(ifp);
1500 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1503 pmstat = pci_read_config(sc->jme_dev,
1504 pmc + PCIR_POWER_STATUS, 2);
1505 /* Disable PME clear PME status. */
1506 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1507 pci_write_config(sc->jme_dev,
1508 pmc + PCIR_POWER_STATUS, pmstat, 2);
1512 if (ifp->if_flags & IFF_UP)
1515 ifnet_deserialize_all(ifp);
1521 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1523 struct jme_txdesc *txd;
1524 struct jme_desc *desc;
1526 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1528 int error, i, prod, symbol_desc;
1529 uint32_t cflags, flag64;
1531 M_ASSERTPKTHDR((*m_head));
1533 prod = sc->jme_cdata.jme_tx_prod;
1534 txd = &sc->jme_cdata.jme_txdesc[prod];
1536 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1541 maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1542 (JME_TXD_RSVD + symbol_desc);
1543 if (maxsegs > JME_MAXTXSEGS)
1544 maxsegs = JME_MAXTXSEGS;
1545 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1546 ("not enough segments %d", maxsegs));
1548 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1549 txd->tx_dmamap, m_head,
1550 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1554 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1555 BUS_DMASYNC_PREWRITE);
1560 /* Configure checksum offload. */
1561 if (m->m_pkthdr.csum_flags & CSUM_IP)
1562 cflags |= JME_TD_IPCSUM;
1563 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1564 cflags |= JME_TD_TCPCSUM;
1565 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1566 cflags |= JME_TD_UDPCSUM;
1568 /* Configure VLAN. */
1569 if (m->m_flags & M_VLANTAG) {
1570 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1571 cflags |= JME_TD_VLAN_TAG;
1574 desc = &sc->jme_cdata.jme_tx_ring[prod];
1575 desc->flags = htole32(cflags);
1576 desc->addr_hi = htole32(m->m_pkthdr.len);
1577 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1579 * Use 64bits TX desc chain format.
1581 * The first TX desc of the chain, which is setup here,
1582 * is just a symbol TX desc carrying no payload.
1584 flag64 = JME_TD_64BIT;
1588 /* No effective TX desc is consumed */
1592 * Use 32bits TX desc chain format.
1594 * The first TX desc of the chain, which is setup here,
1595 * is an effective TX desc carrying the first segment of
1599 desc->buflen = htole32(txsegs[0].ds_len);
1600 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1602 /* One effective TX desc is consumed */
1605 sc->jme_cdata.jme_tx_cnt++;
1606 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1607 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1608 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1610 txd->tx_ndesc = 1 - i;
1611 for (; i < nsegs; i++) {
1612 desc = &sc->jme_cdata.jme_tx_ring[prod];
1613 desc->buflen = htole32(txsegs[i].ds_len);
1614 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1615 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1616 desc->flags = htole32(JME_TD_OWN | flag64);
1618 sc->jme_cdata.jme_tx_cnt++;
1619 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1620 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1621 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1624 /* Update producer index. */
1625 sc->jme_cdata.jme_tx_prod = prod;
1627 * Finally request interrupt and give the first descriptor
1628 * owenership to hardware.
1630 desc = txd->tx_desc;
1631 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1634 txd->tx_ndesc += nsegs;
1644 jme_start(struct ifnet *ifp)
1646 struct jme_softc *sc = ifp->if_softc;
1647 struct mbuf *m_head;
1650 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1652 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1653 ifq_purge(&ifp->if_snd);
1657 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1660 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1663 while (!ifq_is_empty(&ifp->if_snd)) {
1665 * Check number of available TX descs, always
1666 * leave JME_TXD_RSVD free TX descs.
1668 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1669 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
1670 ifp->if_flags |= IFF_OACTIVE;
1674 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1679 * Pack the data into the transmit ring. If we
1680 * don't have room, set the OACTIVE flag and wait
1681 * for the NIC to drain the ring.
1683 if (jme_encap(sc, &m_head)) {
1684 KKASSERT(m_head == NULL);
1686 ifp->if_flags |= IFF_OACTIVE;
1692 * If there's a BPF listener, bounce a copy of this frame
1695 ETHER_BPF_MTAP(ifp, m_head);
1700 * Reading TXCSR takes very long time under heavy load
1701 * so cache TXCSR value and writes the ORed value with
1702 * the kick command to the TXCSR. This saves one register
1705 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1706 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1707 /* Set a timeout in case the chip goes out to lunch. */
1708 ifp->if_timer = JME_TX_TIMEOUT;
1713 jme_watchdog(struct ifnet *ifp)
1715 struct jme_softc *sc = ifp->if_softc;
1717 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1719 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1720 if_printf(ifp, "watchdog timeout (missed link)\n");
1727 if (sc->jme_cdata.jme_tx_cnt == 0) {
1728 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1730 if (!ifq_is_empty(&ifp->if_snd))
1735 if_printf(ifp, "watchdog timeout\n");
1738 if (!ifq_is_empty(&ifp->if_snd))
1743 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1745 struct jme_softc *sc = ifp->if_softc;
1746 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1747 struct ifreq *ifr = (struct ifreq *)data;
1748 int error = 0, mask;
1750 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1754 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1755 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1756 ifr->ifr_mtu > JME_MAX_MTU)) {
1761 if (ifp->if_mtu != ifr->ifr_mtu) {
1763 * No special configuration is required when interface
1764 * MTU is changed but availability of Tx checksum
1765 * offload should be chcked against new MTU size as
1766 * FIFO size is just 2K.
1768 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1769 ifp->if_capenable &= ~IFCAP_TXCSUM;
1770 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1772 ifp->if_mtu = ifr->ifr_mtu;
1773 if (ifp->if_flags & IFF_RUNNING)
1779 if (ifp->if_flags & IFF_UP) {
1780 if (ifp->if_flags & IFF_RUNNING) {
1781 if ((ifp->if_flags ^ sc->jme_if_flags) &
1782 (IFF_PROMISC | IFF_ALLMULTI))
1788 if (ifp->if_flags & IFF_RUNNING)
1791 sc->jme_if_flags = ifp->if_flags;
1796 if (ifp->if_flags & IFF_RUNNING)
1802 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1806 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1808 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1809 ifp->if_capenable ^= IFCAP_TXCSUM;
1810 if (IFCAP_TXCSUM & ifp->if_capenable)
1811 ifp->if_hwassist |= JME_CSUM_FEATURES;
1813 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1815 if (mask & IFCAP_RXCSUM) {
1818 ifp->if_capenable ^= IFCAP_RXCSUM;
1819 reg = CSR_READ_4(sc, JME_RXMAC);
1820 reg &= ~RXMAC_CSUM_ENB;
1821 if (ifp->if_capenable & IFCAP_RXCSUM)
1822 reg |= RXMAC_CSUM_ENB;
1823 CSR_WRITE_4(sc, JME_RXMAC, reg);
1826 if (mask & IFCAP_VLAN_HWTAGGING) {
1827 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1831 if (mask & IFCAP_RSS)
1832 ifp->if_capenable ^= IFCAP_RSS;
1836 error = ether_ioctl(ifp, cmd, data);
1843 jme_mac_config(struct jme_softc *sc)
1845 struct mii_data *mii;
1846 uint32_t ghc, rxmac, txmac, txpause, gp1;
1847 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1849 mii = device_get_softc(sc->jme_miibus);
1851 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1853 CSR_WRITE_4(sc, JME_GHC, 0);
1855 rxmac = CSR_READ_4(sc, JME_RXMAC);
1856 rxmac &= ~RXMAC_FC_ENB;
1857 txmac = CSR_READ_4(sc, JME_TXMAC);
1858 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1859 txpause = CSR_READ_4(sc, JME_TXPFC);
1860 txpause &= ~TXPFC_PAUSE_ENB;
1861 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1862 ghc |= GHC_FULL_DUPLEX;
1863 rxmac &= ~RXMAC_COLL_DET_ENB;
1864 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1865 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1868 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1869 txpause |= TXPFC_PAUSE_ENB;
1870 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1871 rxmac |= RXMAC_FC_ENB;
1873 /* Disable retry transmit timer/retry limit. */
1874 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1875 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1877 rxmac |= RXMAC_COLL_DET_ENB;
1878 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1879 /* Enable retry transmit timer/retry limit. */
1880 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1881 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1885 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1887 gp1 = CSR_READ_4(sc, JME_GPREG1);
1888 gp1 &= ~GPREG1_WA_HDX;
1890 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1893 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1895 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1897 gp1 |= GPREG1_WA_HDX;
1901 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1903 gp1 |= GPREG1_WA_HDX;
1906 * Use extended FIFO depth to workaround CRC errors
1907 * emitted by chips before JMC250B
1909 phyconf = JMPHY_CONF_EXTFIFO;
1913 if (sc->jme_caps & JME_CAP_FASTETH)
1916 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1918 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1924 CSR_WRITE_4(sc, JME_GHC, ghc);
1925 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1926 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1927 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1929 if (sc->jme_workaround & JME_WA_EXTFIFO) {
1930 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1931 JMPHY_CONF, phyconf);
1933 if (sc->jme_workaround & JME_WA_HDX)
1934 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1940 struct jme_softc *sc = xsc;
1941 struct ifnet *ifp = &sc->arpcom.ac_if;
1945 ASSERT_SERIALIZED(&sc->jme_serialize);
1947 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1948 if (status == 0 || status == 0xFFFFFFFF)
1951 /* Disable interrupts. */
1952 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1954 status = CSR_READ_4(sc, JME_INTR_STATUS);
1955 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1958 /* Reset PCC counter/timer and Ack interrupts. */
1959 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1961 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1962 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1964 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1965 if (status & jme_rx_status[r].jme_coal) {
1966 status |= jme_rx_status[r].jme_coal |
1967 jme_rx_status[r].jme_comp;
1971 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1973 if (ifp->if_flags & IFF_RUNNING) {
1974 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1975 jme_rx_intr(sc, status);
1977 if (status & INTR_RXQ_DESC_EMPTY) {
1979 * Notify hardware availability of new Rx buffers.
1980 * Reading RXCSR takes very long time under heavy
1981 * load so cache RXCSR value and writes the ORed
1982 * value with the kick command to the RXCSR. This
1983 * saves one register access cycle.
1985 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1986 RXCSR_RX_ENB | RXCSR_RXQ_START);
1989 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1990 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
1992 if (!ifq_is_empty(&ifp->if_snd))
1994 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
1998 /* Reenable interrupts. */
1999 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2003 jme_txeof(struct jme_softc *sc)
2005 struct ifnet *ifp = &sc->arpcom.ac_if;
2008 cons = sc->jme_cdata.jme_tx_cons;
2009 if (cons == sc->jme_cdata.jme_tx_prod)
2013 * Go through our Tx list and free mbufs for those
2014 * frames which have been transmitted.
2016 while (cons != sc->jme_cdata.jme_tx_prod) {
2017 struct jme_txdesc *txd, *next_txd;
2018 uint32_t status, next_status;
2019 int next_cons, nsegs;
2021 txd = &sc->jme_cdata.jme_txdesc[cons];
2022 KASSERT(txd->tx_m != NULL,
2023 ("%s: freeing NULL mbuf!", __func__));
2025 status = le32toh(txd->tx_desc->flags);
2026 if ((status & JME_TD_OWN) == JME_TD_OWN)
2031 * This chip will always update the TX descriptor's
2032 * buflen field and this updating always happens
2033 * after clearing the OWN bit, so even if the OWN
2034 * bit is cleared by the chip, we still don't sure
2035 * about whether the buflen field has been updated
2036 * by the chip or not. To avoid this race, we wait
2037 * for the next TX descriptor's OWN bit to be cleared
2038 * by the chip before reusing this TX descriptor.
2041 JME_DESC_ADD(next_cons, txd->tx_ndesc,
2042 sc->jme_cdata.jme_tx_desc_cnt);
2043 next_txd = &sc->jme_cdata.jme_txdesc[next_cons];
2044 if (next_txd->tx_m == NULL)
2046 next_status = le32toh(next_txd->tx_desc->flags);
2047 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2050 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2054 if (status & JME_TD_COLLISION) {
2055 ifp->if_collisions +=
2056 le32toh(txd->tx_desc->buflen) &
2057 JME_TD_BUF_LEN_MASK;
2062 * Only the first descriptor of multi-descriptor
2063 * transmission is updated so driver have to skip entire
2064 * chained buffers for the transmiited frame. In other
2065 * words, JME_TD_OWN bit is valid only at the first
2066 * descriptor of a multi-descriptor transmission.
2068 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2069 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2070 JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
2073 /* Reclaim transferred mbufs. */
2074 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2077 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2078 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2079 ("%s: Active Tx desc counter was garbled", __func__));
2082 sc->jme_cdata.jme_tx_cons = cons;
2084 if (sc->jme_cdata.jme_tx_cnt < JME_MAXTXSEGS + 1)
2087 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2088 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
2089 ifp->if_flags &= ~IFF_OACTIVE;
2092 static __inline void
2093 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2097 for (i = 0; i < count; ++i) {
2098 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
2099 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2103 static __inline struct pktinfo *
2104 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2106 if (flags & JME_RD_IPV4)
2107 pi->pi_netisr = NETISR_IP;
2108 else if (flags & JME_RD_IPV6)
2109 pi->pi_netisr = NETISR_IPV6;
2114 pi->pi_l3proto = IPPROTO_UNKNOWN;
2116 if (flags & JME_RD_MORE_FRAG)
2117 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2118 else if (flags & JME_RD_TCP)
2119 pi->pi_l3proto = IPPROTO_TCP;
2120 else if (flags & JME_RD_UDP)
2121 pi->pi_l3proto = IPPROTO_UDP;
2127 /* Receive a frame. */
2129 jme_rxpkt(struct jme_rxdata *rdata)
2131 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2132 struct jme_desc *desc;
2133 struct jme_rxdesc *rxd;
2134 struct mbuf *mp, *m;
2135 uint32_t flags, status, hash, hashinfo;
2136 int cons, count, nsegs;
2138 cons = rdata->jme_rx_cons;
2139 desc = &rdata->jme_rx_ring[cons];
2141 flags = le32toh(desc->flags);
2142 status = le32toh(desc->buflen);
2143 hash = le32toh(desc->addr_hi);
2144 hashinfo = le32toh(desc->addr_lo);
2145 nsegs = JME_RX_NSEGS(status);
2148 /* Skip the first descriptor. */
2149 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2152 * Clear the OWN bit of the following RX descriptors;
2153 * hardware will not clear the OWN bit except the first
2156 * Since the first RX descriptor is setup, i.e. OWN bit
2157 * on, before its followins RX descriptors, leaving the
2158 * OWN bit on the following RX descriptors will trick
2159 * the hardware into thinking that the following RX
2160 * descriptors are ready to be used too.
2162 for (count = 1; count < nsegs; count++,
2163 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2164 rdata->jme_rx_ring[cons].flags = 0;
2166 cons = rdata->jme_rx_cons;
2169 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2170 "hash 0x%08x, hash info 0x%08x\n",
2171 rdata->jme_rx_idx, flags, hash, hashinfo);
2173 if (status & JME_RX_ERR_STAT) {
2175 jme_discard_rxbufs(rdata, cons, nsegs);
2176 #ifdef JME_SHOW_ERRORS
2177 if_printf(ifp, "%s : receive error = 0x%b\n",
2178 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2180 rdata->jme_rx_cons += nsegs;
2181 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2185 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2186 for (count = 0; count < nsegs; count++,
2187 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2188 rxd = &rdata->jme_rxdesc[cons];
2191 /* Add a new receive buffer to the ring. */
2192 if (jme_newbuf(rdata, rxd, 0) != 0) {
2195 jme_discard_rxbufs(rdata, cons, nsegs - count);
2196 if (rdata->jme_rxhead != NULL) {
2197 m_freem(rdata->jme_rxhead);
2198 JME_RXCHAIN_RESET(rdata);
2204 * Assume we've received a full sized frame.
2205 * Actual size is fixed when we encounter the end of
2206 * multi-segmented frame.
2208 mp->m_len = MCLBYTES;
2210 /* Chain received mbufs. */
2211 if (rdata->jme_rxhead == NULL) {
2212 rdata->jme_rxhead = mp;
2213 rdata->jme_rxtail = mp;
2216 * Receive processor can receive a maximum frame
2217 * size of 65535 bytes.
2219 rdata->jme_rxtail->m_next = mp;
2220 rdata->jme_rxtail = mp;
2223 if (count == nsegs - 1) {
2224 struct pktinfo pi0, *pi;
2226 /* Last desc. for this frame. */
2227 m = rdata->jme_rxhead;
2228 m->m_pkthdr.len = rdata->jme_rxlen;
2230 /* Set first mbuf size. */
2231 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2232 /* Set last mbuf size. */
2233 mp->m_len = rdata->jme_rxlen -
2234 ((MCLBYTES - JME_RX_PAD_BYTES) +
2235 (MCLBYTES * (nsegs - 2)));
2237 m->m_len = rdata->jme_rxlen;
2239 m->m_pkthdr.rcvif = ifp;
2242 * Account for 10bytes auto padding which is used
2243 * to align IP header on 32bit boundary. Also note,
2244 * CRC bytes is automatically removed by the
2247 m->m_data += JME_RX_PAD_BYTES;
2249 /* Set checksum information. */
2250 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2251 (flags & JME_RD_IPV4)) {
2252 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2253 if (flags & JME_RD_IPCSUM)
2254 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2255 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2256 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2257 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2258 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2259 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2260 m->m_pkthdr.csum_flags |=
2261 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2262 m->m_pkthdr.csum_data = 0xffff;
2266 /* Check for VLAN tagged packets. */
2267 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2268 (flags & JME_RD_VLAN_TAG)) {
2269 m->m_pkthdr.ether_vlantag =
2270 flags & JME_RD_VLAN_MASK;
2271 m->m_flags |= M_VLANTAG;
2276 if (ifp->if_capenable & IFCAP_RSS)
2277 pi = jme_pktinfo(&pi0, flags);
2282 (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2283 m->m_flags |= M_HASH;
2284 m->m_pkthdr.hash = toeplitz_hash(hash);
2287 #ifdef JME_RSS_DEBUG
2289 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2290 "isr %d flags %08x, l3 %d %s\n",
2291 pi->pi_netisr, pi->pi_flags,
2293 (m->m_flags & M_HASH) ? "hash" : "");
2298 ether_input_pkt(ifp, m, pi);
2300 /* Reset mbuf chains. */
2301 JME_RXCHAIN_RESET(rdata);
2302 #ifdef JME_RSS_DEBUG
2303 rdata->jme_rx_pkt++;
2308 rdata->jme_rx_cons += nsegs;
2309 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2313 jme_rxeof(struct jme_rxdata *rdata, int count)
2315 struct jme_desc *desc;
2319 #ifdef DEVICE_POLLING
2320 if (count >= 0 && count-- == 0)
2323 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2324 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2326 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2330 * Check number of segments against received bytes.
2331 * Non-matching value would indicate that hardware
2332 * is still trying to update Rx descriptors. I'm not
2333 * sure whether this check is needed.
2335 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2336 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2337 if (nsegs != howmany(pktlen, MCLBYTES)) {
2338 if_printf(&rdata->jme_sc->arpcom.ac_if,
2339 "RX fragment count(%d) and "
2340 "packet size(%d) mismach\n", nsegs, pktlen);
2346 * RSS hash and hash information may _not_ be set by the
2347 * hardware even if the OWN bit is cleared and VALID bit
2350 * If the RSS information is not delivered by the hardware
2351 * yet, we MUST NOT accept this packet, let alone reusing
2352 * its RX descriptor. If this packet was accepted and its
2353 * RX descriptor was reused before hardware delivering the
2354 * RSS information, the RX buffer's address would be trashed
2355 * by the RSS information delivered by the hardware.
2357 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2358 struct jme_rxdesc *rxd;
2361 hashinfo = le32toh(desc->addr_lo);
2362 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2365 * This test should be enough to detect the pending
2366 * RSS information delivery, given:
2367 * - If RSS hash is not calculated, the hashinfo
2368 * will be 0. Howvever, the lower 32bits of RX
2369 * buffers' physical address will never be 0.
2370 * (see jme_rxbuf_dma_filter)
2371 * - If RSS hash is calculated, the lowest 4 bits
2372 * of hashinfo will be set, while the RX buffers
2373 * are at least 2K aligned.
2375 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2376 #ifdef JME_SHOW_RSSWB
2377 if_printf(&rdata->jme_sc->arpcom.ac_if,
2378 "RSS is not written back yet\n");
2384 /* Received a frame. */
2392 struct jme_softc *sc = xsc;
2393 struct ifnet *ifp = &sc->arpcom.ac_if;
2394 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2396 ifnet_serialize_all(ifp);
2399 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2401 ifnet_deserialize_all(ifp);
2405 jme_reset(struct jme_softc *sc)
2409 /* Make sure that TX and RX are stopped */
2414 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2418 * Hold reset bit before stop reset
2421 /* Disable TXMAC and TXOFL clock sources */
2422 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2423 /* Disable RXMAC clock source */
2424 val = CSR_READ_4(sc, JME_GPREG1);
2425 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2427 CSR_READ_4(sc, JME_GHC);
2430 CSR_WRITE_4(sc, JME_GHC, 0);
2432 CSR_READ_4(sc, JME_GHC);
2435 * Clear reset bit after stop reset
2438 /* Enable TXMAC and TXOFL clock sources */
2439 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2440 /* Enable RXMAC clock source */
2441 val = CSR_READ_4(sc, JME_GPREG1);
2442 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2444 CSR_READ_4(sc, JME_GHC);
2446 /* Disable TXMAC and TXOFL clock sources */
2447 CSR_WRITE_4(sc, JME_GHC, 0);
2448 /* Disable RXMAC clock source */
2449 val = CSR_READ_4(sc, JME_GPREG1);
2450 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2452 CSR_READ_4(sc, JME_GHC);
2454 /* Enable TX and RX */
2455 val = CSR_READ_4(sc, JME_TXCSR);
2456 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2457 val = CSR_READ_4(sc, JME_RXCSR);
2458 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2460 CSR_READ_4(sc, JME_TXCSR);
2461 CSR_READ_4(sc, JME_RXCSR);
2463 /* Enable TXMAC and TXOFL clock sources */
2464 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2465 /* Eisable RXMAC clock source */
2466 val = CSR_READ_4(sc, JME_GPREG1);
2467 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2469 CSR_READ_4(sc, JME_GHC);
2471 /* Stop TX and RX */
2479 struct jme_softc *sc = xsc;
2480 struct ifnet *ifp = &sc->arpcom.ac_if;
2481 struct mii_data *mii;
2482 uint8_t eaddr[ETHER_ADDR_LEN];
2487 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2490 * Cancel any pending I/O.
2495 * Reset the chip to a known state.
2500 * Setup MSI/MSI-X vectors to interrupts mapping
2505 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2506 KKASSERT(sc->jme_txd_spare >= 1);
2509 * If we use 64bit address mode for transmitting, each Tx request
2510 * needs one more symbol descriptor.
2512 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2513 sc->jme_txd_spare += 1;
2515 if (JME_ENABLE_HWRSS(sc))
2518 jme_disable_rss(sc);
2520 /* Init RX descriptors */
2521 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2522 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2524 if_printf(ifp, "initialization failed: "
2525 "no memory for %dth RX ring.\n", r);
2531 /* Init TX descriptors */
2532 jme_init_tx_ring(sc);
2534 /* Initialize shadow status block. */
2537 /* Reprogram the station address. */
2538 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2539 CSR_WRITE_4(sc, JME_PAR0,
2540 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2541 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2544 * Configure Tx queue.
2545 * Tx priority queue weight value : 0
2546 * Tx FIFO threshold for processing next packet : 16QW
2547 * Maximum Tx DMA length : 512
2548 * Allow Tx DMA burst.
2550 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2551 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2552 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2553 sc->jme_txcsr |= sc->jme_tx_dma_size;
2554 sc->jme_txcsr |= TXCSR_DMA_BURST;
2555 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2557 /* Set Tx descriptor counter. */
2558 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
2560 /* Set Tx ring address to the hardware. */
2561 paddr = sc->jme_cdata.jme_tx_ring_paddr;
2562 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2563 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2565 /* Configure TxMAC parameters. */
2566 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2567 reg |= TXMAC_THRESH_1_PKT;
2568 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2569 CSR_WRITE_4(sc, JME_TXMAC, reg);
2572 * Configure Rx queue.
2573 * FIFO full threshold for transmitting Tx pause packet : 128T
2574 * FIFO threshold for processing next packet : 128QW
2576 * Max Rx DMA length : 128
2577 * Rx descriptor retry : 32
2578 * Rx descriptor retry time gap : 256ns
2579 * Don't receive runt/bad frame.
2581 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2584 * Since Rx FIFO size is 4K bytes, receiving frames larger
2585 * than 4K bytes will suffer from Rx FIFO overruns. So
2586 * decrease FIFO threshold to reduce the FIFO overruns for
2587 * frames larger than 4000 bytes.
2588 * For best performance of standard MTU sized frames use
2589 * maximum allowable FIFO threshold, 128QW.
2591 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2593 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2595 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2597 /* Improve PCI Express compatibility */
2598 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2600 sc->jme_rxcsr |= sc->jme_rx_dma_size;
2601 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2602 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2603 /* XXX TODO DROP_BAD */
2605 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2606 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2608 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2610 /* Set Rx descriptor counter. */
2611 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2613 /* Set Rx ring address to the hardware. */
2614 paddr = rdata->jme_rx_ring_paddr;
2615 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2616 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2619 /* Clear receive filter. */
2620 CSR_WRITE_4(sc, JME_RXMAC, 0);
2622 /* Set up the receive filter. */
2627 * Disable all WOL bits as WOL can interfere normal Rx
2628 * operation. Also clear WOL detection status bits.
2630 reg = CSR_READ_4(sc, JME_PMCS);
2631 reg &= ~PMCS_WOL_ENB_MASK;
2632 CSR_WRITE_4(sc, JME_PMCS, reg);
2635 * Pad 10bytes right before received frame. This will greatly
2636 * help Rx performance on strict-alignment architectures as
2637 * it does not need to copy the frame to align the payload.
2639 reg = CSR_READ_4(sc, JME_RXMAC);
2640 reg |= RXMAC_PAD_10BYTES;
2642 if (ifp->if_capenable & IFCAP_RXCSUM)
2643 reg |= RXMAC_CSUM_ENB;
2644 CSR_WRITE_4(sc, JME_RXMAC, reg);
2646 /* Configure general purpose reg0 */
2647 reg = CSR_READ_4(sc, JME_GPREG0);
2648 reg &= ~GPREG0_PCC_UNIT_MASK;
2649 /* Set PCC timer resolution to micro-seconds unit. */
2650 reg |= GPREG0_PCC_UNIT_US;
2652 * Disable all shadow register posting as we have to read
2653 * JME_INTR_STATUS register in jme_intr. Also it seems
2654 * that it's hard to synchronize interrupt status between
2655 * hardware and software with shadow posting due to
2656 * requirements of bus_dmamap_sync(9).
2658 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2659 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2660 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2661 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2662 /* Disable posting of DW0. */
2663 reg &= ~GPREG0_POST_DW0_ENB;
2664 /* Clear PME message. */
2665 reg &= ~GPREG0_PME_ENB;
2666 /* Set PHY address. */
2667 reg &= ~GPREG0_PHY_ADDR_MASK;
2668 reg |= sc->jme_phyaddr;
2669 CSR_WRITE_4(sc, JME_GPREG0, reg);
2671 /* Configure Tx queue 0 packet completion coalescing. */
2672 jme_set_tx_coal(sc);
2674 /* Configure Rx queues packet completion coalescing. */
2675 jme_set_rx_coal(sc);
2677 /* Configure shadow status block but don't enable posting. */
2678 paddr = sc->jme_cdata.jme_ssb_block_paddr;
2679 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2680 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2682 /* Disable Timer 1 and Timer 2. */
2683 CSR_WRITE_4(sc, JME_TIMER1, 0);
2684 CSR_WRITE_4(sc, JME_TIMER2, 0);
2686 /* Configure retry transmit period, retry limit value. */
2687 CSR_WRITE_4(sc, JME_TXTRHD,
2688 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2689 TXTRHD_RT_PERIOD_MASK) |
2690 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2691 TXTRHD_RT_LIMIT_SHIFT));
2693 #ifdef DEVICE_POLLING
2694 if (!(ifp->if_flags & IFF_POLLING))
2696 /* Initialize the interrupt mask. */
2697 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2698 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2701 * Enabling Tx/Rx DMA engines and Rx queue processing is
2702 * done after detection of valid link in jme_miibus_statchg.
2704 sc->jme_flags &= ~JME_FLAG_LINK;
2706 /* Set the current media. */
2707 mii = device_get_softc(sc->jme_miibus);
2710 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2712 ifp->if_flags |= IFF_RUNNING;
2713 ifp->if_flags &= ~IFF_OACTIVE;
2717 jme_stop(struct jme_softc *sc)
2719 struct ifnet *ifp = &sc->arpcom.ac_if;
2720 struct jme_txdesc *txd;
2721 struct jme_rxdesc *rxd;
2722 struct jme_rxdata *rdata;
2725 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2728 * Mark the interface down and cancel the watchdog timer.
2730 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2733 callout_stop(&sc->jme_tick_ch);
2734 sc->jme_flags &= ~JME_FLAG_LINK;
2737 * Disable interrupts.
2739 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2740 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2742 /* Disable updating shadow status block. */
2743 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2744 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2746 /* Stop receiver, transmitter. */
2751 * Free partial finished RX segments
2753 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2754 rdata = &sc->jme_cdata.jme_rx_data[r];
2755 if (rdata->jme_rxhead != NULL)
2756 m_freem(rdata->jme_rxhead);
2757 JME_RXCHAIN_RESET(rdata);
2761 * Free RX and TX mbufs still in the queues.
2763 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2764 rdata = &sc->jme_cdata.jme_rx_data[r];
2765 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2766 rxd = &rdata->jme_rxdesc[i];
2767 if (rxd->rx_m != NULL) {
2768 bus_dmamap_unload(rdata->jme_rx_tag,
2775 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2776 txd = &sc->jme_cdata.jme_txdesc[i];
2777 if (txd->tx_m != NULL) {
2778 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2788 jme_stop_tx(struct jme_softc *sc)
2793 reg = CSR_READ_4(sc, JME_TXCSR);
2794 if ((reg & TXCSR_TX_ENB) == 0)
2796 reg &= ~TXCSR_TX_ENB;
2797 CSR_WRITE_4(sc, JME_TXCSR, reg);
2798 for (i = JME_TIMEOUT; i > 0; i--) {
2800 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2804 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2808 jme_stop_rx(struct jme_softc *sc)
2813 reg = CSR_READ_4(sc, JME_RXCSR);
2814 if ((reg & RXCSR_RX_ENB) == 0)
2816 reg &= ~RXCSR_RX_ENB;
2817 CSR_WRITE_4(sc, JME_RXCSR, reg);
2818 for (i = JME_TIMEOUT; i > 0; i--) {
2820 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2824 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2828 jme_init_tx_ring(struct jme_softc *sc)
2830 struct jme_chain_data *cd;
2831 struct jme_txdesc *txd;
2834 sc->jme_cdata.jme_tx_prod = 0;
2835 sc->jme_cdata.jme_tx_cons = 0;
2836 sc->jme_cdata.jme_tx_cnt = 0;
2838 cd = &sc->jme_cdata;
2839 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2840 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2841 txd = &sc->jme_cdata.jme_txdesc[i];
2843 txd->tx_desc = &cd->jme_tx_ring[i];
2849 jme_init_ssb(struct jme_softc *sc)
2851 struct jme_chain_data *cd;
2853 cd = &sc->jme_cdata;
2854 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2858 jme_init_rx_ring(struct jme_rxdata *rdata)
2860 struct jme_rxdesc *rxd;
2863 KKASSERT(rdata->jme_rxhead == NULL &&
2864 rdata->jme_rxtail == NULL &&
2865 rdata->jme_rxlen == 0);
2866 rdata->jme_rx_cons = 0;
2868 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2869 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2872 rxd = &rdata->jme_rxdesc[i];
2874 rxd->rx_desc = &rdata->jme_rx_ring[i];
2875 error = jme_newbuf(rdata, rxd, 1);
2883 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2886 bus_dma_segment_t segs;
2890 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2894 * JMC250 has 64bit boundary alignment limitation so jme(4)
2895 * takes advantage of 10 bytes padding feature of hardware
2896 * in order not to copy entire frame to align IP header on
2899 m->m_len = m->m_pkthdr.len = MCLBYTES;
2901 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2902 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2907 if_printf(&rdata->jme_sc->arpcom.ac_if,
2908 "can't load RX mbuf\n");
2913 if (rxd->rx_m != NULL) {
2914 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2915 BUS_DMASYNC_POSTREAD);
2916 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2918 map = rxd->rx_dmamap;
2919 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2920 rdata->jme_rx_sparemap = map;
2922 rxd->rx_paddr = segs.ds_addr;
2924 jme_setup_rxdesc(rxd);
2929 jme_set_vlan(struct jme_softc *sc)
2931 struct ifnet *ifp = &sc->arpcom.ac_if;
2934 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2936 reg = CSR_READ_4(sc, JME_RXMAC);
2937 reg &= ~RXMAC_VLAN_ENB;
2938 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2939 reg |= RXMAC_VLAN_ENB;
2940 CSR_WRITE_4(sc, JME_RXMAC, reg);
2944 jme_set_filter(struct jme_softc *sc)
2946 struct ifnet *ifp = &sc->arpcom.ac_if;
2947 struct ifmultiaddr *ifma;
2952 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2954 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2955 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2959 * Always accept frames destined to our station address.
2960 * Always accept broadcast frames.
2962 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2964 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2965 if (ifp->if_flags & IFF_PROMISC)
2966 rxcfg |= RXMAC_PROMISC;
2967 if (ifp->if_flags & IFF_ALLMULTI)
2968 rxcfg |= RXMAC_ALLMULTI;
2969 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2970 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2971 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2976 * Set up the multicast address filter by passing all multicast
2977 * addresses through a CRC generator, and then using the low-order
2978 * 6 bits as an index into the 64 bit multicast hash table. The
2979 * high order bits select the register, while the rest of the bits
2980 * select the bit within the register.
2982 rxcfg |= RXMAC_MULTICAST;
2983 bzero(mchash, sizeof(mchash));
2985 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2986 if (ifma->ifma_addr->sa_family != AF_LINK)
2988 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2989 ifma->ifma_addr), ETHER_ADDR_LEN);
2991 /* Just want the 6 least significant bits. */
2994 /* Set the corresponding bit in the hash table. */
2995 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2998 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2999 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3000 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3004 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
3006 struct jme_softc *sc = arg1;
3007 struct ifnet *ifp = &sc->arpcom.ac_if;
3010 ifnet_serialize_all(ifp);
3012 v = sc->jme_tx_coal_to;
3013 error = sysctl_handle_int(oidp, &v, 0, req);
3014 if (error || req->newptr == NULL)
3017 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3022 if (v != sc->jme_tx_coal_to) {
3023 sc->jme_tx_coal_to = v;
3024 if (ifp->if_flags & IFF_RUNNING)
3025 jme_set_tx_coal(sc);
3028 ifnet_deserialize_all(ifp);
3033 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3035 struct jme_softc *sc = arg1;
3036 struct ifnet *ifp = &sc->arpcom.ac_if;
3039 ifnet_serialize_all(ifp);
3041 v = sc->jme_tx_coal_pkt;
3042 error = sysctl_handle_int(oidp, &v, 0, req);
3043 if (error || req->newptr == NULL)
3046 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3051 if (v != sc->jme_tx_coal_pkt) {
3052 sc->jme_tx_coal_pkt = v;
3053 if (ifp->if_flags & IFF_RUNNING)
3054 jme_set_tx_coal(sc);
3057 ifnet_deserialize_all(ifp);
3062 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
3064 struct jme_softc *sc = arg1;
3065 struct ifnet *ifp = &sc->arpcom.ac_if;
3068 ifnet_serialize_all(ifp);
3070 v = sc->jme_rx_coal_to;
3071 error = sysctl_handle_int(oidp, &v, 0, req);
3072 if (error || req->newptr == NULL)
3075 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3080 if (v != sc->jme_rx_coal_to) {
3081 sc->jme_rx_coal_to = v;
3082 if (ifp->if_flags & IFF_RUNNING)
3083 jme_set_rx_coal(sc);
3086 ifnet_deserialize_all(ifp);
3091 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3093 struct jme_softc *sc = arg1;
3094 struct ifnet *ifp = &sc->arpcom.ac_if;
3097 ifnet_serialize_all(ifp);
3099 v = sc->jme_rx_coal_pkt;
3100 error = sysctl_handle_int(oidp, &v, 0, req);
3101 if (error || req->newptr == NULL)
3104 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3109 if (v != sc->jme_rx_coal_pkt) {
3110 sc->jme_rx_coal_pkt = v;
3111 if (ifp->if_flags & IFF_RUNNING)
3112 jme_set_rx_coal(sc);
3115 ifnet_deserialize_all(ifp);
3120 jme_set_tx_coal(struct jme_softc *sc)
3124 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3126 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3127 PCCTX_COAL_PKT_MASK;
3128 reg |= PCCTX_COAL_TXQ0;
3129 CSR_WRITE_4(sc, JME_PCCTX, reg);
3133 jme_set_rx_coal(struct jme_softc *sc)
3138 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3140 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3141 PCCRX_COAL_PKT_MASK;
3142 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3143 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3146 #ifdef DEVICE_POLLING
3149 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3151 struct jme_softc *sc = ifp->if_softc;
3155 ASSERT_SERIALIZED(&sc->jme_serialize);
3159 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3162 case POLL_DEREGISTER:
3163 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3166 case POLL_AND_CHECK_STATUS:
3168 status = CSR_READ_4(sc, JME_INTR_STATUS);
3170 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3171 struct jme_rxdata *rdata =
3172 &sc->jme_cdata.jme_rx_data[r];
3174 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3175 jme_rxeof(rdata, count);
3176 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3179 if (status & INTR_RXQ_DESC_EMPTY) {
3180 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3181 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3182 RXCSR_RX_ENB | RXCSR_RXQ_START);
3185 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3187 if (!ifq_is_empty(&ifp->if_snd))
3189 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3194 #endif /* DEVICE_POLLING */
3197 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3202 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
3203 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3204 JME_RX_RING_ALIGN, 0,
3205 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3206 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3208 device_printf(rdata->jme_sc->jme_dev,
3209 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3212 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3213 rdata->jme_rx_ring_map = dmem.dmem_map;
3214 rdata->jme_rx_ring = dmem.dmem_addr;
3215 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3221 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3223 if ((paddr & 0xffffffff) == 0) {
3225 * Don't allow lower 32bits of the RX buffer's
3226 * physical address to be 0, else it will break
3227 * hardware pending RSS information delivery
3228 * detection on RX path.
3236 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3241 lowaddr = BUS_SPACE_MAXADDR;
3242 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3243 /* jme_rxbuf_dma_filter will be called */
3244 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3247 /* Create tag for Rx buffers. */
3248 error = bus_dma_tag_create(
3249 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3250 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
3251 lowaddr, /* lowaddr */
3252 BUS_SPACE_MAXADDR, /* highaddr */
3253 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
3254 MCLBYTES, /* maxsize */
3256 MCLBYTES, /* maxsegsize */
3257 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3258 &rdata->jme_rx_tag);
3260 device_printf(rdata->jme_sc->jme_dev,
3261 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3265 /* Create DMA maps for Rx buffers. */
3266 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3267 &rdata->jme_rx_sparemap);
3269 device_printf(rdata->jme_sc->jme_dev,
3270 "could not create %dth spare Rx dmamap.\n",
3272 bus_dma_tag_destroy(rdata->jme_rx_tag);
3273 rdata->jme_rx_tag = NULL;
3276 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3277 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3279 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3284 device_printf(rdata->jme_sc->jme_dev,
3285 "could not create %dth Rx dmamap "
3286 "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3288 for (j = 0; j < i; ++j) {
3289 rxd = &rdata->jme_rxdesc[j];
3290 bus_dmamap_destroy(rdata->jme_rx_tag,
3293 bus_dmamap_destroy(rdata->jme_rx_tag,
3294 rdata->jme_rx_sparemap);
3295 bus_dma_tag_destroy(rdata->jme_rx_tag);
3296 rdata->jme_rx_tag = NULL;
3304 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3308 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3309 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3311 if (status & rdata->jme_rx_coal) {
3312 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3313 jme_rxeof(rdata, -1);
3314 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3320 jme_enable_rss(struct jme_softc *sc)
3323 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3326 KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3327 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
3328 ("%s: invalid # of RX rings (%d)",
3329 sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
3331 rssc = RSSC_HASH_64_ENTRY;
3332 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3333 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3334 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3335 CSR_WRITE_4(sc, JME_RSSC, rssc);
3337 toeplitz_get_key(key, sizeof(key));
3338 for (i = 0; i < RSSKEY_NREGS; ++i) {
3341 keyreg = RSSKEY_REGVAL(key, i);
3342 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3344 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3348 * Create redirect table in following fashion:
3349 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3352 for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3355 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3356 ind |= q << (i * 8);
3358 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3360 for (i = 0; i < RSSTBL_NREGS; ++i)
3361 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3365 jme_disable_rss(struct jme_softc *sc)
3367 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3371 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3373 struct jme_softc *sc = ifp->if_softc;
3375 ifnet_serialize_array_enter(sc->jme_serialize_arr,
3376 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3380 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3382 struct jme_softc *sc = ifp->if_softc;
3384 ifnet_serialize_array_exit(sc->jme_serialize_arr,
3385 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3389 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3391 struct jme_softc *sc = ifp->if_softc;
3393 return ifnet_serialize_array_try(sc->jme_serialize_arr,
3394 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3400 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3401 boolean_t serialized)
3403 struct jme_softc *sc = ifp->if_softc;
3405 ifnet_serialize_array_assert(sc->jme_serialize_arr,
3406 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE,
3410 #endif /* INVARIANTS */
3413 jme_msix_try_alloc(device_t dev)
3415 struct jme_softc *sc = device_get_softc(dev);
3416 struct jme_msix_data *msix;
3417 int error, i, r, msix_enable, msix_count;
3419 msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
3420 KKASSERT(msix_count <= JME_NMSIX);
3422 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3425 * We leave the 1st MSI-X vector unused, so we
3426 * actually need msix_count + 1 MSI-X vectors.
3428 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3431 for (i = 0; i < msix_count; ++i)
3432 sc->jme_msix[i].jme_msix_rid = -1;
3436 msix = &sc->jme_msix[i++];
3437 msix->jme_msix_cpuid = 0; /* XXX Put TX to cpu0 */
3438 msix->jme_msix_arg = &sc->jme_cdata;
3439 msix->jme_msix_func = jme_msix_tx;
3440 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3441 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3442 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3443 device_get_nameunit(dev));
3445 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3446 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3448 msix = &sc->jme_msix[i++];
3449 msix->jme_msix_cpuid = r; /* XXX Put RX to cpuX */
3450 msix->jme_msix_arg = rdata;
3451 msix->jme_msix_func = jme_msix_rx;
3452 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3453 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3454 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3455 "%s rx%d", device_get_nameunit(dev), r);
3458 KKASSERT(i == msix_count);
3460 error = pci_setup_msix(dev);
3464 /* Setup jme_msix_cnt early, so we could cleanup */
3465 sc->jme_msix_cnt = msix_count;
3467 for (i = 0; i < msix_count; ++i) {
3468 msix = &sc->jme_msix[i];
3470 msix->jme_msix_vector = i + 1;
3471 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3472 &msix->jme_msix_rid, msix->jme_msix_cpuid);
3476 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3477 &msix->jme_msix_rid, RF_ACTIVE);
3478 if (msix->jme_msix_res == NULL) {
3484 for (i = 0; i < JME_INTR_CNT; ++i) {
3485 uint32_t intr_mask = (1 << i);
3488 if ((JME_INTRS & intr_mask) == 0)
3491 for (x = 0; x < msix_count; ++x) {
3492 msix = &sc->jme_msix[x];
3493 if (msix->jme_msix_intrs & intr_mask) {
3496 reg = i / JME_MSINUM_FACTOR;
3497 KKASSERT(reg < JME_MSINUM_CNT);
3499 shift = (i % JME_MSINUM_FACTOR) * 4;
3501 sc->jme_msinum[reg] |=
3502 (msix->jme_msix_vector << shift);
3510 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3511 device_printf(dev, "MSINUM%d: %#x\n", i,
3516 pci_enable_msix(dev);
3517 sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3525 jme_intr_alloc(device_t dev)
3527 struct jme_softc *sc = device_get_softc(dev);
3530 jme_msix_try_alloc(dev);
3532 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3533 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3534 &sc->jme_irq_rid, &irq_flags);
3536 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3537 &sc->jme_irq_rid, irq_flags);
3538 if (sc->jme_irq_res == NULL) {
3539 device_printf(dev, "can't allocate irq\n");
3547 jme_msix_free(device_t dev)
3549 struct jme_softc *sc = device_get_softc(dev);
3552 KKASSERT(sc->jme_msix_cnt > 1);
3554 for (i = 0; i < sc->jme_msix_cnt; ++i) {
3555 struct jme_msix_data *msix = &sc->jme_msix[i];
3557 if (msix->jme_msix_res != NULL) {
3558 bus_release_resource(dev, SYS_RES_IRQ,
3559 msix->jme_msix_rid, msix->jme_msix_res);
3560 msix->jme_msix_res = NULL;
3562 if (msix->jme_msix_rid >= 0) {
3563 pci_release_msix_vector(dev, msix->jme_msix_rid);
3564 msix->jme_msix_rid = -1;
3567 pci_teardown_msix(dev);
3571 jme_intr_free(device_t dev)
3573 struct jme_softc *sc = device_get_softc(dev);
3575 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3576 if (sc->jme_irq_res != NULL) {
3577 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3580 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3581 pci_release_msi(dev);
3588 jme_msix_tx(void *xcd)
3590 struct jme_chain_data *cd = xcd;
3591 struct jme_softc *sc = cd->jme_sc;
3592 struct ifnet *ifp = &sc->arpcom.ac_if;
3594 ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3596 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3598 CSR_WRITE_4(sc, JME_INTR_STATUS,
3599 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3601 if (ifp->if_flags & IFF_RUNNING) {
3603 if (!ifq_is_empty(&ifp->if_snd))
3607 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3611 jme_msix_rx(void *xrdata)
3613 struct jme_rxdata *rdata = xrdata;
3614 struct jme_softc *sc = rdata->jme_sc;
3615 struct ifnet *ifp = &sc->arpcom.ac_if;
3618 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3620 CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3621 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3623 status = CSR_READ_4(sc, JME_INTR_STATUS);
3624 status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3626 if (status & rdata->jme_rx_coal)
3627 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3628 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3630 if (ifp->if_flags & IFF_RUNNING) {
3631 if (status & rdata->jme_rx_coal)
3632 jme_rxeof(rdata, -1);
3634 if (status & rdata->jme_rx_empty) {
3635 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3636 RXCSR_RX_ENB | RXCSR_RXQ_START);
3640 CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3641 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3645 jme_set_msinum(struct jme_softc *sc)
3649 for (i = 0; i < JME_MSINUM_CNT; ++i)
3650 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3654 jme_intr_setup(device_t dev)
3656 struct jme_softc *sc = device_get_softc(dev);
3657 struct ifnet *ifp = &sc->arpcom.ac_if;
3660 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3661 return jme_msix_setup(dev);
3663 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3664 jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3666 device_printf(dev, "could not set up interrupt handler.\n");
3670 ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3671 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3676 jme_intr_teardown(device_t dev)
3678 struct jme_softc *sc = device_get_softc(dev);
3680 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3681 jme_msix_teardown(dev, sc->jme_msix_cnt);
3683 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3687 jme_msix_setup(device_t dev)
3689 struct jme_softc *sc = device_get_softc(dev);
3690 struct ifnet *ifp = &sc->arpcom.ac_if;
3693 for (x = 0; x < sc->jme_msix_cnt; ++x) {
3694 struct jme_msix_data *msix = &sc->jme_msix[x];
3697 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3698 INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3699 &msix->jme_msix_handle, msix->jme_msix_serialize,
3700 msix->jme_msix_desc);
3702 device_printf(dev, "could not set up %s "
3703 "interrupt handler.\n", msix->jme_msix_desc);
3704 jme_msix_teardown(dev, x);
3708 ifp->if_cpuid = 0; /* XXX */
3713 jme_msix_teardown(device_t dev, int msix_count)
3715 struct jme_softc *sc = device_get_softc(dev);
3718 for (x = 0; x < msix_count; ++x) {
3719 struct jme_msix_data *msix = &sc->jme_msix[x];
3721 bus_teardown_intr(dev, msix->jme_msix_res,
3722 msix->jme_msix_handle);