2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
37 * series chips and several workalikes including the following:
39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
41 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
42 * ASIX Electronics AX88140A (www.asix.com.tw)
43 * ASIX Electronics AX88141 (www.asix.com.tw)
44 * ADMtek AL981 (www.admtek.com.tw)
45 * ADMtek AN985 (www.admtek.com.tw)
46 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
48 * Accton EN1217 (www.accton.com)
49 * Xircom X3201 (www.xircom.com)
51 * Conexant LANfinity (www.conexant.com)
53 * Datasheets for the 21143 are available at developer.intel.com.
54 * Datasheets for the clone parts can be found at their respective sites.
55 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
56 * The PNIC II is essentially a Macronix 98715A chip; the only difference
57 * worth noting is that its multicast hash table is only 128 bits wide
60 * Written by Bill Paul <wpaul@ee.columbia.edu>
61 * Electrical Engineering Department
62 * Columbia University, New York City
66 * The Intel 21143 is the successor to the DEC 21140. It is basically
67 * the same as the 21140 but with a few new features. The 21143 supports
68 * three kinds of media attachments:
70 * o MII port, for 10Mbps and 100Mbps support and NWAY
71 * autonegotiation provided by an external PHY.
72 * o SYM port, for symbol mode 100Mbps support.
76 * The 100Mbps SYM port and 10baseT port can be used together in
77 * combination with the internal NWAY support to create a 10/100
78 * autosensing configuration.
80 * Note that not all tulip workalikes are handled in this driver: we only
81 * deal with those which are relatively well behaved. The Winbond is
82 * handled separately due to its different register offsets and the
83 * special handling needed for its various bugs. The PNIC is handled
84 * here, but I'm not thrilled about it.
86 * All of the workalike chips use some form of MII transceiver support
87 * with the exception of the Macronix chips, which also have a SYM port.
88 * The ASIX AX88140A is also documented to have a SYM port, but all
89 * the cards I've seen use an MII transceiver, probably because the
90 * AX88140A doesn't support internal NWAY.
93 #include "opt_polling.h"
95 #include <sys/param.h>
96 #include <sys/systm.h>
97 #include <sys/sockio.h>
99 #include <sys/malloc.h>
100 #include <sys/kernel.h>
101 #include <sys/interrupt.h>
102 #include <sys/socket.h>
103 #include <sys/sysctl.h>
105 #include <sys/rman.h>
106 #include <sys/thread2.h>
109 #include <net/ifq_var.h>
110 #include <net/if_arp.h>
111 #include <net/ethernet.h>
112 #include <net/if_dl.h>
113 #include <net/if_media.h>
114 #include <net/if_types.h>
115 #include <net/vlan/if_vlan_var.h>
119 #include <vm/vm.h> /* for vtophys */
120 #include <vm/pmap.h> /* for vtophys */
122 #include "../mii_layer/mii.h"
123 #include "../mii_layer/miivar.h"
125 #include <bus/pci/pcireg.h>
126 #include <bus/pci/pcivar.h>
128 #define DC_USEIOSPACE
130 #include "if_dcreg.h"
132 /* "controller miibus0" required. See GENERIC if you get errors here. */
133 #include "miibus_if.h"
136 * Various supported device vendors/types and their names.
138 static const struct dc_type dc_devs[] = {
139 { DC_VENDORID_DEC, DC_DEVICEID_21143,
140 "Intel 21143 10/100BaseTX" },
141 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
142 "Davicom DM9009 10/100BaseTX" },
143 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
144 "Davicom DM9100 10/100BaseTX" },
145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
146 "Davicom DM9102 10/100BaseTX" },
147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
148 "Davicom DM9102A 10/100BaseTX" },
149 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
150 "ADMtek AL981 10/100BaseTX" },
151 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
152 "ADMtek AN985 10/100BaseTX" },
153 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511,
154 "Netgear FA511 10/100BaseTX" },
155 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511,
156 "ADMtek ADM9511 10/100BaseTX" },
157 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513,
158 "ADMtek ADM9513 10/100BaseTX" },
159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
160 "ASIX AX88140A 10/100BaseTX" },
161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
162 "ASIX AX88141 10/100BaseTX" },
163 { DC_VENDORID_MX, DC_DEVICEID_98713,
164 "Macronix 98713 10/100BaseTX" },
165 { DC_VENDORID_MX, DC_DEVICEID_98713,
166 "Macronix 98713A 10/100BaseTX" },
167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
168 "Compex RL100-TX 10/100BaseTX" },
169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
170 "Compex RL100-TX 10/100BaseTX" },
171 { DC_VENDORID_MX, DC_DEVICEID_987x5,
172 "Macronix 98715/98715A 10/100BaseTX" },
173 { DC_VENDORID_MX, DC_DEVICEID_987x5,
174 "Macronix 98715AEC-C 10/100BaseTX" },
175 { DC_VENDORID_MX, DC_DEVICEID_987x5,
176 "Macronix 98725 10/100BaseTX" },
177 { DC_VENDORID_MX, DC_DEVICEID_98727,
178 "Macronix 98727/98732 10/100BaseTX" },
179 { DC_VENDORID_LO, DC_DEVICEID_82C115,
180 "LC82C115 PNIC II 10/100BaseTX" },
181 { DC_VENDORID_LO, DC_DEVICEID_82C168,
182 "82c168 PNIC 10/100BaseTX" },
183 { DC_VENDORID_LO, DC_DEVICEID_82C168,
184 "82c169 PNIC 10/100BaseTX" },
185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
186 "Accton EN1217 10/100BaseTX" },
187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
188 "Accton EN2242 MiniPCI 10/100BaseTX" },
189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201,
190 "Xircom X3201 10/100BaseTX" },
191 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
192 "Conexant LANfinity MiniPCI 10/100BaseTX" },
193 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
194 "3Com OfficeConnect 10/100B" },
195 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500,
196 "Abocom FE2500 10/100BaseTX" },
200 static int dc_probe (device_t);
201 static int dc_attach (device_t);
202 static int dc_detach (device_t);
203 static int dc_suspend (device_t);
204 static int dc_resume (device_t);
205 static void dc_acpi (device_t);
206 static const struct dc_type *dc_devtype (device_t);
207 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
208 static int dc_encap (struct dc_softc *, struct mbuf *,
210 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
211 static int dc_rx_resync (struct dc_softc *);
212 static void dc_rxeof (struct dc_softc *);
213 static void dc_txeof (struct dc_softc *);
214 static void dc_tick (void *);
215 static void dc_tx_underrun (struct dc_softc *);
216 static void dc_intr (void *);
217 static void dc_start (struct ifnet *);
218 static int dc_ioctl (struct ifnet *, u_long, caddr_t,
220 #ifdef DEVICE_POLLING
221 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd,
224 static void dc_init (void *);
225 static void dc_stop (struct dc_softc *);
226 static void dc_watchdog (struct ifnet *);
227 static void dc_shutdown (device_t);
228 static int dc_ifmedia_upd (struct ifnet *);
229 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
231 static void dc_delay (struct dc_softc *);
232 static void dc_eeprom_idle (struct dc_softc *);
233 static void dc_eeprom_putbyte (struct dc_softc *, int);
234 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
235 static void dc_eeprom_getword_pnic
236 (struct dc_softc *, int, u_int16_t *);
237 static void dc_eeprom_getword_xircom
238 (struct dc_softc *, int, u_int16_t *);
239 static void dc_eeprom_width (struct dc_softc *);
240 static void dc_read_eeprom (struct dc_softc *, caddr_t, int,
243 static void dc_mii_writebit (struct dc_softc *, int);
244 static int dc_mii_readbit (struct dc_softc *);
245 static void dc_mii_sync (struct dc_softc *);
246 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
247 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
248 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
249 static int dc_miibus_readreg (device_t, int, int);
250 static int dc_miibus_writereg (device_t, int, int, int);
251 static void dc_miibus_statchg (device_t);
252 static void dc_miibus_mediainit (device_t);
254 static u_int32_t dc_crc_mask (struct dc_softc *);
255 static void dc_setcfg (struct dc_softc *, int);
256 static void dc_setfilt_21143 (struct dc_softc *);
257 static void dc_setfilt_asix (struct dc_softc *);
258 static void dc_setfilt_admtek (struct dc_softc *);
259 static void dc_setfilt_xircom (struct dc_softc *);
261 static void dc_setfilt (struct dc_softc *);
263 static void dc_reset (struct dc_softc *);
264 static int dc_list_rx_init (struct dc_softc *);
265 static int dc_list_tx_init (struct dc_softc *);
267 static void dc_read_srom (struct dc_softc *, int);
268 static void dc_parse_21143_srom (struct dc_softc *);
269 static void dc_decode_leaf_sia (struct dc_softc *,
270 struct dc_eblock_sia *);
271 static void dc_decode_leaf_mii (struct dc_softc *,
272 struct dc_eblock_mii *);
273 static void dc_decode_leaf_sym (struct dc_softc *,
274 struct dc_eblock_sym *);
275 static void dc_apply_fixup (struct dc_softc *, int);
276 static uint32_t dc_mchash_xircom(struct dc_softc *, const uint8_t *);
279 #define DC_RES SYS_RES_IOPORT
280 #define DC_RID DC_PCI_CFBIO
282 #define DC_RES SYS_RES_MEMORY
283 #define DC_RID DC_PCI_CFBMA
286 static device_method_t dc_methods[] = {
287 /* Device interface */
288 DEVMETHOD(device_probe, dc_probe),
289 DEVMETHOD(device_attach, dc_attach),
290 DEVMETHOD(device_detach, dc_detach),
291 DEVMETHOD(device_suspend, dc_suspend),
292 DEVMETHOD(device_resume, dc_resume),
293 DEVMETHOD(device_shutdown, dc_shutdown),
296 DEVMETHOD(bus_print_child, bus_generic_print_child),
297 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
300 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
301 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
302 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
303 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
308 static driver_t dc_driver = {
311 sizeof(struct dc_softc)
314 static devclass_t dc_devclass;
317 static int dc_quick=1;
318 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
319 &dc_quick,0,"do not mdevget in dc driver");
322 DECLARE_DUMMY_MODULE(if_dc);
323 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, NULL, NULL);
324 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, NULL, NULL);
325 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL);
327 #define DC_SETBIT(sc, reg, x) \
328 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
330 #define DC_CLRBIT(sc, reg, x) \
331 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
333 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
334 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
337 dc_delay(struct dc_softc *sc)
341 for (idx = (300 / 33) + 1; idx > 0; idx--)
342 CSR_READ_4(sc, DC_BUSCTL);
346 dc_eeprom_width(struct dc_softc *sc)
350 /* Force EEPROM to idle state. */
353 /* Enter EEPROM access mode. */
354 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
356 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
358 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
360 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
365 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
367 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
369 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
371 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
375 for (i = 1; i <= 12; i++) {
376 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
378 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
379 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
383 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
387 /* Turn off EEPROM access mode. */
395 /* Enter EEPROM access mode. */
396 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
398 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
400 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
402 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
405 /* Turn off EEPROM access mode. */
410 dc_eeprom_idle(struct dc_softc *sc)
414 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
416 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
420 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
423 for (i = 0; i < 25; i++) {
424 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
426 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
430 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
432 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
434 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
440 * Send a read command and address to the EEPROM, check for ACK.
443 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
447 d = DC_EECMD_READ >> 6;
450 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
452 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
454 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
456 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
461 * Feed in each bit and strobe the clock.
463 for (i = sc->dc_romwidth; i--;) {
464 if (addr & (1 << i)) {
465 SIO_SET(DC_SIO_EE_DATAIN);
467 SIO_CLR(DC_SIO_EE_DATAIN);
470 SIO_SET(DC_SIO_EE_CLK);
472 SIO_CLR(DC_SIO_EE_CLK);
480 * Read a word of data stored in the EEPROM at address 'addr.'
481 * The PNIC 82c168/82c169 has its own non-standard way to read
485 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
490 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
492 for (i = 0; i < DC_TIMEOUT; i++) {
494 r = CSR_READ_4(sc, DC_SIO);
495 if (!(r & DC_PN_SIOCTL_BUSY)) {
496 *dest = (u_int16_t)(r & 0xFFFF);
505 * Read a word of data stored in the EEPROM at address 'addr.'
506 * The Xircom X3201 has its own non-standard way to read
510 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
512 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
515 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
516 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff;
518 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
519 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8;
521 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
525 * Read a word of data stored in the EEPROM at address 'addr.'
528 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
533 /* Force EEPROM to idle state. */
536 /* Enter EEPROM access mode. */
537 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
539 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
541 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
543 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
547 * Send address of word we want to read.
549 dc_eeprom_putbyte(sc, addr);
552 * Start reading bits from EEPROM.
554 for (i = 0x8000; i; i >>= 1) {
555 SIO_SET(DC_SIO_EE_CLK);
557 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
560 SIO_CLR(DC_SIO_EE_CLK);
564 /* Turn off EEPROM access mode. */
573 * Read a sequence of words from the EEPROM.
576 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap)
579 u_int16_t word = 0, *ptr;
581 for (i = 0; i < cnt; i++) {
583 dc_eeprom_getword_pnic(sc, off + i, &word);
584 else if (DC_IS_XIRCOM(sc))
585 dc_eeprom_getword_xircom(sc, off + i, &word);
587 dc_eeprom_getword(sc, off + i, &word);
588 ptr = (u_int16_t *)(dest + (i * 2));
599 * The following two routines are taken from the Macronix 98713
600 * Application Notes pp.19-21.
603 * Write a bit to the MII bus.
606 dc_mii_writebit(struct dc_softc *sc, int bit)
609 CSR_WRITE_4(sc, DC_SIO,
610 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
612 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
614 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
615 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
621 * Read a bit from the MII bus.
624 dc_mii_readbit(struct dc_softc *sc)
626 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
627 CSR_READ_4(sc, DC_SIO);
628 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
629 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
630 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
637 * Sync the PHYs by setting data bit and strobing the clock 32 times.
640 dc_mii_sync(struct dc_softc *sc)
644 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
646 for (i = 0; i < 32; i++)
647 dc_mii_writebit(sc, 1);
653 * Clock a series of bits through the MII.
656 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
660 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
661 dc_mii_writebit(sc, bits & i);
665 * Read an PHY register through the MII.
668 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
673 * Set up frame for RX.
675 frame->mii_stdelim = DC_MII_STARTDELIM;
676 frame->mii_opcode = DC_MII_READOP;
677 frame->mii_turnaround = 0;
686 * Send command/address info.
688 dc_mii_send(sc, frame->mii_stdelim, 2);
689 dc_mii_send(sc, frame->mii_opcode, 2);
690 dc_mii_send(sc, frame->mii_phyaddr, 5);
691 dc_mii_send(sc, frame->mii_regaddr, 5);
695 dc_mii_writebit(sc, 1);
696 dc_mii_writebit(sc, 0);
700 ack = dc_mii_readbit(sc);
703 * Now try reading data bits. If the ack failed, we still
704 * need to clock through 16 cycles to keep the PHY(s) in sync.
707 for(i = 0; i < 16; i++) {
713 for (i = 0x8000; i; i >>= 1) {
715 if (dc_mii_readbit(sc))
716 frame->mii_data |= i;
722 dc_mii_writebit(sc, 0);
723 dc_mii_writebit(sc, 0);
731 * Write to a PHY register through the MII.
734 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
737 * Set up frame for TX.
740 frame->mii_stdelim = DC_MII_STARTDELIM;
741 frame->mii_opcode = DC_MII_WRITEOP;
742 frame->mii_turnaround = DC_MII_TURNAROUND;
749 dc_mii_send(sc, frame->mii_stdelim, 2);
750 dc_mii_send(sc, frame->mii_opcode, 2);
751 dc_mii_send(sc, frame->mii_phyaddr, 5);
752 dc_mii_send(sc, frame->mii_regaddr, 5);
753 dc_mii_send(sc, frame->mii_turnaround, 2);
754 dc_mii_send(sc, frame->mii_data, 16);
757 dc_mii_writebit(sc, 0);
758 dc_mii_writebit(sc, 0);
764 dc_miibus_readreg(device_t dev, int phy, int reg)
766 struct dc_mii_frame frame;
768 int i, rval, phy_reg = 0;
770 sc = device_get_softc(dev);
771 bzero((char *)&frame, sizeof(frame));
774 * Note: both the AL981 and AN985 have internal PHYs,
775 * however the AL981 provides direct access to the PHY
776 * registers while the AN985 uses a serial MII interface.
777 * The AN985's MII interface is also buggy in that you
778 * can read from any MII address (0 to 31), but only address 1
779 * behaves normally. To deal with both cases, we pretend
780 * that the PHY is at MII address 1.
782 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
786 * Note: the ukphy probes of the RS7112 report a PHY at
787 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
788 * so we only respond to correct one.
790 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
793 if (sc->dc_pmode != DC_PMODE_MII) {
794 if (phy == (MII_NPHY - 1)) {
798 * Fake something to make the probe
799 * code think there's a PHY here.
801 return(BMSR_MEDIAMASK);
805 return(DC_VENDORID_LO);
806 return(DC_VENDORID_DEC);
810 return(DC_DEVICEID_82C168);
811 return(DC_DEVICEID_21143);
821 if (DC_IS_PNIC(sc)) {
822 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
823 (phy << 23) | (reg << 18));
824 for (i = 0; i < DC_TIMEOUT; i++) {
826 rval = CSR_READ_4(sc, DC_PN_MII);
827 if (!(rval & DC_PN_MII_BUSY)) {
829 return(rval == 0xFFFF ? 0 : rval);
835 if (DC_IS_COMET(sc)) {
838 phy_reg = DC_AL_BMCR;
841 phy_reg = DC_AL_BMSR;
844 phy_reg = DC_AL_VENID;
847 phy_reg = DC_AL_DEVID;
850 phy_reg = DC_AL_ANAR;
853 phy_reg = DC_AL_LPAR;
856 phy_reg = DC_AL_ANER;
859 if_printf(&sc->arpcom.ac_if,
860 "phy_read: bad phy register %x\n", reg);
865 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
872 frame.mii_phyaddr = phy;
873 frame.mii_regaddr = reg;
874 if (sc->dc_type == DC_TYPE_98713) {
875 phy_reg = CSR_READ_4(sc, DC_NETCFG);
876 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
878 dc_mii_readreg(sc, &frame);
879 if (sc->dc_type == DC_TYPE_98713)
880 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
882 return(frame.mii_data);
886 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
889 struct dc_mii_frame frame;
892 sc = device_get_softc(dev);
893 bzero((char *)&frame, sizeof(frame));
895 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
898 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
901 if (DC_IS_PNIC(sc)) {
902 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
903 (phy << 23) | (reg << 10) | data);
904 for (i = 0; i < DC_TIMEOUT; i++) {
905 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
911 if (DC_IS_COMET(sc)) {
914 phy_reg = DC_AL_BMCR;
917 phy_reg = DC_AL_BMSR;
920 phy_reg = DC_AL_VENID;
923 phy_reg = DC_AL_DEVID;
926 phy_reg = DC_AL_ANAR;
929 phy_reg = DC_AL_LPAR;
932 phy_reg = DC_AL_ANER;
935 if_printf(&sc->arpcom.ac_if,
936 "phy_write: bad phy register %x\n", reg);
941 CSR_WRITE_4(sc, phy_reg, data);
945 frame.mii_phyaddr = phy;
946 frame.mii_regaddr = reg;
947 frame.mii_data = data;
949 if (sc->dc_type == DC_TYPE_98713) {
950 phy_reg = CSR_READ_4(sc, DC_NETCFG);
951 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
953 dc_mii_writereg(sc, &frame);
954 if (sc->dc_type == DC_TYPE_98713)
955 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
961 dc_miibus_statchg(device_t dev)
964 struct mii_data *mii;
967 sc = device_get_softc(dev);
968 if (DC_IS_ADMTEK(sc))
971 mii = device_get_softc(sc->dc_miibus);
972 ifm = &mii->mii_media;
973 if (DC_IS_DAVICOM(sc) &&
974 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
975 dc_setcfg(sc, ifm->ifm_media);
976 sc->dc_if_media = ifm->ifm_media;
978 dc_setcfg(sc, mii->mii_media_active);
979 sc->dc_if_media = mii->mii_media_active;
986 * Special support for DM9102A cards with HomePNA PHYs. Note:
987 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
988 * to be impossible to talk to the management interface of the DM9801
989 * PHY (its MDIO pin is not connected to anything). Consequently,
990 * the driver has to just 'know' about the additional mode and deal
991 * with it itself. *sigh*
994 dc_miibus_mediainit(device_t dev)
997 struct mii_data *mii;
1001 rev = pci_get_revid(dev);
1003 sc = device_get_softc(dev);
1004 mii = device_get_softc(sc->dc_miibus);
1005 ifm = &mii->mii_media;
1007 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1008 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1013 #define DC_BITS_512 9
1014 #define DC_BITS_128 7
1015 #define DC_BITS_64 6
1018 dc_crc_mask(struct dc_softc *sc)
1021 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1022 * chips is only 128 bits wide.
1024 if (sc->dc_flags & DC_128BIT_HASH)
1025 return ((1 << DC_BITS_128) - 1);
1027 /* The hash table on the MX98715BEC is only 64 bits wide. */
1028 if (sc->dc_flags & DC_64BIT_HASH)
1029 return ((1 << DC_BITS_64) - 1);
1031 return ((1 << DC_BITS_512) - 1);
1035 * 21143-style RX filter setup routine. Filter programming is done by
1036 * downloading a special setup frame into the TX engine. 21143, Macronix,
1037 * PNIC, PNIC II and Davicom chips are programmed this way.
1039 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1040 * address (our node address) and a 512-bit hash filter for multicast
1041 * frames. We also sneak the broadcast address into the hash filter since
1045 dc_setfilt_21143(struct dc_softc *sc)
1047 struct dc_desc *sframe;
1048 u_int32_t h, crc_mask, *sp;
1049 struct ifmultiaddr *ifma;
1053 ifp = &sc->arpcom.ac_if;
1055 i = sc->dc_cdata.dc_tx_prod;
1056 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1057 sc->dc_cdata.dc_tx_cnt++;
1058 sframe = &sc->dc_ldata->dc_tx_list[i];
1059 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1060 bzero((char *)sp, DC_SFRAME_LEN);
1062 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1063 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1064 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1066 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1068 /* If we want promiscuous mode, set the allframes bit. */
1069 if (ifp->if_flags & IFF_PROMISC)
1070 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1072 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1074 if (ifp->if_flags & IFF_ALLMULTI)
1075 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1077 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1079 crc_mask = dc_crc_mask(sc);
1080 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1081 if (ifma->ifma_addr->sa_family != AF_LINK)
1084 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1085 ETHER_ADDR_LEN) & crc_mask;
1086 sp[h >> 4] |= 1 << (h & 0xF);
1089 if (ifp->if_flags & IFF_BROADCAST) {
1090 h = ether_crc32_le(ifp->if_broadcastaddr,
1091 ETHER_ADDR_LEN) & crc_mask;
1092 sp[h >> 4] |= 1 << (h & 0xF);
1095 /* Set our MAC address */
1096 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1097 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1098 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1100 sframe->dc_status = DC_TXSTAT_OWN;
1101 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1104 * The PNIC takes an exceedingly long time to process its
1105 * setup frame; wait 10ms after posting the setup frame
1106 * before proceeding, just so it has time to swallow its
1117 dc_setfilt_admtek(struct dc_softc *sc)
1122 u_int32_t hashes[2] = { 0, 0 };
1123 struct ifmultiaddr *ifma;
1125 ifp = &sc->arpcom.ac_if;
1127 /* Init our MAC address */
1128 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1129 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1131 /* If we want promiscuous mode, set the allframes bit. */
1132 if (ifp->if_flags & IFF_PROMISC)
1133 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1135 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1137 if (ifp->if_flags & IFF_ALLMULTI)
1138 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1140 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1142 /* first, zot all the existing hash bits */
1143 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1144 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1147 * If we're already in promisc or allmulti mode, we
1148 * don't have to bother programming the multicast filter.
1150 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1153 /* now program new ones */
1154 if (DC_IS_CENTAUR(sc))
1155 crc_mask = dc_crc_mask(sc);
1158 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1159 if (ifma->ifma_addr->sa_family != AF_LINK)
1161 if (DC_IS_CENTAUR(sc)) {
1163 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1164 ETHER_ADDR_LEN) & crc_mask;
1167 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1169 h = (h >> 26) & crc_mask;
1172 hashes[0] |= (1 << h);
1174 hashes[1] |= (1 << (h - 32));
1177 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1178 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1184 dc_setfilt_asix(struct dc_softc *sc)
1188 u_int32_t hashes[2] = { 0, 0 };
1189 struct ifmultiaddr *ifma;
1191 ifp = &sc->arpcom.ac_if;
1193 /* Init our MAC address */
1194 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1195 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1196 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1197 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1198 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1199 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1201 /* If we want promiscuous mode, set the allframes bit. */
1202 if (ifp->if_flags & IFF_PROMISC)
1203 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1205 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1207 if (ifp->if_flags & IFF_ALLMULTI)
1208 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1210 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1213 * The ASIX chip has a special bit to enable reception
1214 * of broadcast frames.
1216 if (ifp->if_flags & IFF_BROADCAST)
1217 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1219 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1221 /* first, zot all the existing hash bits */
1222 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1223 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1228 * If we're already in promisc or allmulti mode, we
1229 * don't have to bother programming the multicast filter.
1231 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1234 /* now program new ones */
1235 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1236 if (ifma->ifma_addr->sa_family != AF_LINK)
1239 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1241 h = (h >> 26) & 0x3f;
1243 hashes[0] |= (1 << h);
1245 hashes[1] |= (1 << (h - 32));
1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1250 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1251 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1257 dc_setfilt_xircom(struct dc_softc *sc)
1259 struct dc_desc *sframe;
1261 struct ifmultiaddr *ifma;
1265 ifp = &sc->arpcom.ac_if;
1266 KASSERT(ifp->if_flags & IFF_RUNNING,
1267 ("%s is not running yet\n", ifp->if_xname));
1269 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1271 i = sc->dc_cdata.dc_tx_prod;
1272 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1273 sc->dc_cdata.dc_tx_cnt++;
1274 sframe = &sc->dc_ldata->dc_tx_list[i];
1275 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1276 bzero(sp, DC_SFRAME_LEN);
1278 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1279 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1280 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1282 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1284 /* If we want promiscuous mode, set the allframes bit. */
1285 if (ifp->if_flags & IFF_PROMISC)
1286 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1288 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1290 if (ifp->if_flags & IFF_ALLMULTI)
1291 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1293 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1295 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1296 if (ifma->ifma_addr->sa_family != AF_LINK)
1298 h = dc_mchash_xircom(sc,
1299 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1300 sp[h >> 4] |= 1 << (h & 0xF);
1303 if (ifp->if_flags & IFF_BROADCAST) {
1304 h = dc_mchash_xircom(sc, (caddr_t)ðerbroadcastaddr);
1305 sp[h >> 4] |= 1 << (h & 0xF);
1308 /* Set our MAC address */
1309 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1310 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1311 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1314 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1315 sframe->dc_status = DC_TXSTAT_OWN;
1316 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1327 dc_setfilt(struct dc_softc *sc)
1329 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1330 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1331 dc_setfilt_21143(sc);
1334 dc_setfilt_asix(sc);
1336 if (DC_IS_ADMTEK(sc))
1337 dc_setfilt_admtek(sc);
1339 if (DC_IS_XIRCOM(sc))
1340 dc_setfilt_xircom(sc);
1344 * In order to fiddle with the
1345 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1346 * first have to put the transmit and/or receive logic in the idle state.
1349 dc_setcfg(struct dc_softc *sc, int media)
1354 if (IFM_SUBTYPE(media) == IFM_NONE)
1357 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1359 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1361 for (i = 0; i < DC_TIMEOUT; i++) {
1362 isr = CSR_READ_4(sc, DC_ISR);
1363 if ((isr & DC_ISR_TX_IDLE) &&
1364 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1365 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1370 if (i == DC_TIMEOUT) {
1371 if_printf(&sc->arpcom.ac_if,
1372 "failed to force tx and rx to idle state\n");
1376 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1377 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1378 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1379 if (sc->dc_pmode == DC_PMODE_MII) {
1382 if (DC_IS_INTEL(sc)) {
1383 /* there's a write enable bit here that reads as 1 */
1384 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1385 watchdogreg &= ~DC_WDOG_CTLWREN;
1386 watchdogreg |= DC_WDOG_JABBERDIS;
1387 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1389 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1391 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1392 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1393 if (sc->dc_type == DC_TYPE_98713)
1394 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1395 DC_NETCFG_SCRAMBLER));
1396 if (!DC_IS_DAVICOM(sc))
1397 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1398 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1399 if (DC_IS_INTEL(sc))
1400 dc_apply_fixup(sc, IFM_AUTO);
1402 if (DC_IS_PNIC(sc)) {
1403 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1404 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1405 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1407 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1408 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1409 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1410 if (DC_IS_INTEL(sc))
1412 (media & IFM_GMASK) == IFM_FDX ?
1413 IFM_100_TX|IFM_FDX : IFM_100_TX);
1417 if (IFM_SUBTYPE(media) == IFM_10_T) {
1418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1419 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1420 if (sc->dc_pmode == DC_PMODE_MII) {
1423 /* there's a write enable bit here that reads as 1 */
1424 if (DC_IS_INTEL(sc)) {
1425 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1426 watchdogreg &= ~DC_WDOG_CTLWREN;
1427 watchdogreg |= DC_WDOG_JABBERDIS;
1428 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1430 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1432 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1433 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1434 if (sc->dc_type == DC_TYPE_98713)
1435 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1436 if (!DC_IS_DAVICOM(sc))
1437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1438 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1439 if (DC_IS_INTEL(sc))
1440 dc_apply_fixup(sc, IFM_AUTO);
1442 if (DC_IS_PNIC(sc)) {
1443 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1444 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1445 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1447 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1448 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1449 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1450 if (DC_IS_INTEL(sc)) {
1451 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1452 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1453 if ((media & IFM_GMASK) == IFM_FDX)
1454 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1456 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1457 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1458 DC_CLRBIT(sc, DC_10BTCTRL,
1459 DC_TCTL_AUTONEGENBL);
1461 (media & IFM_GMASK) == IFM_FDX ?
1462 IFM_10_T|IFM_FDX : IFM_10_T);
1469 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1470 * PHY and we want HomePNA mode, set the portsel bit to turn
1471 * on the external MII port.
1473 if (DC_IS_DAVICOM(sc)) {
1474 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1475 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1482 if ((media & IFM_GMASK) == IFM_FDX) {
1483 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1484 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1485 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1487 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1488 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1489 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1493 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1499 dc_reset(struct dc_softc *sc)
1503 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1505 for (i = 0; i < DC_TIMEOUT; i++) {
1507 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1511 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) ||
1512 DC_IS_CONEXANT(sc)) {
1514 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1518 if (i == DC_TIMEOUT)
1519 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
1521 /* Wait a little while for the chip to get its brains in order. */
1524 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1525 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1526 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1529 * Bring the SIA out of reset. In some cases, it looks
1530 * like failing to unreset the SIA soon enough gets it
1531 * into a state where it will never come out of reset
1532 * until we reset the whole chip again.
1534 if (DC_IS_INTEL(sc)) {
1535 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1536 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1537 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1543 static const struct dc_type *
1544 dc_devtype(device_t dev)
1546 const struct dc_type *t;
1551 while(t->dc_name != NULL) {
1552 if ((pci_get_vendor(dev) == t->dc_vid) &&
1553 (pci_get_device(dev) == t->dc_did)) {
1554 /* Check the PCI revision */
1555 rev = pci_get_revid(dev);
1556 if (t->dc_did == DC_DEVICEID_98713 &&
1557 rev >= DC_REVISION_98713A)
1559 if (t->dc_did == DC_DEVICEID_98713_CP &&
1560 rev >= DC_REVISION_98713A)
1562 if (t->dc_did == DC_DEVICEID_987x5 &&
1563 rev >= DC_REVISION_98715AEC_C)
1565 if (t->dc_did == DC_DEVICEID_987x5 &&
1566 rev >= DC_REVISION_98725)
1568 if (t->dc_did == DC_DEVICEID_AX88140A &&
1569 rev >= DC_REVISION_88141)
1571 if (t->dc_did == DC_DEVICEID_82C168 &&
1572 rev >= DC_REVISION_82C169)
1574 if (t->dc_did == DC_DEVICEID_DM9102 &&
1575 rev >= DC_REVISION_DM9102A)
1586 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1587 * IDs against our list and return a device name if we find a match.
1588 * We do a little bit of extra work to identify the exact type of
1589 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1590 * but different revision IDs. The same is true for 98715/98715A
1591 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1592 * cases, the exact chip revision affects driver behavior.
1595 dc_probe(device_t dev)
1597 const struct dc_type *t;
1599 t = dc_devtype(dev);
1601 struct dc_softc *sc = device_get_softc(dev);
1603 /* Need this info to decide on a chip type. */
1605 device_set_desc(dev, t->dc_name);
1613 dc_acpi(device_t dev)
1615 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1616 uint32_t iobase, membase, irq;
1617 struct dc_softc *sc;
1619 /* Save important PCI config data. */
1620 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1621 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1622 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1624 sc = device_get_softc(dev);
1625 /* Reset the power state. */
1626 if_printf(&sc->arpcom.ac_if,
1627 "chip is in D%d power mode "
1628 "-- setting to D0\n", pci_get_powerstate(dev));
1629 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1631 /* Restore PCI config data. */
1632 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1633 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1634 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1639 dc_apply_fixup(struct dc_softc *sc, int media)
1641 struct dc_mediainfo *m;
1649 if (m->dc_media == media)
1657 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1658 reg = (p[0] | (p[1] << 8)) << 16;
1659 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1662 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1663 reg = (p[0] | (p[1] << 8)) << 16;
1664 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1671 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1673 struct dc_mediainfo *m;
1675 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1676 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){
1677 case DC_SIA_CODE_10BT:
1678 m->dc_media = IFM_10_T;
1681 case DC_SIA_CODE_10BT_FDX:
1682 m->dc_media = IFM_10_T|IFM_FDX;
1685 case DC_SIA_CODE_10B2:
1686 m->dc_media = IFM_10_2;
1689 case DC_SIA_CODE_10B5:
1690 m->dc_media = IFM_10_5;
1693 if (l->dc_sia_code & DC_SIA_CODE_EXT){
1696 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1700 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1703 m->dc_next = sc->dc_mi;
1706 sc->dc_pmode = DC_PMODE_SIA;
1712 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1714 struct dc_mediainfo *m;
1716 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1717 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1718 m->dc_media = IFM_100_TX;
1720 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1721 m->dc_media = IFM_100_TX|IFM_FDX;
1724 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1726 m->dc_next = sc->dc_mi;
1729 sc->dc_pmode = DC_PMODE_SYM;
1735 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1738 struct dc_mediainfo *m;
1740 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1741 /* We abuse IFM_AUTO to represent MII. */
1742 m->dc_media = IFM_AUTO;
1743 m->dc_gp_len = l->dc_gpr_len;
1746 p += sizeof(struct dc_eblock_mii);
1748 p += 2 * l->dc_gpr_len;
1749 m->dc_reset_len = *p;
1751 m->dc_reset_ptr = p;
1753 m->dc_next = sc->dc_mi;
1760 dc_read_srom(struct dc_softc *sc, int bits)
1765 sc->dc_srom = kmalloc(size, M_DEVBUF, M_INTWAIT);
1766 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1770 dc_parse_21143_srom(struct dc_softc *sc)
1772 struct dc_leaf_hdr *lhdr;
1773 struct dc_eblock_hdr *hdr;
1779 loff = sc->dc_srom[27];
1780 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1783 ptr += sizeof(struct dc_leaf_hdr) - 1;
1785 * Look if we got a MII media block.
1787 for (i = 0; i < lhdr->dc_mcnt; i++) {
1788 hdr = (struct dc_eblock_hdr *)ptr;
1789 if (hdr->dc_type == DC_EBLOCK_MII)
1792 ptr += (hdr->dc_len & 0x7F);
1797 * Do the same thing again. Only use SIA and SYM media
1798 * blocks if no MII media block is available.
1801 ptr += sizeof(struct dc_leaf_hdr) - 1;
1802 for (i = 0; i < lhdr->dc_mcnt; i++) {
1803 hdr = (struct dc_eblock_hdr *)ptr;
1804 switch(hdr->dc_type) {
1806 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1810 dc_decode_leaf_sia(sc,
1811 (struct dc_eblock_sia *)hdr);
1815 dc_decode_leaf_sym(sc,
1816 (struct dc_eblock_sym *)hdr);
1819 /* Don't care. Yet. */
1822 ptr += (hdr->dc_len & 0x7F);
1830 * Attach the interface. Allocate softc structures, do ifmedia
1831 * setup and ethernet/BPF attach.
1834 dc_attach(device_t dev)
1837 u_char eaddr[ETHER_ADDR_LEN];
1839 struct dc_softc *sc;
1842 int error = 0, rid, mac_offset;
1845 sc = device_get_softc(dev);
1846 callout_init(&sc->dc_stat_timer);
1848 ifp = &sc->arpcom.ac_if;
1849 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1852 * Handle power management nonsense.
1857 * Map control/status registers.
1859 pci_enable_busmaster(dev);
1862 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1864 if (sc->dc_res == NULL) {
1865 device_printf(dev, "couldn't map ports/memory\n");
1870 sc->dc_btag = rman_get_bustag(sc->dc_res);
1871 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1873 /* Allocate interrupt */
1875 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1876 RF_SHAREABLE | RF_ACTIVE);
1878 if (sc->dc_irq == NULL) {
1879 device_printf(dev, "couldn't map interrupt\n");
1884 revision = pci_get_revid(dev);
1886 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1887 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 &&
1888 sc->dc_info->dc_did != DC_DEVICEID_X3201)
1889 dc_eeprom_width(sc);
1891 switch(sc->dc_info->dc_did) {
1892 case DC_DEVICEID_21143:
1893 sc->dc_type = DC_TYPE_21143;
1894 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1895 sc->dc_flags |= DC_REDUCED_MII_POLL;
1896 /* Save EEPROM contents so we can parse them later. */
1897 dc_read_srom(sc, sc->dc_romwidth);
1899 case DC_DEVICEID_DM9009:
1900 case DC_DEVICEID_DM9100:
1901 case DC_DEVICEID_DM9102:
1902 sc->dc_type = DC_TYPE_DM9102;
1903 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1904 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1905 sc->dc_flags |= DC_TX_ALIGN;
1906 sc->dc_pmode = DC_PMODE_MII;
1907 /* Increase the latency timer value. */
1908 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1909 command &= 0xFFFF00FF;
1910 command |= 0x00008000;
1911 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1913 case DC_DEVICEID_AL981:
1914 sc->dc_type = DC_TYPE_AL981;
1915 sc->dc_flags |= DC_TX_USE_TX_INTR;
1916 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1917 sc->dc_pmode = DC_PMODE_MII;
1918 dc_read_srom(sc, sc->dc_romwidth);
1920 case DC_DEVICEID_AN985:
1921 case DC_DEVICEID_FE2500:
1922 case DC_DEVICEID_ADM9511:
1923 case DC_DEVICEID_ADM9513:
1924 case DC_DEVICEID_FA511:
1925 case DC_DEVICEID_EN2242:
1926 case DC_DEVICEID_3CSOHOB:
1927 sc->dc_type = DC_TYPE_AN985;
1928 sc->dc_flags |= DC_64BIT_HASH;
1929 sc->dc_flags |= DC_TX_USE_TX_INTR;
1930 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1931 sc->dc_pmode = DC_PMODE_MII;
1933 case DC_DEVICEID_98713:
1934 case DC_DEVICEID_98713_CP:
1935 if (revision < DC_REVISION_98713A) {
1936 sc->dc_type = DC_TYPE_98713;
1938 if (revision >= DC_REVISION_98713A) {
1939 sc->dc_type = DC_TYPE_98713A;
1940 sc->dc_flags |= DC_21143_NWAY;
1942 sc->dc_flags |= DC_REDUCED_MII_POLL;
1943 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1945 case DC_DEVICEID_987x5:
1946 case DC_DEVICEID_EN1217:
1948 * Macronix MX98715AEC-C/D/E parts have only a
1949 * 128-bit hash table. We need to deal with these
1950 * in the same manner as the PNIC II so that we
1951 * get the right number of bits out of the
1954 if (revision >= DC_REVISION_98715AEC_C &&
1955 revision < DC_REVISION_98725)
1956 sc->dc_flags |= DC_128BIT_HASH;
1957 sc->dc_type = DC_TYPE_987x5;
1958 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1959 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1961 case DC_DEVICEID_98727:
1962 sc->dc_type = DC_TYPE_987x5;
1963 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1964 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1966 case DC_DEVICEID_82C115:
1967 sc->dc_type = DC_TYPE_PNICII;
1968 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1969 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1971 case DC_DEVICEID_82C168:
1972 sc->dc_type = DC_TYPE_PNIC;
1973 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1974 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1975 sc->dc_pnic_rx_buf = kmalloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK);
1976 if (revision < DC_REVISION_82C169)
1977 sc->dc_pmode = DC_PMODE_SYM;
1979 case DC_DEVICEID_AX88140A:
1980 sc->dc_type = DC_TYPE_ASIX;
1981 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1982 sc->dc_flags |= DC_REDUCED_MII_POLL;
1983 sc->dc_pmode = DC_PMODE_MII;
1985 case DC_DEVICEID_RS7112:
1986 sc->dc_type = DC_TYPE_CONEXANT;
1987 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1988 sc->dc_flags |= DC_REDUCED_MII_POLL;
1989 sc->dc_pmode = DC_PMODE_MII;
1990 dc_read_srom(sc, sc->dc_romwidth);
1992 case DC_DEVICEID_X3201:
1993 sc->dc_type = DC_TYPE_XIRCOM;
1994 sc->dc_flags |= (DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
1997 * We don't actually need to coalesce, but we're doing
1998 * it to obtain a double word aligned buffer.
1999 * The DC_TX_COALESCE flag is required.
2001 sc->dc_pmode = DC_PMODE_MII;
2004 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did);
2008 /* Save the cache line size. */
2009 if (DC_IS_DAVICOM(sc))
2010 sc->dc_cachesize = 0;
2012 sc->dc_cachesize = pci_read_config(dev,
2013 DC_PCI_CFLT, 4) & 0xFF;
2015 /* Reset the adapter. */
2018 /* Take 21143 out of snooze mode */
2019 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2020 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2021 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
2022 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2026 * Try to learn something about the supported media.
2027 * We know that ASIX and ADMtek and Davicom devices
2028 * will *always* be using MII media, so that's a no-brainer.
2029 * The tricky ones are the Macronix/PNIC II and the
2032 if (DC_IS_INTEL(sc))
2033 dc_parse_21143_srom(sc);
2034 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2035 if (sc->dc_type == DC_TYPE_98713)
2036 sc->dc_pmode = DC_PMODE_MII;
2038 sc->dc_pmode = DC_PMODE_SYM;
2039 } else if (!sc->dc_pmode)
2040 sc->dc_pmode = DC_PMODE_MII;
2043 * Get station address from the EEPROM.
2045 switch(sc->dc_type) {
2047 case DC_TYPE_98713A:
2049 case DC_TYPE_PNICII:
2050 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2051 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2052 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2055 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2057 case DC_TYPE_DM9102:
2060 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2064 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0);
2065 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1);
2067 case DC_TYPE_CONEXANT:
2068 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2070 case DC_TYPE_XIRCOM:
2071 /* The MAC comes from the CIS */
2072 mac = pci_get_ether(dev);
2074 device_printf(dev, "No station address in CIS!\n");
2078 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2081 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2085 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
2086 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
2088 if (sc->dc_ldata == NULL) {
2089 device_printf(dev, "no memory for list buffers!\n");
2095 ifp->if_mtu = ETHERMTU;
2096 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2097 ifp->if_ioctl = dc_ioctl;
2098 ifp->if_start = dc_start;
2099 #ifdef DEVICE_POLLING
2100 ifp->if_poll = dc_poll;
2102 ifp->if_watchdog = dc_watchdog;
2103 ifp->if_init = dc_init;
2104 ifp->if_baudrate = 10000000;
2105 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2106 ifq_set_ready(&ifp->if_snd);
2109 * Do MII setup. If this is a 21143, check for a PHY on the
2110 * MII bus after applying any necessary fixups to twiddle the
2111 * GPIO bits. If we don't end up finding a PHY, restore the
2112 * old selection (SIA only or SIA/SYM) and attach the dcphy
2115 if (DC_IS_INTEL(sc)) {
2116 dc_apply_fixup(sc, IFM_AUTO);
2118 sc->dc_pmode = DC_PMODE_MII;
2122 * Setup General Purpose port mode and data so the tulip can talk
2123 * to the MII. This needs to be done before mii_phy_probe so that
2124 * we can actually see them.
2126 if (DC_IS_XIRCOM(sc)) {
2127 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2128 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2130 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2131 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2135 error = mii_phy_probe(dev, &sc->dc_miibus,
2136 dc_ifmedia_upd, dc_ifmedia_sts);
2138 if (error && DC_IS_INTEL(sc)) {
2140 if (sc->dc_pmode != DC_PMODE_SIA)
2141 sc->dc_pmode = DC_PMODE_SYM;
2142 sc->dc_flags |= DC_21143_NWAY;
2143 mii_phy_probe(dev, &sc->dc_miibus,
2144 dc_ifmedia_upd, dc_ifmedia_sts);
2146 * For non-MII cards, we need to have the 21143
2147 * drive the LEDs. Except there are some systems
2148 * like the NEC VersaPro NoteBook PC which have no
2149 * LEDs, and twiddling these bits has adverse effects
2150 * on them. (I.e. you suddenly can't get a link.)
2152 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2153 sc->dc_flags |= DC_TULIP_LEDS;
2158 device_printf(dev, "MII without any PHY!\n");
2164 * Call MI attach routine.
2166 ether_ifattach(ifp, eaddr, NULL);
2168 if (DC_IS_ADMTEK(sc)) {
2170 * Set automatic TX underrun recovery for the ADMtek chips
2172 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2176 * Tell the upper layer(s) we support long frames.
2178 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2180 error = bus_setup_intr(dev, sc->dc_irq, INTR_MPSAFE,
2181 dc_intr, sc, &sc->dc_intrhand,
2182 ifp->if_serializer);
2184 ether_ifdetach(ifp);
2185 device_printf(dev, "couldn't set up irq\n");
2189 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->dc_irq));
2190 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2200 dc_detach(device_t dev)
2202 struct dc_softc *sc = device_get_softc(dev);
2203 struct ifnet *ifp = &sc->arpcom.ac_if;
2204 struct dc_mediainfo *m;
2206 if (device_is_attached(dev)) {
2207 lwkt_serialize_enter(ifp->if_serializer);
2209 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2210 lwkt_serialize_exit(ifp->if_serializer);
2212 ether_ifdetach(ifp);
2216 device_delete_child(dev, sc->dc_miibus);
2217 bus_generic_detach(dev);
2220 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2222 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2225 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2226 if (sc->dc_pnic_rx_buf != NULL)
2227 kfree(sc->dc_pnic_rx_buf, M_DEVBUF);
2229 while (sc->dc_mi != NULL) {
2230 m = sc->dc_mi->dc_next;
2231 kfree(sc->dc_mi, M_DEVBUF);
2236 kfree(sc->dc_srom, M_DEVBUF);
2242 * Initialize the transmit descriptors.
2245 dc_list_tx_init(struct dc_softc *sc)
2247 struct dc_chain_data *cd;
2248 struct dc_list_data *ld;
2253 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2254 if (i == (DC_TX_LIST_CNT - 1)) {
2255 ld->dc_tx_list[i].dc_next =
2256 vtophys(&ld->dc_tx_list[0]);
2258 ld->dc_tx_list[i].dc_next =
2259 vtophys(&ld->dc_tx_list[i + 1]);
2261 cd->dc_tx_chain[i] = NULL;
2262 ld->dc_tx_list[i].dc_data = 0;
2263 ld->dc_tx_list[i].dc_ctl = 0;
2266 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2273 * Initialize the RX descriptors and allocate mbufs for them. Note that
2274 * we arrange the descriptors in a closed ring, so that the last descriptor
2275 * points back to the first.
2278 dc_list_rx_init(struct dc_softc *sc)
2280 struct dc_chain_data *cd;
2281 struct dc_list_data *ld;
2287 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2288 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2290 if (i == (DC_RX_LIST_CNT - 1)) {
2291 ld->dc_rx_list[i].dc_next =
2292 vtophys(&ld->dc_rx_list[0]);
2294 ld->dc_rx_list[i].dc_next =
2295 vtophys(&ld->dc_rx_list[i + 1]);
2305 * Initialize an RX descriptor and attach an MBUF cluster.
2308 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m)
2310 struct mbuf *m_new = NULL;
2313 c = &sc->dc_ldata->dc_rx_list[i];
2316 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2319 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2322 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2323 m_new->m_data = m_new->m_ext.ext_buf;
2326 m_adj(m_new, sizeof(u_int64_t));
2329 * If this is a PNIC chip, zero the buffer. This is part
2330 * of the workaround for the receive bug in the 82c168 and
2333 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2334 bzero((char *)mtod(m_new, char *), m_new->m_len);
2336 sc->dc_cdata.dc_rx_chain[i] = m_new;
2337 c->dc_data = vtophys(mtod(m_new, caddr_t));
2338 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2339 c->dc_status = DC_RXSTAT_OWN;
2346 * The PNIC chip has a terrible bug in it that manifests itself during
2347 * periods of heavy activity. The exact mode of failure if difficult to
2348 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2349 * will happen on slow machines. The bug is that sometimes instead of
2350 * uploading one complete frame during reception, it uploads what looks
2351 * like the entire contents of its FIFO memory. The frame we want is at
2352 * the end of the whole mess, but we never know exactly how much data has
2353 * been uploaded, so salvaging the frame is hard.
2355 * There is only one way to do it reliably, and it's disgusting.
2356 * Here's what we know:
2358 * - We know there will always be somewhere between one and three extra
2359 * descriptors uploaded.
2361 * - We know the desired received frame will always be at the end of the
2362 * total data upload.
2364 * - We know the size of the desired received frame because it will be
2365 * provided in the length field of the status word in the last descriptor.
2367 * Here's what we do:
2369 * - When we allocate buffers for the receive ring, we bzero() them.
2370 * This means that we know that the buffer contents should be all
2371 * zeros, except for data uploaded by the chip.
2373 * - We also force the PNIC chip to upload frames that include the
2374 * ethernet CRC at the end.
2376 * - We gather all of the bogus frame data into a single buffer.
2378 * - We then position a pointer at the end of this buffer and scan
2379 * backwards until we encounter the first non-zero byte of data.
2380 * This is the end of the received frame. We know we will encounter
2381 * some data at the end of the frame because the CRC will always be
2382 * there, so even if the sender transmits a packet of all zeros,
2383 * we won't be fooled.
2385 * - We know the size of the actual received frame, so we subtract
2386 * that value from the current pointer location. This brings us
2387 * to the start of the actual received packet.
2389 * - We copy this into an mbuf and pass it on, along with the actual
2392 * The performance hit is tremendous, but it beats dropping frames all
2396 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2398 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2400 struct dc_desc *cur_rx;
2401 struct dc_desc *c = NULL;
2402 struct mbuf *m = NULL;
2405 u_int32_t rxstat = 0;
2407 i = sc->dc_pnic_rx_bug_save;
2408 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2409 ptr = sc->dc_pnic_rx_buf;
2410 bzero(ptr, DC_RXLEN * 5);
2412 /* Copy all the bytes from the bogus buffers. */
2414 c = &sc->dc_ldata->dc_rx_list[i];
2415 rxstat = c->dc_status;
2416 m = sc->dc_cdata.dc_rx_chain[i];
2417 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2419 /* If this is the last buffer, break out. */
2420 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2422 dc_newbuf(sc, i, m);
2423 DC_INC(i, DC_RX_LIST_CNT);
2426 /* Find the length of the actual receive frame. */
2427 total_len = DC_RXBYTES(rxstat);
2429 /* Scan backwards until we hit a non-zero byte. */
2434 if ((uintptr_t)(ptr) & 0x3)
2437 /* Now find the start of the frame. */
2439 if (ptr < sc->dc_pnic_rx_buf)
2440 ptr = sc->dc_pnic_rx_buf;
2443 * Now copy the salvaged frame to the last mbuf and fake up
2444 * the status word to make it look like a successful
2447 dc_newbuf(sc, i, m);
2448 bcopy(ptr, mtod(m, char *), total_len);
2449 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2455 * This routine searches the RX ring for dirty descriptors in the
2456 * event that the rxeof routine falls out of sync with the chip's
2457 * current descriptor pointer. This may happen sometimes as a result
2458 * of a "no RX buffer available" condition that happens when the chip
2459 * consumes all of the RX buffers before the driver has a chance to
2460 * process the RX ring. This routine may need to be called more than
2461 * once to bring the driver back in sync with the chip, however we
2462 * should still be getting RX DONE interrupts to drive the search
2463 * for new packets in the RX ring, so we should catch up eventually.
2466 dc_rx_resync(struct dc_softc *sc)
2469 struct dc_desc *cur_rx;
2471 pos = sc->dc_cdata.dc_rx_prod;
2473 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2474 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2475 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2477 DC_INC(pos, DC_RX_LIST_CNT);
2480 /* If the ring really is empty, then just return. */
2481 if (i == DC_RX_LIST_CNT)
2484 /* We've fallen behing the chip: catch it. */
2485 sc->dc_cdata.dc_rx_prod = pos;
2491 * A frame has been uploaded: pass the resulting mbuf chain up to
2492 * the higher level protocols.
2495 dc_rxeof(struct dc_softc *sc)
2499 struct dc_desc *cur_rx;
2500 int i, total_len = 0;
2503 ifp = &sc->arpcom.ac_if;
2504 i = sc->dc_cdata.dc_rx_prod;
2506 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2508 #ifdef DEVICE_POLLING
2509 if (ifp->if_flags & IFF_POLLING) {
2510 if (sc->rxcycles <= 0)
2514 #endif /* DEVICE_POLLING */
2515 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2516 rxstat = cur_rx->dc_status;
2517 m = sc->dc_cdata.dc_rx_chain[i];
2518 total_len = DC_RXBYTES(rxstat);
2520 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2521 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2522 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2523 sc->dc_pnic_rx_bug_save = i;
2524 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2525 DC_INC(i, DC_RX_LIST_CNT);
2528 dc_pnic_rx_bug_war(sc, i);
2529 rxstat = cur_rx->dc_status;
2530 total_len = DC_RXBYTES(rxstat);
2534 sc->dc_cdata.dc_rx_chain[i] = NULL;
2537 * If an error occurs, update stats, clear the
2538 * status word and leave the mbuf cluster in place:
2539 * it should simply get re-used next time this descriptor
2540 * comes up in the ring. However, don't report long
2541 * frames as errors since they could be vlans
2543 if ((rxstat & DC_RXSTAT_RXERR)){
2544 if (!(rxstat & DC_RXSTAT_GIANT) ||
2545 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2546 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2547 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2549 if (rxstat & DC_RXSTAT_COLLSEEN)
2550 ifp->if_collisions++;
2551 dc_newbuf(sc, i, m);
2552 if (rxstat & DC_RXSTAT_CRCERR) {
2553 DC_INC(i, DC_RX_LIST_CNT);
2562 /* No errors; receive the packet. */
2563 total_len -= ETHER_CRC_LEN;
2567 * On the x86 we do not have alignment problems, so try to
2568 * allocate a new buffer for the receive ring, and pass up
2569 * the one where the packet is already, saving the expensive
2570 * copy done in m_devget().
2571 * If we are on an architecture with alignment problems, or
2572 * if the allocation fails, then use m_devget and leave the
2573 * existing buffer in the receive ring.
2575 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2576 m->m_pkthdr.rcvif = ifp;
2577 m->m_pkthdr.len = m->m_len = total_len;
2578 DC_INC(i, DC_RX_LIST_CNT);
2584 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2585 total_len + ETHER_ALIGN, 0, ifp, NULL);
2586 dc_newbuf(sc, i, m);
2587 DC_INC(i, DC_RX_LIST_CNT);
2592 m_adj(m0, ETHER_ALIGN);
2597 ifp->if_input(ifp, m);
2600 sc->dc_cdata.dc_rx_prod = i;
2604 * A frame was downloaded to the chip. It's safe for us to clean up
2609 dc_txeof(struct dc_softc *sc)
2611 struct dc_desc *cur_tx = NULL;
2615 ifp = &sc->arpcom.ac_if;
2618 * Go through our tx list and free mbufs for those
2619 * frames that have been transmitted.
2621 idx = sc->dc_cdata.dc_tx_cons;
2622 while(idx != sc->dc_cdata.dc_tx_prod) {
2625 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2626 txstat = cur_tx->dc_status;
2628 if (txstat & DC_TXSTAT_OWN)
2631 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2632 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2633 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2635 * Yes, the PNIC is so brain damaged
2636 * that it will sometimes generate a TX
2637 * underrun error while DMAing the RX
2638 * filter setup frame. If we detect this,
2639 * we have to send the setup frame again,
2640 * or else the filter won't be programmed
2643 if (DC_IS_PNIC(sc)) {
2644 if (txstat & DC_TXSTAT_ERRSUM)
2647 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2649 sc->dc_cdata.dc_tx_cnt--;
2650 DC_INC(idx, DC_TX_LIST_CNT);
2654 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2656 * XXX: Why does my Xircom taunt me so?
2657 * For some reason Conexant chips like
2658 * setting the CARRLOST flag even when
2659 * the carrier is there. In CURRENT we
2660 * have the same problem for Xircom
2663 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2664 sc->dc_pmode == DC_PMODE_MII &&
2665 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2666 DC_TXSTAT_NOCARRIER)))
2667 txstat &= ~DC_TXSTAT_ERRSUM;
2669 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2670 sc->dc_pmode == DC_PMODE_MII &&
2671 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2672 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2673 txstat &= ~DC_TXSTAT_ERRSUM;
2676 if (txstat & DC_TXSTAT_ERRSUM) {
2678 if (txstat & DC_TXSTAT_EXCESSCOLL)
2679 ifp->if_collisions++;
2680 if (txstat & DC_TXSTAT_LATECOLL)
2681 ifp->if_collisions++;
2682 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2688 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2691 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2692 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2693 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2696 sc->dc_cdata.dc_tx_cnt--;
2697 DC_INC(idx, DC_TX_LIST_CNT);
2700 if (idx != sc->dc_cdata.dc_tx_cons) {
2701 /* some buffers have been freed */
2702 sc->dc_cdata.dc_tx_cons = idx;
2703 ifp->if_flags &= ~IFF_OACTIVE;
2705 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2713 struct dc_softc *sc = xsc;
2714 struct ifnet *ifp = &sc->arpcom.ac_if;
2715 struct mii_data *mii;
2718 lwkt_serialize_enter(ifp->if_serializer);
2720 mii = device_get_softc(sc->dc_miibus);
2722 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2723 if (sc->dc_flags & DC_21143_NWAY) {
2724 r = CSR_READ_4(sc, DC_10BTSTAT);
2725 if (IFM_SUBTYPE(mii->mii_media_active) ==
2726 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2730 if (IFM_SUBTYPE(mii->mii_media_active) ==
2731 IFM_10_T && (r & DC_TSTAT_LS10)) {
2735 if (sc->dc_link == 0)
2738 r = CSR_READ_4(sc, DC_ISR);
2739 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2740 sc->dc_cdata.dc_tx_cnt == 0) {
2742 if (!(mii->mii_media_status & IFM_ACTIVE))
2751 * When the init routine completes, we expect to be able to send
2752 * packets right away, and in fact the network code will send a
2753 * gratuitous ARP the moment the init routine marks the interface
2754 * as running. However, even though the MAC may have been initialized,
2755 * there may be a delay of a few seconds before the PHY completes
2756 * autonegotiation and the link is brought up. Any transmissions
2757 * made during that delay will be lost. Dealing with this is tricky:
2758 * we can't just pause in the init routine while waiting for the
2759 * PHY to come ready since that would bring the whole system to
2760 * a screeching halt for several seconds.
2762 * What we do here is prevent the TX start routine from sending
2763 * any packets until a link has been established. After the
2764 * interface has been initialized, the tick routine will poll
2765 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2766 * that time, packets will stay in the send queue, and once the
2767 * link comes up, they will be flushed out to the wire.
2771 if (mii->mii_media_status & IFM_ACTIVE &&
2772 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2774 if (!ifq_is_empty(&ifp->if_snd))
2779 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2780 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc);
2782 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
2784 lwkt_serialize_exit(ifp->if_serializer);
2788 * A transmit underrun has occurred. Back off the transmit threshold,
2789 * or switch to store and forward mode if we have to.
2792 dc_tx_underrun(struct dc_softc *sc)
2797 if (DC_IS_DAVICOM(sc))
2800 if (DC_IS_INTEL(sc)) {
2802 * The real 21143 requires that the transmitter be idle
2803 * in order to change the transmit threshold or store
2804 * and forward state.
2806 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2808 for (i = 0; i < DC_TIMEOUT; i++) {
2809 isr = CSR_READ_4(sc, DC_ISR);
2810 if (isr & DC_ISR_TX_IDLE)
2814 if (i == DC_TIMEOUT) {
2815 if_printf(&sc->arpcom.ac_if,
2816 "failed to force tx to idle state\n");
2821 if_printf(&sc->arpcom.ac_if, "TX underrun -- ");
2822 sc->dc_txthresh += DC_TXTHRESH_INC;
2823 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2824 kprintf("using store and forward mode\n");
2825 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2827 kprintf("increasing TX threshold\n");
2828 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2829 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2832 if (DC_IS_INTEL(sc))
2833 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2838 #ifdef DEVICE_POLLING
2841 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2843 struct dc_softc *sc = ifp->if_softc;
2848 /* Disable interrupts */
2849 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2851 case POLL_DEREGISTER:
2852 /* Re-enable interrupts. */
2853 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2856 sc->rxcycles = count;
2859 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2862 case POLL_AND_CHECK_STATUS:
2863 sc->rxcycles = count;
2866 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2868 status = CSR_READ_4(sc, DC_ISR);
2869 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2870 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2874 /* ack what we have */
2875 CSR_WRITE_4(sc, DC_ISR, status);
2877 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2878 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2879 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2881 if (dc_rx_resync(sc))
2884 /* restart transmit unit if necessary */
2885 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2886 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2888 if (status & DC_ISR_TX_UNDERRUN)
2891 if (status & DC_ISR_BUS_ERR) {
2892 if_printf(ifp, "dc_poll: bus error\n");
2899 #endif /* DEVICE_POLLING */
2904 struct dc_softc *sc;
2910 if (sc->suspended) {
2914 ifp = &sc->arpcom.ac_if;
2916 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2919 /* Suppress unwanted interrupts */
2920 if ((ifp->if_flags & IFF_RUNNING) == 0) {
2921 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2926 /* Disable interrupts. */
2927 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2929 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
2930 status != 0xFFFFFFFF) {
2932 CSR_WRITE_4(sc, DC_ISR, status);
2934 if (status & DC_ISR_RX_OK) {
2936 curpkts = ifp->if_ipackets;
2938 if (curpkts == ifp->if_ipackets) {
2939 while(dc_rx_resync(sc))
2944 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2947 if (status & DC_ISR_TX_IDLE) {
2949 if (sc->dc_cdata.dc_tx_cnt) {
2950 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2951 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2955 if (status & DC_ISR_TX_UNDERRUN)
2958 if ((status & DC_ISR_RX_WATDOGTIMEO)
2959 || (status & DC_ISR_RX_NOBUF)) {
2961 curpkts = ifp->if_ipackets;
2963 if (curpkts == ifp->if_ipackets) {
2964 while(dc_rx_resync(sc))
2969 if (status & DC_ISR_BUS_ERR) {
2975 /* Re-enable interrupts. */
2976 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2978 if (!ifq_is_empty(&ifp->if_snd))
2983 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2984 * pointers to the fragment pointers.
2987 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
2989 struct dc_desc *f = NULL;
2991 int frag, cur, cnt = 0;
2994 * Start packing the mbufs in this chain into
2995 * the fragment pointers. Stop when we run out
2996 * of fragments or hit the end of the mbuf chain.
2999 cur = frag = *txidx;
3001 for (m = m_head; m != NULL; m = m->m_next) {
3002 if (m->m_len != 0) {
3003 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
3004 if (*txidx != sc->dc_cdata.dc_tx_prod &&
3005 frag == (DC_TX_LIST_CNT - 1))
3008 if ((DC_TX_LIST_CNT -
3009 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3012 f = &sc->dc_ldata->dc_tx_list[frag];
3013 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
3016 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
3018 f->dc_status = DC_TXSTAT_OWN;
3019 f->dc_data = vtophys(mtod(m, vm_offset_t));
3021 DC_INC(frag, DC_TX_LIST_CNT);
3029 sc->dc_cdata.dc_tx_cnt += cnt;
3030 sc->dc_cdata.dc_tx_chain[cur] = m_head;
3031 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
3032 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3033 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
3034 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3035 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3036 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3037 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3038 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3045 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3046 * to the mbuf data regions directly in the transmit lists. We also save a
3047 * copy of the pointers since the transmit list fragment pointers are
3048 * physical addresses.
3052 dc_start(struct ifnet *ifp)
3054 struct dc_softc *sc;
3055 struct mbuf *m_head, *m_defragged;
3056 int idx, need_trans;
3061 ifq_purge(&ifp->if_snd);
3065 if (ifp->if_flags & IFF_OACTIVE)
3068 idx = sc->dc_cdata.dc_tx_prod;
3071 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3073 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3077 if ((sc->dc_flags & DC_TX_COALESCE) &&
3078 (m_head->m_next != NULL || (sc->dc_flags & DC_TX_ALIGN))) {
3080 * Check first if coalescing allows us to queue
3081 * the packet. We don't want to loose it if
3082 * the TX queue is full.
3084 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3085 idx != sc->dc_cdata.dc_tx_prod &&
3086 idx == (DC_TX_LIST_CNT - 1)) {
3087 ifp->if_flags |= IFF_OACTIVE;
3088 ifq_prepend(&ifp->if_snd, m_head);
3091 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) {
3092 ifp->if_flags |= IFF_OACTIVE;
3093 ifq_prepend(&ifp->if_snd, m_head);
3097 /* only coalesce if have >1 mbufs */
3098 m_defragged = m_defrag(m_head, MB_DONTWAIT);
3099 if (m_defragged == NULL) {
3100 ifp->if_flags |= IFF_OACTIVE;
3101 ifq_prepend(&ifp->if_snd, m_head);
3104 m_head = m_defragged;
3107 if (dc_encap(sc, m_head, &idx)) {
3110 * Throw away the original packet if the
3111 * defragged packet could not be encapsulated,
3112 * as well as the defragged packet.
3116 ifq_prepend(&ifp->if_snd, m_head);
3118 ifp->if_flags |= IFF_OACTIVE;
3125 * If there's a BPF listener, bounce a copy of this frame
3128 BPF_MTAP(ifp, m_head);
3130 if (sc->dc_flags & DC_TX_ONE) {
3131 ifp->if_flags |= IFF_OACTIVE;
3140 sc->dc_cdata.dc_tx_prod = idx;
3141 if (!(sc->dc_flags & DC_TX_POLL))
3142 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3145 * Set a timeout in case the chip goes out to lunch.
3153 struct dc_softc *sc = xsc;
3154 struct ifnet *ifp = &sc->arpcom.ac_if;
3155 struct mii_data *mii;
3157 mii = device_get_softc(sc->dc_miibus);
3160 * Cancel pending I/O and free all RX/TX buffers.
3166 * Set cache alignment and burst length.
3168 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3169 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3171 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3173 * Evenly share the bus between receive and transmit process.
3175 if (DC_IS_INTEL(sc))
3176 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3177 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3178 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3180 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3182 if (sc->dc_flags & DC_TX_POLL)
3183 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3184 switch(sc->dc_cachesize) {
3186 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3189 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3192 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3196 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3200 if (sc->dc_flags & DC_TX_STORENFWD)
3201 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3203 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3204 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3206 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3207 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3211 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3212 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3214 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3216 * The app notes for the 98713 and 98715A say that
3217 * in order to have the chips operate properly, a magic
3218 * number must be written to CSR16. Macronix does not
3219 * document the meaning of these bits so there's no way
3220 * to know exactly what they do. The 98713 has a magic
3221 * number all its own; the rest all use a different one.
3223 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3224 if (sc->dc_type == DC_TYPE_98713)
3225 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3227 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3230 if (DC_IS_XIRCOM(sc)) {
3232 * Setup General Purpose Port mode and data so the tulip
3233 * can talk to the MII.
3235 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3236 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3238 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3239 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3243 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3244 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3246 /* Init circular RX list. */
3247 if (dc_list_rx_init(sc) == ENOBUFS) {
3248 if_printf(ifp, "initialization failed: no "
3249 "memory for rx buffers\n");
3255 * Init tx descriptors.
3257 dc_list_tx_init(sc);
3260 * Load the address of the RX list.
3262 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3263 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3266 * Enable interrupts.
3268 #ifdef DEVICE_POLLING
3270 * ... but only if we are not polling, and make sure they are off in
3271 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3274 if (ifp->if_flags & IFF_POLLING)
3275 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3278 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3279 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3281 /* Enable transmitter. */
3282 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3285 * If this is an Intel 21143 and we're not using the
3286 * MII port, program the LED control pins so we get
3287 * link and activity indications.
3289 if (sc->dc_flags & DC_TULIP_LEDS) {
3290 CSR_WRITE_4(sc, DC_WATCHDOG,
3291 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3292 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3296 * Set IFF_RUNNING here to keep the assertion in dc_setfilt()
3299 ifp->if_flags |= IFF_RUNNING;
3300 ifp->if_flags &= ~IFF_OACTIVE;
3303 * Load the RX/multicast filter. We do this sort of late
3304 * because the filter programming scheme on the 21143 and
3305 * some clones requires DMAing a setup frame via the TX
3306 * engine, and we need the transmitter enabled for that.
3310 /* Enable receiver. */
3311 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3312 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3315 dc_setcfg(sc, sc->dc_if_media);
3317 /* Don't start the ticker if this is a homePNA link. */
3318 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3321 if (sc->dc_flags & DC_21143_NWAY)
3322 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc);
3324 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
3329 * Set media options.
3332 dc_ifmedia_upd(struct ifnet *ifp)
3334 struct dc_softc *sc;
3335 struct mii_data *mii;
3336 struct ifmedia *ifm;
3339 mii = device_get_softc(sc->dc_miibus);
3341 ifm = &mii->mii_media;
3343 if (DC_IS_DAVICOM(sc) &&
3344 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3345 dc_setcfg(sc, ifm->ifm_media);
3353 * Report current media status.
3356 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3358 struct dc_softc *sc;
3359 struct mii_data *mii;
3360 struct ifmedia *ifm;
3363 mii = device_get_softc(sc->dc_miibus);
3365 ifm = &mii->mii_media;
3366 if (DC_IS_DAVICOM(sc)) {
3367 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3368 ifmr->ifm_active = ifm->ifm_media;
3369 ifmr->ifm_status = 0;
3373 ifmr->ifm_active = mii->mii_media_active;
3374 ifmr->ifm_status = mii->mii_media_status;
3380 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3382 struct dc_softc *sc = ifp->if_softc;
3383 struct ifreq *ifr = (struct ifreq *) data;
3384 struct mii_data *mii;
3389 if (ifp->if_flags & IFF_UP) {
3390 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3391 (IFF_PROMISC | IFF_ALLMULTI);
3392 if (ifp->if_flags & IFF_RUNNING) {
3396 sc->dc_txthresh = 0;
3400 if (ifp->if_flags & IFF_RUNNING)
3403 sc->dc_if_flags = ifp->if_flags;
3407 if (ifp->if_flags & IFF_RUNNING)
3412 mii = device_get_softc(sc->dc_miibus);
3413 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3416 error = ether_ioctl(ifp, command, data);
3424 dc_watchdog(struct ifnet *ifp)
3426 struct dc_softc *sc;
3431 if_printf(ifp, "watchdog timeout\n");
3437 if (!ifq_is_empty(&ifp->if_snd))
3442 * Stop the adapter and free any mbufs allocated to the
3446 dc_stop(struct dc_softc *sc)
3451 ifp = &sc->arpcom.ac_if;
3454 callout_stop(&sc->dc_stat_timer);
3456 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3458 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3459 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3460 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3461 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3465 * Free data in the RX lists.
3467 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3468 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3469 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3470 sc->dc_cdata.dc_rx_chain[i] = NULL;
3473 bzero((char *)&sc->dc_ldata->dc_rx_list,
3474 sizeof(sc->dc_ldata->dc_rx_list));
3477 * Free the TX list buffers.
3479 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3480 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3481 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl &
3483 !(sc->dc_ldata->dc_tx_list[i].dc_ctl &
3484 DC_TXCTL_LASTFRAG)) {
3485 sc->dc_cdata.dc_tx_chain[i] = NULL;
3488 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3489 sc->dc_cdata.dc_tx_chain[i] = NULL;
3492 bzero((char *)&sc->dc_ldata->dc_tx_list,
3493 sizeof(sc->dc_ldata->dc_tx_list));
3497 * Stop all chip I/O so that the kernel's probe routines don't
3498 * get confused by errant DMAs when rebooting.
3501 dc_shutdown(device_t dev)
3503 struct dc_softc *sc;
3506 sc = device_get_softc(dev);
3507 ifp = &sc->arpcom.ac_if;
3508 lwkt_serialize_enter(ifp->if_serializer);
3512 lwkt_serialize_exit(ifp->if_serializer);
3516 * Device suspend routine. Stop the interface and save some PCI
3517 * settings in case the BIOS doesn't restore them properly on
3521 dc_suspend(device_t dev)
3523 struct dc_softc *sc = device_get_softc(dev);
3524 struct ifnet *ifp = &sc->arpcom.ac_if;
3526 lwkt_serialize_enter(ifp->if_serializer);
3529 for (i = 0; i < 5; i++)
3530 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3531 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3532 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3533 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3534 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3538 lwkt_serialize_exit(ifp->if_serializer);
3543 * Device resume routine. Restore some PCI settings in case the BIOS
3544 * doesn't, re-enable busmastering, and restart the interface if
3548 dc_resume(device_t dev)
3550 struct dc_softc *sc = device_get_softc(dev);
3551 struct ifnet *ifp = &sc->arpcom.ac_if;
3554 lwkt_serialize_enter(ifp->if_serializer);
3557 /* better way to do this? */
3558 for (i = 0; i < 5; i++)
3559 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3560 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3561 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3562 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3563 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3565 /* reenable busmastering */
3566 pci_enable_busmaster(dev);
3567 pci_enable_io(dev, DC_RES);
3569 /* reinitialize interface if necessary */
3570 if (ifp->if_flags & IFF_UP)
3574 lwkt_serialize_exit(ifp->if_serializer);
3580 dc_mchash_xircom(struct dc_softc *sc, const uint8_t *addr)
3584 /* Compute CRC for the address value. */
3585 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
3587 if ((crc & 0x180) == 0x180)
3588 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
3590 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + (12 << 4));