2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #define CTLFLAG_RWTUN CTLFLAG_RW
36 * Driver for the Atheros Wireless LAN controller.
38 * This software is derived from work of Atsushi Onoe; his contribution
39 * is greatly appreciated.
45 * This is needed for register operations which are performed
46 * by the driver - eg, calls to ath_hal_gettsf32().
48 * It's also required for any AH_DEBUG checks in here, eg the
49 * module dependencies.
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysctl.h>
58 #include <sys/malloc.h>
60 #include <sys/mutex.h>
61 #include <sys/kernel.h>
62 #include <sys/socket.h>
63 #include <sys/sockio.h>
64 #include <sys/errno.h>
65 #include <sys/callout.h>
67 #include <sys/endian.h>
68 #include <sys/kthread.h>
69 #include <sys/taskqueue.h>
71 #include <sys/module.h>
75 #include <net/if_var.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/if_types.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_llc.h>
82 #include <net/ifq_var.h>
84 #include <netproto/802_11/ieee80211_var.h>
85 #include <netproto/802_11/ieee80211_regdomain.h>
86 #ifdef IEEE80211_SUPPORT_SUPERG
87 #include <netproto/802_11/ieee80211_superg.h>
89 #ifdef IEEE80211_SUPPORT_TDMA
90 #include <netproto/802_11/ieee80211_tdma.h>
96 #include <netinet/in.h>
97 #include <netinet/if_ether.h>
100 #include <dev/netif/ath/ath/if_athvar.h>
101 #include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */
102 #include <dev/netif/ath/ath_hal/ah_diagcodes.h>
104 #include <dev/netif/ath/ath/if_ath_debug.h>
105 #include <dev/netif/ath/ath/if_ath_misc.h>
106 #include <dev/netif/ath/ath/if_ath_tsf.h>
107 #include <dev/netif/ath/ath/if_ath_tx.h>
108 #include <dev/netif/ath/ath/if_ath_sysctl.h>
109 #include <dev/netif/ath/ath/if_ath_led.h>
110 #include <dev/netif/ath/ath/if_ath_keycache.h>
111 #include <dev/netif/ath/ath/if_ath_rx.h>
112 #include <dev/netif/ath/ath/if_ath_rx_edma.h>
113 #include <dev/netif/ath/ath/if_ath_tx_edma.h>
114 #include <dev/netif/ath/ath/if_ath_beacon.h>
115 #include <dev/netif/ath/ath/if_ath_btcoex.h>
116 #include <dev/netif/ath/ath/if_ath_spectral.h>
117 #include <dev/netif/ath/ath/if_ath_lna_div.h>
118 #include <dev/netif/ath/ath/if_athdfs.h>
121 #include <dev/netif/ath/ath/ath_tx99/ath_tx99.h>
125 #include <dev/netif/ath/ath/if_ath_alq.h>
129 * Only enable this if you're working on PS-POLL support.
134 * ATH_BCBUF determines the number of vap's that can transmit
135 * beacons and also (currently) the number of vap's that can
136 * have unique mac addresses/bssid. When staggering beacons
137 * 4 is probably a good max as otherwise the beacons become
138 * very closely spaced and there is limited time for cab q traffic
139 * to go out. You can burst beacons instead but that is not good
140 * for stations in power save and at some point you really want
141 * another radio (and channel).
143 * The limit on the number of mac addresses is tied to our use of
144 * the U/L bit and tracking addresses in a byte; it would be
145 * worthwhile to allow more for applications like proxy sta.
147 CTASSERT(ATH_BCBUF <= 8);
149 static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
150 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
151 const uint8_t [IEEE80211_ADDR_LEN],
152 const uint8_t [IEEE80211_ADDR_LEN]);
153 static void ath_vap_delete(struct ieee80211vap *);
154 static void ath_init(void *);
155 static void ath_stop_locked(struct ifnet *);
156 static void ath_stop(struct ifnet *);
157 static int ath_reset_vap(struct ieee80211vap *, u_long);
158 static int ath_transmit(struct ifnet *ifp, struct mbuf *m);
159 #if !defined(__DragonFly__)
160 static void ath_qflush(struct ifnet *ifp);
162 static int ath_media_change(struct ifnet *);
163 static void ath_watchdog(void *);
164 #if defined(__DragonFly__)
165 static int ath_ioctl(struct ifnet *, u_long, caddr_t, struct ucred * __unused);
167 static int ath_ioctl(struct ifnet *, u_long, caddr_t);
169 static void ath_fatal_proc(void *, int);
170 static void ath_bmiss_vap(struct ieee80211vap *);
171 static void ath_bmiss_proc(void *, int);
172 static void ath_key_update_begin(struct ieee80211vap *);
173 static void ath_key_update_end(struct ieee80211vap *);
174 static void ath_update_mcast_hw(struct ath_softc *);
175 static void ath_update_mcast(struct ifnet *);
176 static void ath_update_promisc(struct ifnet *);
177 static void ath_updateslot(struct ifnet *);
178 static void ath_bstuck_proc(void *, int);
179 static void ath_reset_proc(void *, int);
180 static int ath_desc_alloc(struct ath_softc *);
181 static void ath_desc_free(struct ath_softc *);
182 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *,
183 const uint8_t [IEEE80211_ADDR_LEN]);
184 static void ath_node_cleanup(struct ieee80211_node *);
185 static void ath_node_free(struct ieee80211_node *);
186 static void ath_node_getsignal(const struct ieee80211_node *,
188 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
189 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
190 static int ath_tx_setup(struct ath_softc *, int, int);
191 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
192 static void ath_tx_cleanup(struct ath_softc *);
193 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq,
195 static void ath_tx_proc_q0(void *, int);
196 static void ath_tx_proc_q0123(void *, int);
197 static void ath_tx_proc(void *, int);
198 static void ath_txq_sched_tasklet(void *, int);
199 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
200 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
201 static void ath_scan_start(struct ieee80211com *);
202 static void ath_scan_end(struct ieee80211com *);
203 static void ath_set_channel(struct ieee80211com *);
204 #ifdef ATH_ENABLE_11N
205 static void ath_update_chw(struct ieee80211com *);
206 #endif /* ATH_ENABLE_11N */
207 static void ath_calibrate(void *);
208 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
209 static void ath_setup_stationkey(struct ieee80211_node *);
210 static void ath_newassoc(struct ieee80211_node *, int);
211 static int ath_setregdomain(struct ieee80211com *,
212 struct ieee80211_regdomain *, int,
213 struct ieee80211_channel []);
214 static void ath_getradiocaps(struct ieee80211com *, int, int *,
215 struct ieee80211_channel []);
216 static int ath_getchannels(struct ath_softc *);
218 static int ath_rate_setup(struct ath_softc *, u_int mode);
219 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
221 static void ath_announce(struct ath_softc *);
223 static void ath_dfs_tasklet(void *, int);
224 static void ath_node_powersave(struct ieee80211_node *, int);
225 static int ath_node_set_tim(struct ieee80211_node *, int);
226 static void ath_node_recv_pspoll(struct ieee80211_node *, struct mbuf *);
228 #if defined(__DragonFly__)
229 static void ath_start(struct ifnet *ifp, struct ifaltq_subque *ifsq);
232 #ifdef IEEE80211_SUPPORT_TDMA
233 #include <dev/netif/ath/ath/if_ath_tdma.h>
236 SYSCTL_DECL(_hw_ath);
238 /* XXX validate sysctl values */
239 static int ath_longcalinterval = 30; /* long cals every 30 secs */
240 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval,
241 0, "long chip calibration interval (secs)");
242 static int ath_shortcalinterval = 100; /* short cals every 100 ms */
243 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval,
244 0, "short chip calibration interval (msecs)");
245 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */
246 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval,
247 0, "reset chip calibration results (secs)");
248 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */
249 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval,
250 0, "ANI calibration (msecs)");
252 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
253 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RWTUN, &ath_rxbuf,
254 0, "rx buffers allocated");
255 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
257 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
258 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RWTUN, &ath_txbuf,
259 0, "tx buffers allocated");
260 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
262 int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */
263 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RWTUN, &ath_txbuf_mgmt,
264 0, "tx (mgmt) buffers allocated");
265 TUNABLE_INT("hw.ath.txbuf_mgmt", &ath_txbuf_mgmt);
267 int ath_bstuck_threshold = 4; /* max missed beacons */
268 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold,
269 0, "max missed beacon xmits before chip reset");
271 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
274 ath_legacy_attach_comp_func(struct ath_softc *sc)
278 * Special case certain configurations. Note the
279 * CAB queue is handled by these specially so don't
280 * include them when checking the txq setup mask.
282 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
284 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
287 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
290 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
296 * Set the target power mode.
298 * If this is called during a point in time where
299 * the hardware is being programmed elsewhere, it will
300 * simply store it away and update it when all current
301 * uses of the hardware are completed.
304 _ath_power_setpower(struct ath_softc *sc, int power_state, const char *file, int line)
308 sc->sc_target_powerstate = power_state;
310 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
315 sc->sc_powersave_refcnt);
317 if (sc->sc_powersave_refcnt == 0 &&
318 power_state != sc->sc_cur_powerstate) {
319 sc->sc_cur_powerstate = power_state;
320 ath_hal_setpower(sc->sc_ah, power_state);
323 * If the NIC is force-awake, then set the
324 * self-gen frame state appropriately.
326 * If the nic is in network sleep or full-sleep,
327 * we let the above call leave the self-gen
330 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
331 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
332 ath_hal_setselfgenpower(sc->sc_ah,
333 sc->sc_target_selfgen_state);
339 * Set the current self-generated frames state.
341 * This is separate from the target power mode. The chip may be
342 * awake but the desired state is "sleep", so frames sent to the
343 * destination has PWRMGT=1 in the 802.11 header. The NIC also
344 * needs to know to set PWRMGT=1 in self-generated frames.
347 _ath_power_set_selfgen(struct ath_softc *sc, int power_state, const char *file, int line)
352 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
357 sc->sc_target_selfgen_state);
359 sc->sc_target_selfgen_state = power_state;
362 * If the NIC is force-awake, then set the power state.
363 * Network-state and full-sleep will already transition it to
364 * mark self-gen frames as sleeping - and we can't
365 * guarantee the NIC is awake to program the self-gen frame
368 if (sc->sc_cur_powerstate == HAL_PM_AWAKE) {
369 ath_hal_setselfgenpower(sc->sc_ah, power_state);
374 * Set the hardware power mode and take a reference.
376 * This doesn't update the target power mode in the driver;
377 * it just updates the hardware power state.
379 * XXX it should only ever force the hardware awake; it should
380 * never be called to set it asleep.
383 _ath_power_set_power_state(struct ath_softc *sc, int power_state, const char *file, int line)
387 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
392 sc->sc_powersave_refcnt);
394 sc->sc_powersave_refcnt++;
396 if (power_state != sc->sc_cur_powerstate) {
397 ath_hal_setpower(sc->sc_ah, power_state);
398 sc->sc_cur_powerstate = power_state;
401 * Adjust the self-gen powerstate if appropriate.
403 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
404 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
405 ath_hal_setselfgenpower(sc->sc_ah,
406 sc->sc_target_selfgen_state);
413 * Restore the power save mode to what it once was.
415 * This will decrement the reference counter and once it hits
416 * zero, it'll restore the powersave state.
419 _ath_power_restore_power_state(struct ath_softc *sc, const char *file, int line)
424 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) refcnt=%d, target state=%d\n",
428 sc->sc_powersave_refcnt,
429 sc->sc_target_powerstate);
431 if (sc->sc_powersave_refcnt == 0)
432 device_printf(sc->sc_dev, "%s: refcnt=0?\n", __func__);
434 sc->sc_powersave_refcnt--;
436 if (sc->sc_powersave_refcnt == 0 &&
437 sc->sc_target_powerstate != sc->sc_cur_powerstate) {
438 sc->sc_cur_powerstate = sc->sc_target_powerstate;
439 ath_hal_setpower(sc->sc_ah, sc->sc_target_powerstate);
443 * Adjust the self-gen powerstate if appropriate.
445 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
446 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
447 ath_hal_setselfgenpower(sc->sc_ah,
448 sc->sc_target_selfgen_state);
454 * Configure the initial HAL configuration values based on bus
455 * specific parameters.
457 * Some PCI IDs and other information may need tweaking.
459 * XXX TODO: ath9k and the Atheros HAL only program comm2g_switch_enable
460 * if BT antenna diversity isn't enabled.
462 * So, let's also figure out how to enable BT diversity for AR9485.
465 ath_setup_hal_config(struct ath_softc *sc, HAL_OPS_CONFIG *ah_config)
467 /* XXX TODO: only for PCI devices? */
469 if (sc->sc_pci_devinfo & (ATH_PCI_CUS198 | ATH_PCI_CUS230)) {
470 ah_config->ath_hal_ext_lna_ctl_gpio = 0x200; /* bit 9 */
471 ah_config->ath_hal_ext_atten_margin_cfg = AH_TRUE;
472 ah_config->ath_hal_min_gainidx = AH_TRUE;
473 ah_config->ath_hal_ant_ctrl_comm2g_switch_enable = 0x000bbb88;
474 /* XXX low_rssi_thresh */
475 /* XXX fast_div_bias */
476 device_printf(sc->sc_dev, "configuring for %s\n",
477 (sc->sc_pci_devinfo & ATH_PCI_CUS198) ?
478 "CUS198" : "CUS230");
481 if (sc->sc_pci_devinfo & ATH_PCI_CUS217)
482 device_printf(sc->sc_dev, "CUS217 card detected\n");
484 if (sc->sc_pci_devinfo & ATH_PCI_CUS252)
485 device_printf(sc->sc_dev, "CUS252 card detected\n");
487 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_1ANT)
488 device_printf(sc->sc_dev, "WB335 1-ANT card detected\n");
490 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_2ANT)
491 device_printf(sc->sc_dev, "WB335 2-ANT card detected\n");
493 if (sc->sc_pci_devinfo & ATH_PCI_KILLER)
494 device_printf(sc->sc_dev, "Killer Wireless card detected\n");
498 * Some WB335 cards do not support antenna diversity. Since
499 * we use a hardcoded value for AR9565 instead of using the
500 * EEPROM/OTP data, remove the combining feature from
501 * the HW capabilities bitmap.
503 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
504 if (!(sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV))
505 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
508 if (sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV) {
509 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
510 device_printf(sc->sc_dev, "Set BT/WLAN RX diversity capability\n");
514 if (sc->sc_pci_devinfo & ATH_PCI_D3_L1_WAR) {
515 ah_config->ath_hal_pcie_waen = 0x0040473b;
516 device_printf(sc->sc_dev, "Enable WAR for ASPM D3/L1\n");
520 if (sc->sc_pci_devinfo & ATH9K_PCI_NO_PLL_PWRSAVE) {
521 ah->config.no_pll_pwrsave = true;
522 device_printf(sc->sc_dev, "Disable PLL PowerSave\n");
528 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20)
529 #define HAL_MODE_HT40 \
530 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \
531 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)
533 ath_attach(u_int16_t devid, struct ath_softc *sc)
536 struct ieee80211com *ic;
537 struct ath_hal *ah = NULL;
541 uint8_t macaddr[IEEE80211_ADDR_LEN];
542 int rx_chainmask, tx_chainmask;
543 HAL_OPS_CONFIG ah_config;
545 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
547 wlan_serialize_enter();
549 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
551 device_printf(sc->sc_dev, "can not if_alloc()\n");
558 /* set these up early for if_printf use */
559 if_initname(ifp, device_get_name(sc->sc_dev),
560 device_get_unit(sc->sc_dev));
564 * Configure the initial configuration data.
566 * This is stuff that may be needed early during attach
567 * rather than done via configuration calls later.
569 bzero(&ah_config, sizeof(ah_config));
570 ath_setup_hal_config(sc, &ah_config);
572 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,
573 sc->sc_eepromdata, &ah_config, &status);
575 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
581 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
583 sc->sc_debug = ath_debug;
587 * Setup the DMA/EDMA functions based on the current
590 * This is required before the descriptors are allocated.
592 if (ath_hal_hasedma(sc->sc_ah)) {
594 ath_recv_setup_edma(sc);
595 ath_xmit_setup_edma(sc);
597 ath_recv_setup_legacy(sc);
598 ath_xmit_setup_legacy(sc);
601 if (ath_hal_hasmybeacon(sc->sc_ah)) {
602 sc->sc_do_mybeacon = 1;
606 * Check if the MAC has multi-rate retry support.
607 * We do this by trying to setup a fake extended
608 * descriptor. MAC's that don't have support will
609 * return false w/o doing anything. MAC's that do
610 * support it will return true w/o doing anything.
612 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
615 * Check if the device has hardware counters for PHY
616 * errors. If so we need to enable the MIB interrupt
617 * so we can act on stat triggers.
619 if (ath_hal_hwphycounters(ah))
623 * Get the hardware key cache size.
625 sc->sc_keymax = ath_hal_keycachesize(ah);
626 if (sc->sc_keymax > ATH_KEYMAX) {
627 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
628 ATH_KEYMAX, sc->sc_keymax);
629 sc->sc_keymax = ATH_KEYMAX;
632 * Reset the key cache since some parts do not
633 * reset the contents on initial power up.
635 for (i = 0; i < sc->sc_keymax; i++)
636 ath_hal_keyreset(ah, i);
639 * Collect the default channel list.
641 error = ath_getchannels(sc);
646 * Setup rate tables for all potential media types.
648 ath_rate_setup(sc, IEEE80211_MODE_11A);
649 ath_rate_setup(sc, IEEE80211_MODE_11B);
650 ath_rate_setup(sc, IEEE80211_MODE_11G);
651 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
652 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
653 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
654 ath_rate_setup(sc, IEEE80211_MODE_11NA);
655 ath_rate_setup(sc, IEEE80211_MODE_11NG);
656 ath_rate_setup(sc, IEEE80211_MODE_HALF);
657 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
659 /* NB: setup here so ath_rate_update is happy */
660 ath_setcurmode(sc, IEEE80211_MODE_11A);
663 * Allocate TX descriptors and populate the lists.
665 error = ath_desc_alloc(sc);
667 if_printf(ifp, "failed to allocate TX descriptors: %d\n",
671 error = ath_txdma_setup(sc);
673 if_printf(ifp, "failed to allocate TX descriptors: %d\n",
679 * Allocate RX descriptors and populate the lists.
681 error = ath_rxdma_setup(sc);
683 if_printf(ifp, "failed to allocate RX descriptors: %d\n",
688 callout_init_lk(&sc->sc_cal_ch, &sc->sc_mtx);
689 callout_init_lk(&sc->sc_wd_ch, &sc->sc_mtx);
691 ATH_TXBUF_LOCK_INIT(sc);
693 sc->sc_tq = taskqueue_create("ath_taskq", M_INTWAIT,
694 taskqueue_thread_enqueue, &sc->sc_tq);
695 taskqueue_start_threads(&sc->sc_tq, 1, TDPRI_KERN_DAEMON, -1,
696 "%s taskq", ifp->if_xname);
698 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc);
699 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
700 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
701 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc);
702 TASK_INIT(&sc->sc_txqtask, 0, ath_txq_sched_tasklet, sc);
703 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
706 * Allocate hardware transmit queues: one queue for
707 * beacon frames and one data queue for each QoS
708 * priority. Note that the hal handles resetting
709 * these queues at the needed time.
713 sc->sc_bhalq = ath_beaconq_setup(sc);
714 if (sc->sc_bhalq == (u_int) -1) {
715 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
719 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
720 if (sc->sc_cabq == NULL) {
721 if_printf(ifp, "unable to setup CAB xmit queue!\n");
725 /* NB: insure BK queue is the lowest priority h/w queue */
726 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
727 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
728 ieee80211_wme_acnames[WME_AC_BK]);
732 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
733 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
734 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
736 * Not enough hardware tx queues to properly do WME;
737 * just punt and assign them all to the same h/w queue.
738 * We could do a better job of this if, for example,
739 * we allocate queues when we switch from station to
742 if (sc->sc_ac2q[WME_AC_VI] != NULL)
743 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
744 if (sc->sc_ac2q[WME_AC_BE] != NULL)
745 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
746 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
747 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
748 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
752 * Attach the TX completion function.
754 * The non-EDMA chips may have some special case optimisations;
755 * this method gives everyone a chance to attach cleanly.
757 sc->sc_tx.xmit_attach_comp_func(sc);
760 * Setup rate control. Some rate control modules
761 * call back to change the anntena state so expose
762 * the necessary entry points.
763 * XXX maybe belongs in struct ath_ratectrl?
765 sc->sc_setdefantenna = ath_setdefantenna;
766 sc->sc_rc = ath_rate_attach(sc);
767 if (sc->sc_rc == NULL) {
772 /* Attach DFS module */
773 if (! ath_dfs_attach(sc)) {
774 device_printf(sc->sc_dev,
775 "%s: unable to attach DFS\n", __func__);
780 /* Attach spectral module */
781 if (ath_spectral_attach(sc) < 0) {
782 device_printf(sc->sc_dev,
783 "%s: unable to attach spectral\n", __func__);
788 /* Attach bluetooth coexistence module */
789 if (ath_btcoex_attach(sc) < 0) {
790 device_printf(sc->sc_dev,
791 "%s: unable to attach bluetooth coexistence\n", __func__);
796 /* Attach LNA diversity module */
797 if (ath_lna_div_attach(sc) < 0) {
798 device_printf(sc->sc_dev,
799 "%s: unable to attach LNA diversity\n", __func__);
804 /* Start DFS processing tasklet */
805 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
807 /* Configure LED state */
810 sc->sc_ledon = 0; /* low true */
811 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
812 callout_init_mp(&sc->sc_ledtimer);
815 * Don't setup hardware-based blinking.
817 * Although some NICs may have this configured in the
818 * default reset register values, the user may wish
819 * to alter which pins have which function.
821 * The reference driver attaches the MAC network LED to GPIO1 and
822 * the MAC power LED to GPIO2. However, the DWA-552 cardbus
823 * NIC has these reversed.
825 sc->sc_hardled = (1 == 0);
826 sc->sc_led_net_pin = -1;
827 sc->sc_led_pwr_pin = -1;
829 * Auto-enable soft led processing for IBM cards and for
830 * 5211 minipci cards. Users can also manually enable/disable
831 * support with a sysctl.
833 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
835 ath_hal_setledstate(ah, HAL_LED_INIT);
838 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
839 #if defined(__DragonFly__)
840 ifp->if_start = ath_start;
842 ifp->if_transmit = ath_transmit;
843 ifp->if_qflush = ath_qflush;
845 ifp->if_ioctl = ath_ioctl;
846 ifp->if_init = ath_init;
847 #if defined(__DragonFly__)
848 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
850 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
851 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
852 IFQ_SET_READY(&ifp->if_snd);
856 /* XXX not right but it's not used anywhere important */
857 ic->ic_phytype = IEEE80211_T_OFDM;
858 ic->ic_opmode = IEEE80211_M_STA;
860 IEEE80211_C_STA /* station mode */
861 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
862 | IEEE80211_C_HOSTAP /* hostap mode */
863 | IEEE80211_C_MONITOR /* monitor mode */
864 | IEEE80211_C_AHDEMO /* adhoc demo mode */
865 | IEEE80211_C_WDS /* 4-address traffic works */
866 | IEEE80211_C_MBSS /* mesh point link mode */
867 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
868 | IEEE80211_C_SHSLOT /* short slot time supported */
869 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
870 #ifndef ATH_ENABLE_11N
871 | IEEE80211_C_BGSCAN /* capable of bg scanning */
873 | IEEE80211_C_TXFRAG /* handle tx frags */
874 #ifdef ATH_ENABLE_DFS
875 | IEEE80211_C_DFS /* Enable radar detection */
877 | IEEE80211_C_PMGT /* Station side power mgmt */
878 | IEEE80211_C_SWSLEEP
881 * Query the hal to figure out h/w crypto support.
883 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
884 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
885 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
886 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
887 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
888 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
889 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
890 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
891 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
892 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
894 * Check if h/w does the MIC and/or whether the
895 * separate key cache entries are required to
896 * handle both tx+rx MIC keys.
898 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
899 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
901 * If the h/w supports storing tx+rx MIC keys
902 * in one cache slot automatically enable use.
904 if (ath_hal_hastkipsplit(ah) ||
905 !ath_hal_settkipsplit(ah, AH_FALSE))
908 * If the h/w can do TKIP MIC together with WME then
909 * we use it; otherwise we force the MIC to be done
910 * in software by the net80211 layer.
912 if (ath_hal_haswmetkipmic(ah))
913 sc->sc_wmetkipmic = 1;
915 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
917 * Check for multicast key search support.
919 if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
920 !ath_hal_getmcastkeysearch(sc->sc_ah)) {
921 ath_hal_setmcastkeysearch(sc->sc_ah, 1);
923 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
925 * Mark key cache slots associated with global keys
926 * as in use. If we knew TKIP was not to be used we
927 * could leave the +32, +64, and +32+64 slots free.
929 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
930 setbit(sc->sc_keymap, i);
931 setbit(sc->sc_keymap, i+64);
932 if (sc->sc_splitmic) {
933 setbit(sc->sc_keymap, i+32);
934 setbit(sc->sc_keymap, i+32+64);
938 * TPC support can be done either with a global cap or
939 * per-packet support. The latter is not available on
940 * all parts. We're a bit pedantic here as all parts
941 * support a global cap.
943 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
944 ic->ic_caps |= IEEE80211_C_TXPMGT;
947 * Mark WME capability only if we have sufficient
948 * hardware queues to do proper priority scheduling.
950 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
951 ic->ic_caps |= IEEE80211_C_WME;
953 * Check for misc other capabilities.
955 if (ath_hal_hasbursting(ah))
956 ic->ic_caps |= IEEE80211_C_BURST;
957 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
958 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
959 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
960 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah);
961 sc->sc_rxtsf32 = ath_hal_has_long_rxdesc_tsf(ah);
962 sc->sc_hasenforcetxop = ath_hal_hasenforcetxop(ah);
963 sc->sc_rx_lnamixer = ath_hal_hasrxlnamixer(ah);
964 sc->sc_hasdivcomb = ath_hal_hasdivantcomb(ah);
966 if (ath_hal_hasfastframes(ah))
967 ic->ic_caps |= IEEE80211_C_FF;
968 wmodes = ath_hal_getwirelessmodes(ah);
969 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO))
970 ic->ic_caps |= IEEE80211_C_TURBOP;
971 #ifdef IEEE80211_SUPPORT_TDMA
972 if (ath_hal_macversion(ah) > 0x78) {
973 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */
974 ic->ic_tdma_update = ath_tdma_update;
979 * TODO: enforce that at least this many frames are available
980 * in the txbuf list before allowing data frames (raw or
981 * otherwise) to be transmitted.
983 sc->sc_txq_data_minfree = 10;
985 * Leave this as default to maintain legacy behaviour.
986 * Shortening the cabq/mcastq may end up causing some
987 * undesirable behaviour.
989 sc->sc_txq_mcastq_maxdepth = ath_txbuf;
992 * How deep can the node software TX queue get whilst it's asleep.
994 sc->sc_txq_node_psq_maxdepth = 16;
997 * Default the maximum queue depth for a given node
998 * to 1/4'th the TX buffers, or 64, whichever
1001 sc->sc_txq_node_maxdepth = MAX(64, ath_txbuf / 4);
1003 /* Enable CABQ by default */
1004 sc->sc_cabq_enable = 1;
1007 * Allow the TX and RX chainmasks to be overridden by
1008 * environment variables and/or device.hints.
1010 * This must be done early - before the hardware is
1011 * calibrated or before the 802.11n stream calculation
1014 if (resource_int_value(device_get_name(sc->sc_dev),
1015 device_get_unit(sc->sc_dev), "rx_chainmask",
1016 &rx_chainmask) == 0) {
1017 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n",
1019 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask);
1021 if (resource_int_value(device_get_name(sc->sc_dev),
1022 device_get_unit(sc->sc_dev), "tx_chainmask",
1023 &tx_chainmask) == 0) {
1024 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n",
1026 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask);
1030 * Query the TX/RX chainmask configuration.
1032 * This is only relevant for 11n devices.
1034 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);
1035 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);
1038 * Disable MRR with protected frames by default.
1039 * Only 802.11n series NICs can handle this.
1041 sc->sc_mrrprot = 0; /* XXX should be a capability */
1044 * Query the enterprise mode information the HAL.
1046 if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0,
1047 &sc->sc_ent_cfg) == HAL_OK)
1050 #ifdef ATH_ENABLE_11N
1052 * Query HT capabilities
1054 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK &&
1055 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) {
1058 device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
1060 sc->sc_mrrprot = 1; /* XXX should be a capability */
1062 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */
1063 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */
1064 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */
1065 | IEEE80211_HTCAP_MAXAMSDU_3839
1066 /* max A-MSDU length */
1067 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */
1071 * Enable short-GI for HT20 only if the hardware
1072 * advertises support.
1073 * Notably, anything earlier than the AR9287 doesn't.
1075 if ((ath_hal_getcapability(ah,
1076 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) &&
1077 (wmodes & HAL_MODE_HT20)) {
1078 device_printf(sc->sc_dev,
1079 "[HT] enabling short-GI in 20MHz mode\n");
1080 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20;
1083 if (wmodes & HAL_MODE_HT40)
1084 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40
1085 | IEEE80211_HTCAP_SHORTGI40;
1088 * TX/RX streams need to be taken into account when
1089 * negotiating which MCS rates it'll receive and
1090 * what MCS rates are available for TX.
1092 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs);
1093 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs);
1094 ic->ic_txstream = txs;
1095 ic->ic_rxstream = rxs;
1098 * Setup TX and RX STBC based on what the HAL allows and
1099 * the currently configured chainmask set.
1100 * Ie - don't enable STBC TX if only one chain is enabled.
1101 * STBC RX is fine on a single RX chain; it just won't
1102 * provide any real benefit.
1104 if (ath_hal_getcapability(ah, HAL_CAP_RX_STBC, 0,
1107 device_printf(sc->sc_dev,
1108 "[HT] 1 stream STBC receive enabled\n");
1109 ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_1STREAM;
1111 if (txs > 1 && ath_hal_getcapability(ah, HAL_CAP_TX_STBC, 0,
1114 device_printf(sc->sc_dev,
1115 "[HT] 1 stream STBC transmit enabled\n");
1116 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC;
1119 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1,
1120 &sc->sc_rts_aggr_limit);
1121 if (sc->sc_rts_aggr_limit != (64 * 1024))
1122 device_printf(sc->sc_dev,
1123 "[HT] RTS aggregates limited to %d KiB\n",
1124 sc->sc_rts_aggr_limit / 1024);
1126 device_printf(sc->sc_dev,
1127 "[HT] %d RX streams; %d TX streams\n", rxs, txs);
1132 * Initial aggregation settings.
1134 sc->sc_hwq_limit_aggr = ATH_AGGR_MIN_QDEPTH;
1135 sc->sc_hwq_limit_nonaggr = ATH_NONAGGR_MIN_QDEPTH;
1136 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
1137 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
1138 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE;
1139 sc->sc_delim_min_pad = 0;
1142 * Check if the hardware requires PCI register serialisation.
1143 * Some of the Owl based MACs require this.
1146 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
1147 0, NULL) == HAL_OK) {
1148 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
1149 device_printf(sc->sc_dev,
1150 "Enabling register serialisation\n");
1154 * Initialise the deferred completed RX buffer list.
1156 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
1157 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
1160 * Indicate we need the 802.11 header padded to a
1161 * 32-bit boundary for 4-address and QoS frames.
1163 ic->ic_flags |= IEEE80211_F_DATAPAD;
1166 * Query the hal about antenna support.
1168 sc->sc_defant = ath_hal_getdefantenna(ah);
1171 * Not all chips have the VEOL support we want to
1172 * use with IBSS beacons; check here for it.
1174 sc->sc_hasveol = ath_hal_hasveol(ah);
1176 /* get mac address from hardware */
1177 ath_hal_getmac(ah, macaddr);
1178 if (sc->sc_hasbmask)
1179 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
1181 /* NB: used to size node table key mapping array */
1182 ic->ic_max_keyix = sc->sc_keymax;
1183 /* Call MI attach routine. */
1184 ieee80211_ifattach(ic, macaddr);
1185 ic->ic_setregdomain = ath_setregdomain;
1186 ic->ic_getradiocaps = ath_getradiocaps;
1187 sc->sc_opmode = HAL_M_STA;
1189 /* override default methods */
1190 ic->ic_newassoc = ath_newassoc;
1191 ic->ic_updateslot = ath_updateslot;
1192 ic->ic_wme.wme_update = ath_wme_update;
1193 ic->ic_vap_create = ath_vap_create;
1194 ic->ic_vap_delete = ath_vap_delete;
1195 ic->ic_raw_xmit = ath_raw_xmit;
1196 ic->ic_update_mcast = ath_update_mcast;
1197 ic->ic_update_promisc = ath_update_promisc;
1198 ic->ic_node_alloc = ath_node_alloc;
1199 sc->sc_node_free = ic->ic_node_free;
1200 ic->ic_node_free = ath_node_free;
1201 sc->sc_node_cleanup = ic->ic_node_cleanup;
1202 ic->ic_node_cleanup = ath_node_cleanup;
1203 ic->ic_node_getsignal = ath_node_getsignal;
1204 ic->ic_scan_start = ath_scan_start;
1205 ic->ic_scan_end = ath_scan_end;
1206 ic->ic_set_channel = ath_set_channel;
1207 #ifdef ATH_ENABLE_11N
1208 /* 802.11n specific - but just override anyway */
1209 sc->sc_addba_request = ic->ic_addba_request;
1210 sc->sc_addba_response = ic->ic_addba_response;
1211 sc->sc_addba_stop = ic->ic_addba_stop;
1212 sc->sc_bar_response = ic->ic_bar_response;
1213 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout;
1215 ic->ic_addba_request = ath_addba_request;
1216 ic->ic_addba_response = ath_addba_response;
1217 ic->ic_addba_response_timeout = ath_addba_response_timeout;
1218 ic->ic_addba_stop = ath_addba_stop;
1219 ic->ic_bar_response = ath_bar_response;
1221 ic->ic_update_chw = ath_update_chw;
1222 #endif /* ATH_ENABLE_11N */
1224 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
1226 * There's one vendor bitmap entry in the RX radiotap
1227 * header; make sure that's taken into account.
1229 ieee80211_radiotap_attachv(ic,
1230 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0,
1231 ATH_TX_RADIOTAP_PRESENT,
1232 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1,
1233 ATH_RX_RADIOTAP_PRESENT);
1236 * No vendor bitmap/extensions are present.
1238 ieee80211_radiotap_attach(ic,
1239 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
1240 ATH_TX_RADIOTAP_PRESENT,
1241 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
1242 ATH_RX_RADIOTAP_PRESENT);
1243 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
1246 * Setup the ALQ logging if required
1248 #ifdef ATH_DEBUG_ALQ
1249 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev));
1250 if_ath_alq_setcfg(&sc->sc_alq,
1251 sc->sc_ah->ah_macVersion,
1252 sc->sc_ah->ah_macRev,
1253 sc->sc_ah->ah_phyRev,
1254 sc->sc_ah->ah_magic);
1258 * Setup dynamic sysctl's now that country code and
1259 * regdomain are available from the hal.
1261 ath_sysctlattach(sc);
1262 ath_sysctl_stats_attach(sc);
1263 ath_sysctl_hal_attach(sc);
1266 ieee80211_announce(ic);
1270 * Put it to sleep for now.
1273 ath_power_setpower(sc, HAL_PM_FULL_SLEEP);
1276 wlan_serialize_exit();
1282 ath_txdma_teardown(sc);
1283 ath_rxdma_teardown(sc);
1289 * To work around scoping issues with CURVNET_SET/CURVNET_RESTORE..
1291 #if !defined(__DragonFly__)
1292 if (ifp != NULL && ifp->if_vnet) {
1293 CURVNET_SET(ifp->if_vnet);
1301 wlan_serialize_exit();
1307 ath_detach(struct ath_softc *sc)
1309 struct ifnet *ifp = sc->sc_ifp;
1311 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1312 __func__, ifp->if_flags);
1315 * NB: the order of these is important:
1316 * o stop the chip so no more interrupts will fire
1317 * o call the 802.11 layer before detaching the hal to
1318 * insure callbacks into the driver to delete global
1319 * key cache entries can be handled
1320 * o free the taskqueue which drains any pending tasks
1321 * o reclaim the tx queue data structures after calling
1322 * the 802.11 layer as we'll get called back to reclaim
1323 * node state and potentially want to use them
1324 * o to cleanup the tx queues the hal is called, so detach
1326 * Other than that, it's straightforward...
1330 * XXX Wake the hardware up first. ath_stop() will still
1331 * wake it up first, but I'd rather do it here just to
1332 * ensure it's awake.
1335 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1336 ath_power_setpower(sc, HAL_PM_AWAKE);
1340 * Stop things cleanly.
1344 wlan_serialize_enter();
1345 ieee80211_ifdetach(ifp->if_l2com);
1346 wlan_serialize_exit();
1347 taskqueue_free(sc->sc_tq);
1348 #ifdef ATH_TX99_DIAG
1349 if (sc->sc_tx99 != NULL)
1350 sc->sc_tx99->detach(sc->sc_tx99);
1352 ath_rate_detach(sc->sc_rc);
1353 #ifdef ATH_DEBUG_ALQ
1354 if_ath_alq_tidyup(&sc->sc_alq);
1356 ath_lna_div_detach(sc);
1357 ath_btcoex_detach(sc);
1358 ath_spectral_detach(sc);
1361 ath_txdma_teardown(sc);
1362 ath_rxdma_teardown(sc);
1364 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
1366 CURVNET_SET(ifp->if_vnet);
1374 * MAC address handling for multiple BSS on the same radio.
1375 * The first vap uses the MAC address from the EEPROM. For
1376 * subsequent vap's we set the U/L bit (bit 1) in the MAC
1377 * address and use the next six bits as an index.
1380 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
1384 if (clone && sc->sc_hasbmask) {
1385 /* NB: we only do this if h/w supports multiple bssid */
1386 for (i = 0; i < 8; i++)
1387 if ((sc->sc_bssidmask & (1<<i)) == 0)
1390 mac[0] |= (i << 2)|0x2;
1393 sc->sc_bssidmask |= 1<<i;
1394 sc->sc_hwbssidmask[0] &= ~mac[0];
1400 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
1402 int i = mac[0] >> 2;
1405 if (i != 0 || --sc->sc_nbssid0 == 0) {
1406 sc->sc_bssidmask &= ~(1<<i);
1407 /* recalculate bssid mask from remaining addresses */
1409 for (i = 1; i < 8; i++)
1410 if (sc->sc_bssidmask & (1<<i))
1411 mask &= ~((i<<2)|0x2);
1412 sc->sc_hwbssidmask[0] |= mask;
1417 * Assign a beacon xmit slot. We try to space out
1418 * assignments so when beacons are staggered the
1419 * traffic coming out of the cab q has maximal time
1420 * to go out before the next beacon is scheduled.
1423 assign_bslot(struct ath_softc *sc)
1428 for (slot = 0; slot < ATH_BCBUF; slot++)
1429 if (sc->sc_bslot[slot] == NULL) {
1430 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
1431 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
1434 /* NB: keep looking for a double slot */
1439 static struct ieee80211vap *
1440 ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1441 enum ieee80211_opmode opmode, int flags,
1442 const uint8_t bssid[IEEE80211_ADDR_LEN],
1443 const uint8_t mac0[IEEE80211_ADDR_LEN])
1445 struct ath_softc *sc = ic->ic_ifp->if_softc;
1446 struct ath_vap *avp;
1447 struct ieee80211vap *vap;
1448 uint8_t mac[IEEE80211_ADDR_LEN];
1449 int needbeacon, error;
1450 enum ieee80211_opmode ic_opmode;
1452 avp = kmalloc(sizeof(struct ath_vap), M_80211_VAP, M_WAITOK | M_ZERO);
1454 IEEE80211_ADDR_COPY(mac, mac0);
1457 ic_opmode = opmode; /* default to opmode of new vap */
1459 case IEEE80211_M_STA:
1460 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
1461 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
1466 * With multiple vaps we must fall back
1467 * to s/w beacon miss handling.
1469 flags |= IEEE80211_CLONE_NOBEACONS;
1471 if (flags & IEEE80211_CLONE_NOBEACONS) {
1473 * Station mode w/o beacons are implemented w/ AP mode.
1475 ic_opmode = IEEE80211_M_HOSTAP;
1478 case IEEE80211_M_IBSS:
1479 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
1480 device_printf(sc->sc_dev,
1481 "only 1 ibss vap supported\n");
1486 case IEEE80211_M_AHDEMO:
1487 #ifdef IEEE80211_SUPPORT_TDMA
1488 if (flags & IEEE80211_CLONE_TDMA) {
1489 if (sc->sc_nvaps != 0) {
1490 device_printf(sc->sc_dev,
1491 "only 1 tdma vap supported\n");
1495 flags |= IEEE80211_CLONE_NOBEACONS;
1499 case IEEE80211_M_MONITOR:
1500 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
1502 * Adopt existing mode. Adding a monitor or ahdemo
1503 * vap to an existing configuration is of dubious
1504 * value but should be ok.
1506 /* XXX not right for monitor mode */
1507 ic_opmode = ic->ic_opmode;
1510 case IEEE80211_M_HOSTAP:
1511 case IEEE80211_M_MBSS:
1514 case IEEE80211_M_WDS:
1515 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
1516 device_printf(sc->sc_dev,
1517 "wds not supported in sta mode\n");
1521 * Silently remove any request for a unique
1522 * bssid; WDS vap's always share the local
1525 flags &= ~IEEE80211_CLONE_BSSID;
1526 if (sc->sc_nvaps == 0)
1527 ic_opmode = IEEE80211_M_HOSTAP;
1529 ic_opmode = ic->ic_opmode;
1532 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
1536 * Check that a beacon buffer is available; the code below assumes it.
1538 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) {
1539 device_printf(sc->sc_dev, "no beacon buffer available\n");
1544 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) {
1545 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
1546 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1550 /* XXX can't hold mutex across if_alloc */
1552 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
1556 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
1561 /* h/w crypto support */
1562 vap->iv_key_alloc = ath_key_alloc;
1563 vap->iv_key_delete = ath_key_delete;
1564 vap->iv_key_set = ath_key_set;
1565 vap->iv_key_update_begin = ath_key_update_begin;
1566 vap->iv_key_update_end = ath_key_update_end;
1568 /* override various methods */
1569 avp->av_recv_mgmt = vap->iv_recv_mgmt;
1570 vap->iv_recv_mgmt = ath_recv_mgmt;
1571 vap->iv_reset = ath_reset_vap;
1572 vap->iv_update_beacon = ath_beacon_update;
1573 avp->av_newstate = vap->iv_newstate;
1574 vap->iv_newstate = ath_newstate;
1575 avp->av_bmiss = vap->iv_bmiss;
1576 vap->iv_bmiss = ath_bmiss_vap;
1578 avp->av_node_ps = vap->iv_node_ps;
1579 vap->iv_node_ps = ath_node_powersave;
1581 avp->av_set_tim = vap->iv_set_tim;
1582 vap->iv_set_tim = ath_node_set_tim;
1584 avp->av_recv_pspoll = vap->iv_recv_pspoll;
1585 vap->iv_recv_pspoll = ath_node_recv_pspoll;
1587 /* Set default parameters */
1590 * Anything earlier than some AR9300 series MACs don't
1591 * support a smaller MPDU density.
1593 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8;
1595 * All NICs can handle the maximum size, however
1596 * AR5416 based MACs can only TX aggregates w/ RTS
1597 * protection when the total aggregate size is <= 8k.
1598 * However, for now that's enforced by the TX path.
1600 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1605 * Allocate beacon state and setup the q for buffered
1606 * multicast frames. We know a beacon buffer is
1607 * available because we checked above.
1609 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf);
1610 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list);
1611 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1613 * Assign the vap to a beacon xmit slot. As above
1614 * this cannot fail to find a free one.
1616 avp->av_bslot = assign_bslot(sc);
1617 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1618 ("beacon slot %u not empty", avp->av_bslot));
1619 sc->sc_bslot[avp->av_bslot] = vap;
1622 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1624 * Multple vaps are to transmit beacons and we
1625 * have h/w support for TSF adjusting; enable
1626 * use of staggered beacons.
1628 sc->sc_stagbeacons = 1;
1630 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1633 ic->ic_opmode = ic_opmode;
1634 if (opmode != IEEE80211_M_WDS) {
1636 if (opmode == IEEE80211_M_STA)
1638 if (opmode == IEEE80211_M_MBSS)
1641 switch (ic_opmode) {
1642 case IEEE80211_M_IBSS:
1643 sc->sc_opmode = HAL_M_IBSS;
1645 case IEEE80211_M_STA:
1646 sc->sc_opmode = HAL_M_STA;
1648 case IEEE80211_M_AHDEMO:
1649 #ifdef IEEE80211_SUPPORT_TDMA
1650 if (vap->iv_caps & IEEE80211_C_TDMA) {
1652 /* NB: disable tsf adjust */
1653 sc->sc_stagbeacons = 0;
1656 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1661 case IEEE80211_M_HOSTAP:
1662 case IEEE80211_M_MBSS:
1663 sc->sc_opmode = HAL_M_HOSTAP;
1665 case IEEE80211_M_MONITOR:
1666 sc->sc_opmode = HAL_M_MONITOR;
1669 /* XXX should not happen */
1672 if (sc->sc_hastsfadd) {
1674 * Configure whether or not TSF adjust should be done.
1676 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1678 if (flags & IEEE80211_CLONE_NOBEACONS) {
1680 * Enable s/w beacon miss handling.
1686 /* complete setup */
1687 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
1690 reclaim_address(sc, mac);
1691 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1693 kfree(avp, M_80211_VAP);
1699 ath_vap_delete(struct ieee80211vap *vap)
1701 struct ieee80211com *ic = vap->iv_ic;
1702 struct ifnet *ifp = ic->ic_ifp;
1703 struct ath_softc *sc = ifp->if_softc;
1704 struct ath_hal *ah = sc->sc_ah;
1705 struct ath_vap *avp = ATH_VAP(vap);
1708 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1711 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
1712 if (ifp->if_flags & IFF_RUNNING) {
1714 * Quiesce the hardware while we remove the vap. In
1715 * particular we need to reclaim all references to
1716 * the vap state by any frames pending on the tx queues.
1718 ath_hal_intrset(ah, 0); /* disable interrupts */
1719 /* XXX Do all frames from all vaps/nodes need draining here? */
1720 ath_stoprecv(sc, 1); /* stop recv side */
1721 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */
1724 /* .. leave the hardware awake for now. */
1726 ieee80211_vap_detach(vap);
1729 * XXX Danger Will Robinson! Danger!
1731 * Because ieee80211_vap_detach() can queue a frame (the station
1732 * diassociate message?) after we've drained the TXQ and
1733 * flushed the software TXQ, we will end up with a frame queued
1734 * to a node whose vap is about to be freed.
1736 * To work around this, flush the hardware/software again.
1737 * This may be racy - the ath task may be running and the packet
1738 * may be being scheduled between sw->hw txq. Tsk.
1740 * TODO: figure out why a new node gets allocated somewhere around
1741 * here (after the ath_tx_swq() call; and after an ath_stop_locked()
1745 ath_draintxq(sc, ATH_RESET_DEFAULT);
1749 * Reclaim beacon state. Note this must be done before
1750 * the vap instance is reclaimed as we may have a reference
1751 * to it in the buffer for the beacon frame.
1753 if (avp->av_bcbuf != NULL) {
1754 if (avp->av_bslot != -1) {
1755 sc->sc_bslot[avp->av_bslot] = NULL;
1758 ath_beacon_return(sc, avp->av_bcbuf);
1759 avp->av_bcbuf = NULL;
1760 if (sc->sc_nbcnvaps == 0) {
1761 sc->sc_stagbeacons = 0;
1762 if (sc->sc_hastsfadd)
1763 ath_hal_settsfadjust(sc->sc_ah, 0);
1766 * Reclaim any pending mcast frames for the vap.
1768 ath_tx_draintxq(sc, &avp->av_mcastq);
1771 * Update bookkeeping.
1773 if (vap->iv_opmode == IEEE80211_M_STA) {
1775 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1777 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1778 vap->iv_opmode == IEEE80211_M_MBSS) {
1779 reclaim_address(sc, vap->iv_myaddr);
1780 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1781 if (vap->iv_opmode == IEEE80211_M_MBSS)
1784 if (vap->iv_opmode != IEEE80211_M_WDS)
1786 #ifdef IEEE80211_SUPPORT_TDMA
1787 /* TDMA operation ceases when the last vap is destroyed */
1788 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1793 kfree(avp, M_80211_VAP);
1795 if (ifp->if_flags & IFF_RUNNING) {
1797 * Restart rx+tx machines if still running (RUNNING will
1798 * be reset if we just destroyed the last vap).
1800 if (ath_startrecv(sc) != 0)
1801 if_printf(ifp, "%s: unable to restart recv logic\n",
1803 if (sc->sc_beacons) { /* restart beacons */
1804 #ifdef IEEE80211_SUPPORT_TDMA
1806 ath_tdma_config(sc, NULL);
1809 ath_beacon_config(sc, NULL);
1811 ath_hal_intrset(ah, sc->sc_imask);
1814 /* Ok, let the hardware asleep. */
1815 ath_power_restore_power_state(sc);
1820 ath_suspend(struct ath_softc *sc)
1822 struct ifnet *ifp = sc->sc_ifp;
1823 struct ieee80211com *ic = ifp->if_l2com;
1825 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1826 __func__, ifp->if_flags);
1828 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0;
1830 ieee80211_suspend_all(ic);
1832 * NB: don't worry about putting the chip in low power
1833 * mode; pci will power off our socket on suspend and
1834 * CardBus detaches the device.
1836 * XXX TODO: well, that's great, except for non-cardbus
1841 * XXX This doesn't wait until all pending taskqueue
1842 * items and parallel transmit/receive/other threads
1845 ath_hal_intrset(sc->sc_ah, 0);
1846 taskqueue_block(sc->sc_tq);
1849 callout_stop_sync(&sc->sc_cal_ch);
1853 * XXX ensure sc_invalid is 1
1856 /* Disable the PCIe PHY, complete with workarounds */
1857 ath_hal_enablepcie(sc->sc_ah, 1, 1);
1861 * Reset the key cache since some parts do not reset the
1862 * contents on resume. First we clear all entries, then
1863 * re-load keys that the 802.11 layer assumes are setup
1867 ath_reset_keycache(struct ath_softc *sc)
1869 struct ifnet *ifp = sc->sc_ifp;
1870 struct ieee80211com *ic = ifp->if_l2com;
1871 struct ath_hal *ah = sc->sc_ah;
1875 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1876 for (i = 0; i < sc->sc_keymax; i++)
1877 ath_hal_keyreset(ah, i);
1878 ath_power_restore_power_state(sc);
1880 ieee80211_crypto_reload_keys(ic);
1884 * Fetch the current chainmask configuration based on the current
1885 * operating channel and options.
1888 ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan)
1892 * Set TX chainmask to the currently configured chainmask;
1893 * the TX chainmask depends upon the current operating mode.
1895 sc->sc_cur_rxchainmask = sc->sc_rxchainmask;
1896 if (IEEE80211_IS_CHAN_HT(chan)) {
1897 sc->sc_cur_txchainmask = sc->sc_txchainmask;
1899 sc->sc_cur_txchainmask = 1;
1902 DPRINTF(sc, ATH_DEBUG_RESET,
1903 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n",
1905 sc->sc_cur_txchainmask,
1906 sc->sc_cur_rxchainmask);
1910 ath_resume(struct ath_softc *sc)
1912 struct ifnet *ifp = sc->sc_ifp;
1913 struct ieee80211com *ic = ifp->if_l2com;
1914 struct ath_hal *ah = sc->sc_ah;
1917 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1918 __func__, ifp->if_flags);
1920 /* Re-enable PCIe, re-enable the PCIe bus */
1921 ath_hal_enablepcie(ah, 0, 0);
1924 * Must reset the chip before we reload the
1925 * keycache as we were powered down on suspend.
1927 ath_update_chainmasks(sc,
1928 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan);
1929 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
1930 sc->sc_cur_rxchainmask);
1932 /* Ensure we set the current power state to on */
1934 ath_power_setselfgen(sc, HAL_PM_AWAKE);
1935 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1936 ath_power_setpower(sc, HAL_PM_AWAKE);
1939 ath_hal_reset(ah, sc->sc_opmode,
1940 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1942 ath_reset_keycache(sc);
1945 sc->sc_rx_stopped = 1;
1946 sc->sc_rx_resetted = 1;
1949 /* Let DFS at it in case it's a DFS channel */
1950 ath_dfs_radar_enable(sc, ic->ic_curchan);
1952 /* Let spectral at in case spectral is enabled */
1953 ath_spectral_enable(sc, ic->ic_curchan);
1956 * Let bluetooth coexistence at in case it's needed for this channel
1958 ath_btcoex_enable(sc, ic->ic_curchan);
1961 * If we're doing TDMA, enforce the TXOP limitation for chips that
1964 if (sc->sc_hasenforcetxop && sc->sc_tdma)
1965 ath_hal_setenforcetxop(sc->sc_ah, 1);
1967 ath_hal_setenforcetxop(sc->sc_ah, 0);
1969 /* Restore the LED configuration */
1971 ath_hal_setledstate(ah, HAL_LED_INIT);
1973 if (sc->sc_resume_up)
1974 ieee80211_resume_all(ic);
1977 ath_power_restore_power_state(sc);
1984 ath_shutdown(struct ath_softc *sc)
1986 struct ifnet *ifp = sc->sc_ifp;
1988 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1989 __func__, ifp->if_flags);
1992 /* NB: no point powering down chip as we're about to reboot */
1996 * Interrupt handler. Most of the actual processing is deferred.
2001 struct ath_softc *sc = arg;
2002 struct ifnet *ifp = sc->sc_ifp;
2003 struct ath_hal *ah = sc->sc_ah;
2008 * If we're inside a reset path, just print a warning and
2009 * clear the ISR. The reset routine will finish it for us.
2012 if (sc->sc_inreset_cnt) {
2014 ath_hal_getisr(ah, &status); /* clear ISR */
2015 ath_hal_intrset(ah, 0); /* disable further intr's */
2016 DPRINTF(sc, ATH_DEBUG_ANY,
2017 "%s: in reset, ignoring: status=0x%x\n",
2023 if (sc->sc_invalid) {
2025 * The hardware is not ready/present, don't touch anything.
2026 * Note this can happen early on if the IRQ is shared.
2028 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
2032 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */
2038 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2041 if ((ifp->if_flags & IFF_UP) == 0 ||
2042 (ifp->if_flags & IFF_RUNNING) == 0) {
2045 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
2046 __func__, ifp->if_flags);
2047 ath_hal_getisr(ah, &status); /* clear ISR */
2048 ath_hal_intrset(ah, 0); /* disable further intr's */
2052 ath_power_restore_power_state(sc);
2058 * Figure out the reason(s) for the interrupt. Note
2059 * that the hal returns a pseudo-ISR that may include
2060 * bits we haven't explicitly enabled so we mask the
2061 * value to insure we only process bits we requested.
2063 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
2064 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
2065 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status);
2066 #ifdef ATH_DEBUG_ALQ
2067 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate,
2069 #endif /* ATH_DEBUG_ALQ */
2070 #ifdef ATH_KTR_INTR_DEBUG
2071 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5,
2072 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x",
2073 ah->ah_intrstate[0],
2074 ah->ah_intrstate[1],
2075 ah->ah_intrstate[2],
2076 ah->ah_intrstate[3],
2077 ah->ah_intrstate[6]);
2080 /* Squirrel away SYNC interrupt debugging */
2081 if (ah->ah_syncstate != 0) {
2083 for (i = 0; i < 32; i++)
2084 if (ah->ah_syncstate & (i << i))
2085 sc->sc_intr_stats.sync_intr[i]++;
2088 status &= sc->sc_imask; /* discard unasked for bits */
2090 /* Short-circuit un-handled interrupts */
2091 if (status == 0x0) {
2095 ath_power_restore_power_state(sc);
2102 * Take a note that we're inside the interrupt handler, so
2103 * the reset routines know to wait.
2109 * Handle the interrupt. We won't run concurrent with the reset
2110 * or channel change routines as they'll wait for sc_intr_cnt
2111 * to be 0 before continuing.
2113 if (status & HAL_INT_FATAL) {
2114 sc->sc_stats.ast_hardware++;
2115 ath_hal_intrset(ah, 0); /* disable intr's until reset */
2116 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
2118 if (status & HAL_INT_SWBA) {
2120 * Software beacon alert--time to send a beacon.
2121 * Handle beacon transmission directly; deferring
2122 * this is too slow to meet timing constraints
2125 #ifdef IEEE80211_SUPPORT_TDMA
2127 if (sc->sc_tdmaswba == 0) {
2128 struct ieee80211com *ic = ifp->if_l2com;
2129 struct ieee80211vap *vap =
2130 TAILQ_FIRST(&ic->ic_vaps);
2131 ath_tdma_beacon_send(sc, vap);
2133 vap->iv_tdma->tdma_bintval;
2139 ath_beacon_proc(sc, 0);
2140 #ifdef IEEE80211_SUPPORT_SUPERG
2142 * Schedule the rx taskq in case there's no
2143 * traffic so any frames held on the staging
2144 * queue are aged and potentially flushed.
2146 sc->sc_rx.recv_sched(sc, 1);
2150 if (status & HAL_INT_RXEOL) {
2152 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL");
2153 if (! sc->sc_isedma) {
2156 * NB: the hardware should re-read the link when
2157 * RXE bit is written, but it doesn't work at
2158 * least on older hardware revs.
2160 sc->sc_stats.ast_rxeol++;
2162 * Disable RXEOL/RXORN - prevent an interrupt
2163 * storm until the PCU logic can be reset.
2164 * In case the interface is reset some other
2165 * way before "sc_kickpcu" is called, don't
2166 * modify sc_imask - that way if it is reset
2167 * by a call to ath_reset() somehow, the
2168 * interrupt mask will be correctly reprogrammed.
2170 imask = sc->sc_imask;
2171 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
2172 ath_hal_intrset(ah, imask);
2174 * Only blank sc_rxlink if we've not yet kicked
2177 * This isn't entirely correct - the correct solution
2178 * would be to have a PCU lock and engage that for
2179 * the duration of the PCU fiddling; which would include
2180 * running the RX process. Otherwise we could end up
2181 * messing up the RX descriptor chain and making the
2182 * RX desc list much shorter.
2184 if (! sc->sc_kickpcu)
2185 sc->sc_rxlink = NULL;
2190 * Enqueue an RX proc to handle whatever
2191 * is in the RX queue.
2192 * This will then kick the PCU if required.
2194 sc->sc_rx.recv_sched(sc, 1);
2196 if (status & HAL_INT_TXURN) {
2197 sc->sc_stats.ast_txurn++;
2198 /* bump tx trigger level */
2199 ath_hal_updatetxtriglevel(ah, AH_TRUE);
2202 * Handle both the legacy and RX EDMA interrupt bits.
2203 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC.
2205 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) {
2206 sc->sc_stats.ast_rx_intr++;
2207 sc->sc_rx.recv_sched(sc, 1);
2209 if (status & HAL_INT_TX) {
2210 sc->sc_stats.ast_tx_intr++;
2212 * Grab all the currently set bits in the HAL txq bitmap
2213 * and blank them. This is the only place we should be
2216 if (! sc->sc_isedma) {
2219 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs);
2220 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3,
2221 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x",
2224 sc->sc_txq_active | txqs);
2225 sc->sc_txq_active |= txqs;
2228 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
2230 if (status & HAL_INT_BMISS) {
2231 sc->sc_stats.ast_bmiss++;
2232 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
2234 if (status & HAL_INT_GTT)
2235 sc->sc_stats.ast_tx_timeout++;
2236 if (status & HAL_INT_CST)
2237 sc->sc_stats.ast_tx_cst++;
2238 if (status & HAL_INT_MIB) {
2239 sc->sc_stats.ast_mib++;
2242 * Disable interrupts until we service the MIB
2243 * interrupt; otherwise it will continue to fire.
2245 ath_hal_intrset(ah, 0);
2247 * Let the hal handle the event. We assume it will
2248 * clear whatever condition caused the interrupt.
2250 ath_hal_mibevent(ah, &sc->sc_halstats);
2252 * Don't reset the interrupt if we've just
2253 * kicked the PCU, or we may get a nested
2254 * RXEOL before the rxproc has had a chance
2257 if (sc->sc_kickpcu == 0)
2258 ath_hal_intrset(ah, sc->sc_imask);
2261 if (status & HAL_INT_RXORN) {
2262 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
2263 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN");
2264 sc->sc_stats.ast_rxorn++;
2266 if (status & HAL_INT_TSFOOR) {
2267 device_printf(sc->sc_dev, "%s: TSFOOR\n", __func__);
2268 sc->sc_syncbeacon = 1;
2276 ath_power_restore_power_state(sc);
2281 ath_fatal_proc(void *arg, int pending)
2283 struct ath_softc *sc = arg;
2284 struct ifnet *ifp = sc->sc_ifp;
2289 if_printf(ifp, "hardware error; resetting\n");
2291 * Fatal errors are unrecoverable. Typically these
2292 * are caused by DMA errors. Collect h/w state from
2293 * the hal so we can diagnose what's going on.
2295 wlan_serialize_enter();
2296 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
2297 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
2299 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
2300 state[0], state[1] , state[2], state[3],
2301 state[4], state[5]);
2303 ath_reset(ifp, ATH_RESET_NOLOSS);
2304 wlan_serialize_exit();
2308 ath_bmiss_vap(struct ieee80211vap *vap)
2310 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2313 * Workaround phantom bmiss interrupts by sanity-checking
2314 * the time of our last rx'd frame. If it is within the
2315 * beacon miss interval then ignore the interrupt. If it's
2316 * truly a bmiss we'll get another interrupt soon and that'll
2317 * be dispatched up for processing. Note this applies only
2318 * for h/w beacon miss events.
2322 * XXX TODO: Just read the TSF during the interrupt path;
2323 * that way we don't have to wake up again just to read it
2327 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2330 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
2331 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2332 struct ath_softc *sc = ifp->if_softc;
2333 u_int64_t lastrx = sc->sc_lastrx;
2334 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
2335 /* XXX should take a locked ref to iv_bss */
2336 u_int bmisstimeout =
2337 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
2339 DPRINTF(sc, ATH_DEBUG_BEACON,
2340 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
2341 __func__, (unsigned long long) tsf,
2342 (unsigned long long)(tsf - lastrx),
2343 (unsigned long long) lastrx, bmisstimeout);
2345 if (tsf - lastrx <= bmisstimeout) {
2346 sc->sc_stats.ast_bmiss_phantom++;
2349 ath_power_restore_power_state(sc);
2357 * There's no need to keep the hardware awake during the call
2361 ath_power_restore_power_state(sc);
2365 * Attempt to force a beacon resync.
2367 sc->sc_syncbeacon = 1;
2369 ATH_VAP(vap)->av_bmiss(vap);
2372 /* XXX this needs a force wakeup! */
2374 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
2379 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize))
2381 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
2382 *hangs = *(uint32_t *)sp;
2387 ath_bmiss_proc(void *arg, int pending)
2389 struct ath_softc *sc = arg;
2390 struct ifnet *ifp = sc->sc_ifp;
2393 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
2396 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2399 ath_beacon_miss(sc);
2402 * Do a reset upon any becaon miss event.
2404 * It may be a non-recognised RX clear hang which needs a reset
2407 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
2408 ath_reset(ifp, ATH_RESET_NOLOSS);
2409 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs);
2411 ath_reset(ifp, ATH_RESET_NOLOSS);
2412 ieee80211_beacon_miss(ifp->if_l2com);
2415 /* Force a beacon resync, in case they've drifted */
2416 sc->sc_syncbeacon = 1;
2419 ath_power_restore_power_state(sc);
2424 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
2425 * calcs together with WME. If necessary disable the crypto
2426 * hardware and mark the 802.11 state so keys will be setup
2427 * with the MIC work done in software.
2430 ath_settkipmic(struct ath_softc *sc)
2432 struct ifnet *ifp = sc->sc_ifp;
2433 struct ieee80211com *ic = ifp->if_l2com;
2435 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
2436 if (ic->ic_flags & IEEE80211_F_WME) {
2437 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
2438 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
2440 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
2441 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
2449 struct ath_softc *sc = (struct ath_softc *) arg;
2450 struct ifnet *ifp = sc->sc_ifp;
2451 struct ieee80211com *ic = ifp->if_l2com;
2452 struct ath_hal *ah = sc->sc_ah;
2455 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
2456 __func__, ifp->if_flags);
2460 * Force the sleep state awake.
2462 ath_power_setselfgen(sc, HAL_PM_AWAKE);
2463 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2464 ath_power_setpower(sc, HAL_PM_AWAKE);
2467 * Stop anything previously setup. This is safe
2468 * whether this is the first time through or not.
2470 ath_stop_locked(ifp);
2473 * The basic interface to setting the hardware in a good
2474 * state is ``reset''. On return the hardware is known to
2475 * be powered up and with interrupts disabled. This must
2476 * be followed by initialization of the appropriate bits
2477 * and then setup of the interrupt mask.
2480 ath_update_chainmasks(sc, ic->ic_curchan);
2481 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2482 sc->sc_cur_rxchainmask);
2484 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) {
2485 if_printf(ifp, "unable to reset hardware; hal status %u\n",
2492 sc->sc_rx_stopped = 1;
2493 sc->sc_rx_resetted = 1;
2496 ath_chan_change(sc, ic->ic_curchan);
2498 /* Let DFS at it in case it's a DFS channel */
2499 ath_dfs_radar_enable(sc, ic->ic_curchan);
2501 /* Let spectral at in case spectral is enabled */
2502 ath_spectral_enable(sc, ic->ic_curchan);
2505 * Let bluetooth coexistence at in case it's needed for this channel
2507 ath_btcoex_enable(sc, ic->ic_curchan);
2510 * If we're doing TDMA, enforce the TXOP limitation for chips that
2513 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2514 ath_hal_setenforcetxop(sc->sc_ah, 1);
2516 ath_hal_setenforcetxop(sc->sc_ah, 0);
2519 * Likewise this is set during reset so update
2520 * state cached in the driver.
2522 sc->sc_diversity = ath_hal_getdiversity(ah);
2523 sc->sc_lastlongcal = 0;
2524 sc->sc_resetcal = 1;
2525 sc->sc_lastcalreset = 0;
2527 sc->sc_lastshortcal = 0;
2528 sc->sc_doresetcal = AH_FALSE;
2530 * Beacon timers were cleared here; give ath_newstate()
2531 * a hint that the beacon timers should be poked when
2532 * things transition to the RUN state.
2537 * Setup the hardware after reset: the key cache
2538 * is filled as needed and the receive engine is
2539 * set going. Frame transmit is handled entirely
2540 * in the frame output path; there's nothing to do
2541 * here except setup the interrupt mask.
2543 if (ath_startrecv(sc) != 0) {
2544 if_printf(ifp, "unable to start recv logic\n");
2545 ath_power_restore_power_state(sc);
2551 * Enable interrupts.
2553 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
2554 | HAL_INT_RXORN | HAL_INT_TXURN
2555 | HAL_INT_FATAL | HAL_INT_GLOBAL;
2558 * Enable RX EDMA bits. Note these overlap with
2559 * HAL_INT_RX and HAL_INT_RXDESC respectively.
2562 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP);
2565 * If we're an EDMA NIC, we don't care about RXEOL.
2566 * Writing a new descriptor in will simply restart
2569 if (! sc->sc_isedma)
2570 sc->sc_imask |= HAL_INT_RXEOL;
2573 * Enable MIB interrupts when there are hardware phy counters.
2574 * Note we only do this (at the moment) for station mode.
2576 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
2577 sc->sc_imask |= HAL_INT_MIB;
2580 * XXX add capability for this.
2582 * If we're in STA mode (and maybe IBSS?) then register for
2583 * TSFOOR interrupts.
2585 if (ic->ic_opmode == IEEE80211_M_STA)
2586 sc->sc_imask |= HAL_INT_TSFOOR;
2588 /* Enable global TX timeout and carrier sense timeout if available */
2589 if (ath_hal_gtxto_supported(ah))
2590 sc->sc_imask |= HAL_INT_GTT;
2592 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
2593 __func__, sc->sc_imask);
2595 ifp->if_flags |= IFF_RUNNING;
2596 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
2597 ath_hal_intrset(ah, sc->sc_imask);
2599 ath_power_restore_power_state(sc);
2602 #ifdef ATH_TX99_DIAG
2603 if (sc->sc_tx99 != NULL)
2604 sc->sc_tx99->start(sc->sc_tx99);
2607 ieee80211_start_all(ic); /* start all vap's */
2611 ath_stop_locked(struct ifnet *ifp)
2613 struct ath_softc *sc = ifp->if_softc;
2614 struct ath_hal *ah = sc->sc_ah;
2616 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
2617 __func__, sc->sc_invalid, ifp->if_flags);
2619 ATH_LOCK_ASSERT(sc);
2622 * Wake the hardware up before fiddling with it.
2624 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2626 if (ifp->if_flags & IFF_RUNNING) {
2628 * Shutdown the hardware and driver:
2629 * reset 802.11 state machine
2631 * disable interrupts
2632 * turn off the radio
2633 * clear transmit machinery
2634 * clear receive machinery
2635 * drain and release tx queues
2636 * reclaim beacon resources
2637 * power down hardware
2639 * Note that some of this work is not possible if the
2640 * hardware is gone (invalid).
2642 #ifdef ATH_TX99_DIAG
2643 if (sc->sc_tx99 != NULL)
2644 sc->sc_tx99->stop(sc->sc_tx99);
2646 callout_stop_sync(&sc->sc_wd_ch);
2647 sc->sc_wd_timer = 0;
2648 ifp->if_flags &= ~IFF_RUNNING;
2649 if (!sc->sc_invalid) {
2650 if (sc->sc_softled) {
2651 callout_stop_sync(&sc->sc_ledtimer);
2652 ath_hal_gpioset(ah, sc->sc_ledpin,
2654 sc->sc_blinking = 0;
2656 ath_hal_intrset(ah, 0);
2658 /* XXX we should stop RX regardless of whether it's valid */
2659 if (!sc->sc_invalid) {
2660 ath_stoprecv(sc, 1);
2661 ath_hal_phydisable(ah);
2663 sc->sc_rxlink = NULL;
2664 ath_draintxq(sc, ATH_RESET_DEFAULT);
2665 ath_beacon_free(sc); /* XXX not needed */
2668 /* And now, restore the current power state */
2669 ath_power_restore_power_state(sc);
2673 * Wait until all pending TX/RX has completed.
2675 * This waits until all existing transmit, receive and interrupts
2676 * have completed. It's assumed that the caller has first
2677 * grabbed the reset lock so it doesn't try to do overlapping
2680 #define MAX_TXRX_ITERATIONS 100
2682 ath_txrx_stop_locked(struct ath_softc *sc)
2684 int i = MAX_TXRX_ITERATIONS;
2686 ATH_UNLOCK_ASSERT(sc);
2687 ATH_PCU_LOCK_ASSERT(sc);
2690 * Sleep until all the pending operations have completed.
2692 * The caller must ensure that reset has been incremented
2693 * or the pending operations may continue being queued.
2695 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt ||
2696 sc->sc_txstart_cnt || sc->sc_intr_cnt) {
2699 if (wlan_is_serialized()) {
2700 wlan_serialize_exit();
2701 lksleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop",
2702 msecs_to_ticks(10));
2703 wlan_serialize_enter();
2705 lksleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop",
2706 msecs_to_ticks(10));
2712 device_printf(sc->sc_dev,
2713 "%s: didn't finish after %d iterations\n",
2714 __func__, MAX_TXRX_ITERATIONS);
2716 #undef MAX_TXRX_ITERATIONS
2720 ath_txrx_stop(struct ath_softc *sc)
2722 ATH_UNLOCK_ASSERT(sc);
2723 ATH_PCU_UNLOCK_ASSERT(sc);
2726 ath_txrx_stop_locked(sc);
2732 ath_txrx_start(struct ath_softc *sc)
2735 taskqueue_unblock(sc->sc_tq);
2739 * Grab the reset lock, and wait around until noone else
2740 * is trying to do anything with it.
2742 * This is totally horrible but we can't hold this lock for
2743 * long enough to do TX/RX or we end up with net80211/ip stack
2744 * LORs and eventual deadlock.
2746 * "dowait" signals whether to spin, waiting for the reset
2747 * lock count to reach 0. This should (for now) only be used
2748 * during the reset path, as the rest of the code may not
2749 * be locking-reentrant enough to behave correctly.
2751 * Another, cleaner way should be found to serialise all of
2754 #define MAX_RESET_ITERATIONS 25
2756 ath_reset_grablock(struct ath_softc *sc, int dowait)
2759 int i = MAX_RESET_ITERATIONS;
2761 ATH_PCU_LOCK_ASSERT(sc);
2763 if (sc->sc_inreset_cnt == 0) {
2774 * 1 tick is likely not enough time for long calibrations
2775 * to complete. So we should wait quite a while.
2777 #if defined(__DragonFly__)
2778 tsleep(&sc->sc_inreset_cnt, 0,
2779 "ath_reset_grablock", (hz + 99) / 100);
2781 pause("ath_reset_grablock", msecs_to_ticks(100));
2788 * We always increment the refcounter, regardless
2789 * of whether we succeeded to get it in an exclusive
2792 sc->sc_inreset_cnt++;
2795 device_printf(sc->sc_dev,
2796 "%s: didn't finish after %d iterations\n",
2797 __func__, MAX_RESET_ITERATIONS);
2800 device_printf(sc->sc_dev,
2801 "%s: warning, recursive reset path!\n",
2806 #undef MAX_RESET_ITERATIONS
2809 * XXX TODO: write ath_reset_releaselock
2813 ath_stop(struct ifnet *ifp)
2815 struct ath_softc *sc = ifp->if_softc;
2818 ath_stop_locked(ifp);
2823 * Reset the hardware w/o losing operational state. This is
2824 * basically a more efficient way of doing ath_stop, ath_init,
2825 * followed by state transitions to the current 802.11
2826 * operational state. Used to recover from various errors and
2827 * to reset or reload hardware state.
2830 ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type)
2832 struct ath_softc *sc = ifp->if_softc;
2833 struct ieee80211com *ic = ifp->if_l2com;
2834 struct ath_hal *ah = sc->sc_ah;
2838 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
2840 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
2841 ATH_PCU_UNLOCK_ASSERT(sc);
2842 ATH_UNLOCK_ASSERT(sc);
2844 /* Try to (stop any further TX/RX from occuring */
2845 taskqueue_block(sc->sc_tq);
2848 * Wake the hardware up.
2851 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2857 * Grab the reset lock before TX/RX is stopped.
2859 * This is needed to ensure that when the TX/RX actually does finish,
2860 * no further TX/RX/reset runs in parallel with this.
2862 if (ath_reset_grablock(sc, 1) == 0) {
2863 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
2867 /* disable interrupts */
2868 ath_hal_intrset(ah, 0);
2871 * Now, ensure that any in progress TX/RX completes before we
2874 ath_txrx_stop_locked(sc);
2879 * Regardless of whether we're doing a no-loss flush or
2880 * not, stop the PCU and handle what's in the RX queue.
2881 * That way frames aren't dropped which shouldn't be.
2883 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS));
2887 * Should now wait for pending TX/RX to complete
2888 * and block future ones from occuring. This needs to be
2889 * done before the TX queue is drained.
2891 ath_draintxq(sc, reset_type); /* stop xmit side */
2893 ath_settkipmic(sc); /* configure TKIP MIC handling */
2894 /* NB: indicate channel change so we do a full reset */
2895 ath_update_chainmasks(sc, ic->ic_curchan);
2896 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2897 sc->sc_cur_rxchainmask);
2898 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
2899 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
2901 sc->sc_diversity = ath_hal_getdiversity(ah);
2904 sc->sc_rx_stopped = 1;
2905 sc->sc_rx_resetted = 1;
2908 /* Let DFS at it in case it's a DFS channel */
2909 ath_dfs_radar_enable(sc, ic->ic_curchan);
2911 /* Let spectral at in case spectral is enabled */
2912 ath_spectral_enable(sc, ic->ic_curchan);
2915 * Let bluetooth coexistence at in case it's needed for this channel
2917 ath_btcoex_enable(sc, ic->ic_curchan);
2920 * If we're doing TDMA, enforce the TXOP limitation for chips that
2923 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2924 ath_hal_setenforcetxop(sc->sc_ah, 1);
2926 ath_hal_setenforcetxop(sc->sc_ah, 0);
2928 if (ath_startrecv(sc) != 0) /* restart recv */
2929 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
2931 * We may be doing a reset in response to an ioctl
2932 * that changes the channel so update any state that
2933 * might change as a result.
2935 ath_chan_change(sc, ic->ic_curchan);
2936 if (sc->sc_beacons) { /* restart beacons */
2937 #ifdef IEEE80211_SUPPORT_TDMA
2939 ath_tdma_config(sc, NULL);
2942 ath_beacon_config(sc, NULL);
2946 * Release the reset lock and re-enable interrupts here.
2947 * If an interrupt was being processed in ath_intr(),
2948 * it would disable interrupts at this point. So we have
2949 * to atomically enable interrupts and decrement the
2950 * reset counter - this way ath_intr() doesn't end up
2951 * disabling interrupts without a corresponding enable
2952 * in the rest or channel change path.
2954 * Grab the TX reference in case we need to transmit.
2955 * That way a parallel transmit doesn't.
2958 sc->sc_inreset_cnt--;
2959 sc->sc_txstart_cnt++;
2960 /* XXX only do this if sc_inreset_cnt == 0? */
2961 ath_hal_intrset(ah, sc->sc_imask);
2965 * TX and RX can be started here. If it were started with
2966 * sc_inreset_cnt > 0, the TX and RX path would abort.
2967 * Thus if this is a nested call through the reset or
2968 * channel change code, TX completion will occur but
2969 * RX completion and ath_start / ath_tx_start will not
2973 /* Restart TX/RX as needed */
2976 /* XXX TODO: we need to hold the tx refcount here! */
2978 /* Restart TX completion and pending TX */
2979 if (reset_type == ATH_RESET_NOLOSS) {
2980 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
2981 if (ATH_TXQ_SETUP(sc, i)) {
2982 ATH_TXQ_LOCK(&sc->sc_txq[i]);
2983 ath_txq_restart_dma(sc, &sc->sc_txq[i]);
2984 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
2987 ath_txq_sched(sc, &sc->sc_txq[i]);
2994 * This may have been set during an ath_start() call which
2995 * set this once it detected a concurrent TX was going on.
2998 IF_LOCK(&ifp->if_snd);
2999 #if defined(__DragonFly__)
3000 ifq_clr_oactive(&ifp->if_snd);
3002 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3004 IF_UNLOCK(&ifp->if_snd);
3007 ath_power_restore_power_state(sc);
3011 sc->sc_txstart_cnt--;
3014 /* Handle any frames in the TX queue */
3016 * XXX should this be done by the caller, rather than
3019 ath_tx_kick(sc); /* restart xmit */
3024 ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
3026 struct ieee80211com *ic = vap->iv_ic;
3027 struct ifnet *ifp = ic->ic_ifp;
3028 struct ath_softc *sc = ifp->if_softc;
3029 struct ath_hal *ah = sc->sc_ah;
3032 case IEEE80211_IOC_TXPOWER:
3034 * If per-packet TPC is enabled, then we have nothing
3035 * to do; otherwise we need to force the global limit.
3036 * All this can happen directly; no need to reset.
3038 if (!ath_hal_gettpc(ah))
3039 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
3042 /* XXX? Full or NOLOSS? */
3043 return ath_reset(ifp, ATH_RESET_FULL);
3047 _ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype)
3051 ATH_TXBUF_LOCK_ASSERT(sc);
3053 if (btype == ATH_BUFTYPE_MGMT)
3054 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt);
3056 bf = TAILQ_FIRST(&sc->sc_txbuf);
3059 sc->sc_stats.ast_tx_getnobuf++;
3061 if (bf->bf_flags & ATH_BUF_BUSY) {
3062 sc->sc_stats.ast_tx_getbusybuf++;
3067 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) {
3068 if (btype == ATH_BUFTYPE_MGMT)
3069 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list);
3071 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list);
3075 * This shuldn't happen; however just to be
3076 * safe print a warning and fudge the txbuf
3079 if (sc->sc_txbuf_cnt < 0) {
3080 device_printf(sc->sc_dev,
3081 "%s: sc_txbuf_cnt < 0?\n",
3083 sc->sc_txbuf_cnt = 0;
3090 /* XXX should check which list, mgmt or otherwise */
3091 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
3092 TAILQ_FIRST(&sc->sc_txbuf) == NULL ?
3093 "out of xmit buffers" : "xmit buffer busy");
3097 /* XXX TODO: should do this at buffer list initialisation */
3098 /* XXX (then, ensure the buffer has the right flag set) */
3100 if (btype == ATH_BUFTYPE_MGMT)
3101 bf->bf_flags |= ATH_BUF_MGMT;
3103 bf->bf_flags &= (~ATH_BUF_MGMT);
3105 /* Valid bf here; clear some basic fields */
3106 bf->bf_next = NULL; /* XXX just to be sure */
3107 bf->bf_last = NULL; /* XXX again, just to be sure */
3108 bf->bf_comp = NULL; /* XXX again, just to be sure */
3109 bzero(&bf->bf_state, sizeof(bf->bf_state));
3112 * Track the descriptor ID only if doing EDMA
3114 if (sc->sc_isedma) {
3115 bf->bf_descid = sc->sc_txbuf_descid;
3116 sc->sc_txbuf_descid++;
3123 * When retrying a software frame, buffers marked ATH_BUF_BUSY
3124 * can't be thrown back on the queue as they could still be
3125 * in use by the hardware.
3127 * This duplicates the buffer, or returns NULL.
3129 * The descriptor is also copied but the link pointers and
3130 * the DMA segments aren't copied; this frame should thus
3131 * be again passed through the descriptor setup/chain routines
3132 * so the link is correct.
3134 * The caller must free the buffer using ath_freebuf().
3137 ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf)
3139 struct ath_buf *tbf;
3141 tbf = ath_getbuf(sc,
3142 (bf->bf_flags & ATH_BUF_MGMT) ?
3143 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL);
3145 return NULL; /* XXX failure? Why? */
3148 tbf->bf_next = NULL;
3149 tbf->bf_nseg = bf->bf_nseg;
3150 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE;
3151 tbf->bf_status = bf->bf_status;
3152 tbf->bf_m = bf->bf_m;
3153 tbf->bf_node = bf->bf_node;
3154 KASSERT((bf->bf_node != NULL), ("%s: bf_node=NULL!", __func__));
3155 /* will be setup by the chain/setup function */
3156 tbf->bf_lastds = NULL;
3157 /* for now, last == self */
3159 tbf->bf_comp = bf->bf_comp;
3161 /* NOTE: DMA segments will be setup by the setup/chain functions */
3163 /* The caller has to re-init the descriptor + links */
3166 * Free the DMA mapping here, before we NULL the mbuf.
3167 * We must only call bus_dmamap_unload() once per mbuf chain
3168 * or behaviour is undefined.
3170 if (bf->bf_m != NULL) {
3172 * XXX is this POSTWRITE call required?
3174 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3175 BUS_DMASYNC_POSTWRITE);
3176 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3183 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state));
3189 ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype)
3194 bf = _ath_getbuf_locked(sc, btype);
3196 * If a mgmt buffer was requested but we're out of those,
3197 * try requesting a normal one.
3199 if (bf == NULL && btype == ATH_BUFTYPE_MGMT)
3200 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
3201 ATH_TXBUF_UNLOCK(sc);
3203 struct ifnet *ifp = sc->sc_ifp;
3205 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
3206 sc->sc_stats.ast_tx_qstop++;
3207 IF_LOCK(&ifp->if_snd);
3208 #if defined(__DragonFly__)
3209 ifq_set_oactive(&ifp->if_snd);
3211 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3213 IF_UNLOCK(&ifp->if_snd);
3218 #if !defined(__DragonFly__)
3221 ath_qflush(struct ifnet *ifp)
3230 * Transmit a single frame.
3232 * net80211 will free the node reference if the transmit
3233 * fails, so don't free the node reference here.
3236 ath_transmit(struct ifnet *ifp, struct mbuf *m)
3238 struct ieee80211com *ic = ifp->if_l2com;
3239 struct ath_softc *sc = ic->ic_ifp->if_softc;
3240 struct ieee80211_node *ni;
3247 * Tell the reset path that we're currently transmitting.
3250 if (sc->sc_inreset_cnt > 0) {
3251 DPRINTF(sc, ATH_DEBUG_XMIT,
3252 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
3254 IF_LOCK(&ifp->if_snd);
3255 sc->sc_stats.ast_tx_qstop++;
3256 #if defined(__DragonFly__)
3257 /* removed, DragonFly uses OACTIVE to control if_start calls */
3258 /*ifq_set_oactive(&ifp->if_snd);*/
3260 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3262 IF_UNLOCK(&ifp->if_snd);
3263 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish");
3264 #if defined(__DragonFly__)
3268 return (ENOBUFS); /* XXX should be EINVAL or? */
3270 sc->sc_txstart_cnt++;
3273 /* Wake the hardware up already */
3275 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3278 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: start");
3280 * Grab the TX lock - it's ok to do this here; we haven't
3281 * yet started transmitting.
3286 * Node reference, if there's one.
3288 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
3291 * Enforce how deep a node queue can get.
3293 * XXX it would be nicer if we kept an mbuf queue per
3294 * node and only whacked them into ath_bufs when we
3295 * are ready to schedule some traffic from them.
3296 * .. that may come later.
3298 * XXX we should also track the per-node hardware queue
3299 * depth so it is easy to limit the _SUM_ of the swq and
3300 * hwq frames. Since we only schedule two HWQ frames
3301 * at a time, this should be OK for now.
3303 if ((!(m->m_flags & M_EAPOL)) &&
3304 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) {
3305 sc->sc_stats.ast_tx_nodeq_overflow++;
3313 * Check how many TX buffers are available.
3315 * If this is for non-EAPOL traffic, just leave some
3316 * space free in order for buffer cloning and raw
3317 * frame transmission to occur.
3319 * If it's for EAPOL traffic, ignore this for now.
3320 * Management traffic will be sent via the raw transmit
3321 * method which bypasses this check.
3323 * This is needed to ensure that EAPOL frames during
3324 * (re) keying have a chance to go out.
3326 * See kern/138379 for more information.
3328 if ((!(m->m_flags & M_EAPOL)) &&
3329 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) {
3330 sc->sc_stats.ast_tx_nobuf++;
3338 * Grab a TX buffer and associated resources.
3340 * If it's an EAPOL frame, allocate a MGMT ath_buf.
3341 * That way even with temporary buffer exhaustion due to
3342 * the data path doesn't leave us without the ability
3343 * to transmit management frames.
3345 * Otherwise allocate a normal buffer.
3347 if (m->m_flags & M_EAPOL)
3348 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
3350 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL);
3354 * If we failed to allocate a buffer, fail.
3356 * We shouldn't fail normally, due to the check
3359 sc->sc_stats.ast_tx_nobuf++;
3360 IF_LOCK(&ifp->if_snd);
3361 #if defined(__DragonFly__)
3362 /* removed, DragonFly uses OACTIVE to control if_start calls */
3363 /*ifq_set_oactive(&ifp->if_snd);*/
3365 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3367 IF_UNLOCK(&ifp->if_snd);
3375 * At this point we have a buffer; so we need to free it
3376 * if we hit any error conditions.
3380 * Check for fragmentation. If this frame
3381 * has been broken up verify we have enough
3382 * buffers to send all the fragments so all
3386 if ((m->m_flags & M_FRAG) &&
3387 !ath_txfrag_setup(sc, &frags, m, ni)) {
3388 DPRINTF(sc, ATH_DEBUG_XMIT,
3389 "%s: out of txfrag buffers\n", __func__);
3390 sc->sc_stats.ast_tx_nofrag++;
3391 #if defined(__DragonFly__)
3394 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3401 * At this point if we have any TX fragments, then we will
3402 * have bumped the node reference once for each of those.
3406 * XXX Is there anything actually _enforcing_ that the
3407 * fragments are being transmitted in one hit, rather than
3408 * being interleaved with other transmissions on that
3411 * The ATH TX output lock is the only thing serialising this
3416 * Calculate the "next fragment" length field in ath_buf
3417 * in order to let the transmit path know enough about
3418 * what to next write to the hardware.
3420 if (m->m_flags & M_FRAG) {
3421 struct ath_buf *fbf = bf;
3422 struct ath_buf *n_fbf = NULL;
3423 struct mbuf *fm = m->m_nextpkt;
3426 * We need to walk the list of fragments and set
3427 * the next size to the following buffer.
3428 * However, the first buffer isn't in the frag
3429 * list, so we have to do some gymnastics here.
3431 TAILQ_FOREACH(n_fbf, &frags, bf_list) {
3432 fbf->bf_nextfraglen = fm->m_pkthdr.len;
3439 * Bump the ifp output counter.
3441 * XXX should use atomics?
3443 #if defined(__DragonFly__)
3446 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3450 * Pass the frame to the h/w for transmission.
3451 * Fragmented frames have each frag chained together
3452 * with m_nextpkt. We know there are sufficient ath_buf's
3453 * to send all the frags because of work done by
3454 * ath_txfrag_setup. We leave m_nextpkt set while
3455 * calling ath_tx_start so it can use it to extend the
3456 * the tx duration to cover the subsequent frag and
3457 * so it can reclaim all the mbufs in case of an error;
3458 * ath_tx_start clears m_nextpkt once it commits to
3459 * handing the frame to the hardware.
3461 * Note: if this fails, then the mbufs are freed but
3462 * not the node reference.
3464 next = m->m_nextpkt;
3465 if (ath_tx_start(sc, ni, bf, m)) {
3467 #if defined(__DragonFly__)
3470 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3476 ath_returnbuf_head(sc, bf);
3478 * Free the rest of the node references and
3479 * buffers for the fragment list.
3481 ath_txfrag_cleanup(sc, &frags, ni);
3482 ATH_TXBUF_UNLOCK(sc);
3488 * Check here if the node is in power save state.
3490 ath_tx_update_tim(sc, ni, 1);
3494 * Beware of state changing between frags.
3495 * XXX check sta power-save state?
3497 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
3498 DPRINTF(sc, ATH_DEBUG_XMIT,
3499 "%s: flush fragmented packet, state %s\n",
3501 ieee80211_state_name[ni->ni_vap->iv_state]);
3507 bf = TAILQ_FIRST(&frags);
3508 KASSERT(bf != NULL, ("no buf for txfrag"));
3509 TAILQ_REMOVE(&frags, bf, bf_list);
3514 * Bump watchdog timer.
3516 sc->sc_wd_timer = 5;
3522 * Finished transmitting!
3525 sc->sc_txstart_cnt--;
3528 /* Sleep the hardware if required */
3530 ath_power_restore_power_state(sc);
3533 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: finished");
3539 ath_media_change(struct ifnet *ifp)
3541 int error = ieee80211_media_change(ifp);
3542 /* NB: only the fixed rate can change and that doesn't need a reset */
3543 return (error == ENETRESET ? 0 : error);
3547 * Block/unblock tx+rx processing while a key change is done.
3548 * We assume the caller serializes key management operations
3549 * so we only need to worry about synchronization with other
3550 * uses that originate in the driver.
3553 ath_key_update_begin(struct ieee80211vap *vap)
3555 struct ifnet *ifp = vap->iv_ic->ic_ifp;
3556 struct ath_softc *sc = ifp->if_softc;
3558 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3559 taskqueue_block(sc->sc_tq);
3563 ath_key_update_end(struct ieee80211vap *vap)
3565 struct ifnet *ifp = vap->iv_ic->ic_ifp;
3566 struct ath_softc *sc = ifp->if_softc;
3568 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3569 taskqueue_unblock(sc->sc_tq);
3573 ath_update_promisc(struct ifnet *ifp)
3575 struct ath_softc *sc = ifp->if_softc;
3578 /* configure rx filter */
3580 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3581 rfilt = ath_calcrxfilter(sc);
3582 ath_hal_setrxfilter(sc->sc_ah, rfilt);
3583 ath_power_restore_power_state(sc);
3586 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
3590 * Driver-internal mcast update call.
3592 * Assumes the hardware is already awake.
3595 ath_update_mcast_hw(struct ath_softc *sc)
3597 struct ifnet *ifp = sc->sc_ifp;
3600 /* calculate and install multicast filter */
3601 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
3602 struct ifmultiaddr *ifma;
3604 * Merge multicast addresses to form the hardware filter.
3606 mfilt[0] = mfilt[1] = 0;
3607 #if defined(__DragonFly__)
3610 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */
3612 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3617 /* calculate XOR of eight 6bit values */
3618 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
3619 val = LE_READ_4(dl + 0);
3620 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3621 val = LE_READ_4(dl + 3);
3622 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3624 mfilt[pos / 32] |= (1 << (pos % 32));
3626 #if defined(__DragonFly__)
3629 if_maddr_runlock(ifp);
3632 mfilt[0] = mfilt[1] = ~0;
3634 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
3636 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
3637 __func__, mfilt[0], mfilt[1]);
3641 * Called from the net80211 layer - force the hardware
3642 * awake before operating.
3645 ath_update_mcast(struct ifnet *ifp)
3647 struct ath_softc *sc = ifp->if_softc;
3650 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3653 ath_update_mcast_hw(sc);
3656 ath_power_restore_power_state(sc);
3661 ath_mode_init(struct ath_softc *sc)
3663 struct ifnet *ifp = sc->sc_ifp;
3664 struct ath_hal *ah = sc->sc_ah;
3667 /* configure rx filter */
3668 rfilt = ath_calcrxfilter(sc);
3669 ath_hal_setrxfilter(ah, rfilt);
3671 /* configure operational mode */
3672 ath_hal_setopmode(ah);
3674 #if !defined(__DragonFly__)
3675 DPRINTF(sc, ATH_DEBUG_STATE | ATH_DEBUG_MODE,
3676 "%s: ah=%p, ifp=%p, if_addr=%p\n",
3680 (ifp == NULL) ? NULL : ifp->if_addr);
3683 /* handle any link-level address change */
3684 ath_hal_setmac(ah, IF_LLADDR(ifp));
3686 /* calculate and install multicast filter */
3687 ath_update_mcast_hw(sc);
3691 * Set the slot time based on the current setting.
3694 ath_setslottime(struct ath_softc *sc)
3696 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3697 struct ath_hal *ah = sc->sc_ah;
3700 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
3702 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
3704 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
3705 /* honor short/long slot time only in 11g */
3706 /* XXX shouldn't honor on pure g or turbo g channel */
3707 if (ic->ic_flags & IEEE80211_F_SHSLOT)
3708 usec = HAL_SLOT_TIME_9;
3710 usec = HAL_SLOT_TIME_20;
3712 usec = HAL_SLOT_TIME_9;
3714 DPRINTF(sc, ATH_DEBUG_RESET,
3715 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
3716 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
3717 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
3719 /* Wake up the hardware first before updating the slot time */
3721 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3722 ath_hal_setslottime(ah, usec);
3723 ath_power_restore_power_state(sc);
3724 sc->sc_updateslot = OK;
3729 * Callback from the 802.11 layer to update the
3730 * slot time based on the current setting.
3733 ath_updateslot(struct ifnet *ifp)
3735 struct ath_softc *sc = ifp->if_softc;
3736 struct ieee80211com *ic = ifp->if_l2com;
3739 * When not coordinating the BSS, change the hardware
3740 * immediately. For other operation we defer the change
3741 * until beacon updates have propagated to the stations.
3743 * XXX sc_updateslot isn't changed behind a lock?
3745 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3746 ic->ic_opmode == IEEE80211_M_MBSS)
3747 sc->sc_updateslot = UPDATE;
3749 ath_setslottime(sc);
3753 * Append the contents of src to dst; both queues
3754 * are assumed to be locked.
3757 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
3760 ATH_TXQ_LOCK_ASSERT(src);
3761 ATH_TXQ_LOCK_ASSERT(dst);
3763 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list);
3764 dst->axq_link = src->axq_link;
3765 src->axq_link = NULL;
3766 dst->axq_depth += src->axq_depth;
3767 dst->axq_aggr_depth += src->axq_aggr_depth;
3769 src->axq_aggr_depth = 0;
3773 * Reset the hardware, with no loss.
3775 * This can't be used for a general case reset.
3778 ath_reset_proc(void *arg, int pending)
3780 struct ath_softc *sc = arg;
3781 struct ifnet *ifp = sc->sc_ifp;
3784 if_printf(ifp, "%s: resetting\n", __func__);
3786 wlan_serialize_enter();
3787 ath_reset(ifp, ATH_RESET_NOLOSS);
3788 wlan_serialize_exit();
3792 * Reset the hardware after detecting beacons have stopped.
3795 ath_bstuck_proc(void *arg, int pending)
3797 struct ath_softc *sc = arg;
3798 struct ifnet *ifp = sc->sc_ifp;
3801 wlan_serialize_enter();
3802 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0)
3803 if_printf(ifp, "bb hang detected (0x%x)\n", hangs);
3805 #ifdef ATH_DEBUG_ALQ
3806 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON))
3807 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL);
3810 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
3812 sc->sc_stats.ast_bstuck++;
3814 * This assumes that there's no simultaneous channel mode change
3817 ath_reset(ifp, ATH_RESET_NOLOSS);
3818 wlan_serialize_exit();
3822 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3824 bus_addr_t *paddr = (bus_addr_t*) arg;
3825 KASSERT(error == 0, ("error %u on bus_dma callback", error));
3826 *paddr = segs->ds_addr;
3830 * Allocate the descriptors and appropriate DMA tag/setup.
3832 * For some situations (eg EDMA TX completion), there isn't a requirement
3833 * for the ath_buf entries to be allocated.
3836 ath_descdma_alloc_desc(struct ath_softc *sc,
3837 struct ath_descdma *dd, ath_bufhead *head,
3838 const char *name, int ds_size, int ndesc)
3840 #define DS2PHYS(_dd, _ds) \
3841 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3842 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3843 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3844 struct ifnet *ifp = sc->sc_ifp;
3847 dd->dd_descsize = ds_size;
3849 DPRINTF(sc, ATH_DEBUG_RESET,
3850 "%s: %s DMA: %u desc, %d bytes per descriptor\n",
3851 __func__, name, ndesc, dd->dd_descsize);
3854 dd->dd_desc_len = dd->dd_descsize * ndesc;
3857 * Merlin work-around:
3858 * Descriptors that cross the 4KB boundary can't be used.
3859 * Assume one skipped descriptor per 4KB page.
3861 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3862 int numpages = dd->dd_desc_len / 4096;
3863 dd->dd_desc_len += ds_size * numpages;
3867 * Setup DMA descriptor area.
3869 * BUS_DMA_ALLOCNOW is not used; we never use bounce
3870 * buffers for the descriptors themselves.
3872 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
3873 PAGE_SIZE, 0, /* alignment, bounds */
3874 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3875 BUS_SPACE_MAXADDR, /* highaddr */
3876 NULL, NULL, /* filter, filterarg */
3877 dd->dd_desc_len, /* maxsize */
3879 dd->dd_desc_len, /* maxsegsize */
3881 #if !defined(__DragonFly__)
3882 NULL, /* lockfunc */
3887 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
3891 /* allocate descriptors */
3892 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
3893 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
3896 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
3897 "error %u\n", ndesc, dd->dd_name, error);
3901 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
3902 dd->dd_desc, dd->dd_desc_len,
3903 ath_load_cb, &dd->dd_desc_paddr,
3906 if_printf(ifp, "unable to map %s descriptors, error %u\n",
3907 dd->dd_name, error);
3911 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
3912 __func__, dd->dd_name, (uint8_t *) dd->dd_desc,
3913 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr,
3914 /*XXX*/ (u_long) dd->dd_desc_len);
3919 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3921 bus_dma_tag_destroy(dd->dd_dmat);
3922 memset(dd, 0, sizeof(*dd));
3925 #undef ATH_DESC_4KB_BOUND_CHECK
3929 ath_descdma_setup(struct ath_softc *sc,
3930 struct ath_descdma *dd, ath_bufhead *head,
3931 const char *name, int ds_size, int nbuf, int ndesc)
3933 #define DS2PHYS(_dd, _ds) \
3934 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3935 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3936 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3937 struct ifnet *ifp = sc->sc_ifp;
3940 int i, bsize, error;
3942 /* Allocate descriptors */
3943 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size,
3946 /* Assume any errors during allocation were dealt with */
3951 ds = (uint8_t *) dd->dd_desc;
3953 /* allocate rx buffers */
3954 bsize = sizeof(struct ath_buf) * nbuf;
3955 bf = kmalloc(bsize, M_ATHDEV, M_INTWAIT | M_ZERO);
3957 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3958 dd->dd_name, bsize);
3964 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) {
3965 bf->bf_desc = (struct ath_desc *) ds;
3966 bf->bf_daddr = DS2PHYS(dd, ds);
3967 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3969 * Merlin WAR: Skip descriptor addresses which
3970 * cause 4KB boundary crossing along any point
3971 * in the descriptor.
3973 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr,
3975 /* Start at the next page */
3976 ds += 0x1000 - (bf->bf_daddr & 0xFFF);
3977 bf->bf_desc = (struct ath_desc *) ds;
3978 bf->bf_daddr = DS2PHYS(dd, ds);
3981 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3984 if_printf(ifp, "unable to create dmamap for %s "
3985 "buffer %u, error %u\n", dd->dd_name, i, error);
3986 ath_descdma_cleanup(sc, dd, head);
3989 bf->bf_lastds = bf->bf_desc; /* Just an initial value */
3990 TAILQ_INSERT_TAIL(head, bf, bf_list);
3994 * XXX TODO: ensure that ds doesn't overflow the descriptor
3995 * allocation otherwise weird stuff will occur and crash your
3999 /* XXX this should likely just call ath_descdma_cleanup() */
4001 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
4002 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
4003 bus_dma_tag_destroy(dd->dd_dmat);
4004 memset(dd, 0, sizeof(*dd));
4007 #undef ATH_DESC_4KB_BOUND_CHECK
4011 * Allocate ath_buf entries but no descriptor contents.
4013 * This is for RX EDMA where the descriptors are the header part of
4017 ath_descdma_setup_rx_edma(struct ath_softc *sc,
4018 struct ath_descdma *dd, ath_bufhead *head,
4019 const char *name, int nbuf, int rx_status_len)
4021 struct ifnet *ifp = sc->sc_ifp;
4023 int i, bsize, error;
4025 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n",
4026 __func__, name, nbuf);
4030 * This is (mostly) purely for show. We're not allocating any actual
4031 * descriptors here as EDMA RX has the descriptor be part
4034 * However, dd_desc_len is used by ath_descdma_free() to determine
4035 * whether we have already freed this DMA mapping.
4037 dd->dd_desc_len = rx_status_len * nbuf;
4038 dd->dd_descsize = rx_status_len;
4040 /* allocate rx buffers */
4041 bsize = sizeof(struct ath_buf) * nbuf;
4042 bf = kmalloc(bsize, M_ATHDEV, M_INTWAIT | M_ZERO);
4044 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
4045 dd->dd_name, bsize);
4052 for (i = 0; i < nbuf; i++, bf++) {
4055 bf->bf_lastds = NULL; /* Just an initial value */
4057 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
4060 if_printf(ifp, "unable to create dmamap for %s "
4061 "buffer %u, error %u\n", dd->dd_name, i, error);
4062 ath_descdma_cleanup(sc, dd, head);
4065 TAILQ_INSERT_TAIL(head, bf, bf_list);
4069 memset(dd, 0, sizeof(*dd));
4074 ath_descdma_cleanup(struct ath_softc *sc,
4075 struct ath_descdma *dd, ath_bufhead *head)
4078 struct ieee80211_node *ni;
4081 if (dd->dd_dmamap != 0) {
4082 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
4083 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
4084 bus_dma_tag_destroy(dd->dd_dmat);
4088 TAILQ_FOREACH(bf, head, bf_list) {
4091 * XXX warn if there's buffers here.
4092 * XXX it should have been freed by the
4096 if (do_warning == 0) {
4098 device_printf(sc->sc_dev,
4099 "%s: %s: mbuf should've been"
4100 " unmapped/freed!\n",
4104 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4105 BUS_DMASYNC_POSTREAD);
4106 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4110 if (bf->bf_dmamap != NULL) {
4111 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
4112 bf->bf_dmamap = NULL;
4118 * Reclaim node reference.
4120 ieee80211_free_node(ni);
4128 if (dd->dd_bufptr != NULL)
4129 kfree(dd->dd_bufptr, M_ATHDEV);
4130 memset(dd, 0, sizeof(*dd));
4134 ath_desc_alloc(struct ath_softc *sc)
4138 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
4139 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER);
4143 sc->sc_txbuf_cnt = ath_txbuf;
4145 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt,
4146 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt,
4149 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
4154 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the
4155 * flag doesn't have to be set in ath_getbuf_locked().
4158 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
4159 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1);
4161 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
4162 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
4163 &sc->sc_txbuf_mgmt);
4170 ath_desc_free(struct ath_softc *sc)
4173 if (sc->sc_bdma.dd_desc_len != 0)
4174 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
4175 if (sc->sc_txdma.dd_desc_len != 0)
4176 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
4177 if (sc->sc_txdma_mgmt.dd_desc_len != 0)
4178 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
4179 &sc->sc_txbuf_mgmt);
4182 static struct ieee80211_node *
4183 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
4185 struct ieee80211com *ic = vap->iv_ic;
4186 struct ath_softc *sc = ic->ic_ifp->if_softc;
4187 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
4188 struct ath_node *an;
4190 an = kmalloc(space, M_80211_NODE, M_INTWAIT | M_ZERO);
4195 ath_rate_node_init(sc, an);
4197 /* Setup the mutex - there's no associd yet so set the name to NULL */
4198 ksnprintf(an->an_name, sizeof(an->an_name), "%s: node %p",
4199 device_get_nameunit(sc->sc_dev), an);
4200 lockinit(&an->an_mtx, an->an_name, 0, 0);
4202 /* XXX setup ath_tid */
4203 ath_tx_tid_init(sc, an);
4205 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an);
4206 return &an->an_node;
4210 ath_node_cleanup(struct ieee80211_node *ni)
4212 struct ieee80211com *ic = ni->ni_ic;
4213 struct ath_softc *sc = ic->ic_ifp->if_softc;
4215 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
4216 ni->ni_macaddr, ":", ATH_NODE(ni));
4218 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */
4219 ath_tx_node_flush(sc, ATH_NODE(ni));
4220 ath_rate_node_cleanup(sc, ATH_NODE(ni));
4221 sc->sc_node_cleanup(ni);
4225 ath_node_free(struct ieee80211_node *ni)
4227 struct ieee80211com *ic = ni->ni_ic;
4228 struct ath_softc *sc = ic->ic_ifp->if_softc;
4230 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
4231 ni->ni_macaddr, ":", ATH_NODE(ni));
4232 lockuninit(&ATH_NODE(ni)->an_mtx);
4233 sc->sc_node_free(ni);
4237 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
4239 struct ieee80211com *ic = ni->ni_ic;
4240 struct ath_softc *sc = ic->ic_ifp->if_softc;
4241 struct ath_hal *ah = sc->sc_ah;
4243 *rssi = ic->ic_node_getrssi(ni);
4244 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
4245 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
4247 *noise = -95; /* nominally correct */
4251 * Set the default antenna.
4254 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
4256 struct ath_hal *ah = sc->sc_ah;
4258 /* XXX block beacon interrupts */
4259 ath_hal_setdefantenna(ah, antenna);
4260 if (sc->sc_defant != antenna)
4261 sc->sc_stats.ast_ant_defswitch++;
4262 sc->sc_defant = antenna;
4263 sc->sc_rxotherant = 0;
4267 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
4269 txq->axq_qnum = qnum;
4272 txq->axq_aggr_depth = 0;
4273 txq->axq_intrcnt = 0;
4274 txq->axq_link = NULL;
4275 txq->axq_softc = sc;
4276 TAILQ_INIT(&txq->axq_q);
4277 TAILQ_INIT(&txq->axq_tidq);
4278 TAILQ_INIT(&txq->fifo.axq_q);
4279 ATH_TXQ_LOCK_INIT(sc, txq);
4283 * Setup a h/w transmit queue.
4285 static struct ath_txq *
4286 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
4288 #define N(a) (sizeof(a)/sizeof(a[0]))
4289 struct ath_hal *ah = sc->sc_ah;
4293 memset(&qi, 0, sizeof(qi));
4294 qi.tqi_subtype = subtype;
4295 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
4296 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
4297 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
4299 * Enable interrupts only for EOL and DESC conditions.
4300 * We mark tx descriptors to receive a DESC interrupt
4301 * when a tx queue gets deep; otherwise waiting for the
4302 * EOL to reap descriptors. Note that this is done to
4303 * reduce interrupt load and this only defers reaping
4304 * descriptors, never transmitting frames. Aside from
4305 * reducing interrupts this also permits more concurrency.
4306 * The only potential downside is if the tx queue backs
4307 * up in which case the top half of the kernel may backup
4308 * due to a lack of tx descriptors.
4311 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
4312 HAL_TXQ_TXOKINT_ENABLE;
4314 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
4315 HAL_TXQ_TXDESCINT_ENABLE;
4317 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
4320 * NB: don't print a message, this happens
4321 * normally on parts with too few tx queues
4325 if (qnum >= N(sc->sc_txq)) {
4326 device_printf(sc->sc_dev,
4327 "hal qnum %u out of range, max %zu!\n",
4328 qnum, N(sc->sc_txq));
4329 ath_hal_releasetxqueue(ah, qnum);
4332 if (!ATH_TXQ_SETUP(sc, qnum)) {
4333 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
4334 sc->sc_txqsetup |= 1<<qnum;
4336 return &sc->sc_txq[qnum];
4341 * Setup a hardware data transmit queue for the specified
4342 * access control. The hal may not support all requested
4343 * queues in which case it will return a reference to a
4344 * previously setup queue. We record the mapping from ac's
4345 * to h/w queues for use by ath_tx_start and also track
4346 * the set of h/w queues being used to optimize work in the
4347 * transmit interrupt handler and related routines.
4350 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
4352 #define N(a) (sizeof(a)/sizeof(a[0]))
4353 struct ath_txq *txq;
4355 if (ac >= N(sc->sc_ac2q)) {
4356 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
4357 ac, N(sc->sc_ac2q));
4360 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
4363 sc->sc_ac2q[ac] = txq;
4371 * Update WME parameters for a transmit queue.
4374 ath_txq_update(struct ath_softc *sc, int ac)
4376 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
4377 #define ATH_TXOP_TO_US(v) (v<<5)
4378 struct ifnet *ifp = sc->sc_ifp;
4379 struct ieee80211com *ic = ifp->if_l2com;
4380 struct ath_txq *txq = sc->sc_ac2q[ac];
4381 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
4382 struct ath_hal *ah = sc->sc_ah;
4385 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
4386 #ifdef IEEE80211_SUPPORT_TDMA
4389 * AIFS is zero so there's no pre-transmit wait. The
4390 * burst time defines the slot duration and is configured
4391 * through net80211. The QCU is setup to not do post-xmit
4392 * back off, lockout all lower-priority QCU's, and fire
4393 * off the DMA beacon alert timer which is setup based
4394 * on the slot configuration.
4396 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4397 | HAL_TXQ_TXERRINT_ENABLE
4398 | HAL_TXQ_TXURNINT_ENABLE
4399 | HAL_TXQ_TXEOLINT_ENABLE
4401 | HAL_TXQ_BACKOFF_DISABLE
4402 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
4406 qi.tqi_readyTime = sc->sc_tdmaslotlen;
4407 qi.tqi_burstTime = qi.tqi_readyTime;
4411 * XXX shouldn't this just use the default flags
4412 * used in the previous queue setup?
4414 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4415 | HAL_TXQ_TXERRINT_ENABLE
4416 | HAL_TXQ_TXDESCINT_ENABLE
4417 | HAL_TXQ_TXURNINT_ENABLE
4418 | HAL_TXQ_TXEOLINT_ENABLE
4420 qi.tqi_aifs = wmep->wmep_aifsn;
4421 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
4422 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
4423 qi.tqi_readyTime = 0;
4424 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
4425 #ifdef IEEE80211_SUPPORT_TDMA
4429 DPRINTF(sc, ATH_DEBUG_RESET,
4430 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
4431 __func__, txq->axq_qnum, qi.tqi_qflags,
4432 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
4434 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
4435 if_printf(ifp, "unable to update hardware queue "
4436 "parameters for %s traffic!\n",
4437 ieee80211_wme_acnames[ac]);
4440 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
4443 #undef ATH_TXOP_TO_US
4444 #undef ATH_EXPONENT_TO_VALUE
4448 * Callback from the 802.11 layer to update WME parameters.
4451 ath_wme_update(struct ieee80211com *ic)
4453 struct ath_softc *sc = ic->ic_ifp->if_softc;
4455 return !ath_txq_update(sc, WME_AC_BE) ||
4456 !ath_txq_update(sc, WME_AC_BK) ||
4457 !ath_txq_update(sc, WME_AC_VI) ||
4458 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
4462 * Reclaim resources for a setup queue.
4465 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
4468 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
4469 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
4470 ATH_TXQ_LOCK_DESTROY(txq);
4474 * Reclaim all tx queue resources.
4477 ath_tx_cleanup(struct ath_softc *sc)
4481 ATH_TXBUF_LOCK_DESTROY(sc);
4482 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4483 if (ATH_TXQ_SETUP(sc, i))
4484 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
4488 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
4489 * using the current rates in sc_rixmap.
4492 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
4494 int rix = sc->sc_rixmap[rate];
4495 /* NB: return lowest rix for invalid rate */
4496 return (rix == 0xff ? 0 : rix);
4500 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts,
4503 struct ieee80211_node *ni = bf->bf_node;
4504 struct ifnet *ifp = sc->sc_ifp;
4505 struct ieee80211com *ic = ifp->if_l2com;
4508 if (ts->ts_status == 0) {
4509 u_int8_t txant = ts->ts_antenna;
4510 sc->sc_stats.ast_ant_tx[txant]++;
4511 sc->sc_ant_tx[txant]++;
4512 if (ts->ts_finaltsi != 0)
4513 sc->sc_stats.ast_tx_altrate++;
4514 pri = M_WME_GETAC(bf->bf_m);
4515 if (pri >= WME_AC_VO)
4516 ic->ic_wme.wme_hipri_traffic++;
4517 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)
4518 ni->ni_inact = ni->ni_inact_reload;
4520 if (ts->ts_status & HAL_TXERR_XRETRY)
4521 sc->sc_stats.ast_tx_xretries++;
4522 if (ts->ts_status & HAL_TXERR_FIFO)
4523 sc->sc_stats.ast_tx_fifoerr++;
4524 if (ts->ts_status & HAL_TXERR_FILT)
4525 sc->sc_stats.ast_tx_filtered++;
4526 if (ts->ts_status & HAL_TXERR_XTXOP)
4527 sc->sc_stats.ast_tx_xtxop++;
4528 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED)
4529 sc->sc_stats.ast_tx_timerexpired++;
4531 if (bf->bf_m->m_flags & M_FF)
4532 sc->sc_stats.ast_ff_txerr++;
4534 /* XXX when is this valid? */
4535 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR)
4536 sc->sc_stats.ast_tx_desccfgerr++;
4538 * This can be valid for successful frame transmission!
4539 * If there's a TX FIFO underrun during aggregate transmission,
4540 * the MAC will pad the rest of the aggregate with delimiters.
4541 * If a BA is returned, the frame is marked as "OK" and it's up
4542 * to the TX completion code to notice which frames weren't
4543 * successfully transmitted.
4545 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN)
4546 sc->sc_stats.ast_tx_data_underrun++;
4547 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN)
4548 sc->sc_stats.ast_tx_delim_underrun++;
4550 sr = ts->ts_shortretry;
4551 lr = ts->ts_longretry;
4552 sc->sc_stats.ast_tx_shortretry += sr;
4553 sc->sc_stats.ast_tx_longretry += lr;
4558 * The default completion. If fail is 1, this means
4559 * "please don't retry the frame, and just return -1 status
4560 * to the net80211 stack.
4563 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
4565 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
4571 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ?
4572 ts->ts_status : HAL_TXERR_XRETRY;
4575 if (bf->bf_state.bfs_dobaw)
4576 device_printf(sc->sc_dev,
4577 "%s: bf %p: seqno %d: dobaw should've been cleared!\n",
4580 SEQNO(bf->bf_state.bfs_seqno));
4582 if (bf->bf_next != NULL)
4583 device_printf(sc->sc_dev,
4584 "%s: bf %p: seqno %d: bf_next not NULL!\n",
4587 SEQNO(bf->bf_state.bfs_seqno));
4590 * Check if the node software queue is empty; if so
4591 * then clear the TIM.
4593 * This needs to be done before the buffer is freed as
4594 * otherwise the node reference will have been released
4595 * and the node may not actually exist any longer.
4597 * XXX I don't like this belonging here, but it's cleaner
4598 * to do it here right now then all the other places
4599 * where ath_tx_default_comp() is called.
4601 * XXX TODO: during drain, ensure that the callback is
4602 * being called so we get a chance to update the TIM.
4606 ath_tx_update_tim(sc, bf->bf_node, 0);
4611 * Do any tx complete callback. Note this must
4612 * be done before releasing the node reference.
4613 * This will free the mbuf, release the net80211
4614 * node and recycle the ath_buf.
4616 ath_tx_freebuf(sc, bf, st);
4620 * Update rate control with the given completion status.
4623 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
4624 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen,
4625 int nframes, int nbad)
4627 struct ath_node *an;
4629 /* Only for unicast frames */
4634 ATH_NODE_UNLOCK_ASSERT(an);
4636 if ((ts->ts_status & HAL_TXERR_FILT) == 0) {
4638 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad);
4639 ATH_NODE_UNLOCK(an);
4644 * Process the completion of the given buffer.
4646 * This calls the rate control update and then the buffer completion.
4647 * This will either free the buffer or requeue it. In any case, the
4648 * bf pointer should be treated as invalid after this function is called.
4651 ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq,
4652 struct ath_tx_status *ts, struct ath_buf *bf)
4654 struct ieee80211_node *ni = bf->bf_node;
4656 ATH_TX_UNLOCK_ASSERT(sc);
4657 ATH_TXQ_UNLOCK_ASSERT(txq);
4659 /* If unicast frame, update general statistics */
4661 /* update statistics */
4662 ath_tx_update_stats(sc, ts, bf);
4666 * Call the completion handler.
4667 * The completion handler is responsible for
4668 * calling the rate control code.
4670 * Frames with no completion handler get the
4671 * rate control code called here.
4673 if (bf->bf_comp == NULL) {
4674 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4675 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) {
4677 * XXX assume this isn't an aggregate
4680 ath_tx_update_ratectrl(sc, ni,
4681 bf->bf_state.bfs_rc, ts,
4682 bf->bf_state.bfs_pktlen, 1,
4683 (ts->ts_status == 0 ? 0 : 1));
4685 ath_tx_default_comp(sc, bf, 0);
4687 bf->bf_comp(sc, bf, 0);
4693 * Process completed xmit descriptors from the specified queue.
4694 * Kick the packet scheduler if needed. This can occur from this
4698 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched)
4700 struct ath_hal *ah = sc->sc_ah;
4702 struct ath_desc *ds;
4703 struct ath_tx_status *ts;
4704 struct ieee80211_node *ni;
4705 #ifdef IEEE80211_SUPPORT_SUPERG
4706 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
4707 #endif /* IEEE80211_SUPPORT_SUPERG */
4711 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4712 __func__, txq->axq_qnum,
4713 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4716 ATH_KTR(sc, ATH_KTR_TXCOMP, 4,
4717 "ath_tx_processq: txq=%u head %p link %p depth %p",
4719 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4726 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4727 bf = TAILQ_FIRST(&txq->axq_q);
4729 ATH_TXQ_UNLOCK(txq);
4732 ds = bf->bf_lastds; /* XXX must be setup correctly! */
4733 ts = &bf->bf_status.ds_txstat;
4735 status = ath_hal_txprocdesc(ah, ds, ts);
4737 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4738 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4740 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0))
4741 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4744 #ifdef ATH_DEBUG_ALQ
4745 if (if_ath_alq_checkdebug(&sc->sc_alq,
4746 ATH_ALQ_EDMA_TXSTATUS)) {
4747 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
4748 sc->sc_tx_statuslen,
4753 if (status == HAL_EINPROGRESS) {
4754 ATH_KTR(sc, ATH_KTR_TXCOMP, 3,
4755 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS",
4756 txq->axq_qnum, bf, ds);
4757 ATH_TXQ_UNLOCK(txq);
4760 ATH_TXQ_REMOVE(txq, bf, bf_list);
4765 if (txq->axq_qnum != bf->bf_state.bfs_tx_queue) {
4766 device_printf(sc->sc_dev,
4767 "%s: TXQ=%d: bf=%p, bfs_tx_queue=%d\n",
4771 bf->bf_state.bfs_tx_queue);
4773 if (txq->axq_qnum != bf->bf_last->bf_state.bfs_tx_queue) {
4774 device_printf(sc->sc_dev,
4775 "%s: TXQ=%d: bf_last=%p, bfs_tx_queue=%d\n",
4779 bf->bf_last->bf_state.bfs_tx_queue);
4783 if (txq->axq_depth > 0) {
4785 * More frames follow. Mark the buffer busy
4786 * so it's not re-used while the hardware may
4787 * still re-read the link field in the descriptor.
4789 * Use the last buffer in an aggregate as that
4790 * is where the hardware may be - intermediate
4791 * descriptors won't be "busy".
4793 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4795 txq->axq_link = NULL;
4797 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4799 if (bf->bf_state.bfs_aggr)
4800 txq->axq_aggr_depth--;
4804 ATH_KTR(sc, ATH_KTR_TXCOMP, 5,
4805 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x",
4806 txq->axq_qnum, bf, ds, ni, ts->ts_status);
4808 * If unicast frame was ack'd update RSSI,
4809 * including the last rx time used to
4810 * workaround phantom bmiss interrupts.
4812 if (ni != NULL && ts->ts_status == 0 &&
4813 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
4815 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4816 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4819 ATH_TXQ_UNLOCK(txq);
4822 * Update statistics and call completion
4824 ath_tx_process_buf_completion(sc, txq, ts, bf);
4826 /* XXX at this point, bf and ni may be totally invalid */
4828 #ifdef IEEE80211_SUPPORT_SUPERG
4830 * Flush fast-frame staging queue when traffic slows.
4832 if (txq->axq_depth <= 1)
4833 ieee80211_ff_flush(ic, txq->axq_ac);
4836 /* Kick the software TXQ scheduler */
4839 ath_txq_sched(sc, txq);
4843 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4844 "ath_tx_processq: txq=%u: done",
4850 #define TXQACTIVE(t, q) ( (t) & (1 << (q)))
4853 * Deferred processing of transmit interrupt; special-cased
4854 * for a single hardware transmit queue (e.g. 5210 and 5211).
4857 ath_tx_proc_q0(void *arg, int npending)
4859 struct ath_softc *sc = arg;
4860 struct ifnet *ifp = sc->sc_ifp;
4864 sc->sc_txproc_cnt++;
4865 txqs = sc->sc_txq_active;
4866 sc->sc_txq_active &= ~txqs;
4870 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4873 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4874 "ath_tx_proc_q0: txqs=0x%08x", txqs);
4876 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1))
4877 /* XXX why is lastrx updated in tx code? */
4878 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4879 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4880 ath_tx_processq(sc, sc->sc_cabq, 1);
4881 IF_LOCK(&ifp->if_snd);
4882 #if defined(__DragonFly__)
4883 ifq_clr_oactive(&ifp->if_snd);
4885 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4887 IF_UNLOCK(&ifp->if_snd);
4888 sc->sc_wd_timer = 0;
4891 ath_led_event(sc, sc->sc_txrix);
4894 sc->sc_txproc_cnt--;
4898 ath_power_restore_power_state(sc);
4905 * Deferred processing of transmit interrupt; special-cased
4906 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
4909 ath_tx_proc_q0123(void *arg, int npending)
4911 struct ath_softc *sc = arg;
4912 struct ifnet *ifp = sc->sc_ifp;
4917 sc->sc_txproc_cnt++;
4918 txqs = sc->sc_txq_active;
4919 sc->sc_txq_active &= ~txqs;
4923 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4926 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4927 "ath_tx_proc_q0123: txqs=0x%08x", txqs);
4930 * Process each active queue.
4933 if (TXQACTIVE(txqs, 0))
4934 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1);
4935 if (TXQACTIVE(txqs, 1))
4936 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1);
4937 if (TXQACTIVE(txqs, 2))
4938 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1);
4939 if (TXQACTIVE(txqs, 3))
4940 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1);
4941 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4942 ath_tx_processq(sc, sc->sc_cabq, 1);
4944 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4946 IF_LOCK(&ifp->if_snd);
4947 #if defined(__DragonFly__)
4948 ifq_clr_oactive(&ifp->if_snd);
4950 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4952 IF_UNLOCK(&ifp->if_snd);
4953 sc->sc_wd_timer = 0;
4956 ath_led_event(sc, sc->sc_txrix);
4959 sc->sc_txproc_cnt--;
4963 ath_power_restore_power_state(sc);
4970 * Deferred processing of transmit interrupt.
4973 ath_tx_proc(void *arg, int npending)
4975 struct ath_softc *sc = arg;
4976 struct ifnet *ifp = sc->sc_ifp;
4981 sc->sc_txproc_cnt++;
4982 txqs = sc->sc_txq_active;
4983 sc->sc_txq_active &= ~txqs;
4987 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4990 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs);
4993 * Process each active queue.
4996 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4997 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i))
4998 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1);
5000 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5002 /* XXX check this inside of IF_LOCK? */
5003 IF_LOCK(&ifp->if_snd);
5004 #if defined(__DragonFly__)
5005 ifq_clr_oactive(&ifp->if_snd);
5007 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5009 IF_UNLOCK(&ifp->if_snd);
5010 sc->sc_wd_timer = 0;
5013 ath_led_event(sc, sc->sc_txrix);
5016 sc->sc_txproc_cnt--;
5020 ath_power_restore_power_state(sc);
5028 * Deferred processing of TXQ rescheduling.
5031 ath_txq_sched_tasklet(void *arg, int npending)
5033 struct ath_softc *sc = arg;
5036 /* XXX is skipping ok? */
5039 if (sc->sc_inreset_cnt > 0) {
5040 device_printf(sc->sc_dev,
5041 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
5046 sc->sc_txproc_cnt++;
5050 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5054 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5055 if (ATH_TXQ_SETUP(sc, i)) {
5056 ath_txq_sched(sc, &sc->sc_txq[i]);
5062 ath_power_restore_power_state(sc);
5066 sc->sc_txproc_cnt--;
5071 ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf)
5074 ATH_TXBUF_LOCK_ASSERT(sc);
5076 if (bf->bf_flags & ATH_BUF_MGMT)
5077 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list);
5079 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
5081 if (sc->sc_txbuf_cnt > ath_txbuf) {
5082 device_printf(sc->sc_dev,
5083 "%s: sc_txbuf_cnt > %d?\n",
5086 sc->sc_txbuf_cnt = ath_txbuf;
5092 ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf)
5095 ATH_TXBUF_LOCK_ASSERT(sc);
5097 if (bf->bf_flags & ATH_BUF_MGMT)
5098 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list);
5100 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
5102 if (sc->sc_txbuf_cnt > ATH_TXBUF) {
5103 device_printf(sc->sc_dev,
5104 "%s: sc_txbuf_cnt > %d?\n",
5107 sc->sc_txbuf_cnt = ATH_TXBUF;
5113 * Free the holding buffer if it exists
5116 ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq)
5118 ATH_TXBUF_UNLOCK_ASSERT(sc);
5119 ATH_TXQ_LOCK_ASSERT(txq);
5121 if (txq->axq_holdingbf == NULL)
5124 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY;
5127 ath_returnbuf_tail(sc, txq->axq_holdingbf);
5128 ATH_TXBUF_UNLOCK(sc);
5130 txq->axq_holdingbf = NULL;
5134 * Add this buffer to the holding queue, freeing the previous
5138 ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf)
5140 struct ath_txq *txq;
5142 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
5144 ATH_TXBUF_UNLOCK_ASSERT(sc);
5145 ATH_TXQ_LOCK_ASSERT(txq);
5147 /* XXX assert ATH_BUF_BUSY is set */
5149 /* XXX assert the tx queue is under the max number */
5150 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) {
5151 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n",
5154 bf->bf_state.bfs_tx_queue);
5155 bf->bf_flags &= ~ATH_BUF_BUSY;
5156 ath_returnbuf_tail(sc, bf);
5159 ath_txq_freeholdingbuf(sc, txq);
5160 txq->axq_holdingbf = bf;
5164 * Return a buffer to the pool and update the 'busy' flag on the
5165 * previous 'tail' entry.
5167 * This _must_ only be called when the buffer is involved in a completed
5168 * TX. The logic is that if it was part of an active TX, the previous
5169 * buffer on the list is now not involved in a halted TX DMA queue, waiting
5170 * for restart (eg for TDMA.)
5172 * The caller must free the mbuf and recycle the node reference.
5174 * XXX This method of handling busy / holding buffers is insanely stupid.
5175 * It requires bf_state.bfs_tx_queue to be correctly assigned. It would
5176 * be much nicer if buffers in the processq() methods would instead be
5177 * always completed there (pushed onto a txq or ath_bufhead) so we knew
5178 * exactly what hardware queue they came from in the first place.
5181 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf)
5183 struct ath_txq *txq;
5185 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
5187 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__));
5188 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__));
5191 * If this buffer is busy, push it onto the holding queue.
5193 if (bf->bf_flags & ATH_BUF_BUSY) {
5195 ath_txq_addholdingbuf(sc, bf);
5196 ATH_TXQ_UNLOCK(txq);
5201 * Not a busy buffer, so free normally
5204 ath_returnbuf_tail(sc, bf);
5205 ATH_TXBUF_UNLOCK(sc);
5209 * This is currently used by ath_tx_draintxq() and
5210 * ath_tx_tid_free_pkts().
5212 * It recycles a single ath_buf.
5215 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status)
5217 struct ieee80211_node *ni = bf->bf_node;
5218 struct mbuf *m0 = bf->bf_m;
5221 * Make sure that we only sync/unload if there's an mbuf.
5222 * If not (eg we cloned a buffer), the unload will have already
5225 if (bf->bf_m != NULL) {
5226 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
5227 BUS_DMASYNC_POSTWRITE);
5228 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5234 /* Free the buffer, it's not needed any longer */
5235 ath_freebuf(sc, bf);
5237 /* Pass the buffer back to net80211 - completing it */
5238 ieee80211_tx_complete(ni, m0, status);
5241 static struct ath_buf *
5242 ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq)
5246 ATH_TXQ_LOCK_ASSERT(txq);
5249 * Drain the FIFO queue first, then if it's
5250 * empty, move to the normal frame queue.
5252 bf = TAILQ_FIRST(&txq->fifo.axq_q);
5255 * Is it the last buffer in this set?
5256 * Decrement the FIFO counter.
5258 if (bf->bf_flags & ATH_BUF_FIFOEND) {
5259 if (txq->axq_fifo_depth == 0) {
5260 device_printf(sc->sc_dev,
5261 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n",
5264 txq->fifo.axq_depth);
5266 txq->axq_fifo_depth--;
5268 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
5275 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) {
5276 device_printf(sc->sc_dev,
5277 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n",
5280 txq->axq_fifo_depth,
5281 txq->fifo.axq_depth);
5285 * Now drain the pending queue.
5287 bf = TAILQ_FIRST(&txq->axq_q);
5289 txq->axq_link = NULL;
5292 ATH_TXQ_REMOVE(txq, bf, bf_list);
5297 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
5300 struct ath_hal *ah = sc->sc_ah;
5306 * NB: this assumes output has been stopped and
5307 * we do not need to block ath_tx_proc
5309 for (ix = 0;; ix++) {
5311 bf = ath_tx_draintxq_get_one(sc, txq);
5313 ATH_TXQ_UNLOCK(txq);
5316 if (bf->bf_state.bfs_aggr)
5317 txq->axq_aggr_depth--;
5319 if (sc->sc_debug & ATH_DEBUG_RESET) {
5320 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5324 * EDMA operation has a TX completion FIFO
5325 * separate from the TX descriptor, so this
5326 * method of checking the "completion" status
5329 if (! sc->sc_isedma) {
5330 status = (ath_hal_txprocdesc(ah,
5332 &bf->bf_status.ds_txstat) == HAL_OK);
5334 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status);
5335 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
5336 bf->bf_m->m_len, 0, -1);
5338 #endif /* ATH_DEBUG */
5340 * Since we're now doing magic in the completion
5341 * functions, we -must- call it for aggregation
5342 * destinations or BAW tracking will get upset.
5345 * Clear ATH_BUF_BUSY; the completion handler
5346 * will free the buffer.
5348 ATH_TXQ_UNLOCK(txq);
5349 bf->bf_flags &= ~ATH_BUF_BUSY;
5351 bf->bf_comp(sc, bf, 1);
5353 ath_tx_default_comp(sc, bf, 1);
5357 * Free the holding buffer if it exists
5360 ath_txq_freeholdingbuf(sc, txq);
5361 ATH_TXQ_UNLOCK(txq);
5364 * Drain software queued frames which are on
5367 ath_tx_txq_drain(sc, txq);
5371 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
5373 struct ath_hal *ah = sc->sc_ah;
5375 ATH_TXQ_LOCK_ASSERT(txq);
5377 DPRINTF(sc, ATH_DEBUG_RESET,
5378 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, "
5379 "link %p, holdingbf=%p\n",
5382 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
5383 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)),
5384 (int) ath_hal_numtxpending(ah, txq->axq_qnum),
5387 txq->axq_holdingbf);
5389 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
5390 /* We've stopped TX DMA, so mark this as stopped. */
5391 txq->axq_flags &= ~ATH_TXQ_PUTRUNNING;
5394 if ((sc->sc_debug & ATH_DEBUG_RESET)
5395 && (txq->axq_holdingbf != NULL)) {
5396 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0);
5402 ath_stoptxdma(struct ath_softc *sc)
5404 struct ath_hal *ah = sc->sc_ah;
5407 /* XXX return value */
5411 if (!sc->sc_invalid) {
5412 /* don't touch the hardware if marked invalid */
5413 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5414 __func__, sc->sc_bhalq,
5415 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
5418 /* stop the beacon queue */
5419 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
5421 /* Stop the data queues */
5422 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5423 if (ATH_TXQ_SETUP(sc, i)) {
5424 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5425 ath_tx_stopdma(sc, &sc->sc_txq[i]);
5426 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5436 ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq)
5438 struct ath_hal *ah = sc->sc_ah;
5442 if (! (sc->sc_debug & ATH_DEBUG_RESET))
5445 device_printf(sc->sc_dev, "%s: Q%d: begin\n",
5446 __func__, txq->axq_qnum);
5447 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
5448 ath_printtxbuf(sc, bf, txq->axq_qnum, i,
5449 ath_hal_txprocdesc(ah, bf->bf_lastds,
5450 &bf->bf_status.ds_txstat) == HAL_OK);
5453 device_printf(sc->sc_dev, "%s: Q%d: end\n",
5454 __func__, txq->axq_qnum);
5456 #endif /* ATH_DEBUG */
5459 * Drain the transmit queues and reclaim resources.
5462 ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
5464 struct ath_hal *ah = sc->sc_ah;
5465 struct ifnet *ifp = sc->sc_ifp;
5467 struct ath_buf *bf_last;
5469 (void) ath_stoptxdma(sc);
5472 * Dump the queue contents
5474 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5476 * XXX TODO: should we just handle the completed TX frames
5477 * here, whether or not the reset is a full one or not?
5479 if (ATH_TXQ_SETUP(sc, i)) {
5481 if (sc->sc_debug & ATH_DEBUG_RESET)
5482 ath_tx_dump(sc, &sc->sc_txq[i]);
5483 #endif /* ATH_DEBUG */
5484 if (reset_type == ATH_RESET_NOLOSS) {
5485 ath_tx_processq(sc, &sc->sc_txq[i], 0);
5486 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5488 * Free the holding buffer; DMA is now
5491 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
5493 * Setup the link pointer to be the
5494 * _last_ buffer/descriptor in the list.
5495 * If there's nothing in the list, set it
5498 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i],
5500 if (bf_last != NULL) {
5501 ath_hal_gettxdesclinkptr(ah,
5503 &sc->sc_txq[i].axq_link);
5505 sc->sc_txq[i].axq_link = NULL;
5507 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5509 ath_tx_draintxq(sc, &sc->sc_txq[i]);
5513 if (sc->sc_debug & ATH_DEBUG_RESET) {
5514 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf);
5515 if (bf != NULL && bf->bf_m != NULL) {
5516 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
5517 ath_hal_txprocdesc(ah, bf->bf_lastds,
5518 &bf->bf_status.ds_txstat) == HAL_OK);
5519 ieee80211_dump_pkt(ifp->if_l2com,
5520 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
5524 #endif /* ATH_DEBUG */
5525 IF_LOCK(&ifp->if_snd);
5526 #if defined(__DragonFly__)
5527 ifq_clr_oactive(&ifp->if_snd);
5529 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5531 IF_UNLOCK(&ifp->if_snd);
5532 sc->sc_wd_timer = 0;
5536 * Update internal state after a channel change.
5539 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
5541 enum ieee80211_phymode mode;
5544 * Change channels and update the h/w rate map
5545 * if we're switching; e.g. 11a to 11b/g.
5547 mode = ieee80211_chan2mode(chan);
5548 if (mode != sc->sc_curmode)
5549 ath_setcurmode(sc, mode);
5550 sc->sc_curchan = chan;
5554 * Set/change channels. If the channel is really being changed,
5555 * it's done by resetting the chip. To accomplish this we must
5556 * first cleanup any pending DMA, then restart stuff after a la
5560 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
5562 struct ifnet *ifp = sc->sc_ifp;
5563 struct ieee80211com *ic = ifp->if_l2com;
5564 struct ath_hal *ah = sc->sc_ah;
5567 /* Treat this as an interface reset */
5568 ATH_PCU_UNLOCK_ASSERT(sc);
5569 ATH_UNLOCK_ASSERT(sc);
5571 /* (Try to) stop TX/RX from occuring */
5572 taskqueue_block(sc->sc_tq);
5576 /* Disable interrupts */
5577 ath_hal_intrset(ah, 0);
5579 /* Stop new RX/TX/interrupt completion */
5580 if (ath_reset_grablock(sc, 1) == 0) {
5581 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
5585 /* Stop pending RX/TX completion */
5586 ath_txrx_stop_locked(sc);
5590 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
5591 __func__, ieee80211_chan2ieee(ic, chan),
5592 chan->ic_freq, chan->ic_flags);
5593 if (chan != sc->sc_curchan) {
5596 * To switch channels clear any pending DMA operations;
5597 * wait long enough for the RX fifo to drain, reset the
5598 * hardware at the new frequency, and then re-enable
5599 * the relevant bits of the h/w.
5602 ath_hal_intrset(ah, 0); /* disable interrupts */
5604 ath_stoprecv(sc, 1); /* turn off frame recv */
5606 * First, handle completed TX/RX frames.
5609 ath_draintxq(sc, ATH_RESET_NOLOSS);
5611 * Next, flush the non-scheduled frames.
5613 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
5615 ath_update_chainmasks(sc, chan);
5616 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
5617 sc->sc_cur_rxchainmask);
5618 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
5619 if_printf(ifp, "%s: unable to reset "
5620 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
5621 __func__, ieee80211_chan2ieee(ic, chan),
5622 chan->ic_freq, chan->ic_flags, status);
5626 sc->sc_diversity = ath_hal_getdiversity(ah);
5629 sc->sc_rx_stopped = 1;
5630 sc->sc_rx_resetted = 1;
5633 /* Let DFS at it in case it's a DFS channel */
5634 ath_dfs_radar_enable(sc, chan);
5636 /* Let spectral at in case spectral is enabled */
5637 ath_spectral_enable(sc, chan);
5640 * Let bluetooth coexistence at in case it's needed for this
5643 ath_btcoex_enable(sc, ic->ic_curchan);
5646 * If we're doing TDMA, enforce the TXOP limitation for chips
5649 if (sc->sc_hasenforcetxop && sc->sc_tdma)
5650 ath_hal_setenforcetxop(sc->sc_ah, 1);
5652 ath_hal_setenforcetxop(sc->sc_ah, 0);
5655 * Re-enable rx framework.
5657 if (ath_startrecv(sc) != 0) {
5658 if_printf(ifp, "%s: unable to restart recv logic\n",
5665 * Change channels and update the h/w rate map
5666 * if we're switching; e.g. 11a to 11b/g.
5668 ath_chan_change(sc, chan);
5671 * Reset clears the beacon timers; reset them
5674 if (sc->sc_beacons) { /* restart beacons */
5675 #ifdef IEEE80211_SUPPORT_TDMA
5677 ath_tdma_config(sc, NULL);
5680 ath_beacon_config(sc, NULL);
5684 * Re-enable interrupts.
5687 ath_hal_intrset(ah, sc->sc_imask);
5693 sc->sc_inreset_cnt--;
5694 /* XXX only do this if sc_inreset_cnt == 0? */
5695 ath_hal_intrset(ah, sc->sc_imask);
5698 IF_LOCK(&ifp->if_snd);
5699 #if defined(__DragonFly__)
5700 ifq_clr_oactive(&ifp->if_snd);
5702 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5704 IF_UNLOCK(&ifp->if_snd);
5706 /* XXX ath_start? */
5712 * Periodically recalibrate the PHY to account
5713 * for temperature/environment changes.
5716 ath_calibrate(void *arg)
5718 struct ath_softc *sc = arg;
5719 struct ath_hal *ah = sc->sc_ah;
5720 struct ifnet *ifp = sc->sc_ifp;
5721 struct ieee80211com *ic = ifp->if_l2com;
5722 HAL_BOOL longCal, isCalDone = AH_TRUE;
5723 HAL_BOOL aniCal, shortCal = AH_FALSE;
5726 ATH_LOCK_ASSERT(sc);
5729 * Force the hardware awake for ANI work.
5731 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5733 /* Skip trying to do this if we're in reset */
5734 if (sc->sc_inreset_cnt)
5737 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
5739 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
5740 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000);
5741 if (sc->sc_doresetcal)
5742 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000);
5744 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal);
5746 sc->sc_stats.ast_ani_cal++;
5747 sc->sc_lastani = ticks;
5748 ath_hal_ani_poll(ah, sc->sc_curchan);
5752 sc->sc_stats.ast_per_cal++;
5753 sc->sc_lastlongcal = ticks;
5754 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
5756 * Rfgain is out of bounds, reset the chip
5757 * to load new gain values.
5759 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5760 "%s: rfgain change\n", __func__);
5761 sc->sc_stats.ast_per_rfgain++;
5762 sc->sc_resetcal = 0;
5763 sc->sc_doresetcal = AH_TRUE;
5764 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5765 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5766 ath_power_restore_power_state(sc);
5770 * If this long cal is after an idle period, then
5771 * reset the data collection state so we start fresh.
5773 if (sc->sc_resetcal) {
5774 (void) ath_hal_calreset(ah, sc->sc_curchan);
5775 sc->sc_lastcalreset = ticks;
5776 sc->sc_lastshortcal = ticks;
5777 sc->sc_resetcal = 0;
5778 sc->sc_doresetcal = AH_TRUE;
5782 /* Only call if we're doing a short/long cal, not for ANI calibration */
5783 if (shortCal || longCal) {
5784 isCalDone = AH_FALSE;
5785 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5788 * Calibrate noise floor data again in case of change.
5790 ath_hal_process_noisefloor(ah);
5793 DPRINTF(sc, ATH_DEBUG_ANY,
5794 "%s: calibration of channel %u failed\n",
5795 __func__, sc->sc_curchan->ic_freq);
5796 sc->sc_stats.ast_per_calfail++;
5799 sc->sc_lastshortcal = ticks;
5804 * Use a shorter interval to potentially collect multiple
5805 * data samples required to complete calibration. Once
5806 * we're told the work is done we drop back to a longer
5807 * interval between requests. We're more aggressive doing
5808 * work when operating as an AP to improve operation right
5811 sc->sc_lastshortcal = ticks;
5812 nextcal = ath_shortcalinterval*hz/1000;
5813 if (sc->sc_opmode != HAL_M_HOSTAP)
5815 sc->sc_doresetcal = AH_TRUE;
5817 /* nextcal should be the shortest time for next event */
5818 nextcal = ath_longcalinterval*hz;
5819 if (sc->sc_lastcalreset == 0)
5820 sc->sc_lastcalreset = sc->sc_lastlongcal;
5821 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5822 sc->sc_resetcal = 1; /* setup reset next trip */
5823 sc->sc_doresetcal = AH_FALSE;
5825 /* ANI calibration may occur more often than short/long/resetcal */
5826 if (ath_anicalinterval > 0)
5827 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000);
5830 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5831 __func__, nextcal, isCalDone ? "" : "!");
5832 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5834 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5836 /* NB: don't rearm timer */
5839 * Restore power state now that we're done.
5841 ath_power_restore_power_state(sc);
5845 ath_scan_start(struct ieee80211com *ic)
5847 struct ifnet *ifp = ic->ic_ifp;
5848 struct ath_softc *sc = ifp->if_softc;
5849 struct ath_hal *ah = sc->sc_ah;
5852 /* XXX calibration timer? */
5855 sc->sc_scanning = 1;
5856 sc->sc_syncbeacon = 0;
5857 rfilt = ath_calcrxfilter(sc);
5861 ath_hal_setrxfilter(ah, rfilt);
5862 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
5865 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5866 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
5870 ath_scan_end(struct ieee80211com *ic)
5872 struct ifnet *ifp = ic->ic_ifp;
5873 struct ath_softc *sc = ifp->if_softc;
5874 struct ath_hal *ah = sc->sc_ah;
5878 sc->sc_scanning = 0;
5879 rfilt = ath_calcrxfilter(sc);
5883 ath_hal_setrxfilter(ah, rfilt);
5884 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5886 ath_hal_process_noisefloor(ah);
5889 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5890 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5894 #ifdef ATH_ENABLE_11N
5896 * For now, just do a channel change.
5898 * Later, we'll go through the hard slog of suspending tx/rx, changing rate
5899 * control state and resetting the hardware without dropping frames out
5902 * The unfortunate trouble here is making absolutely sure that the
5903 * channel width change has propagated enough so the hardware
5904 * absolutely isn't handed bogus frames for it's current operating
5905 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and
5906 * does occur in parallel, we need to make certain we've blocked
5907 * any further ongoing TX (and RX, that can cause raw TX)
5908 * before we do this.
5911 ath_update_chw(struct ieee80211com *ic)
5913 struct ifnet *ifp = ic->ic_ifp;
5914 struct ath_softc *sc = ifp->if_softc;
5916 DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__);
5917 ath_set_channel(ic);
5919 #endif /* ATH_ENABLE_11N */
5922 ath_set_channel(struct ieee80211com *ic)
5924 struct ifnet *ifp = ic->ic_ifp;
5925 struct ath_softc *sc = ifp->if_softc;
5928 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5931 (void) ath_chan_set(sc, ic->ic_curchan);
5933 * If we are returning to our bss channel then mark state
5934 * so the next recv'd beacon's tsf will be used to sync the
5935 * beacon timers. Note that since we only hear beacons in
5936 * sta/ibss mode this has no effect in other operating modes.
5939 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5940 sc->sc_syncbeacon = 1;
5941 ath_power_restore_power_state(sc);
5946 * Walk the vap list and check if there any vap's in RUN state.
5949 ath_isanyrunningvaps(struct ieee80211vap *this)
5951 struct ieee80211com *ic = this->iv_ic;
5952 struct ieee80211vap *vap;
5954 IEEE80211_LOCK_ASSERT(ic);
5956 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5957 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5964 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5966 struct ieee80211com *ic = vap->iv_ic;
5967 struct ath_softc *sc = ic->ic_ifp->if_softc;
5968 struct ath_vap *avp = ATH_VAP(vap);
5969 struct ath_hal *ah = sc->sc_ah;
5970 struct ieee80211_node *ni = NULL;
5971 int i, error, stamode;
5973 int csa_run_transition = 0;
5974 enum ieee80211_state ostate = vap->iv_state;
5976 static const HAL_LED_STATE leds[] = {
5977 HAL_LED_INIT, /* IEEE80211_S_INIT */
5978 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5979 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5980 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5981 HAL_LED_RUN, /* IEEE80211_S_CAC */
5982 HAL_LED_RUN, /* IEEE80211_S_RUN */
5983 HAL_LED_RUN, /* IEEE80211_S_CSA */
5984 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5987 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5988 ieee80211_state_name[ostate],
5989 ieee80211_state_name[nstate]);
5992 * net80211 _should_ have the comlock asserted at this point.
5993 * There are some comments around the calls to vap->iv_newstate
5994 * which indicate that it (newstate) may end up dropping the
5995 * lock. This and the subsequent lock assert check after newstate
5996 * are an attempt to catch these and figure out how/why.
5998 IEEE80211_LOCK_ASSERT(ic);
6000 /* Before we touch the hardware - wake it up */
6003 * If the NIC is in anything other than SLEEP state,
6004 * we need to ensure that self-generated frames are
6005 * set for PWRMGT=0. Otherwise we may end up with
6006 * strange situations.
6008 * XXX TODO: is this actually the case? :-)
6010 if (nstate != IEEE80211_S_SLEEP)
6011 ath_power_setselfgen(sc, HAL_PM_AWAKE);
6014 * Now, wake the thing up.
6016 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6019 * And stop the calibration callout whilst we have
6022 callout_stop_sync(&sc->sc_cal_ch);
6025 if (ostate == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN)
6026 csa_run_transition = 1;
6028 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
6030 if (nstate == IEEE80211_S_SCAN) {
6032 * Scanning: turn off beacon miss and don't beacon.
6033 * Mark beacon state so when we reach RUN state we'll
6034 * [re]setup beacons. Unblock the task q thread so
6035 * deferred interrupt processing is done.
6038 /* Ensure we stay awake during scan */
6040 ath_power_setselfgen(sc, HAL_PM_AWAKE);
6041 ath_power_setpower(sc, HAL_PM_AWAKE);
6045 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
6046 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
6048 taskqueue_unblock(sc->sc_tq);
6051 ni = ieee80211_ref_node(vap->iv_bss);
6052 rfilt = ath_calcrxfilter(sc);
6053 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
6054 vap->iv_opmode == IEEE80211_M_AHDEMO ||
6055 vap->iv_opmode == IEEE80211_M_IBSS);
6058 * XXX Dont need to do this (and others) if we've transitioned
6061 if (stamode && nstate == IEEE80211_S_RUN) {
6062 sc->sc_curaid = ni->ni_associd;
6063 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
6064 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
6066 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
6067 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
6068 ath_hal_setrxfilter(ah, rfilt);
6070 /* XXX is this to restore keycache on resume? */
6071 if (vap->iv_opmode != IEEE80211_M_STA &&
6072 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
6073 for (i = 0; i < IEEE80211_WEP_NKID; i++)
6074 if (ath_hal_keyisvalid(ah, i))
6075 ath_hal_keysetmac(ah, i, ni->ni_bssid);
6079 * Invoke the parent method to do net80211 work.
6081 error = avp->av_newstate(vap, nstate, arg);
6086 * See above: ensure av_newstate() doesn't drop the lock
6089 IEEE80211_LOCK_ASSERT(ic);
6091 if (nstate == IEEE80211_S_RUN) {
6092 /* NB: collect bss node again, it may have changed */
6093 ieee80211_free_node(ni);
6094 ni = ieee80211_ref_node(vap->iv_bss);
6096 DPRINTF(sc, ATH_DEBUG_STATE,
6097 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
6098 "capinfo 0x%04x chan %d\n", __func__,
6099 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
6100 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
6102 switch (vap->iv_opmode) {
6103 #ifdef IEEE80211_SUPPORT_TDMA
6104 case IEEE80211_M_AHDEMO:
6105 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
6109 case IEEE80211_M_HOSTAP:
6110 case IEEE80211_M_IBSS:
6111 case IEEE80211_M_MBSS:
6113 * Allocate and setup the beacon frame.
6115 * Stop any previous beacon DMA. This may be
6116 * necessary, for example, when an ibss merge
6117 * causes reconfiguration; there will be a state
6118 * transition from RUN->RUN that means we may
6119 * be called with beacon transmission active.
6121 ath_hal_stoptxdma(ah, sc->sc_bhalq);
6123 error = ath_beacon_alloc(sc, ni);
6127 * If joining an adhoc network defer beacon timer
6128 * configuration to the next beacon frame so we
6129 * have a current TSF to use. Otherwise we're
6130 * starting an ibss/bss so there's no need to delay;
6131 * if this is the first vap moving to RUN state, then
6132 * beacon state needs to be [re]configured.
6134 if (vap->iv_opmode == IEEE80211_M_IBSS &&
6135 ni->ni_tstamp.tsf != 0) {
6136 sc->sc_syncbeacon = 1;
6137 } else if (!sc->sc_beacons) {
6138 #ifdef IEEE80211_SUPPORT_TDMA
6139 if (vap->iv_caps & IEEE80211_C_TDMA)
6140 ath_tdma_config(sc, vap);
6143 ath_beacon_config(sc, vap);
6147 case IEEE80211_M_STA:
6149 * Defer beacon timer configuration to the next
6150 * beacon frame so we have a current TSF to use
6151 * (any TSF collected when scanning is likely old).
6152 * However if it's due to a CSA -> RUN transition,
6153 * force a beacon update so we pick up a lack of
6154 * beacons from an AP in CAC and thus force a
6157 * And, there's also corner cases here where
6158 * after a scan, the AP may have disappeared.
6159 * In that case, we may not receive an actual
6160 * beacon to update the beacon timer and thus we
6161 * won't get notified of the missing beacons.
6163 if (ostate != IEEE80211_S_RUN &&
6164 ostate != IEEE80211_S_SLEEP) {
6165 DPRINTF(sc, ATH_DEBUG_BEACON,
6166 "%s: STA; syncbeacon=1\n", __func__);
6167 sc->sc_syncbeacon = 1;
6169 if (csa_run_transition)
6170 ath_beacon_config(sc, vap);
6175 * Reconfigure beacons during reset; as otherwise
6176 * we won't get the beacon timers reprogrammed
6177 * after a reset and thus we won't pick up a
6178 * beacon miss interrupt.
6180 * Hopefully we'll see a beacon before the BMISS
6181 * timer fires (too often), leading to a STA
6187 case IEEE80211_M_MONITOR:
6189 * Monitor mode vaps have only INIT->RUN and RUN->RUN
6190 * transitions so we must re-enable interrupts here to
6191 * handle the case of a single monitor mode vap.
6193 ath_hal_intrset(ah, sc->sc_imask);
6195 case IEEE80211_M_WDS:
6201 * Let the hal process statistics collected during a
6202 * scan so it can provide calibrated noise floor data.
6204 ath_hal_process_noisefloor(ah);
6206 * Reset rssi stats; maybe not the best place...
6208 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
6209 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
6210 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
6213 * Force awake for RUN mode.
6216 ath_power_setselfgen(sc, HAL_PM_AWAKE);
6217 ath_power_setpower(sc, HAL_PM_AWAKE);
6220 * Finally, start any timers and the task q thread
6221 * (in case we didn't go through SCAN state).
6223 if (ath_longcalinterval != 0) {
6224 /* start periodic recalibration timer */
6225 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
6227 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
6228 "%s: calibration disabled\n", __func__);
6232 taskqueue_unblock(sc->sc_tq);
6233 } else if (nstate == IEEE80211_S_INIT) {
6235 * If there are no vaps left in RUN state then
6236 * shutdown host/driver operation:
6237 * o disable interrupts
6238 * o disable the task queue thread
6239 * o mark beacon processing as stopped
6241 if (!ath_isanyrunningvaps(vap)) {
6242 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
6243 /* disable interrupts */
6244 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
6245 taskqueue_block(sc->sc_tq);
6248 #ifdef IEEE80211_SUPPORT_TDMA
6249 ath_hal_setcca(ah, AH_TRUE);
6251 } else if (nstate == IEEE80211_S_SLEEP) {
6252 /* We're going to sleep, so transition appropriately */
6253 /* For now, only do this if we're a single STA vap */
6254 if (sc->sc_nvaps == 1 &&
6255 vap->iv_opmode == IEEE80211_M_STA) {
6256 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: syncbeacon=%d\n", __func__, sc->sc_syncbeacon);
6259 * Always at least set the self-generated
6260 * frame config to set PWRMGT=1.
6262 ath_power_setselfgen(sc, HAL_PM_NETWORK_SLEEP);
6265 * If we're not syncing beacons, transition
6268 * We stay awake if syncbeacon > 0 in case
6269 * we need to listen for some beacons otherwise
6270 * our beacon timer config may be wrong.
6272 if (sc->sc_syncbeacon == 0) {
6273 ath_power_setpower(sc, HAL_PM_NETWORK_SLEEP);
6279 ieee80211_free_node(ni);
6282 * Restore the power state - either to what it was, or
6283 * to network_sleep if it's alright.
6286 ath_power_restore_power_state(sc);
6292 * Allocate a key cache slot to the station so we can
6293 * setup a mapping from key index to node. The key cache
6294 * slot is needed for managing antenna state and for
6295 * compression when stations do not use crypto. We do
6296 * it uniliaterally here; if crypto is employed this slot
6297 * will be reassigned.
6300 ath_setup_stationkey(struct ieee80211_node *ni)
6302 struct ieee80211vap *vap = ni->ni_vap;
6303 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
6304 ieee80211_keyix keyix, rxkeyix;
6306 /* XXX should take a locked ref to vap->iv_bss */
6307 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
6309 * Key cache is full; we'll fall back to doing
6310 * the more expensive lookup in software. Note
6311 * this also means no h/w compression.
6313 /* XXX msg+statistic */
6316 ni->ni_ucastkey.wk_keyix = keyix;
6317 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
6318 /* NB: must mark device key to get called back on delete */
6319 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
6320 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
6321 /* NB: this will create a pass-thru key entry */
6322 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss);
6327 * Setup driver-specific state for a newly associated node.
6328 * Note that we're called also on a re-associate, the isnew
6329 * param tells us if this is the first time or not.
6332 ath_newassoc(struct ieee80211_node *ni, int isnew)
6334 struct ath_node *an = ATH_NODE(ni);
6335 struct ieee80211vap *vap = ni->ni_vap;
6336 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
6337 const struct ieee80211_txparam *tp = ni->ni_txparms;
6339 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
6340 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
6342 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: reassoc; isnew=%d, is_powersave=%d\n",
6347 an->an_is_powersave);
6350 ath_rate_newassoc(sc, an, isnew);
6351 ATH_NODE_UNLOCK(an);
6354 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
6355 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
6356 ath_setup_stationkey(ni);
6359 * If we're reassociating, make sure that any paused queues
6362 * Now, we may hvae frames in the hardware queue for this node.
6363 * So if we are reassociating and there are frames in the queue,
6364 * we need to go through the cleanup path to ensure that they're
6365 * marked as non-aggregate.
6368 DPRINTF(sc, ATH_DEBUG_NODE,
6369 "%s: %6D: reassoc; is_powersave=%d\n",
6373 an->an_is_powersave);
6375 /* XXX for now, we can't hold the lock across assoc */
6376 ath_tx_node_reassoc(sc, an);
6378 /* XXX for now, we can't hold the lock across wakeup */
6379 if (an->an_is_powersave)
6380 ath_tx_node_wakeup(sc, an);
6385 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
6386 int nchans, struct ieee80211_channel chans[])
6388 struct ath_softc *sc = ic->ic_ifp->if_softc;
6389 struct ath_hal *ah = sc->sc_ah;
6392 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6393 "%s: rd %u cc %u location %c%s\n",
6394 __func__, reg->regdomain, reg->country, reg->location,
6395 reg->ecm ? " ecm" : "");
6397 status = ath_hal_set_channels(ah, chans, nchans,
6398 reg->country, reg->regdomain);
6399 if (status != HAL_OK) {
6400 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
6402 return EINVAL; /* XXX */
6409 ath_getradiocaps(struct ieee80211com *ic,
6410 int maxchans, int *nchans, struct ieee80211_channel chans[])
6412 struct ath_softc *sc = ic->ic_ifp->if_softc;
6413 struct ath_hal *ah = sc->sc_ah;
6415 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
6416 __func__, SKU_DEBUG, CTRY_DEFAULT);
6418 /* XXX check return */
6419 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
6420 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
6425 ath_getchannels(struct ath_softc *sc)
6427 struct ifnet *ifp = sc->sc_ifp;
6428 struct ieee80211com *ic = ifp->if_l2com;
6429 struct ath_hal *ah = sc->sc_ah;
6433 * Collect channel set based on EEPROM contents.
6435 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
6436 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
6437 if (status != HAL_OK) {
6438 if_printf(ifp, "%s: unable to collect channel list from hal, "
6439 "status %d\n", __func__, status);
6442 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
6443 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
6444 /* XXX map Atheros sku's to net80211 SKU's */
6445 /* XXX net80211 types too small */
6446 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
6447 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
6448 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
6449 ic->ic_regdomain.isocc[1] = ' ';
6451 ic->ic_regdomain.ecm = 1;
6452 ic->ic_regdomain.location = 'I';
6454 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6455 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
6456 __func__, sc->sc_eerd, sc->sc_eecc,
6457 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
6458 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
6463 ath_rate_setup(struct ath_softc *sc, u_int mode)
6465 struct ath_hal *ah = sc->sc_ah;
6466 const HAL_RATE_TABLE *rt;
6469 case IEEE80211_MODE_11A:
6470 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
6472 case IEEE80211_MODE_HALF:
6473 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
6475 case IEEE80211_MODE_QUARTER:
6476 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
6478 case IEEE80211_MODE_11B:
6479 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
6481 case IEEE80211_MODE_11G:
6482 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
6484 case IEEE80211_MODE_TURBO_A:
6485 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
6487 case IEEE80211_MODE_TURBO_G:
6488 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
6490 case IEEE80211_MODE_STURBO_A:
6491 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
6493 case IEEE80211_MODE_11NA:
6494 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
6496 case IEEE80211_MODE_11NG:
6497 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
6500 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
6504 sc->sc_rates[mode] = rt;
6505 return (rt != NULL);
6509 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
6511 #define N(a) (sizeof(a)/sizeof(a[0]))
6512 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
6513 static const struct {
6514 u_int rate; /* tx/rx 802.11 rate */
6515 u_int16_t timeOn; /* LED on time (ms) */
6516 u_int16_t timeOff; /* LED off time (ms) */
6532 /* XXX half/quarter rates */
6534 const HAL_RATE_TABLE *rt;
6537 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
6538 rt = sc->sc_rates[mode];
6539 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
6540 for (i = 0; i < rt->rateCount; i++) {
6541 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6542 if (rt->info[i].phy != IEEE80211_T_HT)
6543 sc->sc_rixmap[ieeerate] = i;
6545 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
6547 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
6548 for (i = 0; i < N(sc->sc_hwmap); i++) {
6549 if (i >= rt->rateCount) {
6550 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
6551 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
6554 sc->sc_hwmap[i].ieeerate =
6555 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6556 if (rt->info[i].phy == IEEE80211_T_HT)
6557 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
6558 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
6559 if (rt->info[i].shortPreamble ||
6560 rt->info[i].phy == IEEE80211_T_OFDM)
6561 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6562 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
6563 for (j = 0; j < N(blinkrates)-1; j++)
6564 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
6566 /* NB: this uses the last entry if the rate isn't found */
6567 /* XXX beware of overlow */
6568 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
6569 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
6571 sc->sc_currates = rt;
6572 sc->sc_curmode = mode;
6574 * All protection frames are transmited at 2Mb/s for
6575 * 11g, otherwise at 1Mb/s.
6577 if (mode == IEEE80211_MODE_11G)
6578 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
6580 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
6581 /* NB: caller is responsible for resetting rate control state */
6586 ath_watchdog(void *arg)
6588 struct ath_softc *sc = arg;
6591 ATH_LOCK_ASSERT(sc);
6593 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
6594 struct ifnet *ifp = sc->sc_ifp;
6597 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6599 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
6601 if_printf(ifp, "%s hang detected (0x%x)\n",
6602 hangs & 0xff ? "bb" : "mac", hangs);
6604 if_printf(ifp, "device timeout\n");
6606 #if defined(__DragonFly__)
6609 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
6611 sc->sc_stats.ast_watchdog++;
6613 ath_power_restore_power_state(sc);
6617 * We can't hold the lock across the ath_reset() call.
6619 * And since this routine can't hold a lock and sleep,
6620 * do the reset deferred.
6623 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
6626 #if defined(__DragonFly__)
6627 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
6629 callout_schedule(&sc->sc_wd_ch, hz);
6633 #if defined(__DragonFly__)
6636 * (DragonFly network start)
6639 ath_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
6641 struct ath_softc *sc = ifp->if_softc;
6645 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
6646 wst = wlan_serialize_push();
6648 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) {
6649 ifq_purge(&ifp->if_snd);
6650 wlan_serialize_pop(wst);
6653 ifq_set_oactive(&ifp->if_snd);
6655 m = ifq_dequeue(&ifp->if_snd);
6658 ath_transmit(ifp, m);
6660 ifq_clr_oactive(&ifp->if_snd);
6661 wlan_serialize_pop(wst);
6667 * Fetch the rate control statistics for the given node.
6670 ath_ioctl_ratestats(struct ath_softc *sc, struct ath_rateioctl *rs)
6672 struct ath_node *an;
6673 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
6674 struct ieee80211_node *ni;
6677 /* Perform a lookup on the given node */
6678 ni = ieee80211_find_node(&ic->ic_sta, rs->is_u.macaddr);
6684 /* Lock the ath_node */
6688 /* Fetch the rate control stats for this node */
6689 error = ath_rate_fetch_node_stats(sc, an, rs);
6691 /* No matter what happens here, just drop through */
6693 /* Unlock the ath_node */
6694 ATH_NODE_UNLOCK(an);
6696 /* Unref the node */
6697 ieee80211_node_decref(ni);
6705 * Diagnostic interface to the HAL. This is used by various
6706 * tools to do things like retrieve register contents for
6707 * debugging. The mechanism is intentionally opaque so that
6708 * it can change frequently w/o concern for compatiblity.
6711 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
6713 struct ath_hal *ah = sc->sc_ah;
6714 u_int id = ad->ad_id & ATH_DIAG_ID;
6715 void *indata = NULL;
6716 void *outdata = NULL;
6717 u_int32_t insize = ad->ad_in_size;
6718 u_int32_t outsize = ad->ad_out_size;
6721 if (ad->ad_id & ATH_DIAG_IN) {
6725 indata = kmalloc(insize, M_TEMP, M_INTWAIT);
6726 if (indata == NULL) {
6730 error = copyin(ad->ad_in_data, indata, insize);
6734 if (ad->ad_id & ATH_DIAG_DYN) {
6736 * Allocate a buffer for the results (otherwise the HAL
6737 * returns a pointer to a buffer where we can read the
6738 * results). Note that we depend on the HAL leaving this
6739 * pointer for us to use below in reclaiming the buffer;
6740 * may want to be more defensive.
6742 outdata = kmalloc(outsize, M_TEMP, M_INTWAIT);
6743 if (outdata == NULL) {
6751 if (id != HAL_DIAG_REGS)
6752 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6755 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
6756 if (outsize < ad->ad_out_size)
6757 ad->ad_out_size = outsize;
6758 if (outdata != NULL)
6759 error = copyout(outdata, ad->ad_out_data,
6766 if (id != HAL_DIAG_REGS)
6767 ath_power_restore_power_state(sc);
6771 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
6772 kfree(indata, M_TEMP);
6773 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
6774 kfree(outdata, M_TEMP);
6777 #endif /* ATH_DIAGAPI */
6779 #if defined(__DragonFly__)
6782 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data,
6783 struct ucred *cred __unused)
6788 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
6792 #define IS_RUNNING(ifp) \
6793 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING))
6794 struct ath_softc *sc = ifp->if_softc;
6795 struct ieee80211com *ic = ifp->if_l2com;
6796 struct ifreq *ifr = (struct ifreq *)data;
6797 const HAL_RATE_TABLE *rt;
6802 if (IS_RUNNING(ifp)) {
6804 * To avoid rescanning another access point,
6805 * do not call ath_init() here. Instead,
6806 * only reflect promisc mode settings.
6809 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6811 ath_power_restore_power_state(sc);
6813 } else if (ifp->if_flags & IFF_UP) {
6815 * Beware of being called during attach/detach
6816 * to reset promiscuous mode. In that case we
6817 * will still be marked UP but not RUNNING.
6818 * However trying to re-init the interface
6819 * is the wrong thing to do as we've already
6820 * torn down much of our state. There's
6821 * probably a better way to deal with this.
6823 if (!sc->sc_invalid)
6824 ath_init(sc); /* XXX lose error */
6827 ath_stop_locked(ifp);
6828 if (!sc->sc_invalid)
6829 ath_power_setpower(sc, HAL_PM_FULL_SLEEP);
6835 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
6838 /* NB: embed these numbers to get a consistent view */
6839 #if defined(__DragonFly__)
6840 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
6841 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
6843 sc->sc_stats.ast_tx_packets = ifp->if_get_counter(ifp,
6844 IFCOUNTER_OPACKETS);
6845 sc->sc_stats.ast_rx_packets = ifp->if_get_counter(ifp,
6846 IFCOUNTER_IPACKETS);
6848 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi);
6849 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi);
6850 #ifdef IEEE80211_SUPPORT_TDMA
6851 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap);
6852 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam);
6854 rt = sc->sc_currates;
6855 sc->sc_stats.ast_tx_rate =
6856 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC;
6857 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT)
6858 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS;
6859 error = copyout(&sc->sc_stats,
6860 ifr->ifr_data, sizeof (sc->sc_stats));
6862 case SIOCGATHAGSTATS:
6863 error = copyout(&sc->sc_aggr_stats,
6864 ifr->ifr_data, sizeof (sc->sc_aggr_stats));
6867 error = priv_check(curthread, PRIV_DRIVER);
6869 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
6870 memset(&sc->sc_aggr_stats, 0,
6871 sizeof(sc->sc_aggr_stats));
6872 memset(&sc->sc_intr_stats, 0,
6873 sizeof(sc->sc_intr_stats));
6878 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
6880 case SIOCGATHPHYERR:
6881 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr);
6884 case SIOCGATHSPECTRAL:
6885 error = ath_ioctl_spectral(sc,(struct ath_diag*) ifr);
6887 case SIOCGATHNODERATESTATS:
6888 error = ath_ioctl_ratestats(sc, (struct ath_rateioctl *) ifr);
6891 error = ether_ioctl(ifp, cmd, data);
6902 * Announce various information on device/driver attach.
6905 ath_announce(struct ath_softc *sc)
6907 struct ifnet *ifp = sc->sc_ifp;
6908 struct ath_hal *ah = sc->sc_ah;
6910 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
6911 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
6912 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
6913 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
6914 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
6917 for (i = 0; i <= WME_AC_VO; i++) {
6918 struct ath_txq *txq = sc->sc_ac2q[i];
6919 if_printf(ifp, "Use hw queue %u for %s traffic\n",
6920 txq->axq_qnum, ieee80211_wme_acnames[i]);
6922 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
6923 sc->sc_cabq->axq_qnum);
6924 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
6926 if (ath_rxbuf != ATH_RXBUF)
6927 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
6928 if (ath_txbuf != ATH_TXBUF)
6929 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
6930 if (sc->sc_mcastkey && bootverbose)
6931 if_printf(ifp, "using multicast key search\n");
6935 ath_dfs_tasklet(void *p, int npending)
6937 struct ath_softc *sc = (struct ath_softc *) p;
6938 struct ifnet *ifp = sc->sc_ifp;
6939 struct ieee80211com *ic = ifp->if_l2com;
6942 * If previous processing has found a radar event,
6943 * signal this to the net80211 layer to begin DFS
6946 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
6947 /* DFS event found, initiate channel change */
6949 * XXX doesn't currently tell us whether the event
6950 * XXX was found in the primary or extension
6954 ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
6955 IEEE80211_UNLOCK(ic);
6960 * Enable/disable power save. This must be called with
6961 * no TX driver locks currently held, so it should only
6962 * be called from the RX path (which doesn't hold any
6966 ath_node_powersave(struct ieee80211_node *ni, int enable)
6969 struct ath_node *an = ATH_NODE(ni);
6970 struct ieee80211com *ic = ni->ni_ic;
6971 struct ath_softc *sc = ic->ic_ifp->if_softc;
6972 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6974 /* XXX and no TXQ locks should be held here */
6976 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n",
6982 /* Suspend or resume software queue handling */
6984 ath_tx_node_sleep(sc, an);
6986 ath_tx_node_wakeup(sc, an);
6988 /* Update net80211 state */
6989 avp->av_node_ps(ni, enable);
6991 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6993 /* Update net80211 state */
6994 avp->av_node_ps(ni, enable);
6995 #endif/* ATH_SW_PSQ */
6999 * Notification from net80211 that the powersave queue state has
7002 * Since the software queue also may have some frames:
7004 * + if the node software queue has frames and the TID state
7005 * is 0, we set the TIM;
7006 * + if the node and the stack are both empty, we clear the TIM bit.
7007 * + If the stack tries to set the bit, always set it.
7008 * + If the stack tries to clear the bit, only clear it if the
7009 * software queue in question is also cleared.
7011 * TODO: this is called during node teardown; so let's ensure this
7012 * is all correctly handled and that the TIM bit is cleared.
7013 * It may be that the node flush is called _AFTER_ the net80211
7014 * stack clears the TIM.
7016 * Here is the racy part. Since it's possible >1 concurrent,
7017 * overlapping TXes will appear complete with a TX completion in
7018 * another thread, it's possible that the concurrent TIM calls will
7019 * clash. We can't hold the node lock here because setting the
7020 * TIM grabs the net80211 comlock and this may cause a LOR.
7021 * The solution is either to totally serialise _everything_ at
7022 * this point (ie, all TX, completion and any reset/flush go into
7023 * one taskqueue) or a new "ath TIM lock" needs to be created that
7024 * just wraps the driver state change and this call to avp->av_set_tim().
7026 * The same race exists in the net80211 power save queue handling
7027 * as well. Since multiple transmitting threads may queue frames
7028 * into the driver, as well as ps-poll and the driver transmitting
7029 * frames (and thus clearing the psq), it's quite possible that
7030 * a packet entering the PSQ and a ps-poll being handled will
7031 * race, causing the TIM to be cleared and not re-set.
7034 ath_node_set_tim(struct ieee80211_node *ni, int enable)
7037 struct ieee80211com *ic = ni->ni_ic;
7038 struct ath_softc *sc = ic->ic_ifp->if_softc;
7039 struct ath_node *an = ATH_NODE(ni);
7040 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
7044 an->an_stack_psq = enable;
7047 * This will get called for all operating modes,
7048 * even if avp->av_set_tim is unset.
7049 * It's currently set for hostap/ibss modes; but
7050 * the same infrastructure is used for both STA
7051 * and AP/IBSS node power save.
7053 if (avp->av_set_tim == NULL) {
7059 * If setting the bit, always set it here.
7060 * If clearing the bit, only clear it if the
7061 * software queue is also empty.
7063 * If the node has left power save, just clear the TIM
7064 * bit regardless of the state of the power save queue.
7066 * XXX TODO: although atomics are used, it's quite possible
7067 * that a race will occur between this and setting/clearing
7068 * in another thread. TX completion will occur always in
7069 * one thread, however setting/clearing the TIM bit can come
7070 * from a variety of different process contexts!
7072 if (enable && an->an_tim_set == 1) {
7073 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7074 "%s: %6D: enable=%d, tim_set=1, ignoring\n",
7080 } else if (enable) {
7081 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7082 "%s: %6D: enable=%d, enabling TIM\n",
7089 changed = avp->av_set_tim(ni, enable);
7090 } else if (an->an_swq_depth == 0) {
7092 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7093 "%s: %6D: enable=%d, an_swq_depth == 0, disabling\n",
7100 changed = avp->av_set_tim(ni, enable);
7101 } else if (! an->an_is_powersave) {
7103 * disable regardless; the node isn't in powersave now
7105 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7106 "%s: %6D: enable=%d, an_pwrsave=0, disabling\n",
7113 changed = avp->av_set_tim(ni, enable);
7116 * psq disable, node is currently in powersave, node
7117 * software queue isn't empty, so don't clear the TIM bit
7121 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7122 "%s: %6D: enable=%d, an_swq_depth > 0, ignoring\n",
7132 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
7135 * Some operating modes don't set av_set_tim(), so don't
7138 if (avp->av_set_tim == NULL)
7141 return (avp->av_set_tim(ni, enable));
7142 #endif /* ATH_SW_PSQ */
7146 * Set or update the TIM from the software queue.
7148 * Check the software queue depth before attempting to do lock
7149 * anything; that avoids trying to obtain the lock. Then,
7150 * re-check afterwards to ensure nothing has changed in the
7153 * set: This is designed to be called from the TX path, after
7154 * a frame has been queued; to see if the swq > 0.
7156 * clear: This is designed to be called from the buffer completion point
7157 * (right now it's ath_tx_default_comp()) where the state of
7158 * a software queue has changed.
7160 * It makes sense to place it at buffer free / completion rather
7161 * than after each software queue operation, as there's no real
7162 * point in churning the TIM bit as the last frames in the software
7163 * queue are transmitted. If they fail and we retry them, we'd
7164 * just be setting the TIM bit again anyway.
7167 ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni,
7171 struct ath_node *an;
7172 struct ath_vap *avp;
7174 /* Don't do this for broadcast/etc frames */
7179 avp = ATH_VAP(ni->ni_vap);
7182 * And for operating modes without the TIM handler set, let's
7185 if (avp->av_set_tim == NULL)
7188 ATH_TX_LOCK_ASSERT(sc);
7191 if (an->an_is_powersave &&
7192 an->an_tim_set == 0 &&
7193 an->an_swq_depth != 0) {
7194 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7195 "%s: %6D: swq_depth>0, tim_set=0, set!\n",
7200 (void) avp->av_set_tim(ni, 1);
7204 * Don't bother grabbing the lock unless the queue is empty.
7206 if (an->an_swq_depth != 0)
7209 if (an->an_is_powersave &&
7210 an->an_stack_psq == 0 &&
7211 an->an_tim_set == 1 &&
7212 an->an_swq_depth == 0) {
7213 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7214 "%s: %6D: swq_depth=0, tim_set=1, psq_set=0,"
7220 (void) avp->av_set_tim(ni, 0);
7225 #endif /* ATH_SW_PSQ */
7229 * A device_printf() equivalent that does not require gcc hacks
7232 athdev_printf(device_t dev, const char *ctl, ...)
7237 retval = device_print_prettyname(dev);
7238 __va_start(va, ctl);
7239 retval += kvprintf(ctl, va);
7247 * Received a ps-poll frame from net80211.
7249 * Here we get a chance to serve out a software-queued frame ourselves
7250 * before we punt it to net80211 to transmit us one itself - either
7251 * because there's traffic in the net80211 psq, or a NULL frame to
7252 * indicate there's nothing else.
7255 ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m)
7258 struct ath_node *an;
7259 struct ath_vap *avp;
7260 struct ieee80211com *ic = ni->ni_ic;
7261 struct ath_softc *sc = ic->ic_ifp->if_softc;
7269 * Unassociated (temporary node) station.
7271 if (ni->ni_associd == 0)
7275 * We do have an active node, so let's begin looking into it.
7278 avp = ATH_VAP(ni->ni_vap);
7281 * For now, we just call the original ps-poll method.
7282 * Once we're ready to flip this on:
7284 * + Set leak to 1, as no matter what we're going to have
7286 * + Check the software queue and if there's something in it,
7287 * schedule the highest TID thas has traffic from this node.
7288 * Then make sure we schedule the software scheduler to
7289 * run so it picks up said frame.
7291 * That way whatever happens, we'll at least send _a_ frame
7292 * to the given node.
7294 * Again, yes, it's crappy QoS if the node has multiple
7295 * TIDs worth of traffic - but let's get it working first
7296 * before we optimise it.
7298 * Also yes, there's definitely latency here - we're not
7299 * direct dispatching to the hardware in this path (and
7300 * we're likely being called from the packet receive path,
7301 * so going back into TX may be a little hairy!) but again
7302 * I'd like to get this working first before optimising
7309 * Legacy - we're called and the node isn't asleep.
7312 if (! an->an_is_powersave) {
7313 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7314 "%s: %6D: not in powersave?\n",
7319 avp->av_recv_pspoll(ni, m);
7324 * We're in powersave.
7328 an->an_leak_count = 1;
7331 * Now, if there's no frames in the node, just punt to
7334 * Don't bother checking if the TIM bit is set, we really
7335 * only care if there are any frames here!
7337 if (an->an_swq_depth == 0) {
7339 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7340 "%s: %6D: SWQ empty; punting to net80211\n",
7344 avp->av_recv_pspoll(ni, m);
7349 * Ok, let's schedule the highest TID that has traffic
7350 * and then schedule something.
7352 for (tid = IEEE80211_TID_SIZE - 1; tid >= 0; tid--) {
7353 struct ath_tid *atid = &an->an_tid[tid];
7357 if (atid->axq_depth == 0)
7359 ath_tx_tid_sched(sc, atid);
7361 * XXX we could do a direct call to the TXQ
7362 * scheduler code here to optimise latency
7363 * at the expense of a REALLY deep callstack.
7366 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
7367 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7368 "%s: %6D: leaking frame to TID %d\n",
7379 * XXX nothing in the TIDs at this point? Eek.
7381 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7382 "%s: %6D: TIDs empty, but ath_node showed traffic?!\n",
7386 avp->av_recv_pspoll(ni, m);
7388 avp->av_recv_pspoll(ni, m);
7389 #endif /* ATH_SW_PSQ */
7392 MODULE_VERSION(if_ath, 1);
7393 MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
7394 #if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ) || defined(ATH_DEBUG_ALQ)
7395 MODULE_DEPEND(if_ath, alq, 1, 1, 1);