sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35 #include <linux/workqueue.h>
  36
  37 extern struct drm_i915_private *i915_mch_dev;
  38
  39 extern void i915_pineview_get_mem_freq(struct drm_device *dev);
  40 extern void i915_ironlake_get_mem_freq(struct drm_device *dev);
  41 static int i915_driver_unload_int(struct drm_device *dev, bool locked);
  42
  43 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  44 {
  45         /*
  46          * The dri breadcrumb update races against the drm master disappearing.
  47          * Instead of trying to fix this (this is by far not the only ums issue)
  48          * just don't do the update in kms mode.
  49          */
  50         if (drm_core_check_feature(dev, DRIVER_MODESET))
  51                 return;
  52
  53         /* XXX: don't do it at all actually */
  54         return;
  55 }
  56
  57 static void i915_write_hws_pga(struct drm_device *dev)
  58 {
  59         drm_i915_private_t *dev_priv = dev->dev_private;
  60         u32 addr;
  61
  62         addr = dev_priv->status_page_dmah->busaddr;
  63         if (INTEL_INFO(dev)->gen >= 4)
  64                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  65         I915_WRITE(HWS_PGA, addr);
  66 }
  67
  68 /**
  69  * Sets up the hardware status page for devices that need a physical address
  70  * in the register.
  71  */
  72 static int i915_init_phys_hws(struct drm_device *dev)
  73 {
  74         drm_i915_private_t *dev_priv = dev->dev_private;
  75         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  76
  77         /*
  78          * Program Hardware Status Page
  79          * XXXKIB Keep 4GB limit for allocation for now.  This method
  80          * of allocation is used on <= 965 hardware, that has several
  81          * erratas regarding the use of physical memory > 4 GB.
  82          */
  83         DRM_UNLOCK(dev);
  84         dev_priv->status_page_dmah =
  85                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  86         DRM_LOCK(dev);
  87         if (!dev_priv->status_page_dmah) {
  88                 DRM_ERROR("Can not allocate hardware status page\n");
  89                 return -ENOMEM;
  90         }
  91         ring->status_page.page_addr = dev_priv->hw_status_page =
  92             dev_priv->status_page_dmah->vaddr;
  93         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  94
  95         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  96
  97         i915_write_hws_pga(dev);
  98         DRM_DEBUG("Enabled hardware status page, phys %jx\n",
  99             (uintmax_t)dev_priv->dma_status_page);
 100         return 0;
 101 }
 102
 103 /**
 104  * Frees the hardware status page, whether it's a physical address or a virtual
 105  * address set up by the X Server.
 106  */
 107 static void i915_free_hws(struct drm_device *dev)
 108 {
 109         drm_i915_private_t *dev_priv = dev->dev_private;
 110         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 111
 112         if (dev_priv->status_page_dmah) {
 113                 drm_pci_free(dev, dev_priv->status_page_dmah);
 114                 dev_priv->status_page_dmah = NULL;
 115         }
 116
 117         if (dev_priv->status_gfx_addr) {
 118                 dev_priv->status_gfx_addr = 0;
 119                 ring->status_page.gfx_addr = 0;
 120                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 121         }
 122
 123         /* Need to rewrite hardware status page */
 124         I915_WRITE(HWS_PGA, 0x1ffff000);
 125 }
 126
 127 void i915_kernel_lost_context(struct drm_device * dev)
 128 {
 129         drm_i915_private_t *dev_priv = dev->dev_private;
 130         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 131
 132         /*
 133          * We should never lose context on the ring with modesetting
 134          * as we don't expose it to userspace
 135          */
 136         if (drm_core_check_feature(dev, DRIVER_MODESET))
 137                 return;
 138
 139         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 140         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 141         ring->space = ring->head - (ring->tail + 8);
 142         if (ring->space < 0)
 143                 ring->space += ring->size;
 144
 145 #if 1
 146         KIB_NOTYET();
 147 #else
 148         if (!dev->primary->master)
 149                 return;
 150 #endif
 151
 152         if (ring->head == ring->tail && dev_priv->sarea_priv)
 153                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 154 }
 155
 156 static int i915_dma_cleanup(struct drm_device * dev)
 157 {
 158         drm_i915_private_t *dev_priv = dev->dev_private;
 159         int i;
 160
 161
 162         /* Make sure interrupts are disabled here because the uninstall ioctl
 163          * may not have been called from userspace and after dev_private
 164          * is freed, it's too late.
 165          */
 166         if (dev->irq_enabled)
 167                 drm_irq_uninstall(dev);
 168
 169         for (i = 0; i < I915_NUM_RINGS; i++)
 170                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 171
 172         /* Clear the HWS virtual address at teardown */
 173         if (I915_NEED_GFX_HWS(dev))
 174                 i915_free_hws(dev);
 175
 176         return 0;
 177 }
 178
 179 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 180 {
 181         drm_i915_private_t *dev_priv = dev->dev_private;
 182         int ret;
 183
 184         dev_priv->sarea = drm_getsarea(dev);
 185         if (!dev_priv->sarea) {
 186                 DRM_ERROR("can not find sarea!\n");
 187                 i915_dma_cleanup(dev);
 188                 return -EINVAL;
 189         }
 190
 191         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 192             ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
 193
 194         if (init->ring_size != 0) {
 195                 if (LP_RING(dev_priv)->obj != NULL) {
 196                         i915_dma_cleanup(dev);
 197                         DRM_ERROR("Client tried to initialize ringbuffer in "
 198                                   "GEM mode\n");
 199                         return -EINVAL;
 200                 }
 201
 202                 ret = intel_render_ring_init_dri(dev,
 203                                                  init->ring_start,
 204                                                  init->ring_size);
 205                 if (ret) {
 206                         i915_dma_cleanup(dev);
 207                         return ret;
 208                 }
 209         }
 210
 211         dev_priv->cpp = init->cpp;
 212         dev_priv->back_offset = init->back_offset;
 213         dev_priv->front_offset = init->front_offset;
 214         dev_priv->current_page = 0;
 215         dev_priv->sarea_priv->pf_current_page = 0;
 216
 217         /* Allow hardware batchbuffers unless told otherwise.
 218          */
 219         dev_priv->allow_batchbuffer = 1;
 220
 221         return 0;
 222 }
 223
 224 static int i915_dma_resume(struct drm_device * dev)
 225 {
 226         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 227         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 228
 229         DRM_DEBUG("\n");
 230
 231         if (ring->map.handle == NULL) {
 232                 DRM_ERROR("can not ioremap virtual address for"
 233                           " ring buffer\n");
 234                 return -ENOMEM;
 235         }
 236
 237         /* Program Hardware Status Page */
 238         if (!ring->status_page.page_addr) {
 239                 DRM_ERROR("Can not find hardware status page\n");
 240                 return -EINVAL;
 241         }
 242         DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
 243         if (ring->status_page.gfx_addr != 0)
 244                 intel_ring_setup_status_page(ring);
 245         else
 246                 i915_write_hws_pga(dev);
 247
 248         DRM_DEBUG("Enabled hardware status page\n");
 249
 250         return 0;
 251 }
 252
 253 static int i915_dma_init(struct drm_device *dev, void *data,
 254                          struct drm_file *file_priv)
 255 {
 256         drm_i915_init_t *init = data;
 257         int retcode = 0;
 258
 259         switch (init->func) {
 260         case I915_INIT_DMA:
 261                 retcode = i915_initialize(dev, init);
 262                 break;
 263         case I915_CLEANUP_DMA:
 264                 retcode = i915_dma_cleanup(dev);
 265                 break;
 266         case I915_RESUME_DMA:
 267                 retcode = i915_dma_resume(dev);
 268                 break;
 269         default:
 270                 retcode = -EINVAL;
 271                 break;
 272         }
 273
 274         return retcode;
 275 }
 276
 277 /* Implement basically the same security restrictions as hardware does
 278  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 279  *
 280  * Most of the calculations below involve calculating the size of a
 281  * particular instruction.  It's important to get the size right as
 282  * that tells us where the next instruction to check is.  Any illegal
 283  * instruction detected will be given a size of zero, which is a
 284  * signal to abort the rest of the buffer.
 285  */
 286 static int do_validate_cmd(int cmd)
 287 {
 288         switch (((cmd >> 29) & 0x7)) {
 289         case 0x0:
 290                 switch ((cmd >> 23) & 0x3f) {
 291                 case 0x0:
 292                         return 1;       /* MI_NOOP */
 293                 case 0x4:
 294                         return 1;       /* MI_FLUSH */
 295                 default:
 296                         return 0;       /* disallow everything else */
 297                 }
 298                 break;
 299         case 0x1:
 300                 return 0;       /* reserved */
 301         case 0x2:
 302                 return (cmd & 0xff) + 2;        /* 2d commands */
 303         case 0x3:
 304                 if (((cmd >> 24) & 0x1f) <= 0x18)
 305                         return 1;
 306
 307                 switch ((cmd >> 24) & 0x1f) {
 308                 case 0x1c:
 309                         return 1;
 310                 case 0x1d:
 311                         switch ((cmd >> 16) & 0xff) {
 312                         case 0x3:
 313                                 return (cmd & 0x1f) + 2;
 314                         case 0x4:
 315                                 return (cmd & 0xf) + 2;
 316                         default:
 317                                 return (cmd & 0xffff) + 2;
 318                         }
 319                 case 0x1e:
 320                         if (cmd & (1 << 23))
 321                                 return (cmd & 0xffff) + 1;
 322                         else
 323                                 return 1;
 324                 case 0x1f:
 325                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 326                                 return (cmd & 0x1ffff) + 2;
 327                         else if (cmd & (1 << 17))       /* indirect random */
 328                                 if ((cmd & 0xffff) == 0)
 329                                         return 0;       /* unknown length, too hard */
 330                                 else
 331                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 332                         else
 333                                 return 2;       /* indirect sequential */
 334                 default:
 335                         return 0;
 336                 }
 337         default:
 338                 return 0;
 339         }
 340
 341         return 0;
 342 }
 343
 344 static int validate_cmd(int cmd)
 345 {
 346         int ret = do_validate_cmd(cmd);
 347
 348 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 349
 350         return ret;
 351 }
 352
 353 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 354                           int dwords)
 355 {
 356         drm_i915_private_t *dev_priv = dev->dev_private;
 357         int i, ret;
 358
 359         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 360                 return -EINVAL;
 361
 362         ret = BEGIN_LP_RING((dwords+1)&~1);
 363         if (ret)
 364                 return ret;
 365
 366         for (i = 0; i < dwords;) {
 367                 int cmd, sz;
 368
 369                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 370                         return -EINVAL;
 371
 372                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 373                         return -EINVAL;
 374
 375                 OUT_RING(cmd);
 376
 377                 while (++i, --sz) {
 378                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 379                                                          sizeof(cmd))) {
 380                                 return -EINVAL;
 381                         }
 382                         OUT_RING(cmd);
 383                 }
 384         }
 385
 386         if (dwords & 1)
 387                 OUT_RING(0);
 388
 389         ADVANCE_LP_RING();
 390
 391         return 0;
 392 }
 393
 394 int i915_emit_box(struct drm_device * dev,
 395                   struct drm_clip_rect *boxes,
 396                   int i, int DR1, int DR4)
 397 {
 398         struct drm_clip_rect box;
 399
 400         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 401                 return -EFAULT;
 402         }
 403
 404         return (i915_emit_box_p(dev, &box, DR1, DR4));
 405 }
 406
 407 int
 408 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
 409     int DR1, int DR4)
 410 {
 411         drm_i915_private_t *dev_priv = dev->dev_private;
 412         int ret;
 413
 414         if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
 415             box->x2 <= 0) {
 416                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 417                           box->x1, box->y1, box->x2, box->y2);
 418                 return -EINVAL;
 419         }
 420
 421         if (INTEL_INFO(dev)->gen >= 4) {
 422                 ret = BEGIN_LP_RING(4);
 423                 if (ret != 0)
 424                         return (ret);
 425
 426                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 427                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 428                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 429                 OUT_RING(DR4);
 430         } else {
 431                 ret = BEGIN_LP_RING(6);
 432                 if (ret != 0)
 433                         return (ret);
 434
 435                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 436                 OUT_RING(DR1);
 437                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 438                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 439                 OUT_RING(DR4);
 440                 OUT_RING(0);
 441         }
 442         ADVANCE_LP_RING();
 443
 444         return 0;
 445 }
 446
 447 /* XXX: Emitting the counter should really be moved to part of the IRQ
 448  * emit. For now, do it in both places:
 449  */
 450
 451 static void i915_emit_breadcrumb(struct drm_device *dev)
 452 {
 453         drm_i915_private_t *dev_priv = dev->dev_private;
 454
 455         if (++dev_priv->counter > 0x7FFFFFFFUL)
 456                 dev_priv->counter = 0;
 457         if (dev_priv->sarea_priv)
 458                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 459
 460         if (BEGIN_LP_RING(4) == 0) {
 461                 OUT_RING(MI_STORE_DWORD_INDEX);
 462                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 463                 OUT_RING(dev_priv->counter);
 464                 OUT_RING(0);
 465                 ADVANCE_LP_RING();
 466         }
 467 }
 468
 469 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 470     drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
 471 {
 472         int nbox = cmd->num_cliprects;
 473         int i = 0, count, ret;
 474
 475         if (cmd->sz & 0x3) {
 476                 DRM_ERROR("alignment\n");
 477                 return -EINVAL;
 478         }
 479
 480         i915_kernel_lost_context(dev);
 481
 482         count = nbox ? nbox : 1;
 483
 484         for (i = 0; i < count; i++) {
 485                 if (i < nbox) {
 486                         ret = i915_emit_box_p(dev, &cmd->cliprects[i],
 487                             cmd->DR1, cmd->DR4);
 488                         if (ret)
 489                                 return ret;
 490                 }
 491
 492                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 493                 if (ret)
 494                         return ret;
 495         }
 496
 497         i915_emit_breadcrumb(dev);
 498         return 0;
 499 }
 500
 501 static int
 502 i915_dispatch_batchbuffer(struct drm_device * dev,
 503     drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
 504 {
 505         drm_i915_private_t *dev_priv = dev->dev_private;
 506         int nbox = batch->num_cliprects;
 507         int i, count, ret;
 508
 509         if ((batch->start | batch->used) & 0x7) {
 510                 DRM_ERROR("alignment\n");
 511                 return -EINVAL;
 512         }
 513
 514         i915_kernel_lost_context(dev);
 515
 516         count = nbox ? nbox : 1;
 517
 518         for (i = 0; i < count; i++) {
 519                 if (i < nbox) {
 520                         int ret = i915_emit_box_p(dev, &cliprects[i],
 521                             batch->DR1, batch->DR4);
 522                         if (ret)
 523                                 return ret;
 524                 }
 525
 526                 if (!IS_I830(dev) && !IS_845G(dev)) {
 527                         ret = BEGIN_LP_RING(2);
 528                         if (ret != 0)
 529                                 return (ret);
 530
 531                         if (INTEL_INFO(dev)->gen >= 4) {
 532                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
 533                                     MI_BATCH_NON_SECURE_I965);
 534                                 OUT_RING(batch->start);
 535                         } else {
 536                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 537                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 538                         }
 539                 } else {
 540                         ret = BEGIN_LP_RING(4);
 541                         if (ret != 0)
 542                                 return (ret);
 543
 544                         OUT_RING(MI_BATCH_BUFFER);
 545                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 546                         OUT_RING(batch->start + batch->used - 4);
 547                         OUT_RING(0);
 548                 }
 549                 ADVANCE_LP_RING();
 550         }
 551
 552         i915_emit_breadcrumb(dev);
 553
 554         return 0;
 555 }
 556
 557 static int i915_dispatch_flip(struct drm_device * dev)
 558 {
 559         drm_i915_private_t *dev_priv = dev->dev_private;
 560         int ret;
 561
 562         if (!dev_priv->sarea_priv)
 563                 return -EINVAL;
 564
 565         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 566                   __func__,
 567                   dev_priv->current_page,
 568                   dev_priv->sarea_priv->pf_current_page);
 569
 570         i915_kernel_lost_context(dev);
 571
 572         ret = BEGIN_LP_RING(10);
 573         if (ret)
 574                 return ret;
 575         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 576         OUT_RING(0);
 577
 578         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 579         OUT_RING(0);
 580         if (dev_priv->current_page == 0) {
 581                 OUT_RING(dev_priv->back_offset);
 582                 dev_priv->current_page = 1;
 583         } else {
 584                 OUT_RING(dev_priv->front_offset);
 585                 dev_priv->current_page = 0;
 586         }
 587         OUT_RING(0);
 588
 589         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 590         OUT_RING(0);
 591
 592         ADVANCE_LP_RING();
 593
 594         if (++dev_priv->counter > 0x7FFFFFFFUL)
 595                 dev_priv->counter = 0;
 596         if (dev_priv->sarea_priv)
 597                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 598
 599         if (BEGIN_LP_RING(4) == 0) {
 600                 OUT_RING(MI_STORE_DWORD_INDEX);
 601                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 602                 OUT_RING(dev_priv->counter);
 603                 OUT_RING(0);
 604                 ADVANCE_LP_RING();
 605         }
 606
 607         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 608         return 0;
 609 }
 610
 611 static int i915_quiescent(struct drm_device *dev)
 612 {
 613         i915_kernel_lost_context(dev);
 614         return intel_ring_idle(LP_RING(dev->dev_private));
 615 }
 616
 617 static int
 618 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 619 {
 620         int ret;
 621
 622         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 623
 624         DRM_LOCK(dev);
 625         ret = i915_quiescent(dev);
 626         DRM_UNLOCK(dev);
 627
 628         return (ret);
 629 }
 630
 631 static int i915_batchbuffer(struct drm_device *dev, void *data,
 632                             struct drm_file *file_priv)
 633 {
 634         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 635         drm_i915_sarea_t *sarea_priv;
 636         drm_i915_batchbuffer_t *batch = data;
 637         struct drm_clip_rect *cliprects;
 638         size_t cliplen;
 639         int ret;
 640
 641         if (!dev_priv->allow_batchbuffer) {
 642                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 643                 return -EINVAL;
 644         }
 645         DRM_UNLOCK(dev);
 646
 647         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 648                   batch->start, batch->used, batch->num_cliprects);
 649
 650         cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
 651         if (batch->num_cliprects < 0)
 652                 return -EFAULT;
 653         if (batch->num_cliprects != 0) {
 654                 cliprects = kmalloc(batch->num_cliprects *
 655                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 656                     M_WAITOK | M_ZERO);
 657
 658                 ret = -copyin(batch->cliprects, cliprects,
 659                     batch->num_cliprects * sizeof(struct drm_clip_rect));
 660                 if (ret != 0) {
 661                         DRM_LOCK(dev);
 662                         goto fail_free;
 663                 }
 664         } else
 665                 cliprects = NULL;
 666
 667         DRM_LOCK(dev);
 668         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 669         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 670
 671         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 672         if (sarea_priv)
 673                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 674
 675 fail_free:
 676         drm_free(cliprects, DRM_MEM_DMA);
 677         return ret;
 678 }
 679
 680 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 681                           struct drm_file *file_priv)
 682 {
 683         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 684         drm_i915_sarea_t *sarea_priv;
 685         drm_i915_cmdbuffer_t *cmdbuf = data;
 686         struct drm_clip_rect *cliprects = NULL;
 687         void *batch_data;
 688         int ret;
 689
 690         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 691                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 692
 693         if (cmdbuf->num_cliprects < 0)
 694                 return -EINVAL;
 695
 696         DRM_UNLOCK(dev);
 697
 698         batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
 699
 700         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
 701         if (ret != 0) {
 702                 DRM_LOCK(dev);
 703                 goto fail_batch_free;
 704         }
 705
 706         if (cmdbuf->num_cliprects) {
 707                 cliprects = kmalloc(cmdbuf->num_cliprects *
 708                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 709                     M_WAITOK | M_ZERO);
 710                 ret = -copyin(cmdbuf->cliprects, cliprects,
 711                     cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
 712                 if (ret != 0) {
 713                         DRM_LOCK(dev);
 714                         goto fail_clip_free;
 715                 }
 716         }
 717
 718         DRM_LOCK(dev);
 719         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 720         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 721         if (ret) {
 722                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 723                 goto fail_clip_free;
 724         }
 725
 726         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 727         if (sarea_priv)
 728                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 729
 730 fail_clip_free:
 731         drm_free(cliprects, DRM_MEM_DMA);
 732 fail_batch_free:
 733         drm_free(batch_data, DRM_MEM_DMA);
 734         return ret;
 735 }
 736
 737 static int i915_emit_irq(struct drm_device * dev)
 738 {
 739         drm_i915_private_t *dev_priv = dev->dev_private;
 740 #if 0
 741         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 742 #endif
 743
 744         i915_kernel_lost_context(dev);
 745
 746         DRM_DEBUG("i915: emit_irq\n");
 747
 748         dev_priv->counter++;
 749         if (dev_priv->counter > 0x7FFFFFFFUL)
 750                 dev_priv->counter = 1;
 751 #if 0
 752         if (master_priv->sarea_priv)
 753                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 754 #else
 755         if (dev_priv->sarea_priv)
 756                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 757 #endif
 758
 759         if (BEGIN_LP_RING(4) == 0) {
 760                 OUT_RING(MI_STORE_DWORD_INDEX);
 761                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 762                 OUT_RING(dev_priv->counter);
 763                 OUT_RING(MI_USER_INTERRUPT);
 764                 ADVANCE_LP_RING();
 765         }
 766
 767         return dev_priv->counter;
 768 }
 769
 770 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 771 {
 772         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 773 #if 0
 774         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 775 #endif
 776         int ret = 0;
 777         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 778
 779         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 780                   READ_BREADCRUMB(dev_priv));
 781
 782 #if 0
 783         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 784                 if (master_priv->sarea_priv)
 785                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 786                 return 0;
 787         }
 788
 789         if (master_priv->sarea_priv)
 790                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 791 #else
 792         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 793                 if (dev_priv->sarea_priv) {
 794                         dev_priv->sarea_priv->last_dispatch =
 795                                 READ_BREADCRUMB(dev_priv);
 796                 }
 797                 return 0;
 798         }
 799
 800         if (dev_priv->sarea_priv)
 801                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 802 #endif
 803
 804         if (ring->irq_get(ring)) {
 805                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 806                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 807                 ring->irq_put(ring);
 808         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 809                 ret = -EBUSY;
 810
 811         if (ret == -EBUSY) {
 812                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 813                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 814         }
 815
 816         return ret;
 817 }
 818
 819 /* Needs the lock as it touches the ring.
 820  */
 821 int i915_irq_emit(struct drm_device *dev, void *data,
 822                          struct drm_file *file_priv)
 823 {
 824         drm_i915_private_t *dev_priv = dev->dev_private;
 825         drm_i915_irq_emit_t *emit = data;
 826         int result;
 827
 828         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 829                 DRM_ERROR("called with no initialization\n");
 830                 return -EINVAL;
 831         }
 832
 833         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 834
 835         DRM_LOCK(dev);
 836         result = i915_emit_irq(dev);
 837         DRM_UNLOCK(dev);
 838
 839         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 840                 DRM_ERROR("copy_to_user\n");
 841                 return -EFAULT;
 842         }
 843
 844         return 0;
 845 }
 846
 847 /* Doesn't need the hardware lock.
 848  */
 849 int i915_irq_wait(struct drm_device *dev, void *data,
 850                          struct drm_file *file_priv)
 851 {
 852         drm_i915_private_t *dev_priv = dev->dev_private;
 853         drm_i915_irq_wait_t *irqwait = data;
 854
 855         if (!dev_priv) {
 856                 DRM_ERROR("called with no initialization\n");
 857                 return -EINVAL;
 858         }
 859
 860         return i915_wait_irq(dev, irqwait->irq_seq);
 861 }
 862
 863 static int i915_flip_bufs(struct drm_device *dev, void *data,
 864                           struct drm_file *file_priv)
 865 {
 866         int ret;
 867
 868         DRM_DEBUG("%s\n", __func__);
 869
 870         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 871
 872         ret = i915_dispatch_flip(dev);
 873
 874         return ret;
 875 }
 876
 877 static int i915_getparam(struct drm_device *dev, void *data,
 878                          struct drm_file *file_priv)
 879 {
 880         drm_i915_private_t *dev_priv = dev->dev_private;
 881         drm_i915_getparam_t *param = data;
 882         int value;
 883
 884         if (!dev_priv) {
 885                 DRM_ERROR("called with no initialization\n");
 886                 return -EINVAL;
 887         }
 888
 889         switch (param->param) {
 890         case I915_PARAM_IRQ_ACTIVE:
 891                 value = dev->irq_enabled ? 1 : 0;
 892                 break;
 893         case I915_PARAM_ALLOW_BATCHBUFFER:
 894                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 895                 break;
 896         case I915_PARAM_LAST_DISPATCH:
 897                 value = READ_BREADCRUMB(dev_priv);
 898                 break;
 899         case I915_PARAM_CHIPSET_ID:
 900                 value = dev->pci_device;
 901                 break;
 902         case I915_PARAM_HAS_GEM:
 903                 value = 1;
 904                 break;
 905         case I915_PARAM_NUM_FENCES_AVAIL:
 906                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 907                 break;
 908         case I915_PARAM_HAS_OVERLAY:
 909                 value = dev_priv->overlay ? 1 : 0;
 910                 break;
 911         case I915_PARAM_HAS_PAGEFLIPPING:
 912                 value = 1;
 913                 break;
 914         case I915_PARAM_HAS_EXECBUF2:
 915                 value = 1;
 916                 break;
 917         case I915_PARAM_HAS_BSD:
 918                 value = HAS_BSD(dev);
 919                 break;
 920         case I915_PARAM_HAS_BLT:
 921                 value = HAS_BLT(dev);
 922                 break;
 923         case I915_PARAM_HAS_RELAXED_FENCING:
 924                 value = 1;
 925                 break;
 926         case I915_PARAM_HAS_COHERENT_RINGS:
 927                 value = 1;
 928                 break;
 929         case I915_PARAM_HAS_EXEC_CONSTANTS:
 930                 value = INTEL_INFO(dev)->gen >= 4;
 931                 break;
 932         case I915_PARAM_HAS_RELAXED_DELTA:
 933                 value = 1;
 934                 break;
 935         case I915_PARAM_HAS_GEN7_SOL_RESET:
 936                 value = 1;
 937                 break;
 938         case I915_PARAM_HAS_LLC:
 939                 value = HAS_LLC(dev);
 940                 break;
 941         default:
 942                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 943                                  param->param);
 944                 return -EINVAL;
 945         }
 946
 947         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 948                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 949                 return -EFAULT;
 950         }
 951
 952         return 0;
 953 }
 954
 955 static int i915_setparam(struct drm_device *dev, void *data,
 956                          struct drm_file *file_priv)
 957 {
 958         drm_i915_private_t *dev_priv = dev->dev_private;
 959         drm_i915_setparam_t *param = data;
 960
 961         if (!dev_priv) {
 962                 DRM_ERROR("called with no initialization\n");
 963                 return -EINVAL;
 964         }
 965
 966         switch (param->param) {
 967         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 968                 break;
 969         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 970                 dev_priv->tex_lru_log_granularity = param->value;
 971                 break;
 972         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 973                 dev_priv->allow_batchbuffer = param->value;
 974                 break;
 975         case I915_SETPARAM_NUM_USED_FENCES:
 976                 if (param->value > dev_priv->num_fence_regs ||
 977                     param->value < 0)
 978                         return -EINVAL;
 979                 /* Userspace can use first N regs */
 980                 dev_priv->fence_reg_start = param->value;
 981                 break;
 982         default:
 983                 DRM_DEBUG("unknown parameter %d\n", param->param);
 984                 return -EINVAL;
 985         }
 986
 987         return 0;
 988 }
 989
 990 static int i915_set_status_page(struct drm_device *dev, void *data,
 991                                 struct drm_file *file_priv)
 992 {
 993         drm_i915_private_t *dev_priv = dev->dev_private;
 994         drm_i915_hws_addr_t *hws = data;
 995         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 996
 997         if (!I915_NEED_GFX_HWS(dev))
 998                 return -EINVAL;
 999
1000         if (!dev_priv) {
1001                 DRM_ERROR("called with no initialization\n");
1002                 return -EINVAL;
1003         }
1004
1005         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1006         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1007                 DRM_ERROR("tried to set status page when mode setting active\n");
1008                 return 0;
1009         }
1010
1011         ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
1012             hws->addr & (0x1ffff<<12);
1013
1014         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1015         dev_priv->hws_map.size = 4*1024;
1016         dev_priv->hws_map.type = 0;
1017         dev_priv->hws_map.flags = 0;
1018         dev_priv->hws_map.mtrr = 0;
1019
1020         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
1021         if (dev_priv->hws_map.virtual == NULL) {
1022                 i915_dma_cleanup(dev);
1023                 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
1024                 DRM_ERROR("can not ioremap virtual address for"
1025                                 " G33 hw status page\n");
1026                 return -ENOMEM;
1027         }
1028         ring->status_page.page_addr = dev_priv->hw_status_page =
1029             dev_priv->hws_map.virtual;
1030
1031         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1032         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1033         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
1034                         dev_priv->status_gfx_addr);
1035         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1036         return 0;
1037 }
1038
1039 static bool
1040 intel_enable_ppgtt(struct drm_device *dev)
1041 {
1042         if (i915_enable_ppgtt >= 0)
1043                 return i915_enable_ppgtt;
1044
1045         /* Disable ppgtt on SNB if VT-d is on. */
1046         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
1047                 return false;
1048
1049         return true;
1050 }
1051
1052 static int
1053 i915_load_gem_init(struct drm_device *dev)
1054 {
1055         struct drm_i915_private *dev_priv = dev->dev_private;
1056         unsigned long prealloc_size, gtt_size, mappable_size;
1057         int ret;
1058
1059         prealloc_size = dev_priv->mm.gtt->stolen_size;
1060         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1061         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1062
1063         /* Basic memrange allocator for stolen space */
1064         drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1065
1066         DRM_LOCK(dev);
1067         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
1068                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
1069                  * aperture accordingly when using aliasing ppgtt. */
1070                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
1071                 /* For paranoia keep the guard page in between. */
1072                 gtt_size -= PAGE_SIZE;
1073
1074                 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
1075
1076                 ret = i915_gem_init_aliasing_ppgtt(dev);
1077                 if (ret) {
1078                         DRM_UNLOCK(dev);
1079                         return ret;
1080                 }
1081         } else {
1082                 /* Let GEM Manage all of the aperture.
1083                  *
1084                  * However, leave one page at the end still bound to the scratch
1085                  * page.  There are a number of places where the hardware
1086                  * apparently prefetches past the end of the object, and we've
1087                  * seen multiple hangs with the GPU head pointer stuck in a
1088                  * batchbuffer bound at the last page of the aperture.  One page
1089                  * should be enough to keep any prefetching inside of the
1090                  * aperture.
1091                  */
1092                 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1093         }
1094
1095         ret = i915_gem_init_hw(dev);
1096         DRM_UNLOCK(dev);
1097         if (ret != 0) {
1098                 i915_gem_cleanup_aliasing_ppgtt(dev);
1099                 return (ret);
1100         }
1101
1102 #if 0
1103         /* Try to set up FBC with a reasonable compressed buffer size */
1104         if (I915_HAS_FBC(dev) && i915_powersave) {
1105                 int cfb_size;
1106
1107                 /* Leave 1M for line length buffer & misc. */
1108
1109                 /* Try to get a 32M buffer... */
1110                 if (prealloc_size > (36*1024*1024))
1111                         cfb_size = 32*1024*1024;
1112                 else /* fall back to 7/8 of the stolen space */
1113                         cfb_size = prealloc_size * 7 / 8;
1114                 i915_setup_compression(dev, cfb_size);
1115         }
1116 #endif
1117
1118         /* Allow hardware batchbuffers unless told otherwise. */
1119         dev_priv->allow_batchbuffer = 1;
1120         return 0;
1121 }
1122
1123 static int
1124 i915_load_modeset_init(struct drm_device *dev)
1125 {
1126         struct drm_i915_private *dev_priv = dev->dev_private;
1127         int ret;
1128
1129         ret = intel_parse_bios(dev);
1130         if (ret)
1131                 DRM_INFO("failed to find VBIOS tables\n");
1132
1133 #if 0
1134         intel_register_dsm_handler();
1135 #endif
1136
1137         /* IIR "flip pending" bit means done if this bit is set */
1138         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1139                 dev_priv->flip_pending_is_done = true;
1140
1141         intel_modeset_init(dev);
1142
1143         ret = i915_load_gem_init(dev);
1144         if (ret != 0)
1145                 goto cleanup_gem;
1146
1147         intel_modeset_gem_init(dev);
1148
1149         ret = drm_irq_install(dev);
1150         if (ret)
1151                 goto cleanup_gem;
1152
1153         dev->vblank_disable_allowed = 1;
1154
1155         ret = intel_fbdev_init(dev);
1156         if (ret)
1157                 goto cleanup_gem;
1158
1159         drm_kms_helper_poll_init(dev);
1160
1161         /* We're off and running w/KMS */
1162         dev_priv->mm.suspended = 0;
1163
1164         return (0);
1165
1166 cleanup_gem:
1167         DRM_LOCK(dev);
1168         i915_gem_cleanup_ringbuffer(dev);
1169         DRM_UNLOCK(dev);
1170         i915_gem_cleanup_aliasing_ppgtt(dev);
1171         return (ret);
1172 }
1173
1174 static int
1175 i915_get_bridge_dev(struct drm_device *dev)
1176 {
1177         struct drm_i915_private *dev_priv;
1178
1179         dev_priv = dev->dev_private;
1180
1181         dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1182         if (dev_priv->bridge_dev == NULL) {
1183                 DRM_ERROR("bridge device not found\n");
1184                 return (-1);
1185         }
1186         return (0);
1187 }
1188
1189 #define MCHBAR_I915 0x44
1190 #define MCHBAR_I965 0x48
1191 #define MCHBAR_SIZE (4*4096)
1192
1193 #define DEVEN_REG 0x54
1194 #define   DEVEN_MCHBAR_EN (1 << 28)
1195
1196 /* Allocate space for the MCH regs if needed, return nonzero on error */
1197 static int
1198 intel_alloc_mchbar_resource(struct drm_device *dev)
1199 {
1200         drm_i915_private_t *dev_priv;
1201         device_t vga;
1202         int reg;
1203         u32 temp_lo, temp_hi;
1204         u64 mchbar_addr, temp;
1205
1206         dev_priv = dev->dev_private;
1207         reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1208
1209         if (INTEL_INFO(dev)->gen >= 4)
1210                 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1211         else
1212                 temp_hi = 0;
1213         temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1214         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1215
1216         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1217 #ifdef XXX_CONFIG_PNP
1218         if (mchbar_addr &&
1219             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1220                 return 0;
1221 #endif
1222
1223         /* Get some space for it */
1224         vga = device_get_parent(dev->dev);
1225         dev_priv->mch_res_rid = 0x100;
1226         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1227             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1228             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1229         if (dev_priv->mch_res == NULL) {
1230                 DRM_ERROR("failed mchbar resource alloc\n");
1231                 return (-ENOMEM);
1232         }
1233
1234         if (INTEL_INFO(dev)->gen >= 4) {
1235                 temp = rman_get_start(dev_priv->mch_res);
1236                 temp >>= 32;
1237                 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1238         }
1239         pci_write_config(dev_priv->bridge_dev, reg,
1240             rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1241         return (0);
1242 }
1243
1244 static void
1245 intel_setup_mchbar(struct drm_device *dev)
1246 {
1247         drm_i915_private_t *dev_priv;
1248         int mchbar_reg;
1249         u32 temp;
1250         bool enabled;
1251
1252         dev_priv = dev->dev_private;
1253         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1254
1255         dev_priv->mchbar_need_disable = false;
1256
1257         if (IS_I915G(dev) || IS_I915GM(dev)) {
1258                 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1259                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1260         } else {
1261                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1262                 enabled = temp & 1;
1263         }
1264
1265         /* If it's already enabled, don't have to do anything */
1266         if (enabled) {
1267                 DRM_DEBUG("mchbar already enabled\n");
1268                 return;
1269         }
1270
1271         if (intel_alloc_mchbar_resource(dev))
1272                 return;
1273
1274         dev_priv->mchbar_need_disable = true;
1275
1276         /* Space is allocated or reserved, so enable it. */
1277         if (IS_I915G(dev) || IS_I915GM(dev)) {
1278                 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1279                     temp | DEVEN_MCHBAR_EN, 4);
1280         } else {
1281                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1282                 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1283         }
1284 }
1285
1286 static void
1287 intel_teardown_mchbar(struct drm_device *dev)
1288 {
1289         drm_i915_private_t *dev_priv;
1290         device_t vga;
1291         int mchbar_reg;
1292         u32 temp;
1293
1294         dev_priv = dev->dev_private;
1295         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1296
1297         if (dev_priv->mchbar_need_disable) {
1298                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1299                         temp = pci_read_config(dev_priv->bridge_dev,
1300                             DEVEN_REG, 4);
1301                         temp &= ~DEVEN_MCHBAR_EN;
1302                         pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1303                             temp, 4);
1304                 } else {
1305                         temp = pci_read_config(dev_priv->bridge_dev,
1306                             mchbar_reg, 4);
1307                         temp &= ~1;
1308                         pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1309                             temp, 4);
1310                 }
1311         }
1312
1313         if (dev_priv->mch_res != NULL) {
1314                 vga = device_get_parent(dev->dev);
1315                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1316                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1317                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1318                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1319                 dev_priv->mch_res = NULL;
1320         }
1321 }
1322
1323 /**
1324  * i915_driver_load - setup chip and create an initial config
1325  * @dev: DRM device
1326  * @flags: startup flags
1327  *
1328  * The driver load routine has to do several things:
1329  *   - drive output discovery via intel_modeset_init()
1330  *   - initialize the memory manager
1331  *   - allocate initial config memory
1332  *   - setup the DRM framebuffer with the allocated memory
1333  */
1334 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1335 {
1336         struct drm_i915_private *dev_priv = dev->dev_private;
1337         unsigned long base, size;
1338         int mmio_bar, ret;
1339
1340         ret = 0;
1341
1342         /* i915 has 4 more counters */
1343         dev->counters += 4;
1344         dev->types[6] = _DRM_STAT_IRQ;
1345         dev->types[7] = _DRM_STAT_PRIMARY;
1346         dev->types[8] = _DRM_STAT_SECONDARY;
1347         dev->types[9] = _DRM_STAT_DMA;
1348
1349         dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1350             M_ZERO | M_WAITOK);
1351         if (dev_priv == NULL)
1352                 return -ENOMEM;
1353
1354         dev->dev_private = (void *)dev_priv;
1355         dev_priv->dev = dev;
1356         dev_priv->info = i915_get_device_id(dev->pci_device);
1357
1358         if (i915_get_bridge_dev(dev)) {
1359                 drm_free(dev_priv, DRM_MEM_DRIVER);
1360                 return (-EIO);
1361         }
1362         dev_priv->mm.gtt = intel_gtt_get();
1363
1364         /* Add register map (needed for suspend/resume) */
1365         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1366         base = drm_get_resource_start(dev, mmio_bar);
1367         size = drm_get_resource_len(dev, mmio_bar);
1368
1369         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1370             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1371
1372         /* The i915 workqueue is primarily used for batched retirement of
1373          * requests (and thus managing bo) once the task has been completed
1374          * by the GPU. i915_gem_retire_requests() is called directly when we
1375          * need high-priority retirement, such as waiting for an explicit
1376          * bo.
1377          *
1378          * It is also used for periodic low-priority events, such as
1379          * idle-timers and recording error state.
1380          *
1381          * All tasks on the workqueue are expected to acquire the dev mutex
1382          * so there is no point in running more than one instance of the
1383          * workqueue at any time.  Use an ordered one.
1384          */
1385         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1386         if (dev_priv->wq == NULL) {
1387                 DRM_ERROR("Failed to create our workqueue.\n");
1388                 ret = -ENOMEM;
1389                 goto out_mtrrfree;
1390         }
1391
1392         intel_irq_init(dev);
1393         intel_gt_init(dev);
1394
1395         /* Try to make sure MCHBAR is enabled before poking at it */
1396         intel_setup_mchbar(dev);
1397         intel_setup_gmbus(dev);
1398         intel_opregion_setup(dev);
1399
1400         intel_setup_bios(dev);
1401
1402         i915_gem_load(dev);
1403
1404         /* On the 945G/GM, the chipset reports the MSI capability on the
1405          * integrated graphics even though the support isn't actually there
1406          * according to the published specs.  It doesn't appear to function
1407          * correctly in testing on 945G.
1408          * This may be a side effect of MSI having been made available for PEG
1409          * and the registers being closely associated.
1410          *
1411          * According to chipset errata, on the 965GM, MSI interrupts may
1412          * be lost or delayed, but we use them anyways to avoid
1413          * stuck interrupts on some machines.
1414          */
1415
1416         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1417         lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1418         spin_init(&dev_priv->rps.lock);
1419         lockinit(&dev_priv->error_completion_lock, "915cmp", 0, LK_CANRECURSE);
1420
1421         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1422
1423         /* Init HWS */
1424         if (!I915_NEED_GFX_HWS(dev)) {
1425                 ret = i915_init_phys_hws(dev);
1426                 if (ret != 0) {
1427                         drm_rmmap(dev, dev_priv->mmio_map);
1428                         drm_free(dev_priv, DRM_MEM_DRIVER);
1429                         return ret;
1430                 }
1431         }
1432
1433         if (IS_PINEVIEW(dev))
1434                 i915_pineview_get_mem_freq(dev);
1435         else if (IS_GEN5(dev))
1436                 i915_ironlake_get_mem_freq(dev);
1437
1438         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1439                 dev_priv->num_pipe = 3;
1440         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1441                 dev_priv->num_pipe = 2;
1442         else
1443                 dev_priv->num_pipe = 1;
1444
1445         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1446         if (ret)
1447                 goto out_gem_unload;
1448
1449         /* Start out suspended */
1450         dev_priv->mm.suspended = 1;
1451
1452         intel_detect_pch(dev);
1453
1454         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1455                 ret = i915_load_modeset_init(dev);
1456                 if (ret < 0) {
1457                         DRM_ERROR("failed to init modeset\n");
1458                         goto out_gem_unload;
1459                 }
1460         }
1461
1462         intel_opregion_init(dev);
1463
1464         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1465                     (unsigned long) dev);
1466
1467         if (IS_GEN5(dev)) {
1468                 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1469                 i915_mch_dev = dev_priv;
1470                 dev_priv->mchdev_lock = &mchdev_lock;
1471                 lockmgr(&mchdev_lock, LK_RELEASE);
1472         }
1473
1474         return (0);
1475
1476 out_gem_unload:
1477         /* XXXKIB */
1478         (void) i915_driver_unload_int(dev, true);
1479         return (ret);
1480 out_mtrrfree:
1481         return ret;
1482 }
1483
1484 static int
1485 i915_driver_unload_int(struct drm_device *dev, bool locked)
1486 {
1487         struct drm_i915_private *dev_priv = dev->dev_private;
1488         int ret;
1489
1490         if (!locked)
1491                 DRM_LOCK(dev);
1492         ret = i915_gpu_idle(dev);
1493         if (ret)
1494                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1495         if (!locked)
1496                 DRM_UNLOCK(dev);
1497
1498         i915_free_hws(dev);
1499
1500         intel_teardown_mchbar(dev);
1501
1502         if (locked)
1503                 DRM_UNLOCK(dev);
1504         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1505                 intel_fbdev_fini(dev);
1506                 intel_modeset_cleanup(dev);
1507         }
1508
1509         /* Free error state after interrupts are fully disabled. */
1510         del_timer_sync(&dev_priv->hangcheck_timer);
1511
1512         i915_destroy_error_state(dev);
1513
1514         intel_opregion_fini(dev);
1515
1516         if (locked)
1517                 DRM_LOCK(dev);
1518
1519         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1520                 if (!locked)
1521                         DRM_LOCK(dev);
1522                 i915_gem_free_all_phys_object(dev);
1523                 i915_gem_cleanup_ringbuffer(dev);
1524                 if (!locked)
1525                         DRM_UNLOCK(dev);
1526                 i915_gem_cleanup_aliasing_ppgtt(dev);
1527 #if 1
1528                 KIB_NOTYET();
1529 #else
1530                 if (I915_HAS_FBC(dev) && i915_powersave)
1531                         i915_cleanup_compression(dev);
1532 #endif
1533                 drm_mm_takedown(&dev_priv->mm.stolen);
1534
1535                 intel_cleanup_overlay(dev);
1536
1537                 if (!I915_NEED_GFX_HWS(dev))
1538                         i915_free_hws(dev);
1539         }
1540
1541         i915_gem_unload(dev);
1542
1543         lockuninit(&dev_priv->irq_lock);
1544
1545         if (dev_priv->wq != NULL)
1546                 destroy_workqueue(dev_priv->wq);
1547
1548         bus_generic_detach(dev->dev);
1549         drm_rmmap(dev, dev_priv->mmio_map);
1550         intel_teardown_gmbus(dev);
1551
1552         lockuninit(&dev_priv->error_lock);
1553         lockuninit(&dev_priv->error_completion_lock);
1554         drm_free(dev->dev_private, DRM_MEM_DRIVER);
1555
1556         return (0);
1557 }
1558
1559 int
1560 i915_driver_unload(struct drm_device *dev)
1561 {
1562
1563         return (i915_driver_unload_int(dev, true));
1564 }
1565
1566 int
1567 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1568 {
1569         struct drm_i915_file_private *i915_file_priv;
1570
1571         i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1572             M_WAITOK | M_ZERO);
1573
1574         spin_init(&i915_file_priv->mm.lock);
1575         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1576         file_priv->driver_priv = i915_file_priv;
1577
1578         return (0);
1579 }
1580
1581 void
1582 i915_driver_lastclose(struct drm_device * dev)
1583 {
1584         drm_i915_private_t *dev_priv = dev->dev_private;
1585
1586         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1587 #if 1
1588                 KIB_NOTYET();
1589 #else
1590                 drm_fb_helper_restore();
1591                 vga_switcheroo_process_delayed_switch();
1592 #endif
1593                 return;
1594         }
1595         i915_gem_lastclose(dev);
1596         i915_dma_cleanup(dev);
1597 }
1598
1599 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1600 {
1601
1602         i915_gem_release(dev, file_priv);
1603 }
1604
1605 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1606 {
1607         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1608
1609         spin_uninit(&i915_file_priv->mm.lock);
1610         drm_free(i915_file_priv, DRM_MEM_FILES);
1611 }
1612
1613 struct drm_ioctl_desc i915_ioctls[] = {
1614         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1615         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1616         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1617         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1618         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1619         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1620         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1621         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1622         DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1623         DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1624         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1625         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1626         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1627         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1628         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1629         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1630         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1631         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1632         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1633         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1634         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1635         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1636         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1637         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1638         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1639         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1640         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1641         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1642         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1643         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1644         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1645         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1646         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1647         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1648         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1649         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1650         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1651         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1652         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1653         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1654         DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1655         DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1656 };
1657
1658 struct drm_driver i915_driver_info = {
1659         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1660             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1661             DRIVER_GEM /*| DRIVER_MODESET*/,
1662
1663         .buf_priv_size  = sizeof(drm_i915_private_t),
1664         .load           = i915_driver_load,
1665         .open           = i915_driver_open,
1666         .unload         = i915_driver_unload,
1667         .preclose       = i915_driver_preclose,
1668         .lastclose      = i915_driver_lastclose,
1669         .postclose      = i915_driver_postclose,
1670         .device_is_agp  = i915_driver_device_is_agp,
1671         .gem_init_object = i915_gem_init_object,
1672         .gem_free_object = i915_gem_free_object,
1673         .gem_pager_ops  = &i915_gem_pager_ops,
1674         .dumb_create    = i915_gem_dumb_create,
1675         .dumb_map_offset = i915_gem_mmap_gtt,
1676         .dumb_destroy   = i915_gem_dumb_destroy,
1677         .sysctl_init    = i915_sysctl_init,
1678         .sysctl_cleanup = i915_sysctl_cleanup,
1679
1680         .ioctls         = i915_ioctls,
1681         .max_ioctl      = DRM_ARRAY_SIZE(i915_ioctls),
1682
1683         .name           = DRIVER_NAME,
1684         .desc           = DRIVER_DESC,
1685         .date           = DRIVER_DATE,
1686         .major          = DRIVER_MAJOR,
1687         .minor          = DRIVER_MINOR,
1688         .patchlevel     = DRIVER_PATCHLEVEL,
1689 };
1690
1691 /**
1692  * Determine if the device really is AGP or not.
1693  *
1694  * All Intel graphics chipsets are treated as AGP, even if they are really
1695  * built-in.
1696  *
1697  * \param dev   The device to be tested.
1698  *
1699  * \returns
1700  * A value of 1 is always retured to indictate every i9x5 is AGP.
1701  */
1702 int i915_driver_device_is_agp(struct drm_device * dev)
1703 {
1704         return 1;
1705 }