sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35 #include <linux/workqueue.h>
  36
  37 extern struct drm_i915_private *i915_mch_dev;
  38
  39 extern void i915_pineview_get_mem_freq(struct drm_device *dev);
  40 extern void i915_ironlake_get_mem_freq(struct drm_device *dev);
  41 static int i915_driver_unload_int(struct drm_device *dev, bool locked);
  42
  43 static void i915_write_hws_pga(struct drm_device *dev)
  44 {
  45         drm_i915_private_t *dev_priv = dev->dev_private;
  46         u32 addr;
  47
  48         addr = dev_priv->status_page_dmah->busaddr;
  49         if (INTEL_INFO(dev)->gen >= 4)
  50                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  51         I915_WRITE(HWS_PGA, addr);
  52 }
  53
  54 /**
  55  * Sets up the hardware status page for devices that need a physical address
  56  * in the register.
  57  */
  58 static int i915_init_phys_hws(struct drm_device *dev)
  59 {
  60         drm_i915_private_t *dev_priv = dev->dev_private;
  61         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  62
  63         /*
  64          * Program Hardware Status Page
  65          * XXXKIB Keep 4GB limit for allocation for now.  This method
  66          * of allocation is used on <= 965 hardware, that has several
  67          * erratas regarding the use of physical memory > 4 GB.
  68          */
  69         DRM_UNLOCK(dev);
  70         dev_priv->status_page_dmah =
  71                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  72         DRM_LOCK(dev);
  73         if (!dev_priv->status_page_dmah) {
  74                 DRM_ERROR("Can not allocate hardware status page\n");
  75                 return -ENOMEM;
  76         }
  77         ring->status_page.page_addr = dev_priv->hw_status_page =
  78             dev_priv->status_page_dmah->vaddr;
  79         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  80
  81         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  82
  83         i915_write_hws_pga(dev);
  84         DRM_DEBUG("Enabled hardware status page, phys %jx\n",
  85             (uintmax_t)dev_priv->dma_status_page);
  86         return 0;
  87 }
  88
  89 /**
  90  * Frees the hardware status page, whether it's a physical address or a virtual
  91  * address set up by the X Server.
  92  */
  93 static void i915_free_hws(struct drm_device *dev)
  94 {
  95         drm_i915_private_t *dev_priv = dev->dev_private;
  96         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  97
  98         if (dev_priv->status_page_dmah) {
  99                 drm_pci_free(dev, dev_priv->status_page_dmah);
 100                 dev_priv->status_page_dmah = NULL;
 101         }
 102
 103         if (dev_priv->status_gfx_addr) {
 104                 dev_priv->status_gfx_addr = 0;
 105                 ring->status_page.gfx_addr = 0;
 106                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 107         }
 108
 109         /* Need to rewrite hardware status page */
 110         I915_WRITE(HWS_PGA, 0x1ffff000);
 111 }
 112
 113 void i915_kernel_lost_context(struct drm_device * dev)
 114 {
 115         drm_i915_private_t *dev_priv = dev->dev_private;
 116         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 117
 118         /*
 119          * We should never lose context on the ring with modesetting
 120          * as we don't expose it to userspace
 121          */
 122         if (drm_core_check_feature(dev, DRIVER_MODESET))
 123                 return;
 124
 125         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 126         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 127         ring->space = ring->head - (ring->tail + 8);
 128         if (ring->space < 0)
 129                 ring->space += ring->size;
 130
 131 #if 1
 132         KIB_NOTYET();
 133 #else
 134         if (!dev->primary->master)
 135                 return;
 136 #endif
 137
 138         if (ring->head == ring->tail && dev_priv->sarea_priv)
 139                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 140 }
 141
 142 static int i915_dma_cleanup(struct drm_device * dev)
 143 {
 144         drm_i915_private_t *dev_priv = dev->dev_private;
 145         int i;
 146
 147
 148         /* Make sure interrupts are disabled here because the uninstall ioctl
 149          * may not have been called from userspace and after dev_private
 150          * is freed, it's too late.
 151          */
 152         if (dev->irq_enabled)
 153                 drm_irq_uninstall(dev);
 154
 155         for (i = 0; i < I915_NUM_RINGS; i++)
 156                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 157
 158         /* Clear the HWS virtual address at teardown */
 159         if (I915_NEED_GFX_HWS(dev))
 160                 i915_free_hws(dev);
 161
 162         return 0;
 163 }
 164
 165 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 166 {
 167         drm_i915_private_t *dev_priv = dev->dev_private;
 168         int ret;
 169
 170         dev_priv->sarea = drm_getsarea(dev);
 171         if (!dev_priv->sarea) {
 172                 DRM_ERROR("can not find sarea!\n");
 173                 i915_dma_cleanup(dev);
 174                 return -EINVAL;
 175         }
 176
 177         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 178             ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
 179
 180         if (init->ring_size != 0) {
 181                 if (LP_RING(dev_priv)->obj != NULL) {
 182                         i915_dma_cleanup(dev);
 183                         DRM_ERROR("Client tried to initialize ringbuffer in "
 184                                   "GEM mode\n");
 185                         return -EINVAL;
 186                 }
 187
 188                 ret = intel_render_ring_init_dri(dev,
 189                                                  init->ring_start,
 190                                                  init->ring_size);
 191                 if (ret) {
 192                         i915_dma_cleanup(dev);
 193                         return ret;
 194                 }
 195         }
 196
 197         dev_priv->cpp = init->cpp;
 198         dev_priv->back_offset = init->back_offset;
 199         dev_priv->front_offset = init->front_offset;
 200         dev_priv->current_page = 0;
 201         dev_priv->sarea_priv->pf_current_page = 0;
 202
 203         /* Allow hardware batchbuffers unless told otherwise.
 204          */
 205         dev_priv->allow_batchbuffer = 1;
 206
 207         return 0;
 208 }
 209
 210 static int i915_dma_resume(struct drm_device * dev)
 211 {
 212         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 213         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 214
 215         DRM_DEBUG("\n");
 216
 217         if (ring->map.handle == NULL) {
 218                 DRM_ERROR("can not ioremap virtual address for"
 219                           " ring buffer\n");
 220                 return -ENOMEM;
 221         }
 222
 223         /* Program Hardware Status Page */
 224         if (!ring->status_page.page_addr) {
 225                 DRM_ERROR("Can not find hardware status page\n");
 226                 return -EINVAL;
 227         }
 228         DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
 229         if (ring->status_page.gfx_addr != 0)
 230                 intel_ring_setup_status_page(ring);
 231         else
 232                 i915_write_hws_pga(dev);
 233
 234         DRM_DEBUG("Enabled hardware status page\n");
 235
 236         return 0;
 237 }
 238
 239 static int i915_dma_init(struct drm_device *dev, void *data,
 240                          struct drm_file *file_priv)
 241 {
 242         drm_i915_init_t *init = data;
 243         int retcode = 0;
 244
 245         switch (init->func) {
 246         case I915_INIT_DMA:
 247                 retcode = i915_initialize(dev, init);
 248                 break;
 249         case I915_CLEANUP_DMA:
 250                 retcode = i915_dma_cleanup(dev);
 251                 break;
 252         case I915_RESUME_DMA:
 253                 retcode = i915_dma_resume(dev);
 254                 break;
 255         default:
 256                 retcode = -EINVAL;
 257                 break;
 258         }
 259
 260         return retcode;
 261 }
 262
 263 /* Implement basically the same security restrictions as hardware does
 264  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 265  *
 266  * Most of the calculations below involve calculating the size of a
 267  * particular instruction.  It's important to get the size right as
 268  * that tells us where the next instruction to check is.  Any illegal
 269  * instruction detected will be given a size of zero, which is a
 270  * signal to abort the rest of the buffer.
 271  */
 272 static int do_validate_cmd(int cmd)
 273 {
 274         switch (((cmd >> 29) & 0x7)) {
 275         case 0x0:
 276                 switch ((cmd >> 23) & 0x3f) {
 277                 case 0x0:
 278                         return 1;       /* MI_NOOP */
 279                 case 0x4:
 280                         return 1;       /* MI_FLUSH */
 281                 default:
 282                         return 0;       /* disallow everything else */
 283                 }
 284                 break;
 285         case 0x1:
 286                 return 0;       /* reserved */
 287         case 0x2:
 288                 return (cmd & 0xff) + 2;        /* 2d commands */
 289         case 0x3:
 290                 if (((cmd >> 24) & 0x1f) <= 0x18)
 291                         return 1;
 292
 293                 switch ((cmd >> 24) & 0x1f) {
 294                 case 0x1c:
 295                         return 1;
 296                 case 0x1d:
 297                         switch ((cmd >> 16) & 0xff) {
 298                         case 0x3:
 299                                 return (cmd & 0x1f) + 2;
 300                         case 0x4:
 301                                 return (cmd & 0xf) + 2;
 302                         default:
 303                                 return (cmd & 0xffff) + 2;
 304                         }
 305                 case 0x1e:
 306                         if (cmd & (1 << 23))
 307                                 return (cmd & 0xffff) + 1;
 308                         else
 309                                 return 1;
 310                 case 0x1f:
 311                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 312                                 return (cmd & 0x1ffff) + 2;
 313                         else if (cmd & (1 << 17))       /* indirect random */
 314                                 if ((cmd & 0xffff) == 0)
 315                                         return 0;       /* unknown length, too hard */
 316                                 else
 317                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 318                         else
 319                                 return 2;       /* indirect sequential */
 320                 default:
 321                         return 0;
 322                 }
 323         default:
 324                 return 0;
 325         }
 326
 327         return 0;
 328 }
 329
 330 static int validate_cmd(int cmd)
 331 {
 332         int ret = do_validate_cmd(cmd);
 333
 334 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 335
 336         return ret;
 337 }
 338
 339 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 340                           int dwords)
 341 {
 342         drm_i915_private_t *dev_priv = dev->dev_private;
 343         int i, ret;
 344
 345         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 346                 return -EINVAL;
 347
 348         ret = BEGIN_LP_RING((dwords+1)&~1);
 349         if (ret)
 350                 return ret;
 351
 352         for (i = 0; i < dwords;) {
 353                 int cmd, sz;
 354
 355                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 356                         return -EINVAL;
 357
 358                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 359                         return -EINVAL;
 360
 361                 OUT_RING(cmd);
 362
 363                 while (++i, --sz) {
 364                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 365                                                          sizeof(cmd))) {
 366                                 return -EINVAL;
 367                         }
 368                         OUT_RING(cmd);
 369                 }
 370         }
 371
 372         if (dwords & 1)
 373                 OUT_RING(0);
 374
 375         ADVANCE_LP_RING();
 376
 377         return 0;
 378 }
 379
 380 int i915_emit_box(struct drm_device * dev,
 381                   struct drm_clip_rect *boxes,
 382                   int i, int DR1, int DR4)
 383 {
 384         struct drm_clip_rect box;
 385
 386         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 387                 return -EFAULT;
 388         }
 389
 390         return (i915_emit_box_p(dev, &box, DR1, DR4));
 391 }
 392
 393 int
 394 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
 395     int DR1, int DR4)
 396 {
 397         drm_i915_private_t *dev_priv = dev->dev_private;
 398         int ret;
 399
 400         if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
 401             box->x2 <= 0) {
 402                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 403                           box->x1, box->y1, box->x2, box->y2);
 404                 return -EINVAL;
 405         }
 406
 407         if (INTEL_INFO(dev)->gen >= 4) {
 408                 ret = BEGIN_LP_RING(4);
 409                 if (ret != 0)
 410                         return (ret);
 411
 412                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 413                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 414                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 415                 OUT_RING(DR4);
 416         } else {
 417                 ret = BEGIN_LP_RING(6);
 418                 if (ret != 0)
 419                         return (ret);
 420
 421                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 422                 OUT_RING(DR1);
 423                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 424                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 425                 OUT_RING(DR4);
 426                 OUT_RING(0);
 427         }
 428         ADVANCE_LP_RING();
 429
 430         return 0;
 431 }
 432
 433 /* XXX: Emitting the counter should really be moved to part of the IRQ
 434  * emit. For now, do it in both places:
 435  */
 436
 437 static void i915_emit_breadcrumb(struct drm_device *dev)
 438 {
 439         drm_i915_private_t *dev_priv = dev->dev_private;
 440
 441         if (++dev_priv->counter > 0x7FFFFFFFUL)
 442                 dev_priv->counter = 0;
 443         if (dev_priv->sarea_priv)
 444                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 445
 446         if (BEGIN_LP_RING(4) == 0) {
 447                 OUT_RING(MI_STORE_DWORD_INDEX);
 448                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 449                 OUT_RING(dev_priv->counter);
 450                 OUT_RING(0);
 451                 ADVANCE_LP_RING();
 452         }
 453 }
 454
 455 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 456     drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
 457 {
 458         int nbox = cmd->num_cliprects;
 459         int i = 0, count, ret;
 460
 461         if (cmd->sz & 0x3) {
 462                 DRM_ERROR("alignment\n");
 463                 return -EINVAL;
 464         }
 465
 466         i915_kernel_lost_context(dev);
 467
 468         count = nbox ? nbox : 1;
 469
 470         for (i = 0; i < count; i++) {
 471                 if (i < nbox) {
 472                         ret = i915_emit_box_p(dev, &cmd->cliprects[i],
 473                             cmd->DR1, cmd->DR4);
 474                         if (ret)
 475                                 return ret;
 476                 }
 477
 478                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 479                 if (ret)
 480                         return ret;
 481         }
 482
 483         i915_emit_breadcrumb(dev);
 484         return 0;
 485 }
 486
 487 static int
 488 i915_dispatch_batchbuffer(struct drm_device * dev,
 489     drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
 490 {
 491         drm_i915_private_t *dev_priv = dev->dev_private;
 492         int nbox = batch->num_cliprects;
 493         int i, count, ret;
 494
 495         if ((batch->start | batch->used) & 0x7) {
 496                 DRM_ERROR("alignment\n");
 497                 return -EINVAL;
 498         }
 499
 500         i915_kernel_lost_context(dev);
 501
 502         count = nbox ? nbox : 1;
 503
 504         for (i = 0; i < count; i++) {
 505                 if (i < nbox) {
 506                         int ret = i915_emit_box_p(dev, &cliprects[i],
 507                             batch->DR1, batch->DR4);
 508                         if (ret)
 509                                 return ret;
 510                 }
 511
 512                 if (!IS_I830(dev) && !IS_845G(dev)) {
 513                         ret = BEGIN_LP_RING(2);
 514                         if (ret != 0)
 515                                 return (ret);
 516
 517                         if (INTEL_INFO(dev)->gen >= 4) {
 518                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
 519                                     MI_BATCH_NON_SECURE_I965);
 520                                 OUT_RING(batch->start);
 521                         } else {
 522                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 523                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 524                         }
 525                 } else {
 526                         ret = BEGIN_LP_RING(4);
 527                         if (ret != 0)
 528                                 return (ret);
 529
 530                         OUT_RING(MI_BATCH_BUFFER);
 531                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 532                         OUT_RING(batch->start + batch->used - 4);
 533                         OUT_RING(0);
 534                 }
 535                 ADVANCE_LP_RING();
 536         }
 537
 538         i915_emit_breadcrumb(dev);
 539
 540         return 0;
 541 }
 542
 543 static int i915_dispatch_flip(struct drm_device * dev)
 544 {
 545         drm_i915_private_t *dev_priv = dev->dev_private;
 546         int ret;
 547
 548         if (!dev_priv->sarea_priv)
 549                 return -EINVAL;
 550
 551         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 552                   __func__,
 553                   dev_priv->current_page,
 554                   dev_priv->sarea_priv->pf_current_page);
 555
 556         i915_kernel_lost_context(dev);
 557
 558         ret = BEGIN_LP_RING(10);
 559         if (ret)
 560                 return ret;
 561         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 562         OUT_RING(0);
 563
 564         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 565         OUT_RING(0);
 566         if (dev_priv->current_page == 0) {
 567                 OUT_RING(dev_priv->back_offset);
 568                 dev_priv->current_page = 1;
 569         } else {
 570                 OUT_RING(dev_priv->front_offset);
 571                 dev_priv->current_page = 0;
 572         }
 573         OUT_RING(0);
 574
 575         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 576         OUT_RING(0);
 577
 578         ADVANCE_LP_RING();
 579
 580         if (++dev_priv->counter > 0x7FFFFFFFUL)
 581                 dev_priv->counter = 0;
 582         if (dev_priv->sarea_priv)
 583                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 584
 585         if (BEGIN_LP_RING(4) == 0) {
 586                 OUT_RING(MI_STORE_DWORD_INDEX);
 587                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 588                 OUT_RING(dev_priv->counter);
 589                 OUT_RING(0);
 590                 ADVANCE_LP_RING();
 591         }
 592
 593         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 594         return 0;
 595 }
 596
 597 static int
 598 i915_quiescent(struct drm_device *dev)
 599 {
 600         struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
 601
 602         i915_kernel_lost_context(dev);
 603         return (intel_wait_ring_idle(ring));
 604 }
 605
 606 static int
 607 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 608 {
 609         int ret;
 610
 611         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 612
 613         DRM_LOCK(dev);
 614         ret = i915_quiescent(dev);
 615         DRM_UNLOCK(dev);
 616
 617         return (ret);
 618 }
 619
 620 static int i915_batchbuffer(struct drm_device *dev, void *data,
 621                             struct drm_file *file_priv)
 622 {
 623         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 624         drm_i915_sarea_t *sarea_priv;
 625         drm_i915_batchbuffer_t *batch = data;
 626         struct drm_clip_rect *cliprects;
 627         size_t cliplen;
 628         int ret;
 629
 630         if (!dev_priv->allow_batchbuffer) {
 631                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 632                 return -EINVAL;
 633         }
 634         DRM_UNLOCK(dev);
 635
 636         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 637                   batch->start, batch->used, batch->num_cliprects);
 638
 639         cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
 640         if (batch->num_cliprects < 0)
 641                 return -EFAULT;
 642         if (batch->num_cliprects != 0) {
 643                 cliprects = kmalloc(batch->num_cliprects *
 644                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 645                     M_WAITOK | M_ZERO);
 646
 647                 ret = -copyin(batch->cliprects, cliprects,
 648                     batch->num_cliprects * sizeof(struct drm_clip_rect));
 649                 if (ret != 0) {
 650                         DRM_LOCK(dev);
 651                         goto fail_free;
 652                 }
 653         } else
 654                 cliprects = NULL;
 655
 656         DRM_LOCK(dev);
 657         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 658         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 659
 660         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 661         if (sarea_priv)
 662                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 663
 664 fail_free:
 665         drm_free(cliprects, DRM_MEM_DMA);
 666         return ret;
 667 }
 668
 669 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 670                           struct drm_file *file_priv)
 671 {
 672         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 673         drm_i915_sarea_t *sarea_priv;
 674         drm_i915_cmdbuffer_t *cmdbuf = data;
 675         struct drm_clip_rect *cliprects = NULL;
 676         void *batch_data;
 677         int ret;
 678
 679         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 680                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 681
 682         if (cmdbuf->num_cliprects < 0)
 683                 return -EINVAL;
 684
 685         DRM_UNLOCK(dev);
 686
 687         batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
 688
 689         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
 690         if (ret != 0) {
 691                 DRM_LOCK(dev);
 692                 goto fail_batch_free;
 693         }
 694
 695         if (cmdbuf->num_cliprects) {
 696                 cliprects = kmalloc(cmdbuf->num_cliprects *
 697                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 698                     M_WAITOK | M_ZERO);
 699                 ret = -copyin(cmdbuf->cliprects, cliprects,
 700                     cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
 701                 if (ret != 0) {
 702                         DRM_LOCK(dev);
 703                         goto fail_clip_free;
 704                 }
 705         }
 706
 707         DRM_LOCK(dev);
 708         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 709         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 710         if (ret) {
 711                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 712                 goto fail_clip_free;
 713         }
 714
 715         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 716         if (sarea_priv)
 717                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 718
 719 fail_clip_free:
 720         drm_free(cliprects, DRM_MEM_DMA);
 721 fail_batch_free:
 722         drm_free(batch_data, DRM_MEM_DMA);
 723         return ret;
 724 }
 725
 726 static int i915_flip_bufs(struct drm_device *dev, void *data,
 727                           struct drm_file *file_priv)
 728 {
 729         int ret;
 730
 731         DRM_DEBUG("%s\n", __func__);
 732
 733         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 734
 735         ret = i915_dispatch_flip(dev);
 736
 737         return ret;
 738 }
 739
 740 static int i915_getparam(struct drm_device *dev, void *data,
 741                          struct drm_file *file_priv)
 742 {
 743         drm_i915_private_t *dev_priv = dev->dev_private;
 744         drm_i915_getparam_t *param = data;
 745         int value;
 746
 747         if (!dev_priv) {
 748                 DRM_ERROR("called with no initialization\n");
 749                 return -EINVAL;
 750         }
 751
 752         switch (param->param) {
 753         case I915_PARAM_IRQ_ACTIVE:
 754                 value = dev->irq_enabled ? 1 : 0;
 755                 break;
 756         case I915_PARAM_ALLOW_BATCHBUFFER:
 757                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 758                 break;
 759         case I915_PARAM_LAST_DISPATCH:
 760                 value = READ_BREADCRUMB(dev_priv);
 761                 break;
 762         case I915_PARAM_CHIPSET_ID:
 763                 value = dev->pci_device;
 764                 break;
 765         case I915_PARAM_HAS_GEM:
 766                 value = 1;
 767                 break;
 768         case I915_PARAM_NUM_FENCES_AVAIL:
 769                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 770                 break;
 771         case I915_PARAM_HAS_OVERLAY:
 772                 value = dev_priv->overlay ? 1 : 0;
 773                 break;
 774         case I915_PARAM_HAS_PAGEFLIPPING:
 775                 value = 1;
 776                 break;
 777         case I915_PARAM_HAS_EXECBUF2:
 778                 value = 1;
 779                 break;
 780         case I915_PARAM_HAS_BSD:
 781                 value = HAS_BSD(dev);
 782                 break;
 783         case I915_PARAM_HAS_BLT:
 784                 value = HAS_BLT(dev);
 785                 break;
 786         case I915_PARAM_HAS_RELAXED_FENCING:
 787                 value = 1;
 788                 break;
 789         case I915_PARAM_HAS_COHERENT_RINGS:
 790                 value = 1;
 791                 break;
 792         case I915_PARAM_HAS_EXEC_CONSTANTS:
 793                 value = INTEL_INFO(dev)->gen >= 4;
 794                 break;
 795         case I915_PARAM_HAS_RELAXED_DELTA:
 796                 value = 1;
 797                 break;
 798         case I915_PARAM_HAS_GEN7_SOL_RESET:
 799                 value = 1;
 800                 break;
 801         case I915_PARAM_HAS_LLC:
 802                 value = HAS_LLC(dev);
 803                 break;
 804         default:
 805                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 806                                  param->param);
 807                 return -EINVAL;
 808         }
 809
 810         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 811                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 812                 return -EFAULT;
 813         }
 814
 815         return 0;
 816 }
 817
 818 static int i915_setparam(struct drm_device *dev, void *data,
 819                          struct drm_file *file_priv)
 820 {
 821         drm_i915_private_t *dev_priv = dev->dev_private;
 822         drm_i915_setparam_t *param = data;
 823
 824         if (!dev_priv) {
 825                 DRM_ERROR("called with no initialization\n");
 826                 return -EINVAL;
 827         }
 828
 829         switch (param->param) {
 830         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 831                 break;
 832         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 833                 dev_priv->tex_lru_log_granularity = param->value;
 834                 break;
 835         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 836                 dev_priv->allow_batchbuffer = param->value;
 837                 break;
 838         case I915_SETPARAM_NUM_USED_FENCES:
 839                 if (param->value > dev_priv->num_fence_regs ||
 840                     param->value < 0)
 841                         return -EINVAL;
 842                 /* Userspace can use first N regs */
 843                 dev_priv->fence_reg_start = param->value;
 844                 break;
 845         default:
 846                 DRM_DEBUG("unknown parameter %d\n", param->param);
 847                 return -EINVAL;
 848         }
 849
 850         return 0;
 851 }
 852
 853 static int i915_set_status_page(struct drm_device *dev, void *data,
 854                                 struct drm_file *file_priv)
 855 {
 856         drm_i915_private_t *dev_priv = dev->dev_private;
 857         drm_i915_hws_addr_t *hws = data;
 858         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 859
 860         if (!I915_NEED_GFX_HWS(dev))
 861                 return -EINVAL;
 862
 863         if (!dev_priv) {
 864                 DRM_ERROR("called with no initialization\n");
 865                 return -EINVAL;
 866         }
 867
 868         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
 869         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 870                 DRM_ERROR("tried to set status page when mode setting active\n");
 871                 return 0;
 872         }
 873
 874         ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
 875             hws->addr & (0x1ffff<<12);
 876
 877         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 878         dev_priv->hws_map.size = 4*1024;
 879         dev_priv->hws_map.type = 0;
 880         dev_priv->hws_map.flags = 0;
 881         dev_priv->hws_map.mtrr = 0;
 882
 883         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 884         if (dev_priv->hws_map.virtual == NULL) {
 885                 i915_dma_cleanup(dev);
 886                 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
 887                 DRM_ERROR("can not ioremap virtual address for"
 888                                 " G33 hw status page\n");
 889                 return -ENOMEM;
 890         }
 891         ring->status_page.page_addr = dev_priv->hw_status_page =
 892             dev_priv->hws_map.virtual;
 893
 894         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 895         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 896         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
 897                         dev_priv->status_gfx_addr);
 898         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 899         return 0;
 900 }
 901
 902 static bool
 903 intel_enable_ppgtt(struct drm_device *dev)
 904 {
 905         if (i915_enable_ppgtt >= 0)
 906                 return i915_enable_ppgtt;
 907
 908         /* Disable ppgtt on SNB if VT-d is on. */
 909         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
 910                 return false;
 911
 912         return true;
 913 }
 914
 915 static int
 916 i915_load_gem_init(struct drm_device *dev)
 917 {
 918         struct drm_i915_private *dev_priv = dev->dev_private;
 919         unsigned long prealloc_size, gtt_size, mappable_size;
 920         int ret;
 921
 922         prealloc_size = dev_priv->mm.gtt->stolen_size;
 923         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
 924         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
 925
 926         /* Basic memrange allocator for stolen space */
 927         drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
 928
 929         DRM_LOCK(dev);
 930         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 931                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 932                  * aperture accordingly when using aliasing ppgtt. */
 933                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 934                 /* For paranoia keep the guard page in between. */
 935                 gtt_size -= PAGE_SIZE;
 936
 937                 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
 938
 939                 ret = i915_gem_init_aliasing_ppgtt(dev);
 940                 if (ret) {
 941                         DRM_UNLOCK(dev);
 942                         return ret;
 943                 }
 944         } else {
 945                 /* Let GEM Manage all of the aperture.
 946                  *
 947                  * However, leave one page at the end still bound to the scratch
 948                  * page.  There are a number of places where the hardware
 949                  * apparently prefetches past the end of the object, and we've
 950                  * seen multiple hangs with the GPU head pointer stuck in a
 951                  * batchbuffer bound at the last page of the aperture.  One page
 952                  * should be enough to keep any prefetching inside of the
 953                  * aperture.
 954                  */
 955                 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
 956         }
 957
 958         ret = i915_gem_init_hw(dev);
 959         DRM_UNLOCK(dev);
 960         if (ret != 0) {
 961                 i915_gem_cleanup_aliasing_ppgtt(dev);
 962                 return (ret);
 963         }
 964
 965 #if 0
 966         /* Try to set up FBC with a reasonable compressed buffer size */
 967         if (I915_HAS_FBC(dev) && i915_powersave) {
 968                 int cfb_size;
 969
 970                 /* Leave 1M for line length buffer & misc. */
 971
 972                 /* Try to get a 32M buffer... */
 973                 if (prealloc_size > (36*1024*1024))
 974                         cfb_size = 32*1024*1024;
 975                 else /* fall back to 7/8 of the stolen space */
 976                         cfb_size = prealloc_size * 7 / 8;
 977                 i915_setup_compression(dev, cfb_size);
 978         }
 979 #endif
 980
 981         /* Allow hardware batchbuffers unless told otherwise. */
 982         dev_priv->allow_batchbuffer = 1;
 983         return 0;
 984 }
 985
 986 static int
 987 i915_load_modeset_init(struct drm_device *dev)
 988 {
 989         struct drm_i915_private *dev_priv = dev->dev_private;
 990         int ret;
 991
 992         ret = intel_parse_bios(dev);
 993         if (ret)
 994                 DRM_INFO("failed to find VBIOS tables\n");
 995
 996 #if 0
 997         intel_register_dsm_handler();
 998 #endif
 999
1000         /* IIR "flip pending" bit means done if this bit is set */
1001         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1002                 dev_priv->flip_pending_is_done = true;
1003
1004         intel_modeset_init(dev);
1005
1006         ret = i915_load_gem_init(dev);
1007         if (ret != 0)
1008                 goto cleanup_gem;
1009
1010         intel_modeset_gem_init(dev);
1011
1012         ret = drm_irq_install(dev);
1013         if (ret)
1014                 goto cleanup_gem;
1015
1016         dev->vblank_disable_allowed = 1;
1017
1018         ret = intel_fbdev_init(dev);
1019         if (ret)
1020                 goto cleanup_gem;
1021
1022         drm_kms_helper_poll_init(dev);
1023
1024         /* We're off and running w/KMS */
1025         dev_priv->mm.suspended = 0;
1026
1027         return (0);
1028
1029 cleanup_gem:
1030         DRM_LOCK(dev);
1031         i915_gem_cleanup_ringbuffer(dev);
1032         DRM_UNLOCK(dev);
1033         i915_gem_cleanup_aliasing_ppgtt(dev);
1034         return (ret);
1035 }
1036
1037 static int
1038 i915_get_bridge_dev(struct drm_device *dev)
1039 {
1040         struct drm_i915_private *dev_priv;
1041
1042         dev_priv = dev->dev_private;
1043
1044         dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1045         if (dev_priv->bridge_dev == NULL) {
1046                 DRM_ERROR("bridge device not found\n");
1047                 return (-1);
1048         }
1049         return (0);
1050 }
1051
1052 #define MCHBAR_I915 0x44
1053 #define MCHBAR_I965 0x48
1054 #define MCHBAR_SIZE (4*4096)
1055
1056 #define DEVEN_REG 0x54
1057 #define   DEVEN_MCHBAR_EN (1 << 28)
1058
1059 /* Allocate space for the MCH regs if needed, return nonzero on error */
1060 static int
1061 intel_alloc_mchbar_resource(struct drm_device *dev)
1062 {
1063         drm_i915_private_t *dev_priv;
1064         device_t vga;
1065         int reg;
1066         u32 temp_lo, temp_hi;
1067         u64 mchbar_addr, temp;
1068
1069         dev_priv = dev->dev_private;
1070         reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1071
1072         if (INTEL_INFO(dev)->gen >= 4)
1073                 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1074         else
1075                 temp_hi = 0;
1076         temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1077         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1078
1079         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1080 #ifdef XXX_CONFIG_PNP
1081         if (mchbar_addr &&
1082             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1083                 return 0;
1084 #endif
1085
1086         /* Get some space for it */
1087         vga = device_get_parent(dev->dev);
1088         dev_priv->mch_res_rid = 0x100;
1089         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1090             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1091             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1092         if (dev_priv->mch_res == NULL) {
1093                 DRM_ERROR("failed mchbar resource alloc\n");
1094                 return (-ENOMEM);
1095         }
1096
1097         if (INTEL_INFO(dev)->gen >= 4) {
1098                 temp = rman_get_start(dev_priv->mch_res);
1099                 temp >>= 32;
1100                 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1101         }
1102         pci_write_config(dev_priv->bridge_dev, reg,
1103             rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1104         return (0);
1105 }
1106
1107 static void
1108 intel_setup_mchbar(struct drm_device *dev)
1109 {
1110         drm_i915_private_t *dev_priv;
1111         int mchbar_reg;
1112         u32 temp;
1113         bool enabled;
1114
1115         dev_priv = dev->dev_private;
1116         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1117
1118         dev_priv->mchbar_need_disable = false;
1119
1120         if (IS_I915G(dev) || IS_I915GM(dev)) {
1121                 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1122                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1123         } else {
1124                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1125                 enabled = temp & 1;
1126         }
1127
1128         /* If it's already enabled, don't have to do anything */
1129         if (enabled) {
1130                 DRM_DEBUG("mchbar already enabled\n");
1131                 return;
1132         }
1133
1134         if (intel_alloc_mchbar_resource(dev))
1135                 return;
1136
1137         dev_priv->mchbar_need_disable = true;
1138
1139         /* Space is allocated or reserved, so enable it. */
1140         if (IS_I915G(dev) || IS_I915GM(dev)) {
1141                 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1142                     temp | DEVEN_MCHBAR_EN, 4);
1143         } else {
1144                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1145                 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1146         }
1147 }
1148
1149 static void
1150 intel_teardown_mchbar(struct drm_device *dev)
1151 {
1152         drm_i915_private_t *dev_priv;
1153         device_t vga;
1154         int mchbar_reg;
1155         u32 temp;
1156
1157         dev_priv = dev->dev_private;
1158         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1159
1160         if (dev_priv->mchbar_need_disable) {
1161                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1162                         temp = pci_read_config(dev_priv->bridge_dev,
1163                             DEVEN_REG, 4);
1164                         temp &= ~DEVEN_MCHBAR_EN;
1165                         pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1166                             temp, 4);
1167                 } else {
1168                         temp = pci_read_config(dev_priv->bridge_dev,
1169                             mchbar_reg, 4);
1170                         temp &= ~1;
1171                         pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1172                             temp, 4);
1173                 }
1174         }
1175
1176         if (dev_priv->mch_res != NULL) {
1177                 vga = device_get_parent(dev->dev);
1178                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1179                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1180                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1181                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1182                 dev_priv->mch_res = NULL;
1183         }
1184 }
1185
1186 /**
1187  * i915_driver_load - setup chip and create an initial config
1188  * @dev: DRM device
1189  * @flags: startup flags
1190  *
1191  * The driver load routine has to do several things:
1192  *   - drive output discovery via intel_modeset_init()
1193  *   - initialize the memory manager
1194  *   - allocate initial config memory
1195  *   - setup the DRM framebuffer with the allocated memory
1196  */
1197 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1198 {
1199         struct drm_i915_private *dev_priv = dev->dev_private;
1200         unsigned long base, size;
1201         int mmio_bar, ret;
1202
1203         ret = 0;
1204
1205         /* i915 has 4 more counters */
1206         dev->counters += 4;
1207         dev->types[6] = _DRM_STAT_IRQ;
1208         dev->types[7] = _DRM_STAT_PRIMARY;
1209         dev->types[8] = _DRM_STAT_SECONDARY;
1210         dev->types[9] = _DRM_STAT_DMA;
1211
1212         dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1213             M_ZERO | M_WAITOK);
1214         if (dev_priv == NULL)
1215                 return -ENOMEM;
1216
1217         dev->dev_private = (void *)dev_priv;
1218         dev_priv->dev = dev;
1219         dev_priv->info = i915_get_device_id(dev->pci_device);
1220
1221         if (i915_get_bridge_dev(dev)) {
1222                 drm_free(dev_priv, DRM_MEM_DRIVER);
1223                 return (-EIO);
1224         }
1225         dev_priv->mm.gtt = intel_gtt_get();
1226
1227         /* Add register map (needed for suspend/resume) */
1228         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1229         base = drm_get_resource_start(dev, mmio_bar);
1230         size = drm_get_resource_len(dev, mmio_bar);
1231
1232         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1233             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1234
1235         /* The i915 workqueue is primarily used for batched retirement of
1236          * requests (and thus managing bo) once the task has been completed
1237          * by the GPU. i915_gem_retire_requests() is called directly when we
1238          * need high-priority retirement, such as waiting for an explicit
1239          * bo.
1240          *
1241          * It is also used for periodic low-priority events, such as
1242          * idle-timers and recording error state.
1243          *
1244          * All tasks on the workqueue are expected to acquire the dev mutex
1245          * so there is no point in running more than one instance of the
1246          * workqueue at any time.  Use an ordered one.
1247          */
1248         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1249         if (dev_priv->wq == NULL) {
1250                 DRM_ERROR("Failed to create our workqueue.\n");
1251                 ret = -ENOMEM;
1252                 goto out_mtrrfree;
1253         }
1254
1255         lockinit(&dev_priv->gt_lock, "915gt", 0, LK_CANRECURSE);
1256         lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1257         spin_init(&dev_priv->rps.lock);
1258         lockinit(&dev_priv->error_completion_lock, "915cmp", 0, LK_CANRECURSE);
1259
1260         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1261
1262         dev_priv->has_gem = 1;
1263         intel_irq_init(dev);
1264
1265         intel_setup_mchbar(dev);
1266         intel_setup_gmbus(dev);
1267         intel_opregion_setup(dev);
1268
1269         intel_setup_bios(dev);
1270
1271         i915_gem_load(dev);
1272
1273         /* Init HWS */
1274         if (!I915_NEED_GFX_HWS(dev)) {
1275                 ret = i915_init_phys_hws(dev);
1276                 if (ret != 0) {
1277                         drm_rmmap(dev, dev_priv->mmio_map);
1278                         drm_free(dev_priv, DRM_MEM_DRIVER);
1279                         return ret;
1280                 }
1281         }
1282
1283         if (IS_PINEVIEW(dev))
1284                 i915_pineview_get_mem_freq(dev);
1285         else if (IS_GEN5(dev))
1286                 i915_ironlake_get_mem_freq(dev);
1287
1288         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1289
1290         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1291                 dev_priv->num_pipe = 3;
1292         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1293                 dev_priv->num_pipe = 2;
1294         else
1295                 dev_priv->num_pipe = 1;
1296
1297         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1298         if (ret)
1299                 goto out_gem_unload;
1300
1301         /* Start out suspended */
1302         dev_priv->mm.suspended = 1;
1303
1304         intel_detect_pch(dev);
1305
1306         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1307                 ret = i915_load_modeset_init(dev);
1308                 if (ret < 0) {
1309                         DRM_ERROR("failed to init modeset\n");
1310                         goto out_gem_unload;
1311                 }
1312         }
1313
1314         intel_opregion_init(dev);
1315
1316         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1317                     (unsigned long) dev);
1318
1319         if (IS_GEN5(dev)) {
1320                 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1321                 i915_mch_dev = dev_priv;
1322                 dev_priv->mchdev_lock = &mchdev_lock;
1323                 lockmgr(&mchdev_lock, LK_RELEASE);
1324         }
1325
1326         return (0);
1327
1328 out_gem_unload:
1329         /* XXXKIB */
1330         (void) i915_driver_unload_int(dev, true);
1331         return (ret);
1332 out_mtrrfree:
1333         return ret;
1334 }
1335
1336 static int
1337 i915_driver_unload_int(struct drm_device *dev, bool locked)
1338 {
1339         struct drm_i915_private *dev_priv = dev->dev_private;
1340         int ret;
1341
1342         if (!locked)
1343                 DRM_LOCK(dev);
1344         ret = i915_gpu_idle(dev, true);
1345         if (ret)
1346                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1347         if (!locked)
1348                 DRM_UNLOCK(dev);
1349
1350         i915_free_hws(dev);
1351
1352         intel_teardown_mchbar(dev);
1353
1354         if (locked)
1355                 DRM_UNLOCK(dev);
1356         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1357                 intel_fbdev_fini(dev);
1358                 intel_modeset_cleanup(dev);
1359         }
1360
1361         /* Free error state after interrupts are fully disabled. */
1362         del_timer_sync(&dev_priv->hangcheck_timer);
1363
1364         i915_destroy_error_state(dev);
1365
1366         intel_opregion_fini(dev);
1367
1368         if (locked)
1369                 DRM_LOCK(dev);
1370
1371         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1372                 if (!locked)
1373                         DRM_LOCK(dev);
1374                 i915_gem_free_all_phys_object(dev);
1375                 i915_gem_cleanup_ringbuffer(dev);
1376                 if (!locked)
1377                         DRM_UNLOCK(dev);
1378                 i915_gem_cleanup_aliasing_ppgtt(dev);
1379 #if 1
1380                 KIB_NOTYET();
1381 #else
1382                 if (I915_HAS_FBC(dev) && i915_powersave)
1383                         i915_cleanup_compression(dev);
1384 #endif
1385                 drm_mm_takedown(&dev_priv->mm.stolen);
1386
1387                 intel_cleanup_overlay(dev);
1388
1389                 if (!I915_NEED_GFX_HWS(dev))
1390                         i915_free_hws(dev);
1391         }
1392
1393         i915_gem_unload(dev);
1394
1395         lockuninit(&dev_priv->irq_lock);
1396
1397         if (dev_priv->wq != NULL)
1398                 destroy_workqueue(dev_priv->wq);
1399
1400         bus_generic_detach(dev->dev);
1401         drm_rmmap(dev, dev_priv->mmio_map);
1402         intel_teardown_gmbus(dev);
1403
1404         lockuninit(&dev_priv->error_lock);
1405         lockuninit(&dev_priv->error_completion_lock);
1406         drm_free(dev->dev_private, DRM_MEM_DRIVER);
1407
1408         return (0);
1409 }
1410
1411 int
1412 i915_driver_unload(struct drm_device *dev)
1413 {
1414
1415         return (i915_driver_unload_int(dev, true));
1416 }
1417
1418 int
1419 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1420 {
1421         struct drm_i915_file_private *i915_file_priv;
1422
1423         i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1424             M_WAITOK | M_ZERO);
1425
1426         spin_init(&i915_file_priv->mm.lock);
1427         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1428         file_priv->driver_priv = i915_file_priv;
1429
1430         return (0);
1431 }
1432
1433 void
1434 i915_driver_lastclose(struct drm_device * dev)
1435 {
1436         drm_i915_private_t *dev_priv = dev->dev_private;
1437
1438         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1439 #if 1
1440                 KIB_NOTYET();
1441 #else
1442                 drm_fb_helper_restore();
1443                 vga_switcheroo_process_delayed_switch();
1444 #endif
1445                 return;
1446         }
1447         i915_gem_lastclose(dev);
1448         i915_dma_cleanup(dev);
1449 }
1450
1451 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1452 {
1453
1454         i915_gem_release(dev, file_priv);
1455 }
1456
1457 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1458 {
1459         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1460
1461         spin_uninit(&i915_file_priv->mm.lock);
1462         drm_free(i915_file_priv, DRM_MEM_FILES);
1463 }
1464
1465 struct drm_ioctl_desc i915_ioctls[] = {
1466         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1467         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1468         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1469         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1470         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1471         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1472         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1473         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1474         DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1475         DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1476         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1477         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1478         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1479         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1480         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1481         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1482         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1483         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1484         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1485         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1486         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1487         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1488         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1489         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1490         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1491         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1492         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1493         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1494         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1495         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1496         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1497         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1498         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1499         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1500         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1501         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1502         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1503         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1504         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1505         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1506         DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1507         DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1508 };
1509
1510 struct drm_driver i915_driver_info = {
1511         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1512             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1513             DRIVER_GEM /*| DRIVER_MODESET*/,
1514
1515         .buf_priv_size  = sizeof(drm_i915_private_t),
1516         .load           = i915_driver_load,
1517         .open           = i915_driver_open,
1518         .unload         = i915_driver_unload,
1519         .preclose       = i915_driver_preclose,
1520         .lastclose      = i915_driver_lastclose,
1521         .postclose      = i915_driver_postclose,
1522         .device_is_agp  = i915_driver_device_is_agp,
1523         .gem_init_object = i915_gem_init_object,
1524         .gem_free_object = i915_gem_free_object,
1525         .gem_pager_ops  = &i915_gem_pager_ops,
1526         .dumb_create    = i915_gem_dumb_create,
1527         .dumb_map_offset = i915_gem_mmap_gtt,
1528         .dumb_destroy   = i915_gem_dumb_destroy,
1529         .sysctl_init    = i915_sysctl_init,
1530         .sysctl_cleanup = i915_sysctl_cleanup,
1531
1532         .ioctls         = i915_ioctls,
1533         .max_ioctl      = DRM_ARRAY_SIZE(i915_ioctls),
1534
1535         .name           = DRIVER_NAME,
1536         .desc           = DRIVER_DESC,
1537         .date           = DRIVER_DATE,
1538         .major          = DRIVER_MAJOR,
1539         .minor          = DRIVER_MINOR,
1540         .patchlevel     = DRIVER_PATCHLEVEL,
1541 };
1542
1543 /**
1544  * Determine if the device really is AGP or not.
1545  *
1546  * All Intel graphics chipsets are treated as AGP, even if they are really
1547  * built-in.
1548  *
1549  * \param dev   The device to be tested.
1550  *
1551  * \returns
1552  * A value of 1 is always retured to indictate every i9x5 is AGP.
1553  */
1554 int i915_driver_device_is_agp(struct drm_device * dev)
1555 {
1556         return 1;
1557 }