sys/dev/disk/advansys/adwcam.c

   1 /*
   2  * CAM SCSI interface for the the Advanced Systems Inc.
   3  * Second Generation SCSI controllers.
   4  *
   5  * Product specific probe and attach routines can be found in:
   6  *
   7  * adw_pci.c    ABP[3]940UW, ABP950UW, ABP3940U2W
   8  *
   9  * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
  10  * All rights reserved.
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions, and the following disclaimer,
  17  *    without modification.
  18  * 2. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  25  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/advansys/adwcam.c,v 1.7.2.2 2001/03/05 13:08:55 obrien Exp $
  34  * $DragonFly: src/sys/dev/disk/advansys/adwcam.c,v 1.19 2008/05/18 20:30:20 pavalos Exp $
  35  */
  36 /*
  37  * Ported from:
  38  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
  39  *
  40  * Copyright (c) 1995-1998 Advanced System Products, Inc.
  41  * All Rights Reserved.
  42  *
  43  * Redistribution and use in source and binary forms, with or without
  44  * modification, are permitted provided that redistributions of source
  45  * code retain the above copyright notice and this comment without
  46  * modification.
  47  */
  48
  49 #include <sys/param.h>
  50 #include <sys/systm.h>
  51 #include <sys/kernel.h>
  52 #include <sys/malloc.h>
  53 #include <sys/bus.h>
  54 #include <sys/thread2.h>
  55
  56 #include <machine/clock.h>
  57
  58 #include <sys/rman.h>
  59
  60 #include <bus/cam/cam.h>
  61 #include <bus/cam/cam_ccb.h>
  62 #include <bus/cam/cam_sim.h>
  63 #include <bus/cam/cam_xpt_sim.h>
  64 #include <bus/cam/cam_debug.h>
  65
  66 #include <bus/cam/scsi/scsi_message.h>
  67
  68 #include "adwvar.h"
  69
  70 /* Definitions for our use of the SIM private CCB area */
  71 #define ccb_acb_ptr spriv_ptr0
  72 #define ccb_adw_ptr spriv_ptr1
  73
  74 u_long adw_unit;
  75
  76 static __inline cam_status      adwccbstatus(union ccb*);
  77 static __inline struct acb*     adwgetacb(struct adw_softc *adw);
  78 static __inline void            adwfreeacb(struct adw_softc *adw,
  79                                            struct acb *acb);
  80
  81 static void             adwmapmem(void *arg, bus_dma_segment_t *segs,
  82                                   int nseg, int error);
  83 static struct sg_map_node*
  84                         adwallocsgmap(struct adw_softc *adw);
  85 static int              adwallocacbs(struct adw_softc *adw);
  86
  87 static void             adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs,
  88                                       int nseg, int error);
  89 static void             adw_action(struct cam_sim *sim, union ccb *ccb);
  90 static void             adw_poll(struct cam_sim *sim);
  91 static void             adw_async(void *callback_arg, u_int32_t code,
  92                                   struct cam_path *path, void *arg);
  93 static void             adwprocesserror(struct adw_softc *adw, struct acb *acb);
  94 static void             adwtimeout(void *arg);
  95 static void             adw_handle_device_reset(struct adw_softc *adw,
  96                                                 u_int target);
  97 static void             adw_handle_bus_reset(struct adw_softc *adw,
  98                                              int initiated);
  99
 100 static __inline cam_status
 101 adwccbstatus(union ccb* ccb)
 102 {
 103         return (ccb->ccb_h.status & CAM_STATUS_MASK);
 104 }
 105
 106 static __inline struct acb*
 107 adwgetacb(struct adw_softc *adw)
 108 {
 109         struct  acb* acb;
 110
 111         crit_enter();
 112         if ((acb = SLIST_FIRST(&adw->free_acb_list)) != NULL) {
 113                 SLIST_REMOVE_HEAD(&adw->free_acb_list, links);
 114         } else if (adw->num_acbs < adw->max_acbs) {
 115                 adwallocacbs(adw);
 116                 acb = SLIST_FIRST(&adw->free_acb_list);
 117                 if (acb == NULL)
 118                         kprintf("%s: Can't malloc ACB\n", adw_name(adw));
 119                 else {
 120                         SLIST_REMOVE_HEAD(&adw->free_acb_list, links);
 121                 }
 122         }
 123         crit_exit();
 124
 125         return (acb);
 126 }
 127
 128 static __inline void
 129 adwfreeacb(struct adw_softc *adw, struct acb *acb)
 130 {
 131         crit_enter();
 132         if ((acb->state & ACB_ACTIVE) != 0)
 133                 LIST_REMOVE(&acb->ccb->ccb_h, sim_links.le);
 134         if ((acb->state & ACB_RELEASE_SIMQ) != 0)
 135                 acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 136         else if ((adw->state & ADW_RESOURCE_SHORTAGE) != 0
 137               && (acb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) {
 138                 acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 139                 adw->state &= ~ADW_RESOURCE_SHORTAGE;
 140         }
 141         acb->state = ACB_FREE;
 142         SLIST_INSERT_HEAD(&adw->free_acb_list, acb, links);
 143         crit_exit();
 144 }
 145
 146 static void
 147 adwmapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 148 {
 149         bus_addr_t *busaddrp;
 150
 151         busaddrp = (bus_addr_t *)arg;
 152         *busaddrp = segs->ds_addr;
 153 }
 154
 155 static struct sg_map_node *
 156 adwallocsgmap(struct adw_softc *adw)
 157 {
 158         struct sg_map_node *sg_map;
 159
 160         sg_map = kmalloc(sizeof(*sg_map), M_DEVBUF, M_INTWAIT);
 161
 162         /* Allocate S/G space for the next batch of ACBS */
 163         if (bus_dmamem_alloc(adw->sg_dmat, (void *)&sg_map->sg_vaddr,
 164                              BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
 165                 kfree(sg_map, M_DEVBUF);
 166                 return (NULL);
 167         }
 168
 169         SLIST_INSERT_HEAD(&adw->sg_maps, sg_map, links);
 170
 171         bus_dmamap_load(adw->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr,
 172                         PAGE_SIZE, adwmapmem, &sg_map->sg_physaddr, /*flags*/0);
 173
 174         bzero(sg_map->sg_vaddr, PAGE_SIZE);
 175         return (sg_map);
 176 }
 177
 178 /*
 179  * Allocate another chunk of CCB's. Return count of entries added.
 180  * Assumed to be called under crit_enter().
 181  */
 182 static int
 183 adwallocacbs(struct adw_softc *adw)
 184 {
 185         struct acb *next_acb;
 186         struct sg_map_node *sg_map;
 187         bus_addr_t busaddr;
 188         struct adw_sg_block *blocks;
 189         int newcount;
 190         int i;
 191
 192         next_acb = &adw->acbs[adw->num_acbs];
 193         sg_map = adwallocsgmap(adw);
 194
 195         if (sg_map == NULL)
 196                 return (0);
 197
 198         blocks = sg_map->sg_vaddr;
 199         busaddr = sg_map->sg_physaddr;
 200
 201         newcount = (PAGE_SIZE / (ADW_SG_BLOCKCNT * sizeof(*blocks)));
 202         for (i = 0; adw->num_acbs < adw->max_acbs && i < newcount; i++) {
 203                 int error;
 204
 205                 error = bus_dmamap_create(adw->buffer_dmat, /*flags*/0,
 206                                           &next_acb->dmamap);
 207                 if (error != 0)
 208                         break;
 209                 next_acb->queue.scsi_req_baddr = acbvtob(adw, next_acb);
 210                 next_acb->queue.scsi_req_bo = acbvtobo(adw, next_acb);
 211                 next_acb->queue.sense_baddr =
 212                     acbvtob(adw, next_acb) + offsetof(struct acb, sense_data);
 213                 next_acb->sg_blocks = blocks;
 214                 next_acb->sg_busaddr = busaddr;
 215                 next_acb->state = ACB_FREE;
 216                 SLIST_INSERT_HEAD(&adw->free_acb_list, next_acb, links);
 217                 blocks += ADW_SG_BLOCKCNT;
 218                 busaddr += ADW_SG_BLOCKCNT * sizeof(*blocks);
 219                 next_acb++;
 220                 adw->num_acbs++;
 221         }
 222         return (i);
 223 }
 224
 225 static void
 226 adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
 227 {
 228         struct   acb *acb;
 229         union    ccb *ccb;
 230         struct   adw_softc *adw;
 231
 232         acb = (struct acb *)arg;
 233         ccb = acb->ccb;
 234         adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr;
 235
 236         if (error != 0) {
 237                 if (error != EFBIG)
 238                         kprintf("%s: Unexpected error 0x%x returned from "
 239                                "bus_dmamap_load\n", adw_name(adw), error);
 240                 if (ccb->ccb_h.status == CAM_REQ_INPROG) {
 241                         xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
 242                         ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN;
 243                 }
 244                 adwfreeacb(adw, acb);
 245                 xpt_done(ccb);
 246                 return;
 247         }
 248
 249         if (nseg != 0) {
 250                 bus_dmasync_op_t op;
 251
 252                 acb->queue.data_addr = dm_segs[0].ds_addr;
 253                 acb->queue.data_cnt = ccb->csio.dxfer_len;
 254                 if (nseg > 1) {
 255                         struct adw_sg_block *sg_block;
 256                         struct adw_sg_elm *sg;
 257                         bus_addr_t sg_busaddr;
 258                         u_int sg_index;
 259                         bus_dma_segment_t *end_seg;
 260
 261                         end_seg = dm_segs + nseg;
 262
 263                         sg_busaddr = acb->sg_busaddr;
 264                         sg_index = 0;
 265                         /* Copy the segments into our SG list */
 266                         for (sg_block = acb->sg_blocks;; sg_block++) {
 267                                 u_int i;
 268
 269                                 sg = sg_block->sg_list;
 270                                 for (i = 0; i < ADW_NO_OF_SG_PER_BLOCK; i++) {
 271                                         if (dm_segs >= end_seg)
 272                                                 break;
 273
 274                                         sg->sg_addr = dm_segs->ds_addr;
 275                                         sg->sg_count = dm_segs->ds_len;
 276                                         sg++;
 277                                         dm_segs++;
 278                                 }
 279                                 sg_block->sg_cnt = i;
 280                                 sg_index += i;
 281                                 if (dm_segs == end_seg) {
 282                                         sg_block->sg_busaddr_next = 0;
 283                                         break;
 284                                 } else {
 285                                         sg_busaddr +=
 286                                             sizeof(struct adw_sg_block);
 287                                         sg_block->sg_busaddr_next = sg_busaddr;
 288                                 }
 289                         }
 290                         acb->queue.sg_real_addr = acb->sg_busaddr;
 291                 } else {
 292                         acb->queue.sg_real_addr = 0;
 293                 }
 294
 295                 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
 296                         op = BUS_DMASYNC_PREREAD;
 297                 else
 298                         op = BUS_DMASYNC_PREWRITE;
 299
 300                 bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op);
 301
 302         } else {
 303                 acb->queue.data_addr = 0;
 304                 acb->queue.data_cnt = 0;
 305                 acb->queue.sg_real_addr = 0;
 306         }
 307
 308         crit_enter();
 309
 310         /*
 311          * Last time we need to check if this CCB needs to
 312          * be aborted.
 313          */
 314         if (ccb->ccb_h.status != CAM_REQ_INPROG) {
 315                 if (nseg != 0)
 316                         bus_dmamap_unload(adw->buffer_dmat, acb->dmamap);
 317                 adwfreeacb(adw, acb);
 318                 xpt_done(ccb);
 319                 crit_exit();
 320                 return;
 321         }
 322
 323         acb->state |= ACB_ACTIVE;
 324         ccb->ccb_h.status |= CAM_SIM_QUEUED;
 325         LIST_INSERT_HEAD(&adw->pending_ccbs, &ccb->ccb_h, sim_links.le);
 326         callout_reset(&ccb->ccb_h.timeout_ch, (ccb->ccb_h.timeout * hz) / 1000,
 327             adwtimeout, acb);
 328
 329         adw_send_acb(adw, acb, acbvtob(adw, acb));
 330
 331         crit_exit();
 332 }
 333
 334 static void
 335 adw_action(struct cam_sim *sim, union ccb *ccb)
 336 {
 337         struct  adw_softc *adw;
 338
 339         CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adw_action\n"));
 340
 341         adw = (struct adw_softc *)cam_sim_softc(sim);
 342
 343         switch (ccb->ccb_h.func_code) {
 344         /* Common cases first */
 345         case XPT_SCSI_IO:       /* Execute the requested I/O operation */
 346         {
 347                 struct  ccb_scsiio *csio;
 348                 struct  ccb_hdr *ccbh;
 349                 struct  acb *acb;
 350
 351                 csio = &ccb->csio;
 352                 ccbh = &ccb->ccb_h;
 353
 354                 /* Max supported CDB length is 12 bytes */
 355                 if (csio->cdb_len > 12) {
 356                         ccb->ccb_h.status = CAM_REQ_INVALID;
 357                         xpt_done(ccb);
 358                         return;
 359                 }
 360
 361                 if ((acb = adwgetacb(adw)) == NULL) {
 362                         crit_enter();
 363                         adw->state |= ADW_RESOURCE_SHORTAGE;
 364                         crit_exit();
 365                         xpt_freeze_simq(sim, /*count*/1);
 366                         ccb->ccb_h.status = CAM_REQUEUE_REQ;
 367                         xpt_done(ccb);
 368                         return;
 369                 }
 370
 371                 /* Link acb and ccb so we can find one from the other */
 372                 acb->ccb = ccb;
 373                 ccb->ccb_h.ccb_acb_ptr = acb;
 374                 ccb->ccb_h.ccb_adw_ptr = adw;
 375
 376                 acb->queue.cntl = 0;
 377                 acb->queue.target_cmd = 0;
 378                 acb->queue.target_id = ccb->ccb_h.target_id;
 379                 acb->queue.target_lun = ccb->ccb_h.target_lun;
 380
 381                 acb->queue.mflag = 0;
 382                 acb->queue.sense_len =
 383                         MIN(csio->sense_len, sizeof(acb->sense_data));
 384                 acb->queue.cdb_len = csio->cdb_len;
 385                 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) {
 386                         switch (csio->tag_action) {
 387                         case MSG_SIMPLE_Q_TAG:
 388                                 acb->queue.scsi_cntl = ADW_QSC_SIMPLE_Q_TAG;
 389                                 break;
 390                         case MSG_HEAD_OF_Q_TAG:
 391                                 acb->queue.scsi_cntl = ADW_QSC_HEAD_OF_Q_TAG;
 392                                 break;
 393                         case MSG_ORDERED_Q_TAG:
 394                                 acb->queue.scsi_cntl = ADW_QSC_ORDERED_Q_TAG;
 395                                 break;
 396                         default:
 397                                 acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG;
 398                                 break;
 399                         }
 400                 } else
 401                         acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG;
 402
 403                 if ((ccb->ccb_h.flags & CAM_DIS_DISCONNECT) != 0)
 404                         acb->queue.scsi_cntl |= ADW_QSC_NO_DISC;
 405
 406                 acb->queue.done_status = 0;
 407                 acb->queue.scsi_status = 0;
 408                 acb->queue.host_status = 0;
 409                 acb->queue.sg_wk_ix = 0;
 410                 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) {
 411                         if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) {
 412                                 bcopy(csio->cdb_io.cdb_ptr,
 413                                       acb->queue.cdb, csio->cdb_len);
 414                         } else {
 415                                 /* I guess I could map it in... */
 416                                 ccb->ccb_h.status = CAM_REQ_INVALID;
 417                                 adwfreeacb(adw, acb);
 418                                 xpt_done(ccb);
 419                                 return;
 420                         }
 421                 } else {
 422                         bcopy(csio->cdb_io.cdb_bytes,
 423                               acb->queue.cdb, csio->cdb_len);
 424                 }
 425
 426                 /*
 427                  * If we have any data to send with this command,
 428                  * map it into bus space.
 429                  */
 430                 if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 431                         if ((ccbh->flags & CAM_SCATTER_VALID) == 0) {
 432                                 /*
 433                                  * We've been given a pointer
 434                                  * to a single buffer.
 435                                  */
 436                                 if ((ccbh->flags & CAM_DATA_PHYS) == 0) {
 437                                         int error;
 438
 439                                         crit_enter();
 440                                         error =
 441                                             bus_dmamap_load(adw->buffer_dmat,
 442                                                             acb->dmamap,
 443                                                             csio->data_ptr,
 444                                                             csio->dxfer_len,
 445                                                             adwexecuteacb,
 446                                                             acb, /*flags*/0);
 447                                         if (error == EINPROGRESS) {
 448                                                 /*
 449                                                  * So as to maintain ordering,
 450                                                  * freeze the controller queue
 451                                                  * until our mapping is
 452                                                  * returned.
 453                                                  */
 454                                                 xpt_freeze_simq(sim, 1);
 455                                                 acb->state |= CAM_RELEASE_SIMQ;
 456                                         }
 457                                         crit_exit();
 458                                 } else {
 459                                         struct bus_dma_segment seg;
 460
 461                                         /* Pointer to physical buffer */
 462                                         seg.ds_addr =
 463                                             (bus_addr_t)csio->data_ptr;
 464                                         seg.ds_len = csio->dxfer_len;
 465                                         adwexecuteacb(acb, &seg, 1, 0);
 466                                 }
 467                         } else {
 468                                 struct bus_dma_segment *segs;
 469
 470                                 if ((ccbh->flags & CAM_DATA_PHYS) != 0)
 471                                         panic("adw_action - Physical "
 472                                               "segment pointers "
 473                                               "unsupported");
 474
 475                                 if ((ccbh->flags&CAM_SG_LIST_PHYS)==0)
 476                                         panic("adw_action - Virtual "
 477                                               "segment addresses "
 478                                               "unsupported");
 479
 480                                 /* Just use the segments provided */
 481                                 segs = (struct bus_dma_segment *)csio->data_ptr;
 482                                 adwexecuteacb(acb, segs, csio->sglist_cnt,
 483                                               (csio->sglist_cnt < ADW_SGSIZE)
 484                                               ? 0 : EFBIG);
 485                         }
 486                 } else {
 487                         adwexecuteacb(acb, NULL, 0, 0);
 488                 }
 489                 break;
 490         }
 491         case XPT_RESET_DEV:     /* Bus Device Reset the specified SCSI device */
 492         {
 493                 adw_idle_cmd_status_t status;
 494
 495                 status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET,
 496                                            ccb->ccb_h.target_id);
 497                 if (status == ADW_IDLE_CMD_SUCCESS) {
 498                         ccb->ccb_h.status = CAM_REQ_CMP;
 499                         if (bootverbose) {
 500                                 xpt_print_path(ccb->ccb_h.path);
 501                                 kprintf("BDR Delivered\n");
 502                         }
 503                 } else
 504                         ccb->ccb_h.status = CAM_REQ_CMP_ERR;
 505                 xpt_done(ccb);
 506                 break;
 507         }
 508         case XPT_ABORT:                 /* Abort the specified CCB */
 509                 /* XXX Implement */
 510                 ccb->ccb_h.status = CAM_REQ_INVALID;
 511                 xpt_done(ccb);
 512                 break;
 513         case XPT_SET_TRAN_SETTINGS:
 514         {
 515                 struct ccb_trans_settings_scsi *scsi;
 516                 struct ccb_trans_settings_spi *spi;
 517                 struct    ccb_trans_settings *cts;
 518                 u_int     target_mask;
 519
 520                 cts = &ccb->cts;
 521                 target_mask = 0x01 << ccb->ccb_h.target_id;
 522
 523                 crit_enter();
 524                 scsi = &cts->proto_specific.scsi;
 525                 spi = &cts->xport_specific.spi;
 526                 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
 527                         u_int sdtrdone;
 528
 529                         sdtrdone = adw_lram_read_16(adw, ADW_MC_SDTR_DONE);
 530                         if ((spi->valid & CTS_SPI_VALID_DISC) != 0) {
 531                                 u_int discenb;
 532
 533                                 discenb =
 534                                     adw_lram_read_16(adw, ADW_MC_DISC_ENABLE);
 535
 536                                 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0)
 537                                         discenb |= target_mask;
 538                                 else
 539                                         discenb &= ~target_mask;
 540
 541                                 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE,
 542                                                   discenb);
 543                         }
 544
 545                         if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
 546
 547                                 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0)
 548                                         adw->tagenb |= target_mask;
 549                                 else
 550                                         adw->tagenb &= ~target_mask;
 551                         }
 552
 553                         if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) {
 554                                 u_int wdtrenb_orig;
 555                                 u_int wdtrenb;
 556                                 u_int wdtrdone;
 557
 558                                 wdtrenb_orig =
 559                                     adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
 560                                 wdtrenb = wdtrenb_orig;
 561                                 wdtrdone = adw_lram_read_16(adw,
 562                                                             ADW_MC_WDTR_DONE);
 563                                 switch (spi->bus_width) {
 564                                 case MSG_EXT_WDTR_BUS_32_BIT:
 565                                 case MSG_EXT_WDTR_BUS_16_BIT:
 566                                         wdtrenb |= target_mask;
 567                                         break;
 568                                 case MSG_EXT_WDTR_BUS_8_BIT:
 569                                 default:
 570                                         wdtrenb &= ~target_mask;
 571                                         break;
 572                                 }
 573                                 if (wdtrenb != wdtrenb_orig) {
 574                                         adw_lram_write_16(adw,
 575                                                           ADW_MC_WDTR_ABLE,
 576                                                           wdtrenb);
 577                                         wdtrdone &= ~target_mask;
 578                                         adw_lram_write_16(adw,
 579                                                           ADW_MC_WDTR_DONE,
 580                                                           wdtrdone);
 581                                         /* Wide negotiation forces async */
 582                                         sdtrdone &= ~target_mask;
 583                                         adw_lram_write_16(adw,
 584                                                           ADW_MC_SDTR_DONE,
 585                                                           sdtrdone);
 586                                 }
 587                         }
 588
 589                         if (((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0)
 590                          || ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0)) {
 591                                 u_int sdtr_orig;
 592                                 u_int sdtr;
 593                                 u_int sdtrable_orig;
 594                                 u_int sdtrable;
 595
 596                                 sdtr = adw_get_chip_sdtr(adw,
 597                                                          ccb->ccb_h.target_id);
 598                                 sdtr_orig = sdtr;
 599                                 sdtrable = adw_lram_read_16(adw,
 600                                                             ADW_MC_SDTR_ABLE);
 601                                 sdtrable_orig = sdtrable;
 602
 603                                 if ((spi->valid
 604                                    & CTS_SPI_VALID_SYNC_RATE) != 0) {
 605
 606                                         sdtr =
 607                                             adw_find_sdtr(adw,
 608                                                           spi->sync_period);
 609                                 }
 610
 611                                 if ((spi->valid
 612                                    & CTS_SPI_VALID_SYNC_OFFSET) != 0) {
 613                                         if (spi->sync_offset == 0)
 614                                                 sdtr = ADW_MC_SDTR_ASYNC;
 615                                 }
 616
 617                                 if (sdtr == ADW_MC_SDTR_ASYNC)
 618                                         sdtrable &= ~target_mask;
 619                                 else
 620                                         sdtrable |= target_mask;
 621                                 if (sdtr != sdtr_orig
 622                                  || sdtrable != sdtrable_orig) {
 623                                         adw_set_chip_sdtr(adw,
 624                                                           ccb->ccb_h.target_id,
 625                                                           sdtr);
 626                                         sdtrdone &= ~target_mask;
 627                                         adw_lram_write_16(adw, ADW_MC_SDTR_ABLE,
 628                                                           sdtrable);
 629                                         adw_lram_write_16(adw, ADW_MC_SDTR_DONE,
 630                                                           sdtrdone);
 631
 632                                 }
 633                         }
 634                 }
 635                 crit_exit();
 636                 ccb->ccb_h.status = CAM_REQ_CMP;
 637                 xpt_done(ccb);
 638                 break;
 639         }
 640         case XPT_GET_TRAN_SETTINGS:
 641         /* Get default/user set transfer settings for the target */
 642         {
 643                 struct ccb_trans_settings_scsi *scsi;
 644                 struct ccb_trans_settings_spi *spi;
 645                 struct  ccb_trans_settings *cts;
 646                 u_int   target_mask;
 647
 648                 cts = &ccb->cts;
 649                 target_mask = 0x01 << ccb->ccb_h.target_id;
 650                 cts->protocol = PROTO_SCSI;
 651                 cts->protocol_version = SCSI_REV_2;
 652                 cts->transport = XPORT_SPI;
 653                 cts->transport_version = 2;
 654
 655                 scsi = &cts->proto_specific.scsi;
 656                 spi = &cts->xport_specific.spi;
 657                 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
 658                         u_int mc_sdtr;
 659
 660                         spi->flags = 0;
 661                         if ((adw->user_discenb & target_mask) != 0)
 662                                 spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
 663
 664                         if ((adw->user_tagenb & target_mask) != 0)
 665                                 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
 666
 667                         if ((adw->user_wdtr & target_mask) != 0)
 668                                 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
 669                         else
 670                                 spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
 671
 672                         mc_sdtr = adw_get_user_sdtr(adw, ccb->ccb_h.target_id);
 673                         spi->sync_period = adw_find_period(adw, mc_sdtr);
 674                         if (spi->sync_period != 0)
 675                                 spi->sync_offset = 15; /* XXX ??? */
 676                         else
 677                                 spi->sync_offset = 0;
 678
 679
 680                 } else {
 681                         u_int targ_tinfo;
 682
 683                         spi->flags = 0;
 684                         if ((adw_lram_read_16(adw, ADW_MC_DISC_ENABLE)
 685                           & target_mask) != 0)
 686                                 spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
 687
 688                         if ((adw->tagenb & target_mask) != 0)
 689                                 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
 690
 691                         targ_tinfo =
 692                             adw_lram_read_16(adw,
 693                                              ADW_MC_DEVICE_HSHK_CFG_TABLE
 694                                              + (2 * ccb->ccb_h.target_id));
 695
 696                         if ((targ_tinfo & ADW_HSHK_CFG_WIDE_XFR) != 0)
 697                                 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
 698                         else
 699                                 spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
 700
 701                         spi->sync_period =
 702                             adw_hshk_cfg_period_factor(targ_tinfo);
 703
 704                         spi->sync_offset = targ_tinfo & ADW_HSHK_CFG_OFFSET;
 705                         if (spi->sync_period == 0)
 706                                 spi->sync_offset = 0;
 707
 708                         if (spi->sync_offset == 0)
 709                                 spi->sync_period = 0;
 710                 }
 711
 712                 spi->valid = CTS_SPI_VALID_SYNC_RATE
 713                            | CTS_SPI_VALID_SYNC_OFFSET
 714                            | CTS_SPI_VALID_BUS_WIDTH
 715                            | CTS_SPI_VALID_DISC;
 716                 scsi->valid = CTS_SCSI_VALID_TQ;
 717                 ccb->ccb_h.status = CAM_REQ_CMP;
 718                 xpt_done(ccb);
 719                 break;
 720         }
 721         case XPT_CALC_GEOMETRY:
 722         {
 723                 struct    ccb_calc_geometry *ccg;
 724                 u_int32_t size_mb;
 725                 u_int32_t secs_per_cylinder;
 726                 int       extended;
 727
 728                 /*
 729                  * XXX Use Adaptec translation until I find out how to
 730                  *     get this information from the card.
 731                  */
 732                 ccg = &ccb->ccg;
 733                 size_mb = ccg->volume_size
 734                         / ((1024L * 1024L) / ccg->block_size);
 735                 extended = 1;
 736
 737                 if (size_mb > 1024 && extended) {
 738                         ccg->heads = 255;
 739                         ccg->secs_per_track = 63;
 740                 } else {
 741                         ccg->heads = 64;
 742                         ccg->secs_per_track = 32;
 743                 }
 744                 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
 745                 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
 746                 ccb->ccb_h.status = CAM_REQ_CMP;
 747                 xpt_done(ccb);
 748                 break;
 749         }
 750         case XPT_RESET_BUS:             /* Reset the specified SCSI bus */
 751         {
 752                 int failure;
 753
 754                 failure = adw_reset_bus(adw);
 755                 if (failure != 0) {
 756                         ccb->ccb_h.status = CAM_REQ_CMP_ERR;
 757                 } else {
 758                         if (bootverbose) {
 759                                 xpt_print_path(adw->path);
 760                                 kprintf("Bus Reset Delivered\n");
 761                         }
 762                         ccb->ccb_h.status = CAM_REQ_CMP;
 763                 }
 764                 xpt_done(ccb);
 765                 break;
 766         }
 767         case XPT_TERM_IO:               /* Terminate the I/O process */
 768                 /* XXX Implement */
 769                 ccb->ccb_h.status = CAM_REQ_INVALID;
 770                 xpt_done(ccb);
 771                 break;
 772         case XPT_PATH_INQ:              /* Path routing inquiry */
 773         {
 774                 struct ccb_pathinq *cpi = &ccb->cpi;
 775
 776                 cpi->version_num = 1;
 777                 cpi->hba_inquiry = PI_WIDE_16|PI_SDTR_ABLE|PI_TAG_ABLE;
 778                 cpi->target_sprt = 0;
 779                 cpi->hba_misc = 0;
 780                 cpi->hba_eng_cnt = 0;
 781                 cpi->max_target = ADW_MAX_TID;
 782                 cpi->max_lun = ADW_MAX_LUN;
 783                 cpi->initiator_id = adw->initiator_id;
 784                 cpi->bus_id = cam_sim_bus(sim);
 785                 cpi->base_transfer_speed = 3300;
 786                 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
 787                 strncpy(cpi->hba_vid, "AdvanSys", HBA_IDLEN);
 788                 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
 789                 cpi->unit_number = cam_sim_unit(sim);
 790                 cpi->transport = XPORT_SPI;
 791                 cpi->transport_version = 2;
 792                 cpi->protocol = PROTO_SCSI;
 793                 cpi->protocol_version = SCSI_REV_2;
 794                 cpi->ccb_h.status = CAM_REQ_CMP;
 795                 xpt_done(ccb);
 796                 break;
 797         }
 798         default:
 799                 ccb->ccb_h.status = CAM_REQ_INVALID;
 800                 xpt_done(ccb);
 801                 break;
 802         }
 803 }
 804
 805 static void
 806 adw_poll(struct cam_sim *sim)
 807 {
 808         adw_intr(cam_sim_softc(sim));
 809 }
 810
 811 static void
 812 adw_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg)
 813 {
 814 }
 815
 816 struct adw_softc *
 817 adw_alloc(device_t dev, struct resource *regs, int regs_type, int regs_id)
 818 {
 819         struct   adw_softc *adw;
 820         int      i;
 821
 822         /*
 823          * Allocate a storage area for us
 824          */
 825         adw = kmalloc(sizeof(struct adw_softc), M_DEVBUF, M_INTWAIT | M_ZERO);
 826         LIST_INIT(&adw->pending_ccbs);
 827         SLIST_INIT(&adw->sg_maps);
 828         adw->device = dev;
 829         adw->unit = device_get_unit(dev);
 830         adw->regs_res_type = regs_type;
 831         adw->regs_res_id = regs_id;
 832         adw->regs = regs;
 833         adw->tag = rman_get_bustag(regs);
 834         adw->bsh = rman_get_bushandle(regs);
 835         KKASSERT(adw->unit >= 0 && adw->unit < 100);
 836         i = adw->unit / 10;
 837         adw->name = kmalloc(sizeof("adw") + i + 1, M_DEVBUF, M_INTWAIT);
 838         ksprintf(adw->name, "adw%d", adw->unit);
 839         return(adw);
 840 }
 841
 842 void
 843 adw_free(struct adw_softc *adw)
 844 {
 845         switch (adw->init_level) {
 846         case 9:
 847         {
 848                 struct sg_map_node *sg_map;
 849
 850                 while ((sg_map = SLIST_FIRST(&adw->sg_maps)) != NULL) {
 851                         SLIST_REMOVE_HEAD(&adw->sg_maps, links);
 852                         bus_dmamap_unload(adw->sg_dmat,
 853                                           sg_map->sg_dmamap);
 854                         bus_dmamem_free(adw->sg_dmat, sg_map->sg_vaddr,
 855                                         sg_map->sg_dmamap);
 856                         kfree(sg_map, M_DEVBUF);
 857                 }
 858                 bus_dma_tag_destroy(adw->sg_dmat);
 859         }
 860         case 8:
 861                 bus_dmamap_unload(adw->acb_dmat, adw->acb_dmamap);
 862         case 7:
 863                 bus_dmamem_free(adw->acb_dmat, adw->acbs,
 864                                 adw->acb_dmamap);
 865                 bus_dmamap_destroy(adw->acb_dmat, adw->acb_dmamap);
 866         case 6:
 867                 bus_dma_tag_destroy(adw->acb_dmat);
 868         case 5:
 869                 bus_dmamap_unload(adw->carrier_dmat, adw->carrier_dmamap);
 870         case 4:
 871                 bus_dmamem_free(adw->carrier_dmat, adw->carriers,
 872                                 adw->carrier_dmamap);
 873                 bus_dmamap_destroy(adw->carrier_dmat, adw->carrier_dmamap);
 874         case 3:
 875                 bus_dma_tag_destroy(adw->carrier_dmat);
 876         case 2:
 877                 bus_dma_tag_destroy(adw->buffer_dmat);
 878         case 1:
 879                 bus_dma_tag_destroy(adw->parent_dmat);
 880         case 0:
 881                 break;
 882         }
 883         kfree(adw->name, M_DEVBUF);
 884         kfree(adw, M_DEVBUF);
 885 }
 886
 887 int
 888 adw_init(struct adw_softc *adw)
 889 {
 890         struct    adw_eeprom eep_config;
 891         u_int     tid;
 892         u_int     i;
 893         u_int16_t checksum;
 894         u_int16_t scsicfg1;
 895
 896         checksum = adw_eeprom_read(adw, &eep_config);
 897         bcopy(eep_config.serial_number, adw->serial_number,
 898               sizeof(adw->serial_number));
 899         if (checksum != eep_config.checksum) {
 900                 u_int16_t serial_number[3];
 901
 902                 adw->flags |= ADW_EEPROM_FAILED;
 903                 kprintf("%s: EEPROM checksum failed.  Restoring Defaults\n",
 904                        adw_name(adw));
 905
 906                 /*
 907                  * Restore the default EEPROM settings.
 908                  * Assume the 6 byte board serial number that was read
 909                  * from EEPROM is correct even if the EEPROM checksum
 910                  * failed.
 911                  */
 912                 bcopy(adw->default_eeprom, &eep_config, sizeof(eep_config));
 913                 bcopy(adw->serial_number, eep_config.serial_number,
 914                       sizeof(serial_number));
 915                 adw_eeprom_write(adw, &eep_config);
 916         }
 917
 918         /* Pull eeprom information into our softc. */
 919         adw->bios_ctrl = eep_config.bios_ctrl;
 920         adw->user_wdtr = eep_config.wdtr_able;
 921         for (tid = 0; tid < ADW_MAX_TID; tid++) {
 922                 u_int     mc_sdtr;
 923                 u_int16_t tid_mask;
 924
 925                 tid_mask = 0x1 << tid;
 926                 if ((adw->features & ADW_ULTRA) != 0) {
 927                         /*
 928                          * Ultra chips store sdtr and ultraenb
 929                          * bits in their seeprom, so we must
 930                          * construct valid mc_sdtr entries for
 931                          * indirectly.
 932                          */
 933                         if (eep_config.sync1.sync_enable & tid_mask) {
 934                                 if (eep_config.sync2.ultra_enable & tid_mask)
 935                                         mc_sdtr = ADW_MC_SDTR_20;
 936                                 else
 937                                         mc_sdtr = ADW_MC_SDTR_10;
 938                         } else
 939                                 mc_sdtr = ADW_MC_SDTR_ASYNC;
 940                 } else {
 941                         switch (ADW_TARGET_GROUP(tid)) {
 942                         case 3:
 943                                 mc_sdtr = eep_config.sync4.sdtr4;
 944                                 break;
 945                         case 2:
 946                                 mc_sdtr = eep_config.sync3.sdtr3;
 947                                 break;
 948                         case 1:
 949                                 mc_sdtr = eep_config.sync2.sdtr2;
 950                                 break;
 951                         default: /* Shut up compiler */
 952                         case 0:
 953                                 mc_sdtr = eep_config.sync1.sdtr1;
 954                                 break;
 955                         }
 956                         mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
 957                         mc_sdtr &= 0xFF;
 958                 }
 959                 adw_set_user_sdtr(adw, tid, mc_sdtr);
 960         }
 961         adw->user_tagenb = eep_config.tagqng_able;
 962         adw->user_discenb = eep_config.disc_enable;
 963         adw->max_acbs = eep_config.max_host_qng;
 964         adw->initiator_id = (eep_config.adapter_scsi_id & ADW_MAX_TID);
 965
 966         /*
 967          * Sanity check the number of host openings.
 968          */
 969         if (adw->max_acbs > ADW_DEF_MAX_HOST_QNG)
 970                 adw->max_acbs = ADW_DEF_MAX_HOST_QNG;
 971         else if (adw->max_acbs < ADW_DEF_MIN_HOST_QNG) {
 972                 /* If the value is zero, assume it is uninitialized. */
 973                 if (adw->max_acbs == 0)
 974                         adw->max_acbs = ADW_DEF_MAX_HOST_QNG;
 975                 else
 976                         adw->max_acbs = ADW_DEF_MIN_HOST_QNG;
 977         }
 978
 979         scsicfg1 = 0;
 980         if ((adw->features & ADW_ULTRA2) != 0) {
 981                 switch (eep_config.termination_lvd) {
 982                 default:
 983                         kprintf("%s: Invalid EEPROM LVD Termination Settings.\n",
 984                                adw_name(adw));
 985                         kprintf("%s: Reverting to Automatic LVD Termination\n",
 986                                adw_name(adw));
 987                         /* FALLTHROUGH */
 988                 case ADW_EEPROM_TERM_AUTO:
 989                         break;
 990                 case ADW_EEPROM_TERM_BOTH_ON:
 991                         scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_LO;
 992                         /* FALLTHROUGH */
 993                 case ADW_EEPROM_TERM_HIGH_ON:
 994                         scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_HI;
 995                         /* FALLTHROUGH */
 996                 case ADW_EEPROM_TERM_OFF:
 997                         scsicfg1 |= ADW2_SCSI_CFG1_DIS_TERM_DRV;
 998                         break;
 999                 }
1000         }
1001
1002         switch (eep_config.termination_se) {
1003         default:
1004                 kprintf("%s: Invalid SE EEPROM Termination Settings.\n",
1005                        adw_name(adw));
1006                 kprintf("%s: Reverting to Automatic SE Termination\n",
1007                        adw_name(adw));
1008                 /* FALLTHROUGH */
1009         case ADW_EEPROM_TERM_AUTO:
1010                 break;
1011         case ADW_EEPROM_TERM_BOTH_ON:
1012                 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
1013                 /* FALLTHROUGH */
1014         case ADW_EEPROM_TERM_HIGH_ON:
1015                 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
1016                 /* FALLTHROUGH */
1017         case ADW_EEPROM_TERM_OFF:
1018                 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_MANUAL;
1019                 break;
1020         }
1021         kprintf("%s: SCSI ID %d, ", adw_name(adw), adw->initiator_id);
1022
1023         /* DMA tag for mapping buffers into device visible space. */
1024         if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0,
1025                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
1026                                /*highaddr*/BUS_SPACE_MAXADDR,
1027                                /*filter*/NULL, /*filterarg*/NULL,
1028                                /*maxsize*/MAXBSIZE, /*nsegments*/ADW_SGSIZE,
1029                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1030                                /*flags*/BUS_DMA_ALLOCNOW,
1031                                &adw->buffer_dmat) != 0) {
1032                 return (ENOMEM);
1033         }
1034
1035         adw->init_level++;
1036
1037         /* DMA tag for our ccb carrier structures */
1038         if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/0x10,
1039                                /*boundary*/0,
1040                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
1041                                /*highaddr*/BUS_SPACE_MAXADDR,
1042                                /*filter*/NULL, /*filterarg*/NULL,
1043                                (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
1044                                 * sizeof(struct adw_carrier),
1045                                /*nsegments*/1,
1046                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1047                                /*flags*/0, &adw->carrier_dmat) != 0) {
1048                 return (ENOMEM);
1049         }
1050
1051         adw->init_level++;
1052
1053         /* Allocation for our ccb carrier structures */
1054         if (bus_dmamem_alloc(adw->carrier_dmat, (void *)&adw->carriers,
1055                              BUS_DMA_NOWAIT, &adw->carrier_dmamap) != 0) {
1056                 return (ENOMEM);
1057         }
1058
1059         adw->init_level++;
1060
1061         /* And permanently map them */
1062         bus_dmamap_load(adw->carrier_dmat, adw->carrier_dmamap,
1063                         adw->carriers,
1064                         (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
1065                          * sizeof(struct adw_carrier),
1066                         adwmapmem, &adw->carrier_busbase, /*flags*/0);
1067
1068         /* Clear them out. */
1069         bzero(adw->carriers, (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
1070                              * sizeof(struct adw_carrier));
1071
1072         /* Setup our free carrier list */
1073         adw->free_carriers = adw->carriers;
1074         for (i = 0; i < adw->max_acbs + ADW_NUM_CARRIER_QUEUES; i++) {
1075                 adw->carriers[i].carr_offset =
1076                         carriervtobo(adw, &adw->carriers[i]);
1077                 adw->carriers[i].carr_ba =
1078                         carriervtob(adw, &adw->carriers[i]);
1079                 adw->carriers[i].areq_ba = 0;
1080                 adw->carriers[i].next_ba =
1081                         carriervtobo(adw, &adw->carriers[i+1]);
1082         }
1083         /* Terminal carrier.  Never leaves the freelist */
1084         adw->carriers[i].carr_offset =
1085                 carriervtobo(adw, &adw->carriers[i]);
1086         adw->carriers[i].carr_ba =
1087                 carriervtob(adw, &adw->carriers[i]);
1088         adw->carriers[i].areq_ba = 0;
1089         adw->carriers[i].next_ba = ~0;
1090
1091         adw->init_level++;
1092
1093         /* DMA tag for our acb structures */
1094         if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0,
1095                                /*lowaddr*/BUS_SPACE_MAXADDR,
1096                                /*highaddr*/BUS_SPACE_MAXADDR,
1097                                /*filter*/NULL, /*filterarg*/NULL,
1098                                adw->max_acbs * sizeof(struct acb),
1099                                /*nsegments*/1,
1100                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1101                                /*flags*/0, &adw->acb_dmat) != 0) {
1102                 return (ENOMEM);
1103         }
1104
1105         adw->init_level++;
1106
1107         /* Allocation for our ccbs */
1108         if (bus_dmamem_alloc(adw->acb_dmat, (void *)&adw->acbs,
1109                              BUS_DMA_NOWAIT, &adw->acb_dmamap) != 0)
1110                 return (ENOMEM);
1111
1112         adw->init_level++;
1113
1114         /* And permanently map them */
1115         bus_dmamap_load(adw->acb_dmat, adw->acb_dmamap,
1116                         adw->acbs,
1117                         adw->max_acbs * sizeof(struct acb),
1118                         adwmapmem, &adw->acb_busbase, /*flags*/0);
1119
1120         /* Clear them out. */
1121         bzero(adw->acbs, adw->max_acbs * sizeof(struct acb));
1122
1123         /* DMA tag for our S/G structures.  We allocate in page sized chunks */
1124         if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0,
1125                                /*lowaddr*/BUS_SPACE_MAXADDR,
1126                                /*highaddr*/BUS_SPACE_MAXADDR,
1127                                /*filter*/NULL, /*filterarg*/NULL,
1128                                PAGE_SIZE, /*nsegments*/1,
1129                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
1130                                /*flags*/0, &adw->sg_dmat) != 0) {
1131                 return (ENOMEM);
1132         }
1133
1134         adw->init_level++;
1135
1136         /* Allocate our first batch of ccbs */
1137         if (adwallocacbs(adw) == 0)
1138                 return (ENOMEM);
1139
1140         if (adw_init_chip(adw, scsicfg1) != 0)
1141                 return (ENXIO);
1142
1143         kprintf("Queue Depth %d\n", adw->max_acbs);
1144
1145         return (0);
1146 }
1147
1148 /*
1149  * Attach all the sub-devices we can find
1150  */
1151 int
1152 adw_attach(struct adw_softc *adw)
1153 {
1154         struct ccb_setasync csa;
1155         int error;
1156
1157         error = 0;
1158         crit_enter();
1159         /* Hook up our interrupt handler */
1160         if ((error = bus_setup_intr(adw->device, adw->irq, 0,
1161                                     adw_intr, adw, &adw->ih, NULL)) != 0) {
1162                 device_printf(adw->device, "bus_setup_intr() failed: %d\n",
1163                               error);
1164                 goto fail;
1165         }
1166
1167         /* Start the Risc processor now that we are fully configured. */
1168         adw_outw(adw, ADW_RISC_CSR, ADW_RISC_CSR_RUN);
1169
1170         /*
1171          * Construct our SIM entry.
1172          */
1173         adw->sim = cam_sim_alloc(adw_action, adw_poll, "adw", adw, adw->unit,
1174                                  &sim_mplock, 1, adw->max_acbs, NULL);
1175         if (adw->sim == NULL) {
1176                 error = ENOMEM;
1177                 goto fail;
1178         }
1179
1180         /*
1181          * Register the bus.
1182          */
1183         if (xpt_bus_register(adw->sim, 0) != CAM_SUCCESS) {
1184                 cam_sim_free(adw->sim);
1185                 error = ENOMEM;
1186                 goto fail;
1187         }
1188
1189         if (xpt_create_path(&adw->path, /*periph*/NULL, cam_sim_path(adw->sim),
1190                             CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
1191            == CAM_REQ_CMP) {
1192                 xpt_setup_ccb(&csa.ccb_h, adw->path, /*priority*/5);
1193                 csa.ccb_h.func_code = XPT_SASYNC_CB;
1194                 csa.event_enable = AC_LOST_DEVICE;
1195                 csa.callback = adw_async;
1196                 csa.callback_arg = adw;
1197                 xpt_action((union ccb *)&csa);
1198         }
1199
1200 fail:
1201         crit_exit();
1202         return (error);
1203 }
1204
1205 void
1206 adw_intr(void *arg)
1207 {
1208         struct  adw_softc *adw;
1209         u_int   int_stat;
1210
1211         adw = (struct adw_softc *)arg;
1212         if ((adw_inw(adw, ADW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) == 0)
1213                 return;
1214
1215         /* Reading the register clears the interrupt. */
1216         int_stat = adw_inb(adw, ADW_INTR_STATUS_REG);
1217
1218         if ((int_stat & ADW_INTR_STATUS_INTRB) != 0) {
1219                 u_int intrb_code;
1220
1221                 /* Async Microcode Event */
1222                 intrb_code = adw_lram_read_8(adw, ADW_MC_INTRB_CODE);
1223                 switch (intrb_code) {
1224                 case ADW_ASYNC_CARRIER_READY_FAILURE:
1225                         /*
1226                          * The RISC missed our update of
1227                          * the commandq.
1228                          */
1229                         if (LIST_FIRST(&adw->pending_ccbs) != NULL)
1230                                 adw_tickle_risc(adw, ADW_TICKLE_A);
1231                         break;
1232                 case ADW_ASYNC_SCSI_BUS_RESET_DET:
1233                         /*
1234                          * The firmware detected a SCSI Bus reset.
1235                          */
1236                         kprintf("Someone Reset the Bus\n");
1237                         adw_handle_bus_reset(adw, /*initiated*/FALSE);
1238                         break;
1239                 case ADW_ASYNC_RDMA_FAILURE:
1240                         /*
1241                          * Handle RDMA failure by resetting the
1242                          * SCSI Bus and chip.
1243                          */
1244 #if XXX
1245                         AdvResetChipAndSB(adv_dvc_varp);
1246 #endif
1247                         break;
1248
1249                 case ADW_ASYNC_HOST_SCSI_BUS_RESET:
1250                         /*
1251                          * Host generated SCSI bus reset occurred.
1252                          */
1253                         adw_handle_bus_reset(adw, /*initiated*/TRUE);
1254                         break;
1255                 default:
1256                         kprintf("adw_intr: unknown async code 0x%x\n",
1257                                intrb_code);
1258                         break;
1259                 }
1260         }
1261
1262         /*
1263          * Run down the RequestQ.
1264          */
1265         while ((adw->responseq->next_ba & ADW_RQ_DONE) != 0) {
1266                 struct adw_carrier *free_carrier;
1267                 struct acb *acb;
1268                 union ccb *ccb;
1269
1270 #if 0
1271                 kprintf("0x%x, 0x%x, 0x%x, 0x%x\n",
1272                        adw->responseq->carr_offset,
1273                        adw->responseq->carr_ba,
1274                        adw->responseq->areq_ba,
1275                        adw->responseq->next_ba);
1276 #endif
1277                 /*
1278                  * The firmware copies the adw_scsi_req_q.acb_baddr
1279                  * field into the areq_ba field of the carrier.
1280                  */
1281                 acb = acbbotov(adw, adw->responseq->areq_ba);
1282
1283                 /*
1284                  * The least significant four bits of the next_ba
1285                  * field are used as flags.  Mask them out and then
1286                  * advance through the list.
1287                  */
1288                 free_carrier = adw->responseq;
1289                 adw->responseq =
1290                     carrierbotov(adw, free_carrier->next_ba & ADW_NEXT_BA_MASK);
1291                 free_carrier->next_ba = adw->free_carriers->carr_offset;
1292                 adw->free_carriers = free_carrier;
1293
1294                 /* Process CCB */
1295                 ccb = acb->ccb;
1296                 callout_stop(&ccb->ccb_h.timeout_ch);
1297                 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1298                         bus_dmasync_op_t op;
1299
1300                         if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1301                                 op = BUS_DMASYNC_POSTREAD;
1302                         else
1303                                 op = BUS_DMASYNC_POSTWRITE;
1304                         bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op);
1305                         bus_dmamap_unload(adw->buffer_dmat, acb->dmamap);
1306                         ccb->csio.resid = acb->queue.data_cnt;
1307                 } else
1308                         ccb->csio.resid = 0;
1309
1310                 /* Common Cases inline... */
1311                 if (acb->queue.host_status == QHSTA_NO_ERROR
1312                  && (acb->queue.done_status == QD_NO_ERROR
1313                   || acb->queue.done_status == QD_WITH_ERROR)) {
1314                         ccb->csio.scsi_status = acb->queue.scsi_status;
1315                         ccb->ccb_h.status = 0;
1316                         switch (ccb->csio.scsi_status) {
1317                         case SCSI_STATUS_OK:
1318                                 ccb->ccb_h.status |= CAM_REQ_CMP;
1319                                 break;
1320                         case SCSI_STATUS_CHECK_COND:
1321                         case SCSI_STATUS_CMD_TERMINATED:
1322                                 bcopy(&acb->sense_data, &ccb->csio.sense_data,
1323                                       ccb->csio.sense_len);
1324                                 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
1325                                 ccb->csio.sense_resid = acb->queue.sense_len;
1326                                 /* FALLTHROUGH */
1327                         default:
1328                                 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR
1329                                                   |  CAM_DEV_QFRZN;
1330                                 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1331                                 break;
1332                         }
1333                         adwfreeacb(adw, acb);
1334                         xpt_done(ccb);
1335                 } else {
1336                         adwprocesserror(adw, acb);
1337                 }
1338         }
1339 }
1340
1341 static void
1342 adwprocesserror(struct adw_softc *adw, struct acb *acb)
1343 {
1344         union ccb *ccb;
1345
1346         ccb = acb->ccb;
1347         if (acb->queue.done_status == QD_ABORTED_BY_HOST) {
1348                 ccb->ccb_h.status = CAM_REQ_ABORTED;
1349         } else {
1350
1351                 switch (acb->queue.host_status) {
1352                 case QHSTA_M_SEL_TIMEOUT:
1353                         ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1354                         break;
1355                 case QHSTA_M_SXFR_OFF_UFLW:
1356                 case QHSTA_M_SXFR_OFF_OFLW:
1357                 case QHSTA_M_DATA_OVER_RUN:
1358                         ccb->ccb_h.status = CAM_DATA_RUN_ERR;
1359                         break;
1360                 case QHSTA_M_SXFR_DESELECTED:
1361                 case QHSTA_M_UNEXPECTED_BUS_FREE:
1362                         ccb->ccb_h.status = CAM_UNEXP_BUSFREE;
1363                         break;
1364                 case QHSTA_M_SCSI_BUS_RESET:
1365                 case QHSTA_M_SCSI_BUS_RESET_UNSOL:
1366                         ccb->ccb_h.status = CAM_SCSI_BUS_RESET;
1367                         break;
1368                 case QHSTA_M_BUS_DEVICE_RESET:
1369                         ccb->ccb_h.status = CAM_BDR_SENT;
1370                         break;
1371                 case QHSTA_M_QUEUE_ABORTED:
1372                         /* BDR or Bus Reset */
1373                         kprintf("Saw Queue Aborted\n");
1374                         ccb->ccb_h.status = adw->last_reset;
1375                         break;
1376                 case QHSTA_M_SXFR_SDMA_ERR:
1377                 case QHSTA_M_SXFR_SXFR_PERR:
1378                 case QHSTA_M_RDMA_PERR:
1379                         ccb->ccb_h.status = CAM_UNCOR_PARITY;
1380                         break;
1381                 case QHSTA_M_WTM_TIMEOUT:
1382                 case QHSTA_M_SXFR_WD_TMO:
1383                 {
1384                         /* The SCSI bus hung in a phase */
1385                         xpt_print_path(adw->path);
1386                         kprintf("Watch Dog timer expired.  Reseting bus\n");
1387                         adw_reset_bus(adw);
1388                         break;
1389                 }
1390                 case QHSTA_M_SXFR_XFR_PH_ERR:
1391                         ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1392                         break;
1393                 case QHSTA_M_SXFR_UNKNOWN_ERROR:
1394                         break;
1395                 case QHSTA_M_BAD_CMPL_STATUS_IN:
1396                         /* No command complete after a status message */
1397                         ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1398                         break;
1399                 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1400                         ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1401                         break;
1402                 case QHSTA_M_INVALID_DEVICE:
1403                         ccb->ccb_h.status = CAM_PATH_INVALID;
1404                         break;
1405                 case QHSTA_M_NO_AUTO_REQ_SENSE:
1406                         /*
1407                          * User didn't request sense, but we got a
1408                          * check condition.
1409                          */
1410                         ccb->csio.scsi_status = acb->queue.scsi_status;
1411                         ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1412                         break;
1413                 default:
1414                         panic("%s: Unhandled Host status error %x",
1415                               adw_name(adw), acb->queue.host_status);
1416                         /* NOTREACHED */
1417                 }
1418         }
1419         if ((acb->state & ACB_RECOVERY_ACB) != 0) {
1420                 if (ccb->ccb_h.status == CAM_SCSI_BUS_RESET
1421                  || ccb->ccb_h.status == CAM_BDR_SENT)
1422                         ccb->ccb_h.status = CAM_CMD_TIMEOUT;
1423         }
1424         if (ccb->ccb_h.status != CAM_REQ_CMP) {
1425                 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1426                 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1427         }
1428         adwfreeacb(adw, acb);
1429         xpt_done(ccb);
1430 }
1431
1432 static void
1433 adwtimeout(void *arg)
1434 {
1435         struct acb           *acb;
1436         union  ccb           *ccb;
1437         struct adw_softc     *adw;
1438         adw_idle_cmd_status_t status;
1439         int                   target_id;
1440
1441         acb = (struct acb *)arg;
1442         ccb = acb->ccb;
1443         adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr;
1444         xpt_print_path(ccb->ccb_h.path);
1445         kprintf("ACB %p - timed out\n", (void *)acb);
1446
1447         crit_enter();
1448
1449         if ((acb->state & ACB_ACTIVE) == 0) {
1450                 xpt_print_path(ccb->ccb_h.path);
1451                 kprintf("ACB %p - timed out CCB already completed\n",
1452                        (void *)acb);
1453                 crit_exit();
1454                 return;
1455         }
1456
1457         acb->state |= ACB_RECOVERY_ACB;
1458         target_id = ccb->ccb_h.target_id;
1459
1460         /* Attempt a BDR first */
1461         status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET,
1462                                    ccb->ccb_h.target_id);
1463         crit_exit();
1464         if (status == ADW_IDLE_CMD_SUCCESS) {
1465                 kprintf("%s: BDR Delivered.  No longer in timeout\n",
1466                        adw_name(adw));
1467                 adw_handle_device_reset(adw, target_id);
1468         } else {
1469                 adw_reset_bus(adw);
1470                 xpt_print_path(adw->path);
1471                 kprintf("Bus Reset Delivered.  No longer in timeout\n");
1472         }
1473 }
1474
1475 static void
1476 adw_handle_device_reset(struct adw_softc *adw, u_int target)
1477 {
1478         struct cam_path *path;
1479         cam_status error;
1480
1481         error = xpt_create_path(&path, /*periph*/NULL, cam_sim_path(adw->sim),
1482                                 target, CAM_LUN_WILDCARD);
1483
1484         if (error == CAM_REQ_CMP) {
1485                 xpt_async(AC_SENT_BDR, path, NULL);
1486                 xpt_free_path(path);
1487         }
1488         adw->last_reset = CAM_BDR_SENT;
1489 }
1490
1491 static void
1492 adw_handle_bus_reset(struct adw_softc *adw, int initiated)
1493 {
1494         if (initiated) {
1495                 /*
1496                  * The microcode currently sets the SCSI Bus Reset signal
1497                  * while handling the AscSendIdleCmd() IDLE_CMD_SCSI_RESET
1498                  * command above.  But the SCSI Bus Reset Hold Time in the
1499                  * microcode is not deterministic (it may in fact be for less
1500                  * than the SCSI Spec. minimum of 25 us).  Therefore on return
1501                  * the Adv Library sets the SCSI Bus Reset signal for
1502                  * ADW_SCSI_RESET_HOLD_TIME_US, which is defined to be greater
1503                  * than 25 us.
1504                  */
1505                 u_int scsi_ctrl;
1506
1507                 scsi_ctrl = adw_inw(adw, ADW_SCSI_CTRL) & ~ADW_SCSI_CTRL_RSTOUT;
1508                 adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl | ADW_SCSI_CTRL_RSTOUT);
1509                 DELAY(ADW_SCSI_RESET_HOLD_TIME_US);
1510                 adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl);
1511
1512                 /*
1513                  * We will perform the async notification when the
1514                  * SCSI Reset interrupt occurs.
1515                  */
1516         } else
1517                 xpt_async(AC_BUS_RESET, adw->path, NULL);
1518         adw->last_reset = CAM_SCSI_BUS_RESET;
1519 }