sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36
  37 #include "opt_polling.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <net/bpf.h>
  54 #include <net/ethernet.h>
  55 #include <net/if.h>
  56 #include <net/if_arp.h>
  57 #include <net/if_dl.h>
  58 #include <net/if_media.h>
  59 #include <net/if_types.h>
  60 #include <net/ifq_var.h>
  61 #include <net/vlan/if_vlan_var.h>
  62 #include <net/vlan/if_vlan_ether.h>
  63
  64 #include <dev/netif/mii_layer/mii.h>
  65 #include <dev/netif/mii_layer/miivar.h>
  66 #include <dev/netif/mii_layer/brgphyreg.h>
  67
  68 #include <bus/pci/pcidevs.h>
  69 #include <bus/pci/pcireg.h>
  70 #include <bus/pci/pcivar.h>
  71
  72 #include <dev/netif/bge/if_bgereg.h>
  73 #include <dev/netif/bnx/if_bnxvar.h>
  74
  75 /* "device miibus" required.  See GENERIC if you get errors here. */
  76 #include "miibus_if.h"
  77
  78 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  79
  80 static const struct bnx_type {
  81         uint16_t                bnx_vid;
  82         uint16_t                bnx_did;
  83         char                    *bnx_name;
  84 } bnx_devs[] = {
  85         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
  86                 "Broadcom BCM5717 Gigabit Ethernet" },
  87         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
  88                 "Broadcom BCM5718 Gigabit Ethernet" },
  89         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
  90                 "Broadcom BCM5719 Gigabit Ethernet" },
  91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
  92                 "Broadcom BCM5720 Gigabit Ethernet" },
  93
  94         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
  95                 "Broadcom BCM57761 Gigabit Ethernet" },
  96         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
  97                 "Broadcom BCM57781 Gigabit Ethernet" },
  98         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
  99                 "Broadcom BCM57791 Fast Ethernet" },
 100         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 101                 "Broadcom BCM57765 Gigabit Ethernet" },
 102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 103                 "Broadcom BCM57785 Gigabit Ethernet" },
 104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 105                 "Broadcom BCM57795 Fast Ethernet" },
 106
 107         { 0, 0, NULL }
 108 };
 109
 110 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 111 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 112 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 113 #define BNX_IS_57765_FAMILY(sc)  \
 114         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 115
 116 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 117
 118 static int      bnx_probe(device_t);
 119 static int      bnx_attach(device_t);
 120 static int      bnx_detach(device_t);
 121 static void     bnx_shutdown(device_t);
 122 static int      bnx_suspend(device_t);
 123 static int      bnx_resume(device_t);
 124 static int      bnx_miibus_readreg(device_t, int, int);
 125 static int      bnx_miibus_writereg(device_t, int, int, int);
 126 static void     bnx_miibus_statchg(device_t);
 127
 128 #ifdef DEVICE_POLLING
 129 static void     bnx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 130 #endif
 131 static void     bnx_intr_legacy(void *);
 132 static void     bnx_msi(void *);
 133 static void     bnx_msi_oneshot(void *);
 134 static void     bnx_intr(struct bnx_softc *);
 135 static void     bnx_enable_intr(struct bnx_softc *);
 136 static void     bnx_disable_intr(struct bnx_softc *);
 137 static void     bnx_txeof(struct bnx_softc *, uint16_t);
 138 static void     bnx_rxeof(struct bnx_softc *, uint16_t);
 139
 140 static void     bnx_start(struct ifnet *);
 141 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 142 static void     bnx_init(void *);
 143 static void     bnx_stop(struct bnx_softc *);
 144 static void     bnx_watchdog(struct ifnet *);
 145 static int      bnx_ifmedia_upd(struct ifnet *);
 146 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 147 static void     bnx_tick(void *);
 148
 149 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 150 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 151 static struct bnx_jslot
 152                 *bnx_jalloc(struct bnx_softc *);
 153 static void     bnx_jfree(void *);
 154 static void     bnx_jref(void *);
 155 static int      bnx_newbuf_std(struct bnx_softc *, int, int);
 156 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 157 static void     bnx_setup_rxdesc_std(struct bnx_softc *, int);
 158 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 159 static int      bnx_init_rx_ring_std(struct bnx_softc *);
 160 static void     bnx_free_rx_ring_std(struct bnx_softc *);
 161 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 162 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 163 static void     bnx_free_tx_ring(struct bnx_softc *);
 164 static int      bnx_init_tx_ring(struct bnx_softc *);
 165 static int      bnx_dma_alloc(struct bnx_softc *);
 166 static void     bnx_dma_free(struct bnx_softc *);
 167 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 168                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 169 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 170 static struct mbuf *
 171                 bnx_defrag_shortdma(struct mbuf *);
 172 static int      bnx_encap(struct bnx_softc *, struct mbuf **, uint32_t *);
 173
 174 static void     bnx_reset(struct bnx_softc *);
 175 static int      bnx_chipinit(struct bnx_softc *);
 176 static int      bnx_blockinit(struct bnx_softc *);
 177 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 178 static void     bnx_enable_msi(struct bnx_softc *sc);
 179 static void     bnx_setmulti(struct bnx_softc *);
 180 static void     bnx_setpromisc(struct bnx_softc *);
 181 static void     bnx_stats_update_regs(struct bnx_softc *);
 182 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 183
 184 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 185 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 186 #ifdef notdef
 187 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 188 #endif
 189 static void     bnx_writereg_ind(struct bnx_softc *, uint32_t, uint32_t);
 190 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 191 static void     bnx_writembx(struct bnx_softc *, int, int);
 192 static uint8_t  bnx_nvram_getbyte(struct bnx_softc *, int, uint8_t *);
 193 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 194 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 195 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 196
 197 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 198 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 199 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 200 static void     bnx_link_poll(struct bnx_softc *);
 201
 202 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 203 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 204 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 205 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 206
 207 static void     bnx_coal_change(struct bnx_softc *);
 208 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 209 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 210 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 211 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 212 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 213 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 214 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 215                     int, int, uint32_t);
 216
 217 static int      bnx_msi_enable = 1;
 218 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 219
 220 static device_method_t bnx_methods[] = {
 221         /* Device interface */
 222         DEVMETHOD(device_probe,         bnx_probe),
 223         DEVMETHOD(device_attach,        bnx_attach),
 224         DEVMETHOD(device_detach,        bnx_detach),
 225         DEVMETHOD(device_shutdown,      bnx_shutdown),
 226         DEVMETHOD(device_suspend,       bnx_suspend),
 227         DEVMETHOD(device_resume,        bnx_resume),
 228
 229         /* bus interface */
 230         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 231         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 232
 233         /* MII interface */
 234         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 235         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 236         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 237
 238         { 0, 0 }
 239 };
 240
 241 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 242 static devclass_t bnx_devclass;
 243
 244 DECLARE_DUMMY_MODULE(if_bnx);
 245 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 246 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 247
 248 static uint32_t
 249 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 250 {
 251         device_t dev = sc->bnx_dev;
 252         uint32_t val;
 253
 254         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 255             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 256                 return 0;
 257
 258         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 259         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 260         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 261         return (val);
 262 }
 263
 264 static void
 265 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 266 {
 267         device_t dev = sc->bnx_dev;
 268
 269         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 270             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 271                 return;
 272
 273         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 274         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 275         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 276 }
 277
 278 #ifdef notdef
 279 static uint32_t
 280 bnx_readreg_ind(struct bnx_softc *sc, uin32_t off)
 281 {
 282         device_t dev = sc->bnx_dev;
 283
 284         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 285         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 286 }
 287 #endif
 288
 289 static void
 290 bnx_writereg_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 291 {
 292         device_t dev = sc->bnx_dev;
 293
 294         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 295         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 296 }
 297
 298 static void
 299 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 300 {
 301         CSR_WRITE_4(sc, off, val);
 302 }
 303
 304 static void
 305 bnx_writembx(struct bnx_softc *sc, int off, int val)
 306 {
 307         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906)
 308                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 309
 310         CSR_WRITE_4(sc, off, val);
 311 }
 312
 313 static uint8_t
 314 bnx_nvram_getbyte(struct bnx_softc *sc, int addr, uint8_t *dest)
 315 {
 316         uint32_t access, byte = 0;
 317         int i;
 318
 319         /* Lock. */
 320         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 321         for (i = 0; i < 8000; i++) {
 322                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 323                         break;
 324                 DELAY(20);
 325         }
 326         if (i == 8000)
 327                 return (1);
 328
 329         /* Enable access. */
 330         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 331         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 332
 333         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 334         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 335         for (i = 0; i < BNX_TIMEOUT * 10; i++) {
 336                 DELAY(10);
 337                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 338                         DELAY(10);
 339                         break;
 340                 }
 341         }
 342
 343         if (i == BNX_TIMEOUT * 10) {
 344                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 345                 return (1);
 346         }
 347
 348         /* Get result. */
 349         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 350
 351         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 352
 353         /* Disable access. */
 354         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 355
 356         /* Unlock. */
 357         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 358         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 359
 360         return (0);
 361 }
 362
 363 /*
 364  * Read a sequence of bytes from NVRAM.
 365  */
 366 static int
 367 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 368 {
 369         int err = 0, i;
 370         uint8_t byte = 0;
 371
 372         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 373                 return (1);
 374
 375         for (i = 0; i < cnt; i++) {
 376                 err = bnx_nvram_getbyte(sc, off + i, &byte);
 377                 if (err)
 378                         break;
 379                 *(dest + i) = byte;
 380         }
 381
 382         return (err ? 1 : 0);
 383 }
 384
 385 /*
 386  * Read a byte of data stored in the EEPROM at address 'addr.' The
 387  * BCM570x supports both the traditional bitbang interface and an
 388  * auto access interface for reading the EEPROM. We use the auto
 389  * access method.
 390  */
 391 static uint8_t
 392 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 393 {
 394         int i;
 395         uint32_t byte = 0;
 396
 397         /*
 398          * Enable use of auto EEPROM access so we can avoid
 399          * having to use the bitbang method.
 400          */
 401         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 402
 403         /* Reset the EEPROM, load the clock period. */
 404         CSR_WRITE_4(sc, BGE_EE_ADDR,
 405             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 406         DELAY(20);
 407
 408         /* Issue the read EEPROM command. */
 409         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 410
 411         /* Wait for completion */
 412         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 413                 DELAY(10);
 414                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 415                         break;
 416         }
 417
 418         if (i == BNX_TIMEOUT) {
 419                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 420                 return(1);
 421         }
 422
 423         /* Get result. */
 424         byte = CSR_READ_4(sc, BGE_EE_DATA);
 425
 426         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 427
 428         return(0);
 429 }
 430
 431 /*
 432  * Read a sequence of bytes from the EEPROM.
 433  */
 434 static int
 435 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 436 {
 437         size_t i;
 438         int err;
 439         uint8_t byte;
 440
 441         for (byte = 0, err = 0, i = 0; i < len; i++) {
 442                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 443                 if (err)
 444                         break;
 445                 *(dest + i) = byte;
 446         }
 447
 448         return(err ? 1 : 0);
 449 }
 450
 451 static int
 452 bnx_miibus_readreg(device_t dev, int phy, int reg)
 453 {
 454         struct bnx_softc *sc = device_get_softc(dev);
 455         uint32_t val;
 456         int i;
 457
 458         KASSERT(phy == sc->bnx_phyno,
 459             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 460
 461         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 462         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 463                 CSR_WRITE_4(sc, BGE_MI_MODE,
 464                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 465                 DELAY(80);
 466         }
 467
 468         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 469             BGE_MIPHY(phy) | BGE_MIREG(reg));
 470
 471         /* Poll for the PHY register access to complete. */
 472         for (i = 0; i < BNX_TIMEOUT; i++) {
 473                 DELAY(10);
 474                 val = CSR_READ_4(sc, BGE_MI_COMM);
 475                 if ((val & BGE_MICOMM_BUSY) == 0) {
 476                         DELAY(5);
 477                         val = CSR_READ_4(sc, BGE_MI_COMM);
 478                         break;
 479                 }
 480         }
 481         if (i == BNX_TIMEOUT) {
 482                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 483                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 484                 val = 0;
 485         }
 486
 487         /* Restore the autopoll bit if necessary. */
 488         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 489                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 490                 DELAY(80);
 491         }
 492
 493         if (val & BGE_MICOMM_READFAIL)
 494                 return 0;
 495
 496         return (val & 0xFFFF);
 497 }
 498
 499 static int
 500 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 501 {
 502         struct bnx_softc *sc = device_get_softc(dev);
 503         int i;
 504
 505         KASSERT(phy == sc->bnx_phyno,
 506             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 507
 508         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 509             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 510                return 0;
 511
 512         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 513         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 514                 CSR_WRITE_4(sc, BGE_MI_MODE,
 515                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 516                 DELAY(80);
 517         }
 518
 519         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 520             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 521
 522         for (i = 0; i < BNX_TIMEOUT; i++) {
 523                 DELAY(10);
 524                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 525                         DELAY(5);
 526                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 527                         break;
 528                 }
 529         }
 530         if (i == BNX_TIMEOUT) {
 531                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 532                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 533         }
 534
 535         /* Restore the autopoll bit if necessary. */
 536         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 537                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 538                 DELAY(80);
 539         }
 540
 541         return 0;
 542 }
 543
 544 static void
 545 bnx_miibus_statchg(device_t dev)
 546 {
 547         struct bnx_softc *sc;
 548         struct mii_data *mii;
 549
 550         sc = device_get_softc(dev);
 551         mii = device_get_softc(sc->bnx_miibus);
 552
 553         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 554             (IFM_ACTIVE | IFM_AVALID)) {
 555                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 556                 case IFM_10_T:
 557                 case IFM_100_TX:
 558                         sc->bnx_link = 1;
 559                         break;
 560                 case IFM_1000_T:
 561                 case IFM_1000_SX:
 562                 case IFM_2500_SX:
 563                         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 564                                 sc->bnx_link = 1;
 565                         else
 566                                 sc->bnx_link = 0;
 567                         break;
 568                 default:
 569                         sc->bnx_link = 0;
 570                         break;
 571                 }
 572         } else {
 573                 sc->bnx_link = 0;
 574         }
 575         if (sc->bnx_link == 0)
 576                 return;
 577
 578         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 579         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 580             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 581                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 582         } else {
 583                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 584         }
 585
 586         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 587                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 588         } else {
 589                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 590         }
 591 }
 592
 593 /*
 594  * Memory management for jumbo frames.
 595  */
 596 static int
 597 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 598 {
 599         struct ifnet *ifp = &sc->arpcom.ac_if;
 600         struct bnx_jslot *entry;
 601         uint8_t *ptr;
 602         bus_addr_t paddr;
 603         int i, error;
 604
 605         /*
 606          * Create tag for jumbo mbufs.
 607          * This is really a bit of a kludge. We allocate a special
 608          * jumbo buffer pool which (thanks to the way our DMA
 609          * memory allocation works) will consist of contiguous
 610          * pages. This means that even though a jumbo buffer might
 611          * be larger than a page size, we don't really need to
 612          * map it into more than one DMA segment. However, the
 613          * default mbuf tag will result in multi-segment mappings,
 614          * so we have to create a special jumbo mbuf tag that
 615          * lets us get away with mapping the jumbo buffers as
 616          * a single segment. I think eventually the driver should
 617          * be changed so that it uses ordinary mbufs and cluster
 618          * buffers, i.e. jumbo frames can span multiple DMA
 619          * descriptors. But that's a project for another day.
 620          */
 621
 622         /*
 623          * Create DMA stuffs for jumbo RX ring.
 624          */
 625         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 626                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 627                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 628                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 629                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 630         if (error) {
 631                 if_printf(ifp, "could not create jumbo RX ring\n");
 632                 return error;
 633         }
 634
 635         /*
 636          * Create DMA stuffs for jumbo buffer block.
 637          */
 638         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 639                                     &sc->bnx_cdata.bnx_jumbo_tag,
 640                                     &sc->bnx_cdata.bnx_jumbo_map,
 641                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 642                                     &paddr);
 643         if (error) {
 644                 if_printf(ifp, "could not create jumbo buffer\n");
 645                 return error;
 646         }
 647
 648         SLIST_INIT(&sc->bnx_jfree_listhead);
 649
 650         /*
 651          * Now divide it up into 9K pieces and save the addresses
 652          * in an array. Note that we play an evil trick here by using
 653          * the first few bytes in the buffer to hold the the address
 654          * of the softc structure for this interface. This is because
 655          * bnx_jfree() needs it, but it is called by the mbuf management
 656          * code which will not pass it to us explicitly.
 657          */
 658         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 659                 entry = &sc->bnx_cdata.bnx_jslots[i];
 660                 entry->bnx_sc = sc;
 661                 entry->bnx_buf = ptr;
 662                 entry->bnx_paddr = paddr;
 663                 entry->bnx_inuse = 0;
 664                 entry->bnx_slot = i;
 665                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 666
 667                 ptr += BNX_JLEN;
 668                 paddr += BNX_JLEN;
 669         }
 670         return 0;
 671 }
 672
 673 static void
 674 bnx_free_jumbo_mem(struct bnx_softc *sc)
 675 {
 676         /* Destroy jumbo RX ring. */
 677         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 678                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 679                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 680
 681         /* Destroy jumbo buffer block. */
 682         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 683                            sc->bnx_cdata.bnx_jumbo_map,
 684                            sc->bnx_ldata.bnx_jumbo_buf);
 685 }
 686
 687 /*
 688  * Allocate a jumbo buffer.
 689  */
 690 static struct bnx_jslot *
 691 bnx_jalloc(struct bnx_softc *sc)
 692 {
 693         struct bnx_jslot *entry;
 694
 695         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 696         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 697         if (entry) {
 698                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 699                 entry->bnx_inuse = 1;
 700         } else {
 701                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 702         }
 703         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 704         return(entry);
 705 }
 706
 707 /*
 708  * Adjust usage count on a jumbo buffer.
 709  */
 710 static void
 711 bnx_jref(void *arg)
 712 {
 713         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 714         struct bnx_softc *sc = entry->bnx_sc;
 715
 716         if (sc == NULL)
 717                 panic("bnx_jref: can't find softc pointer!");
 718
 719         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 720                 panic("bnx_jref: asked to reference buffer "
 721                     "that we don't manage!");
 722         } else if (entry->bnx_inuse == 0) {
 723                 panic("bnx_jref: buffer already free!");
 724         } else {
 725                 atomic_add_int(&entry->bnx_inuse, 1);
 726         }
 727 }
 728
 729 /*
 730  * Release a jumbo buffer.
 731  */
 732 static void
 733 bnx_jfree(void *arg)
 734 {
 735         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 736         struct bnx_softc *sc = entry->bnx_sc;
 737
 738         if (sc == NULL)
 739                 panic("bnx_jfree: can't find softc pointer!");
 740
 741         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 742                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 743         } else if (entry->bnx_inuse == 0) {
 744                 panic("bnx_jfree: buffer already free!");
 745         } else {
 746                 /*
 747                  * Possible MP race to 0, use the serializer.  The atomic insn
 748                  * is still needed for races against bnx_jref().
 749                  */
 750                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 751                 atomic_subtract_int(&entry->bnx_inuse, 1);
 752                 if (entry->bnx_inuse == 0) {
 753                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 754                                           entry, jslot_link);
 755                 }
 756                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 757         }
 758 }
 759
 760
 761 /*
 762  * Intialize a standard receive ring descriptor.
 763  */
 764 static int
 765 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
 766 {
 767         struct mbuf *m_new = NULL;
 768         bus_dma_segment_t seg;
 769         bus_dmamap_t map;
 770         int error, nsegs;
 771
 772         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 773         if (m_new == NULL)
 774                 return ENOBUFS;
 775         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 776         m_adj(m_new, ETHER_ALIGN);
 777
 778         error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
 779                         sc->bnx_cdata.bnx_rx_tmpmap, m_new,
 780                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 781         if (error) {
 782                 m_freem(m_new);
 783                 return error;
 784         }
 785
 786         if (!init) {
 787                 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
 788                                 sc->bnx_cdata.bnx_rx_std_dmamap[i],
 789                                 BUS_DMASYNC_POSTREAD);
 790                 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 791                         sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 792         }
 793
 794         map = sc->bnx_cdata.bnx_rx_tmpmap;
 795         sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
 796         sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
 797
 798         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
 799         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
 800
 801         bnx_setup_rxdesc_std(sc, i);
 802         return 0;
 803 }
 804
 805 static void
 806 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
 807 {
 808         struct bnx_rxchain *rc;
 809         struct bge_rx_bd *r;
 810
 811         rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 812         r = &sc->bnx_ldata.bnx_rx_std_ring[i];
 813
 814         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 815         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 816         r->bge_len = rc->bnx_mbuf->m_len;
 817         r->bge_idx = i;
 818         r->bge_flags = BGE_RXBDFLAG_END;
 819 }
 820
 821 /*
 822  * Initialize a jumbo receive ring descriptor. This allocates
 823  * a jumbo buffer from the pool managed internally by the driver.
 824  */
 825 static int
 826 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 827 {
 828         struct mbuf *m_new = NULL;
 829         struct bnx_jslot *buf;
 830         bus_addr_t paddr;
 831
 832         /* Allocate the mbuf. */
 833         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 834         if (m_new == NULL)
 835                 return ENOBUFS;
 836
 837         /* Allocate the jumbo buffer */
 838         buf = bnx_jalloc(sc);
 839         if (buf == NULL) {
 840                 m_freem(m_new);
 841                 return ENOBUFS;
 842         }
 843
 844         /* Attach the buffer to the mbuf. */
 845         m_new->m_ext.ext_arg = buf;
 846         m_new->m_ext.ext_buf = buf->bnx_buf;
 847         m_new->m_ext.ext_free = bnx_jfree;
 848         m_new->m_ext.ext_ref = bnx_jref;
 849         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 850
 851         m_new->m_flags |= M_EXT;
 852
 853         m_new->m_data = m_new->m_ext.ext_buf;
 854         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 855
 856         paddr = buf->bnx_paddr;
 857         m_adj(m_new, ETHER_ALIGN);
 858         paddr += ETHER_ALIGN;
 859
 860         /* Save necessary information */
 861         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
 862         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
 863
 864         /* Set up the descriptor. */
 865         bnx_setup_rxdesc_jumbo(sc, i);
 866         return 0;
 867 }
 868
 869 static void
 870 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 871 {
 872         struct bge_rx_bd *r;
 873         struct bnx_rxchain *rc;
 874
 875         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 876         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 877
 878         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 879         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 880         r->bge_len = rc->bnx_mbuf->m_len;
 881         r->bge_idx = i;
 882         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 883 }
 884
 885 static int
 886 bnx_init_rx_ring_std(struct bnx_softc *sc)
 887 {
 888         int i, error;
 889
 890         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 891                 error = bnx_newbuf_std(sc, i, 1);
 892                 if (error)
 893                         return error;
 894         };
 895
 896         sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
 897         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
 898
 899         return(0);
 900 }
 901
 902 static void
 903 bnx_free_rx_ring_std(struct bnx_softc *sc)
 904 {
 905         int i;
 906
 907         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 908                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 909
 910                 if (rc->bnx_mbuf != NULL) {
 911                         bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 912                                           sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 913                         m_freem(rc->bnx_mbuf);
 914                         rc->bnx_mbuf = NULL;
 915                 }
 916                 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
 917                     sizeof(struct bge_rx_bd));
 918         }
 919 }
 920
 921 static int
 922 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 923 {
 924         struct bge_rcb *rcb;
 925         int i, error;
 926
 927         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 928                 error = bnx_newbuf_jumbo(sc, i, 1);
 929                 if (error)
 930                         return error;
 931         };
 932
 933         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 934
 935         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 936         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 937         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 938
 939         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 940
 941         return(0);
 942 }
 943
 944 static void
 945 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 946 {
 947         int i;
 948
 949         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 950                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 951
 952                 if (rc->bnx_mbuf != NULL) {
 953                         m_freem(rc->bnx_mbuf);
 954                         rc->bnx_mbuf = NULL;
 955                 }
 956                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 957                     sizeof(struct bge_rx_bd));
 958         }
 959 }
 960
 961 static void
 962 bnx_free_tx_ring(struct bnx_softc *sc)
 963 {
 964         int i;
 965
 966         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 967                 if (sc->bnx_cdata.bnx_tx_chain[i] != NULL) {
 968                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
 969                                           sc->bnx_cdata.bnx_tx_dmamap[i]);
 970                         m_freem(sc->bnx_cdata.bnx_tx_chain[i]);
 971                         sc->bnx_cdata.bnx_tx_chain[i] = NULL;
 972                 }
 973                 bzero(&sc->bnx_ldata.bnx_tx_ring[i],
 974                     sizeof(struct bge_tx_bd));
 975         }
 976 }
 977
 978 static int
 979 bnx_init_tx_ring(struct bnx_softc *sc)
 980 {
 981         sc->bnx_txcnt = 0;
 982         sc->bnx_tx_saved_considx = 0;
 983         sc->bnx_tx_prodidx = 0;
 984
 985         /* Initialize transmit producer index for host-memory send ring. */
 986         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bnx_tx_prodidx);
 987         bnx_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 988
 989         return(0);
 990 }
 991
 992 static void
 993 bnx_setmulti(struct bnx_softc *sc)
 994 {
 995         struct ifnet *ifp;
 996         struct ifmultiaddr *ifma;
 997         uint32_t hashes[4] = { 0, 0, 0, 0 };
 998         int h, i;
 999
1000         ifp = &sc->arpcom.ac_if;
1001
1002         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1003                 for (i = 0; i < 4; i++)
1004                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1005                 return;
1006         }
1007
1008         /* First, zot all the existing filters. */
1009         for (i = 0; i < 4; i++)
1010                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1011
1012         /* Now program new ones. */
1013         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1014                 if (ifma->ifma_addr->sa_family != AF_LINK)
1015                         continue;
1016                 h = ether_crc32_le(
1017                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1018                     ETHER_ADDR_LEN) & 0x7f;
1019                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1020         }
1021
1022         for (i = 0; i < 4; i++)
1023                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1024 }
1025
1026 /*
1027  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1028  * self-test results.
1029  */
1030 static int
1031 bnx_chipinit(struct bnx_softc *sc)
1032 {
1033         uint32_t dma_rw_ctl, mode_ctl;
1034         int i;
1035
1036         /* Set endian type before we access any non-PCI registers. */
1037         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1038             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1039
1040         /* Clear the MAC control register */
1041         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1042
1043         /*
1044          * Clear the MAC statistics block in the NIC's
1045          * internal memory.
1046          */
1047         for (i = BGE_STATS_BLOCK;
1048             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1049                 BNX_MEMWIN_WRITE(sc, i, 0);
1050
1051         for (i = BGE_STATUS_BLOCK;
1052             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1053                 BNX_MEMWIN_WRITE(sc, i, 0);
1054
1055         if (BNX_IS_57765_FAMILY(sc)) {
1056                 uint32_t val;
1057
1058                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1059                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1060                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1061
1062                         /* Access the lower 1K of PL PCI-E block registers. */
1063                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1064                             val | BGE_MODECTL_PCIE_PL_SEL);
1065
1066                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1067                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1068                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1069
1070                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1071                 }
1072                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1073                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1074                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1075
1076                         /* Access the lower 1K of DL PCI-E block registers. */
1077                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1078                             val | BGE_MODECTL_PCIE_DL_SEL);
1079
1080                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1081                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1082                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1083                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1084
1085                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1086                 }
1087
1088                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1089                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1090                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1091                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1092         }
1093
1094         /* Set up the PCI DMA control register. */
1095         dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
1096             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1097
1098         if (BNX_IS_57765_PLUS(sc)) {
1099                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1100                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1101                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1102                 /*
1103                  * Enable HW workaround for controllers that misinterpret
1104                  * a status tag update and leave interrupts permanently
1105                  * disabled.
1106                  */
1107                 if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1108                     sc->bnx_asicrev != BGE_ASICREV_BCM57765)
1109                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1110         }
1111         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1112
1113         /*
1114          * Set up general mode register.
1115          */
1116         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1117             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1118         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1119
1120         /*
1121          * Disable memory write invalidate.  Apparently it is not supported
1122          * properly by these devices.  Also ensure that INTx isn't disabled,
1123          * as these chips need it even when using MSI.
1124          */
1125         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1126             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1127
1128         /* Set the timer prescaler (always 66Mhz) */
1129         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1130
1131         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1132                 DELAY(40);      /* XXX */
1133
1134                 /* Put PHY into ready state */
1135                 BNX_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1136                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1137                 DELAY(40);
1138         }
1139
1140         return(0);
1141 }
1142
1143 static int
1144 bnx_blockinit(struct bnx_softc *sc)
1145 {
1146         struct bge_rcb *rcb;
1147         bus_size_t vrcb;
1148         bge_hostaddr taddr;
1149         uint32_t val;
1150         int i, limit;
1151
1152         /*
1153          * Initialize the memory window pointer register so that
1154          * we can access the first 32K of internal NIC RAM. This will
1155          * allow us to set up the TX send ring RCBs and the RX return
1156          * ring RCBs, plus other things which live in NIC memory.
1157          */
1158         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1159
1160         /* Configure mbuf pool watermarks */
1161         if (BNX_IS_57765_PLUS(sc)) {
1162                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1163                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1164                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1165                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1166                 } else {
1167                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1168                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1169                 }
1170         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1171                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1172                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1173                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1174         } else {
1175                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1176                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1177                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1178         }
1179
1180         /* Configure DMA resource watermarks */
1181         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1182         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1183
1184         /* Enable buffer manager */
1185         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1186         /*
1187          * Change the arbitration algorithm of TXMBUF read request to
1188          * round-robin instead of priority based for BCM5719.  When
1189          * TXFIFO is almost empty, RDMA will hold its request until
1190          * TXFIFO is not almost empty.
1191          */
1192         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1193                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1194         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1195             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1196             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1197                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1198         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1199
1200         /* Poll for buffer manager start indication */
1201         for (i = 0; i < BNX_TIMEOUT; i++) {
1202                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1203                         break;
1204                 DELAY(10);
1205         }
1206
1207         if (i == BNX_TIMEOUT) {
1208                 if_printf(&sc->arpcom.ac_if,
1209                           "buffer manager failed to start\n");
1210                 return(ENXIO);
1211         }
1212
1213         /* Enable flow-through queues */
1214         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1215         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1216
1217         /* Wait until queue initialization is complete */
1218         for (i = 0; i < BNX_TIMEOUT; i++) {
1219                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1220                         break;
1221                 DELAY(10);
1222         }
1223
1224         if (i == BNX_TIMEOUT) {
1225                 if_printf(&sc->arpcom.ac_if,
1226                           "flow-through queue init failed\n");
1227                 return(ENXIO);
1228         }
1229
1230         /*
1231          * Summary of rings supported by the controller:
1232          *
1233          * Standard Receive Producer Ring
1234          * - This ring is used to feed receive buffers for "standard"
1235          *   sized frames (typically 1536 bytes) to the controller.
1236          *
1237          * Jumbo Receive Producer Ring
1238          * - This ring is used to feed receive buffers for jumbo sized
1239          *   frames (i.e. anything bigger than the "standard" frames)
1240          *   to the controller.
1241          *
1242          * Mini Receive Producer Ring
1243          * - This ring is used to feed receive buffers for "mini"
1244          *   sized frames to the controller.
1245          * - This feature required external memory for the controller
1246          *   but was never used in a production system.  Should always
1247          *   be disabled.
1248          *
1249          * Receive Return Ring
1250          * - After the controller has placed an incoming frame into a
1251          *   receive buffer that buffer is moved into a receive return
1252          *   ring.  The driver is then responsible to passing the
1253          *   buffer up to the stack.  Many versions of the controller
1254          *   support multiple RR rings.
1255          *
1256          * Send Ring
1257          * - This ring is used for outgoing frames.  Many versions of
1258          *   the controller support multiple send rings.
1259          */
1260
1261         /* Initialize the standard receive producer ring control block. */
1262         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1263         rcb->bge_hostaddr.bge_addr_lo =
1264             BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1265         rcb->bge_hostaddr.bge_addr_hi =
1266             BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1267         if (BNX_IS_57765_PLUS(sc)) {
1268                 /*
1269                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1270                  * Bits 15-2 : Maximum RX frame size
1271                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1272                  * Bit 0     : Reserved
1273                  */
1274                 rcb->bge_maxlen_flags =
1275                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1276         } else {
1277                 /*
1278                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1279                  * Bits 15-2 : Reserved (should be 0)
1280                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1281                  * Bit 0     : Reserved
1282                  */
1283                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1284         }
1285         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1286             sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1287             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1288                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1289         else
1290                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1291         /* Write the standard receive producer ring control block. */
1292         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1293         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1294         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1295         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1296         /* Reset the standard receive producer ring producer index. */
1297         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1298
1299         /*
1300          * Initialize the jumbo RX producer ring control
1301          * block.  We set the 'ring disabled' bit in the
1302          * flags field until we're actually ready to start
1303          * using this ring (i.e. once we set the MTU
1304          * high enough to require it).
1305          */
1306         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1307                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1308                 /* Get the jumbo receive producer ring RCB parameters. */
1309                 rcb->bge_hostaddr.bge_addr_lo =
1310                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1311                 rcb->bge_hostaddr.bge_addr_hi =
1312                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1313                 rcb->bge_maxlen_flags =
1314                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1315                     BGE_RCB_FLAG_RING_DISABLED);
1316                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1317                     sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1318                     sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1319                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1320                 else
1321                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1322                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1323                     rcb->bge_hostaddr.bge_addr_hi);
1324                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1325                     rcb->bge_hostaddr.bge_addr_lo);
1326                 /* Program the jumbo receive producer ring RCB parameters. */
1327                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1328                     rcb->bge_maxlen_flags);
1329                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1330                 /* Reset the jumbo receive producer ring producer index. */
1331                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1332         }
1333
1334         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1335         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
1336             (sc->bnx_chipid == BGE_CHIPID_BCM5906_A0 ||
1337              sc->bnx_chipid == BGE_CHIPID_BCM5906_A1 ||
1338              sc->bnx_chipid == BGE_CHIPID_BCM5906_A2)) {
1339                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1340                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1341         }
1342
1343         /*
1344          * The BD ring replenish thresholds control how often the
1345          * hardware fetches new BD's from the producer rings in host
1346          * memory.  Setting the value too low on a busy system can
1347          * starve the hardware and recue the throughpout.
1348          *
1349          * Set the BD ring replentish thresholds. The recommended
1350          * values are 1/8th the number of descriptors allocated to
1351          * each ring.
1352          */
1353         val = 8;
1354         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1355         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1356                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1357                     BGE_JUMBO_RX_RING_CNT/8);
1358         }
1359         if (BNX_IS_57765_PLUS(sc)) {
1360                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1361                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1362         }
1363
1364         /*
1365          * Disable all send rings by setting the 'ring disabled' bit
1366          * in the flags field of all the TX send ring control blocks,
1367          * located in NIC memory.
1368          */
1369         if (BNX_IS_5717_PLUS(sc))
1370                 limit = 4;
1371         else if (BNX_IS_57765_FAMILY(sc))
1372                 limit = 2;
1373         else
1374                 limit = 1;
1375         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1376         for (i = 0; i < limit; i++) {
1377                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1378                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1379                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1380                 vrcb += sizeof(struct bge_rcb);
1381         }
1382
1383         /* Configure send ring RCB 0 (we use only the first ring) */
1384         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1385         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_tx_ring_paddr);
1386         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1387         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1388         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1389             sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1390             sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1391                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1392         } else {
1393                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1394                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1395         }
1396         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1397             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1398
1399         /*
1400          * Disable all receive return rings by setting the
1401          * 'ring disabled' bit in the flags field of all the receive
1402          * return ring control blocks, located in NIC memory.
1403          */
1404         if (BNX_IS_5717_PLUS(sc)) {
1405                 /* Should be 17, use 16 until we get an SRAM map. */
1406                 limit = 16;
1407         } else if (BNX_IS_57765_FAMILY(sc)) {
1408                 limit = 4;
1409         } else {
1410                 limit = 1;
1411         }
1412         /* Disable all receive return rings. */
1413         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1414         for (i = 0; i < limit; i++) {
1415                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1416                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1417                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1418                     BGE_RCB_FLAG_RING_DISABLED);
1419                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1420                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1421                     (i * (sizeof(uint64_t))), 0);
1422                 vrcb += sizeof(struct bge_rcb);
1423         }
1424
1425         /*
1426          * Set up receive return ring 0.  Note that the NIC address
1427          * for RX return rings is 0x0.  The return rings live entirely
1428          * within the host, so the nicaddr field in the RCB isn't used.
1429          */
1430         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1431         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1432         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1433         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1434         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1435         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1436             BGE_RCB_MAXLEN_FLAGS(sc->bnx_return_ring_cnt, 0));
1437
1438         /* Set random backoff seed for TX */
1439         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1440             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1441             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1442             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1443             BGE_TX_BACKOFF_SEED_MASK);
1444
1445         /* Set inter-packet gap */
1446         val = 0x2620;
1447         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1448                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1449                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1450         }
1451         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1452
1453         /*
1454          * Specify which ring to use for packets that don't match
1455          * any RX rules.
1456          */
1457         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1458
1459         /*
1460          * Configure number of RX lists. One interrupt distribution
1461          * list, sixteen active lists, one bad frames class.
1462          */
1463         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1464
1465         /* Inialize RX list placement stats mask. */
1466         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1467         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1468
1469         /* Disable host coalescing until we get it set up */
1470         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1471
1472         /* Poll to make sure it's shut down. */
1473         for (i = 0; i < BNX_TIMEOUT; i++) {
1474                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1475                         break;
1476                 DELAY(10);
1477         }
1478
1479         if (i == BNX_TIMEOUT) {
1480                 if_printf(&sc->arpcom.ac_if,
1481                           "host coalescing engine failed to idle\n");
1482                 return(ENXIO);
1483         }
1484
1485         /* Set up host coalescing defaults */
1486         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1487         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1488         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1489         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1490         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1491         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1492
1493         /* Set up address of status block */
1494         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1495         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1496             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1497         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1498             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1499
1500         /* Set up status block partail update size. */
1501         val = BGE_STATBLKSZ_32BYTE;
1502 #if 0
1503         /*
1504          * Does not seem to have visible effect in both
1505          * bulk data (1472B UDP datagram) and tiny data
1506          * (18B UDP datagram) TX tests.
1507          */
1508         val |= BGE_HCCMODE_CLRTICK_TX;
1509 #endif
1510         /* Turn on host coalescing state machine */
1511         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1512
1513         /* Turn on RX BD completion state machine and enable attentions */
1514         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1515             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1516
1517         /* Turn on RX list placement state machine */
1518         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1519
1520         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1521             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1522             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1523             BGE_MACMODE_FRMHDR_DMA_ENB;
1524
1525         if (sc->bnx_flags & BNX_FLAG_TBI)
1526                 val |= BGE_PORTMODE_TBI;
1527         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1528                 val |= BGE_PORTMODE_GMII;
1529         else
1530                 val |= BGE_PORTMODE_MII;
1531
1532         /* Turn on DMA, clear stats */
1533         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1534
1535         /* Set misc. local control, enable interrupts on attentions */
1536         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1537
1538 #ifdef notdef
1539         /* Assert GPIO pins for PHY reset */
1540         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1541             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1542         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1543             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1544 #endif
1545
1546         /* Turn on write DMA state machine */
1547         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1548         /* Enable host coalescing bug fix. */
1549         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1550         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1551                 /* Request larger DMA burst size to get better performance. */
1552                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1553         }
1554         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1555         DELAY(40);
1556
1557         if (BNX_IS_57765_PLUS(sc)) {
1558                 uint32_t dmactl;
1559
1560                 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1561                 /*
1562                  * Adjust tx margin to prevent TX data corruption and
1563                  * fix internal FIFO overflow.
1564                  */
1565                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1566                     sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1567                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1568                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1569                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1570                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1571                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1572                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1573                 }
1574                 /*
1575                  * Enable fix for read DMA FIFO overruns.
1576                  * The fix is to limit the number of RX BDs
1577                  * the hardware would fetch at a fime.
1578                  */
1579                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1580                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1581         }
1582
1583         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1584                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1585                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1586                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1587                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1588         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1589                 /*
1590                  * Allow 4KB burst length reads for non-LSO frames.
1591                  * Enable 512B burst length reads for buffer descriptors.
1592                  */
1593                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1594                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1595                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1596                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1597         }
1598
1599         /* Turn on read DMA state machine */
1600         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1601         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1602                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1603         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1604             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1605             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1606                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1607                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1608                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1609         }
1610         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1611                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1612                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1613                 /*
1614                  * Allow multiple outstanding read requests from
1615                  * non-LSO read DMA engine.
1616                  */
1617                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1618         }
1619         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1620         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1621         DELAY(40);
1622
1623         /* Turn on RX data completion state machine */
1624         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1625
1626         /* Turn on RX BD initiator state machine */
1627         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1628
1629         /* Turn on RX data and RX BD initiator state machine */
1630         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1631
1632         /* Turn on send BD completion state machine */
1633         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1634
1635         /* Turn on send data completion state machine */
1636         val = BGE_SDCMODE_ENABLE;
1637         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1638                 val |= BGE_SDCMODE_CDELAY;
1639         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1640
1641         /* Turn on send data initiator state machine */
1642         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1643
1644         /* Turn on send BD initiator state machine */
1645         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1646
1647         /* Turn on send BD selector state machine */
1648         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1649
1650         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1651         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1652             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1653
1654         /* ack/clear link change events */
1655         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1656             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1657             BGE_MACSTAT_LINK_CHANGED);
1658         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1659
1660         /*
1661          * Enable attention when the link has changed state for
1662          * devices that use auto polling.
1663          */
1664         if (sc->bnx_flags & BNX_FLAG_TBI) {
1665                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1666         } else {
1667                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1668                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1669                         DELAY(80);
1670                 }
1671         }
1672
1673         /*
1674          * Clear any pending link state attention.
1675          * Otherwise some link state change events may be lost until attention
1676          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1677          * It's not necessary on newer BCM chips - perhaps enabling link
1678          * state change attentions implies clearing pending attention.
1679          */
1680         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1681             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1682             BGE_MACSTAT_LINK_CHANGED);
1683
1684         /* Enable link state change attentions. */
1685         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1686
1687         return(0);
1688 }
1689
1690 /*
1691  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1692  * against our list and return its name if we find a match. Note
1693  * that since the Broadcom controller contains VPD support, we
1694  * can get the device name string from the controller itself instead
1695  * of the compiled-in string. This is a little slow, but it guarantees
1696  * we'll always announce the right product name.
1697  */
1698 static int
1699 bnx_probe(device_t dev)
1700 {
1701         const struct bnx_type *t;
1702         uint16_t product, vendor;
1703
1704         if (!pci_is_pcie(dev))
1705                 return ENXIO;
1706
1707         product = pci_get_device(dev);
1708         vendor = pci_get_vendor(dev);
1709
1710         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1711                 if (vendor == t->bnx_vid && product == t->bnx_did)
1712                         break;
1713         }
1714         if (t->bnx_name == NULL)
1715                 return ENXIO;
1716
1717         device_set_desc(dev, t->bnx_name);
1718         return 0;
1719 }
1720
1721 static int
1722 bnx_attach(device_t dev)
1723 {
1724         struct ifnet *ifp;
1725         struct bnx_softc *sc;
1726         uint32_t hwcfg = 0, misccfg;
1727         int error = 0, rid, capmask;
1728         uint8_t ether_addr[ETHER_ADDR_LEN];
1729         uint16_t product, vendor;
1730         driver_intr_t *intr_func;
1731         uintptr_t mii_priv = 0;
1732         u_int intr_flags;
1733
1734         sc = device_get_softc(dev);
1735         sc->bnx_dev = dev;
1736         callout_init(&sc->bnx_stat_timer);
1737         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1738
1739         product = pci_get_device(dev);
1740         vendor = pci_get_vendor(dev);
1741
1742 #ifndef BURN_BRIDGES
1743         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1744                 uint32_t irq, mem;
1745
1746                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1747                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1748
1749                 device_printf(dev, "chip is in D%d power mode "
1750                     "-- setting to D0\n", pci_get_powerstate(dev));
1751
1752                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1753
1754                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1755                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1756         }
1757 #endif  /* !BURN_BRIDGE */
1758
1759         /*
1760          * Map control/status registers.
1761          */
1762         pci_enable_busmaster(dev);
1763
1764         rid = BGE_PCI_BAR0;
1765         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1766             RF_ACTIVE);
1767
1768         if (sc->bnx_res == NULL) {
1769                 device_printf(dev, "couldn't map memory\n");
1770                 return ENXIO;
1771         }
1772
1773         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1774         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1775
1776         /* Save various chip information */
1777         sc->bnx_chipid =
1778             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1779             BGE_PCIMISCCTL_ASICREV_SHIFT;
1780         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1781                 /* All chips having dedicated ASICREV register have CPMU */
1782                 sc->bnx_flags |= BNX_FLAG_CPMU;
1783
1784                 switch (product) {
1785                 case PCI_PRODUCT_BROADCOM_BCM5717:
1786                 case PCI_PRODUCT_BROADCOM_BCM5718:
1787                 case PCI_PRODUCT_BROADCOM_BCM5719:
1788                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1789                         sc->bnx_chipid = pci_read_config(dev,
1790                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1791                         break;
1792
1793                 case PCI_PRODUCT_BROADCOM_BCM57761:
1794                 case PCI_PRODUCT_BROADCOM_BCM57765:
1795                 case PCI_PRODUCT_BROADCOM_BCM57781:
1796                 case PCI_PRODUCT_BROADCOM_BCM57785:
1797                 case PCI_PRODUCT_BROADCOM_BCM57791:
1798                 case PCI_PRODUCT_BROADCOM_BCM57795:
1799                         sc->bnx_chipid = pci_read_config(dev,
1800                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1801                         break;
1802
1803                 default:
1804                         sc->bnx_chipid = pci_read_config(dev,
1805                             BGE_PCI_PRODID_ASICREV, 4);
1806                         break;
1807                 }
1808         }
1809         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1810         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1811
1812         switch (sc->bnx_asicrev) {
1813         case BGE_ASICREV_BCM5717:
1814         case BGE_ASICREV_BCM5719:
1815         case BGE_ASICREV_BCM5720:
1816                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1817                 break;
1818
1819         case BGE_ASICREV_BCM57765:
1820                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1821                 break;
1822         }
1823         sc->bnx_flags |= BNX_FLAG_SHORTDMA;
1824
1825         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906)
1826                 sc->bnx_flags |= BNX_FLAG_NO_EEPROM;
1827
1828         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
1829
1830         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1831         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1832             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1833                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1834         else
1835                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1836         device_printf(dev, "CHIP ID 0x%08x; "
1837                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1838                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1839
1840         /*
1841          * Set various PHY quirk flags.
1842          */
1843
1844         capmask = MII_CAPMASK_DEFAULT;
1845         if ((sc->bnx_asicrev == BGE_ASICREV_BCM5703 &&
1846              (misccfg == 0x4000 || misccfg == 0x8000)) ||
1847             (sc->bnx_asicrev == BGE_ASICREV_BCM5705 &&
1848              vendor == PCI_VENDOR_BROADCOM &&
1849              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
1850               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
1851               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
1852             (vendor == PCI_VENDOR_BROADCOM &&
1853              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
1854               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
1855               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
1856             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
1857             sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1858                 /* 10/100 only */
1859                 capmask &= ~BMSR_EXTSTAT;
1860         }
1861
1862         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1863
1864         /*
1865          * Allocate interrupt
1866          */
1867         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1868             &intr_flags);
1869
1870         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1871             intr_flags);
1872         if (sc->bnx_irq == NULL) {
1873                 device_printf(dev, "couldn't map interrupt\n");
1874                 error = ENXIO;
1875                 goto fail;
1876         }
1877
1878         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1879                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1880                 bnx_enable_msi(sc);
1881         }
1882
1883         /* Initialize if_name earlier, so if_printf could be used */
1884         ifp = &sc->arpcom.ac_if;
1885         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1886
1887         /* Try to reset the chip. */
1888         bnx_reset(sc);
1889
1890         if (bnx_chipinit(sc)) {
1891                 device_printf(dev, "chip initialization failed\n");
1892                 error = ENXIO;
1893                 goto fail;
1894         }
1895
1896         /*
1897          * Get station address
1898          */
1899         error = bnx_get_eaddr(sc, ether_addr);
1900         if (error) {
1901                 device_printf(dev, "failed to read station address\n");
1902                 goto fail;
1903         }
1904
1905         if (BNX_IS_57765_PLUS(sc)) {
1906                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT;
1907         } else {
1908                 /* 5705/5750 limits RX return ring to 512 entries. */
1909                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1910         }
1911
1912         error = bnx_dma_alloc(sc);
1913         if (error)
1914                 goto fail;
1915
1916         /* Set default tuneable values. */
1917         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1918         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1919         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1920         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1921         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_DEF;
1922         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_DEF;
1923
1924         /* Set up ifnet structure */
1925         ifp->if_softc = sc;
1926         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1927         ifp->if_ioctl = bnx_ioctl;
1928         ifp->if_start = bnx_start;
1929 #ifdef DEVICE_POLLING
1930         ifp->if_poll = bnx_poll;
1931 #endif
1932         ifp->if_watchdog = bnx_watchdog;
1933         ifp->if_init = bnx_init;
1934         ifp->if_mtu = ETHERMTU;
1935         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1936         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1937         ifq_set_ready(&ifp->if_snd);
1938
1939         ifp->if_capabilities |= IFCAP_HWCSUM;
1940         ifp->if_hwassist = BNX_CSUM_FEATURES;
1941         ifp->if_capenable = ifp->if_capabilities;
1942
1943         /*
1944          * Figure out what sort of media we have by checking the
1945          * hardware config word in the first 32k of NIC internal memory,
1946          * or fall back to examining the EEPROM if necessary.
1947          * Note: on some BCM5700 cards, this value appears to be unset.
1948          * If that's the case, we have to rely on identifying the NIC
1949          * by its PCI subsystem ID, as we do below for the SysKonnect
1950          * SK-9D41.
1951          */
1952         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1953                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1954         } else {
1955                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1956                                     sizeof(hwcfg))) {
1957                         device_printf(dev, "failed to read EEPROM\n");
1958                         error = ENXIO;
1959                         goto fail;
1960                 }
1961                 hwcfg = ntohl(hwcfg);
1962         }
1963
1964         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1965         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1966             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1967                 sc->bnx_flags |= BNX_FLAG_TBI;
1968
1969         /* Setup MI MODE */
1970         if (sc->bnx_flags & BNX_FLAG_CPMU)
1971                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1972         else
1973                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1974
1975         /* Setup link status update stuffs */
1976         if (sc->bnx_flags & BNX_FLAG_TBI) {
1977                 sc->bnx_link_upd = bnx_tbi_link_upd;
1978                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1979         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1980                 sc->bnx_link_upd = bnx_autopoll_link_upd;
1981                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1982         } else {
1983                 sc->bnx_link_upd = bnx_copper_link_upd;
1984                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1985         }
1986
1987         /* Set default PHY address */
1988         sc->bnx_phyno = 1;
1989
1990         /*
1991          * PHY address mapping for various devices.
1992          *
1993          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
1994          * ---------+-------+-------+-------+-------+
1995          * BCM57XX  |   1   |   X   |   X   |   X   |
1996          * BCM5704  |   1   |   X   |   1   |   X   |
1997          * BCM5717  |   1   |   8   |   2   |   9   |
1998          * BCM5719  |   1   |   8   |   2   |   9   |
1999          * BCM5720  |   1   |   8   |   2   |   9   |
2000          *
2001          * Other addresses may respond but they are not
2002          * IEEE compliant PHYs and should be ignored.
2003          */
2004         if (BNX_IS_5717_PLUS(sc)) {
2005                 int f;
2006
2007                 f = pci_get_function(dev);
2008                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2009                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2010                             BGE_SGDIGSTS_IS_SERDES)
2011                                 sc->bnx_phyno = f + 8;
2012                         else
2013                                 sc->bnx_phyno = f + 1;
2014                 } else {
2015                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2016                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2017                                 sc->bnx_phyno = f + 8;
2018                         else
2019                                 sc->bnx_phyno = f + 1;
2020                 }
2021         }
2022
2023         if (sc->bnx_flags & BNX_FLAG_TBI) {
2024                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2025                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2026                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2027                 ifmedia_add(&sc->bnx_ifmedia,
2028                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2029                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2030                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2031                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2032         } else {
2033                 struct mii_probe_args mii_args;
2034
2035                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2036                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2037                 mii_args.mii_capmask = capmask;
2038                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2039                 mii_args.mii_priv = mii_priv;
2040
2041                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2042                 if (error) {
2043                         device_printf(dev, "MII without any PHY!\n");
2044                         goto fail;
2045                 }
2046         }
2047
2048         /*
2049          * Create sysctl nodes.
2050          */
2051         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2052         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2053                                               SYSCTL_STATIC_CHILDREN(_hw),
2054                                               OID_AUTO,
2055                                               device_get_nameunit(dev),
2056                                               CTLFLAG_RD, 0, "");
2057         if (sc->bnx_sysctl_tree == NULL) {
2058                 device_printf(dev, "can't add sysctl node\n");
2059                 error = ENXIO;
2060                 goto fail;
2061         }
2062
2063         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2064                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2065                         OID_AUTO, "rx_coal_ticks",
2066                         CTLTYPE_INT | CTLFLAG_RW,
2067                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2068                         "Receive coalescing ticks (usec).");
2069         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2070                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2071                         OID_AUTO, "tx_coal_ticks",
2072                         CTLTYPE_INT | CTLFLAG_RW,
2073                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2074                         "Transmit coalescing ticks (usec).");
2075         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2076                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2077                         OID_AUTO, "rx_coal_bds",
2078                         CTLTYPE_INT | CTLFLAG_RW,
2079                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2080                         "Receive max coalesced BD count.");
2081         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2082                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2083                         OID_AUTO, "tx_coal_bds",
2084                         CTLTYPE_INT | CTLFLAG_RW,
2085                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2086                         "Transmit max coalesced BD count.");
2087         /*
2088          * A common design characteristic for many Broadcom
2089          * client controllers is that they only support a
2090          * single outstanding DMA read operation on the PCIe
2091          * bus. This means that it will take twice as long to
2092          * fetch a TX frame that is split into header and
2093          * payload buffers as it does to fetch a single,
2094          * contiguous TX frame (2 reads vs. 1 read). For these
2095          * controllers, coalescing buffers to reduce the number
2096          * of memory reads is effective way to get maximum
2097          * performance(about 940Mbps).  Without collapsing TX
2098          * buffers the maximum TCP bulk transfer performance
2099          * is about 850Mbps. However forcing coalescing mbufs
2100          * consumes a lot of CPU cycles, so leave it off by
2101          * default.
2102          */
2103         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2104             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2105             "force_defrag", CTLFLAG_RW, &sc->bnx_force_defrag, 0,
2106             "Force defragment on TX path");
2107
2108         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2109             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2110             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2111             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2112             "Receive max coalesced BD count during interrupt.");
2113         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2114             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2115             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2116             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2117             "Transmit max coalesced BD count during interrupt.");
2118
2119         /*
2120          * Call MI attach routine.
2121          */
2122         ether_ifattach(ifp, ether_addr, NULL);
2123
2124         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2125                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2126                         intr_func = bnx_msi_oneshot;
2127                         if (bootverbose)
2128                                 device_printf(dev, "oneshot MSI\n");
2129                 } else {
2130                         intr_func = bnx_msi;
2131                 }
2132         } else {
2133                 intr_func = bnx_intr_legacy;
2134         }
2135         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2136             &sc->bnx_intrhand, ifp->if_serializer);
2137         if (error) {
2138                 ether_ifdetach(ifp);
2139                 device_printf(dev, "couldn't set up irq\n");
2140                 goto fail;
2141         }
2142
2143         ifp->if_cpuid = rman_get_cpuid(sc->bnx_irq);
2144         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2145
2146         return(0);
2147 fail:
2148         bnx_detach(dev);
2149         return(error);
2150 }
2151
2152 static int
2153 bnx_detach(device_t dev)
2154 {
2155         struct bnx_softc *sc = device_get_softc(dev);
2156
2157         if (device_is_attached(dev)) {
2158                 struct ifnet *ifp = &sc->arpcom.ac_if;
2159
2160                 lwkt_serialize_enter(ifp->if_serializer);
2161                 bnx_stop(sc);
2162                 bnx_reset(sc);
2163                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2164                 lwkt_serialize_exit(ifp->if_serializer);
2165
2166                 ether_ifdetach(ifp);
2167         }
2168
2169         if (sc->bnx_flags & BNX_FLAG_TBI)
2170                 ifmedia_removeall(&sc->bnx_ifmedia);
2171         if (sc->bnx_miibus)
2172                 device_delete_child(dev, sc->bnx_miibus);
2173         bus_generic_detach(dev);
2174
2175         if (sc->bnx_irq != NULL) {
2176                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2177                     sc->bnx_irq);
2178         }
2179         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2180                 pci_release_msi(dev);
2181
2182         if (sc->bnx_res != NULL) {
2183                 bus_release_resource(dev, SYS_RES_MEMORY,
2184                     BGE_PCI_BAR0, sc->bnx_res);
2185         }
2186
2187         if (sc->bnx_sysctl_tree != NULL)
2188                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2189
2190         bnx_dma_free(sc);
2191
2192         return 0;
2193 }
2194
2195 static void
2196 bnx_reset(struct bnx_softc *sc)
2197 {
2198         device_t dev;
2199         uint32_t cachesize, command, pcistate, reset;
2200         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2201         int i, val = 0;
2202         uint16_t devctl;
2203
2204         dev = sc->bnx_dev;
2205
2206         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
2207                 write_op = bnx_writemem_direct;
2208         else
2209                 write_op = bnx_writereg_ind;
2210
2211         /* Save some important PCI state. */
2212         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2213         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2214         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2215
2216         pci_write_config(dev, BGE_PCI_MISC_CTL,
2217             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2218             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2219             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2220
2221         /* Disable fastboot on controllers that support it. */
2222         if (bootverbose)
2223                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2224         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2225
2226         /*
2227          * Write the magic number to SRAM at offset 0xB50.
2228          * When firmware finishes its initialization it will
2229          * write ~BGE_MAGIC_NUMBER to the same location.
2230          */
2231         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2232
2233         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2234
2235         /* XXX: Broadcom Linux driver. */
2236         /* Force PCI-E 1.0a mode */
2237         if (!BNX_IS_57765_PLUS(sc) &&
2238             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2239             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2240              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2241                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2242                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2243         }
2244         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2245                 /* Prevent PCIE link training during global reset */
2246                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2247                 reset |= (1<<29);
2248         }
2249
2250         /*
2251          * Set GPHY Power Down Override to leave GPHY
2252          * powered up in D0 uninitialized.
2253          */
2254         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2255                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2256
2257         /* Issue global reset */
2258         write_op(sc, BGE_MISC_CFG, reset);
2259
2260         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2261                 uint32_t status, ctrl;
2262
2263                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2264                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2265                     status | BGE_VCPU_STATUS_DRV_RESET);
2266                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2267                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2268                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2269         }
2270
2271         DELAY(1000);
2272
2273         /* XXX: Broadcom Linux driver. */
2274         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2275                 uint32_t v;
2276
2277                 DELAY(500000); /* wait for link training to complete */
2278                 v = pci_read_config(dev, 0xc4, 4);
2279                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2280         }
2281
2282         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2283
2284         /* Disable no snoop and disable relaxed ordering. */
2285         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2286
2287         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2288         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2289                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2290                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2291         }
2292
2293         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2294             devctl, 2);
2295
2296         /* Clear error status. */
2297         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2298             PCIEM_DEVSTS_CORR_ERR |
2299             PCIEM_DEVSTS_NFATAL_ERR |
2300             PCIEM_DEVSTS_FATAL_ERR |
2301             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2302
2303         /* Reset some of the PCI state that got zapped by reset */
2304         pci_write_config(dev, BGE_PCI_MISC_CTL,
2305             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2306             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2307             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2308         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2309         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2310         write_op(sc, BGE_MISC_CFG, (65 << 1));
2311
2312         /* Enable memory arbiter */
2313         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2314
2315         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2316                 for (i = 0; i < BNX_TIMEOUT; i++) {
2317                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2318                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2319                                 break;
2320                         DELAY(100);
2321                 }
2322                 if (i == BNX_TIMEOUT) {
2323                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2324                         return;
2325                 }
2326         } else {
2327                 /*
2328                  * Poll until we see the 1's complement of the magic number.
2329                  * This indicates that the firmware initialization
2330                  * is complete.
2331                  */
2332                 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2333                         val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2334                         if (val == ~BGE_MAGIC_NUMBER)
2335                                 break;
2336                         DELAY(10);
2337                 }
2338                 if (i == BNX_FIRMWARE_TIMEOUT) {
2339                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2340                                   "timed out, found 0x%08x\n", val);
2341                 }
2342
2343                 /* BCM57765 A0 needs additional time before accessing. */
2344                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2345                         DELAY(10 * 1000);
2346         }
2347
2348         /*
2349          * XXX Wait for the value of the PCISTATE register to
2350          * return to its original pre-reset state. This is a
2351          * fairly good indicator of reset completion. If we don't
2352          * wait for the reset to fully complete, trying to read
2353          * from the device's non-PCI registers may yield garbage
2354          * results.
2355          */
2356         for (i = 0; i < BNX_TIMEOUT; i++) {
2357                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2358                         break;
2359                 DELAY(10);
2360         }
2361
2362         /* Fix up byte swapping */
2363         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2364
2365         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2366
2367         /*
2368          * The 5704 in TBI mode apparently needs some special
2369          * adjustment to insure the SERDES drive level is set
2370          * to 1.2V.
2371          */
2372         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2373             (sc->bnx_flags & BNX_FLAG_TBI)) {
2374                 uint32_t serdescfg;
2375
2376                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2377                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2378                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2379         }
2380
2381         /* XXX: Broadcom Linux driver. */
2382         if (!BNX_IS_57765_PLUS(sc)) {
2383                 uint32_t v;
2384
2385                 /* Enable Data FIFO protection. */
2386                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2387                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2388         }
2389
2390         DELAY(10000);
2391
2392         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2393                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2394                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2395         }
2396 }
2397
2398 /*
2399  * Frame reception handling. This is called if there's a frame
2400  * on the receive return list.
2401  *
2402  * Note: we have to be able to handle two possibilities here:
2403  * 1) the frame is from the jumbo recieve ring
2404  * 2) the frame is from the standard receive ring
2405  */
2406
2407 static void
2408 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod)
2409 {
2410         struct ifnet *ifp;
2411         int stdcnt = 0, jumbocnt = 0;
2412
2413         ifp = &sc->arpcom.ac_if;
2414
2415         while (sc->bnx_rx_saved_considx != rx_prod) {
2416                 struct bge_rx_bd        *cur_rx;
2417                 uint32_t                rxidx;
2418                 struct mbuf             *m = NULL;
2419                 uint16_t                vlan_tag = 0;
2420                 int                     have_tag = 0;
2421
2422                 cur_rx =
2423             &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2424
2425                 rxidx = cur_rx->bge_idx;
2426                 BNX_INC(sc->bnx_rx_saved_considx, sc->bnx_return_ring_cnt);
2427
2428                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2429                         have_tag = 1;
2430                         vlan_tag = cur_rx->bge_vlan_tag;
2431                 }
2432
2433                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2434                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2435                         jumbocnt++;
2436
2437                         if (rxidx != sc->bnx_jumbo) {
2438                                 ifp->if_ierrors++;
2439                                 if_printf(ifp, "sw jumbo index(%d) "
2440                                     "and hw jumbo index(%d) mismatch, drop!\n",
2441                                     sc->bnx_jumbo, rxidx);
2442                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2443                                 continue;
2444                         }
2445
2446                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2447                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2448                                 ifp->if_ierrors++;
2449                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2450                                 continue;
2451                         }
2452                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2453                                 ifp->if_ierrors++;
2454                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2455                                 continue;
2456                         }
2457                 } else {
2458                         BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2459                         stdcnt++;
2460
2461                         if (rxidx != sc->bnx_std) {
2462                                 ifp->if_ierrors++;
2463                                 if_printf(ifp, "sw std index(%d) "
2464                                     "and hw std index(%d) mismatch, drop!\n",
2465                                     sc->bnx_std, rxidx);
2466                                 bnx_setup_rxdesc_std(sc, rxidx);
2467                                 continue;
2468                         }
2469
2470                         m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2471                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2472                                 ifp->if_ierrors++;
2473                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2474                                 continue;
2475                         }
2476                         if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2477                                 ifp->if_ierrors++;
2478                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2479                                 continue;
2480                         }
2481                 }
2482
2483                 ifp->if_ipackets++;
2484                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2485                 m->m_pkthdr.rcvif = ifp;
2486
2487                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2488                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2489                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2490                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2491                                 if ((cur_rx->bge_error_flag &
2492                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2493                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2494                         }
2495                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2496                                 m->m_pkthdr.csum_data =
2497                                     cur_rx->bge_tcp_udp_csum;
2498                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2499                                     CSUM_PSEUDO_HDR;
2500                         }
2501                 }
2502
2503                 /*
2504                  * If we received a packet with a vlan tag, pass it
2505                  * to vlan_input() instead of ether_input().
2506                  */
2507                 if (have_tag) {
2508                         m->m_flags |= M_VLANTAG;
2509                         m->m_pkthdr.ether_vlantag = vlan_tag;
2510                         have_tag = vlan_tag = 0;
2511                 }
2512                 ifp->if_input(ifp, m);
2513         }
2514
2515         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2516         if (stdcnt)
2517                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2518         if (jumbocnt)
2519                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2520 }
2521
2522 static void
2523 bnx_txeof(struct bnx_softc *sc, uint16_t tx_cons)
2524 {
2525         struct bge_tx_bd *cur_tx = NULL;
2526         struct ifnet *ifp;
2527
2528         ifp = &sc->arpcom.ac_if;
2529
2530         /*
2531          * Go through our tx ring and free mbufs for those
2532          * frames that have been sent.
2533          */
2534         while (sc->bnx_tx_saved_considx != tx_cons) {
2535                 uint32_t idx = 0;
2536
2537                 idx = sc->bnx_tx_saved_considx;
2538                 cur_tx = &sc->bnx_ldata.bnx_tx_ring[idx];
2539                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2540                         ifp->if_opackets++;
2541                 if (sc->bnx_cdata.bnx_tx_chain[idx] != NULL) {
2542                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
2543                             sc->bnx_cdata.bnx_tx_dmamap[idx]);
2544                         m_freem(sc->bnx_cdata.bnx_tx_chain[idx]);
2545                         sc->bnx_cdata.bnx_tx_chain[idx] = NULL;
2546                 }
2547                 sc->bnx_txcnt--;
2548                 BNX_INC(sc->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2549         }
2550
2551         if (cur_tx != NULL &&
2552             (BGE_TX_RING_CNT - sc->bnx_txcnt) >=
2553             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2554                 ifp->if_flags &= ~IFF_OACTIVE;
2555
2556         if (sc->bnx_txcnt == 0)
2557                 ifp->if_timer = 0;
2558
2559         if (!ifq_is_empty(&ifp->if_snd))
2560                 if_devstart(ifp);
2561 }
2562
2563 #ifdef DEVICE_POLLING
2564
2565 static void
2566 bnx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2567 {
2568         struct bnx_softc *sc = ifp->if_softc;
2569         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2570         uint16_t rx_prod, tx_cons;
2571
2572         switch(cmd) {
2573         case POLL_REGISTER:
2574                 bnx_disable_intr(sc);
2575                 break;
2576         case POLL_DEREGISTER:
2577                 bnx_enable_intr(sc);
2578                 break;
2579         case POLL_AND_CHECK_STATUS:
2580                 /*
2581                  * Process link state changes.
2582                  */
2583                 bnx_link_poll(sc);
2584                 /* Fall through */
2585         case POLL_ONLY:
2586                 sc->bnx_status_tag = sblk->bge_status_tag;
2587                 /*
2588                  * Use a load fence to ensure that status_tag
2589                  * is saved  before rx_prod and tx_cons.
2590                  */
2591                 cpu_lfence();
2592
2593                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2594                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2595                 if (ifp->if_flags & IFF_RUNNING) {
2596                         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2597                         if (sc->bnx_rx_saved_considx != rx_prod)
2598                                 bnx_rxeof(sc, rx_prod);
2599
2600                         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2601                         if (sc->bnx_tx_saved_considx != tx_cons)
2602                                 bnx_txeof(sc, tx_cons);
2603                 }
2604                 break;
2605         }
2606 }
2607
2608 #endif
2609
2610 static void
2611 bnx_intr_legacy(void *xsc)
2612 {
2613         struct bnx_softc *sc = xsc;
2614         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2615
2616         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2617                 uint32_t val;
2618
2619                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2620                 if (val & BGE_PCISTAT_INTR_NOTACT)
2621                         return;
2622         }
2623
2624         /*
2625          * NOTE:
2626          * Interrupt will have to be disabled if tagged status
2627          * is used, else interrupt will always be asserted on
2628          * certain chips (at least on BCM5750 AX/BX).
2629          */
2630         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2631
2632         bnx_intr(sc);
2633 }
2634
2635 static void
2636 bnx_msi(void *xsc)
2637 {
2638         struct bnx_softc *sc = xsc;
2639
2640         /* Disable interrupt first */
2641         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2642         bnx_intr(sc);
2643 }
2644
2645 static void
2646 bnx_msi_oneshot(void *xsc)
2647 {
2648         bnx_intr(xsc);
2649 }
2650
2651 static void
2652 bnx_intr(struct bnx_softc *sc)
2653 {
2654         struct ifnet *ifp = &sc->arpcom.ac_if;
2655         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2656         uint16_t rx_prod, tx_cons;
2657         uint32_t status;
2658
2659         sc->bnx_status_tag = sblk->bge_status_tag;
2660         /*
2661          * Use a load fence to ensure that status_tag is saved
2662          * before rx_prod, tx_cons and status.
2663          */
2664         cpu_lfence();
2665
2666         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2667         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2668         status = sblk->bge_status;
2669
2670         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2671                 bnx_link_poll(sc);
2672
2673         if (ifp->if_flags & IFF_RUNNING) {
2674                 if (sc->bnx_rx_saved_considx != rx_prod)
2675                         bnx_rxeof(sc, rx_prod);
2676
2677                 if (sc->bnx_tx_saved_considx != tx_cons)
2678                         bnx_txeof(sc, tx_cons);
2679         }
2680
2681         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2682
2683         if (sc->bnx_coal_chg)
2684                 bnx_coal_change(sc);
2685 }
2686
2687 static void
2688 bnx_tick(void *xsc)
2689 {
2690         struct bnx_softc *sc = xsc;
2691         struct ifnet *ifp = &sc->arpcom.ac_if;
2692
2693         lwkt_serialize_enter(ifp->if_serializer);
2694
2695         bnx_stats_update_regs(sc);
2696
2697         if (sc->bnx_flags & BNX_FLAG_TBI) {
2698                 /*
2699                  * Since in TBI mode auto-polling can't be used we should poll
2700                  * link status manually. Here we register pending link event
2701                  * and trigger interrupt.
2702                  */
2703                 sc->bnx_link_evt++;
2704                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2705         } else if (!sc->bnx_link) {
2706                 mii_tick(device_get_softc(sc->bnx_miibus));
2707         }
2708
2709         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2710
2711         lwkt_serialize_exit(ifp->if_serializer);
2712 }
2713
2714 static void
2715 bnx_stats_update_regs(struct bnx_softc *sc)
2716 {
2717         struct ifnet *ifp = &sc->arpcom.ac_if;
2718         struct bge_mac_stats_regs stats;
2719         uint32_t *s;
2720         int i;
2721
2722         s = (uint32_t *)&stats;
2723         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2724                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2725                 s++;
2726         }
2727
2728         ifp->if_collisions +=
2729            (stats.dot3StatsSingleCollisionFrames +
2730            stats.dot3StatsMultipleCollisionFrames +
2731            stats.dot3StatsExcessiveCollisions +
2732            stats.dot3StatsLateCollisions) -
2733            ifp->if_collisions;
2734 }
2735
2736 /*
2737  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2738  * pointers to descriptors.
2739  */
2740 static int
2741 bnx_encap(struct bnx_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2742 {
2743         struct bge_tx_bd *d = NULL;
2744         uint16_t csum_flags = 0;
2745         bus_dma_segment_t segs[BNX_NSEG_NEW];
2746         bus_dmamap_t map;
2747         int error, maxsegs, nsegs, idx, i;
2748         struct mbuf *m_head = *m_head0, *m_new;
2749
2750         if (m_head->m_pkthdr.csum_flags) {
2751                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2752                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2753                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2754                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2755                 if (m_head->m_flags & M_LASTFRAG)
2756                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2757                 else if (m_head->m_flags & M_FRAG)
2758                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2759         }
2760
2761         idx = *txidx;
2762         map = sc->bnx_cdata.bnx_tx_dmamap[idx];
2763
2764         maxsegs = (BGE_TX_RING_CNT - sc->bnx_txcnt) - BNX_NSEG_RSVD;
2765         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2766                 ("not enough segments %d", maxsegs));
2767
2768         if (maxsegs > BNX_NSEG_NEW)
2769                 maxsegs = BNX_NSEG_NEW;
2770
2771         /*
2772          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2773          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2774          * but when such padded frames employ the bge IP/TCP checksum
2775          * offload, the hardware checksum assist gives incorrect results
2776          * (possibly from incorporating its own padding into the UDP/TCP
2777          * checksum; who knows).  If we pad such runts with zeros, the
2778          * onboard checksum comes out correct.
2779          */
2780         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2781             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2782                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2783                 if (error)
2784                         goto back;
2785         }
2786
2787         if ((sc->bnx_flags & BNX_FLAG_SHORTDMA) && m_head->m_next != NULL) {
2788                 m_new = bnx_defrag_shortdma(m_head);
2789                 if (m_new == NULL) {
2790                         error = ENOBUFS;
2791                         goto back;
2792                 }
2793                 *m_head0 = m_head = m_new;
2794         }
2795         if (sc->bnx_force_defrag && m_head->m_next != NULL) {
2796                 /*
2797                  * Forcefully defragment mbuf chain to overcome hardware
2798                  * limitation which only support a single outstanding
2799                  * DMA read operation.  If it fails, keep moving on using
2800                  * the original mbuf chain.
2801                  */
2802                 m_new = m_defrag(m_head, MB_DONTWAIT);
2803                 if (m_new != NULL)
2804                         *m_head0 = m_head = m_new;
2805         }
2806
2807         error = bus_dmamap_load_mbuf_defrag(sc->bnx_cdata.bnx_tx_mtag, map,
2808                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2809         if (error)
2810                 goto back;
2811
2812         m_head = *m_head0;
2813         bus_dmamap_sync(sc->bnx_cdata.bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2814
2815         for (i = 0; ; i++) {
2816                 d = &sc->bnx_ldata.bnx_tx_ring[idx];
2817
2818                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2819                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2820                 d->bge_len = segs[i].ds_len;
2821                 d->bge_flags = csum_flags;
2822
2823                 if (i == nsegs - 1)
2824                         break;
2825                 BNX_INC(idx, BGE_TX_RING_CNT);
2826         }
2827         /* Mark the last segment as end of packet... */
2828         d->bge_flags |= BGE_TXBDFLAG_END;
2829
2830         /* Set vlan tag to the first segment of the packet. */
2831         d = &sc->bnx_ldata.bnx_tx_ring[*txidx];
2832         if (m_head->m_flags & M_VLANTAG) {
2833                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2834                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2835         } else {
2836                 d->bge_vlan_tag = 0;
2837         }
2838
2839         /*
2840          * Insure that the map for this transmission is placed at
2841          * the array index of the last descriptor in this chain.
2842          */
2843         sc->bnx_cdata.bnx_tx_dmamap[*txidx] = sc->bnx_cdata.bnx_tx_dmamap[idx];
2844         sc->bnx_cdata.bnx_tx_dmamap[idx] = map;
2845         sc->bnx_cdata.bnx_tx_chain[idx] = m_head;
2846         sc->bnx_txcnt += nsegs;
2847
2848         BNX_INC(idx, BGE_TX_RING_CNT);
2849         *txidx = idx;
2850 back:
2851         if (error) {
2852                 m_freem(*m_head0);
2853                 *m_head0 = NULL;
2854         }
2855         return error;
2856 }
2857
2858 /*
2859  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2860  * to the mbuf data regions directly in the transmit descriptors.
2861  */
2862 static void
2863 bnx_start(struct ifnet *ifp)
2864 {
2865         struct bnx_softc *sc = ifp->if_softc;
2866         struct mbuf *m_head = NULL;
2867         uint32_t prodidx;
2868         int need_trans;
2869
2870         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2871                 return;
2872
2873         prodidx = sc->bnx_tx_prodidx;
2874
2875         need_trans = 0;
2876         while (sc->bnx_cdata.bnx_tx_chain[prodidx] == NULL) {
2877                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2878                 if (m_head == NULL)
2879                         break;
2880
2881                 /*
2882                  * XXX
2883                  * The code inside the if() block is never reached since we
2884                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2885                  * requests to checksum TCP/UDP in a fragmented packet.
2886                  *
2887                  * XXX
2888                  * safety overkill.  If this is a fragmented packet chain
2889                  * with delayed TCP/UDP checksums, then only encapsulate
2890                  * it if we have enough descriptors to handle the entire
2891                  * chain at once.
2892                  * (paranoia -- may not actually be needed)
2893                  */
2894                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2895                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2896                         if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
2897                             m_head->m_pkthdr.csum_data + BNX_NSEG_RSVD) {
2898                                 ifp->if_flags |= IFF_OACTIVE;
2899                                 ifq_prepend(&ifp->if_snd, m_head);
2900                                 break;
2901                         }
2902                 }
2903
2904                 /*
2905                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2906                  * descriptors of the end of the ring.  Also make
2907                  * sure there are BGE_NSEG_SPARE descriptors for
2908                  * jumbo buffers' defragmentation.
2909                  */
2910                 if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
2911                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2912                         ifp->if_flags |= IFF_OACTIVE;
2913                         ifq_prepend(&ifp->if_snd, m_head);
2914                         break;
2915                 }
2916
2917                 /*
2918                  * Pack the data into the transmit ring. If we
2919                  * don't have room, set the OACTIVE flag and wait
2920                  * for the NIC to drain the ring.
2921                  */
2922                 if (bnx_encap(sc, &m_head, &prodidx)) {
2923                         ifp->if_flags |= IFF_OACTIVE;
2924                         ifp->if_oerrors++;
2925                         break;
2926                 }
2927                 need_trans = 1;
2928
2929                 ETHER_BPF_MTAP(ifp, m_head);
2930         }
2931
2932         if (!need_trans)
2933                 return;
2934
2935         /* Transmit */
2936         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2937
2938         sc->bnx_tx_prodidx = prodidx;
2939
2940         /*
2941          * Set a timeout in case the chip goes out to lunch.
2942          */
2943         ifp->if_timer = 5;
2944 }
2945
2946 static void
2947 bnx_init(void *xsc)
2948 {
2949         struct bnx_softc *sc = xsc;
2950         struct ifnet *ifp = &sc->arpcom.ac_if;
2951         uint16_t *m;
2952         uint32_t mode;
2953
2954         ASSERT_SERIALIZED(ifp->if_serializer);
2955
2956         /* Cancel pending I/O and flush buffers. */
2957         bnx_stop(sc);
2958         bnx_reset(sc);
2959         bnx_chipinit(sc);
2960
2961         /*
2962          * Init the various state machines, ring
2963          * control blocks and firmware.
2964          */
2965         if (bnx_blockinit(sc)) {
2966                 if_printf(ifp, "initialization failure\n");
2967                 bnx_stop(sc);
2968                 return;
2969         }
2970
2971         /* Specify MTU. */
2972         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2973             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2974
2975         /* Load our MAC address. */
2976         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2977         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2978         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2979
2980         /* Enable or disable promiscuous mode as needed. */
2981         bnx_setpromisc(sc);
2982
2983         /* Program multicast filter. */
2984         bnx_setmulti(sc);
2985
2986         /* Init RX ring. */
2987         if (bnx_init_rx_ring_std(sc)) {
2988                 if_printf(ifp, "RX ring initialization failed\n");
2989                 bnx_stop(sc);
2990                 return;
2991         }
2992
2993         /* Init jumbo RX ring. */
2994         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
2995                 if (bnx_init_rx_ring_jumbo(sc)) {
2996                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
2997                         bnx_stop(sc);
2998                         return;
2999                 }
3000         }
3001
3002         /* Init our RX return ring index */
3003         sc->bnx_rx_saved_considx = 0;
3004
3005         /* Init TX ring. */
3006         bnx_init_tx_ring(sc);
3007
3008         /* Enable TX MAC state machine lockup fix. */
3009         mode = CSR_READ_4(sc, BGE_TX_MODE);
3010         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3011         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
3012                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3013                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3014                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3015         }
3016         /* Turn on transmitter */
3017         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3018
3019         /* Turn on receiver */
3020         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3021
3022         /*
3023          * Set the number of good frames to receive after RX MBUF
3024          * Low Watermark has been reached.  After the RX MAC receives
3025          * this number of frames, it will drop subsequent incoming
3026          * frames until the MBUF High Watermark is reached.
3027          */
3028         if (BNX_IS_57765_FAMILY(sc))
3029                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3030         else
3031                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3032
3033         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3034                 if (bootverbose) {
3035                         if_printf(ifp, "MSI_MODE: %#x\n",
3036                             CSR_READ_4(sc, BGE_MSI_MODE));
3037                 }
3038         }
3039
3040         /* Tell firmware we're alive. */
3041         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3042
3043         /* Enable host interrupts if polling(4) is not enabled. */
3044         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3045 #ifdef DEVICE_POLLING
3046         if (ifp->if_flags & IFF_POLLING)
3047                 bnx_disable_intr(sc);
3048         else
3049 #endif
3050         bnx_enable_intr(sc);
3051
3052         bnx_ifmedia_upd(ifp);
3053
3054         ifp->if_flags |= IFF_RUNNING;
3055         ifp->if_flags &= ~IFF_OACTIVE;
3056
3057         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
3058 }
3059
3060 /*
3061  * Set media options.
3062  */
3063 static int
3064 bnx_ifmedia_upd(struct ifnet *ifp)
3065 {
3066         struct bnx_softc *sc = ifp->if_softc;
3067
3068         /* If this is a 1000baseX NIC, enable the TBI port. */
3069         if (sc->bnx_flags & BNX_FLAG_TBI) {
3070                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3071
3072                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3073                         return(EINVAL);
3074
3075                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3076                 case IFM_AUTO:
3077                         break;
3078
3079                 case IFM_1000_SX:
3080                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3081                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3082                                     BGE_MACMODE_HALF_DUPLEX);
3083                         } else {
3084                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3085                                     BGE_MACMODE_HALF_DUPLEX);
3086                         }
3087                         break;
3088                 default:
3089                         return(EINVAL);
3090                 }
3091         } else {
3092                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3093
3094                 sc->bnx_link_evt++;
3095                 sc->bnx_link = 0;
3096                 if (mii->mii_instance) {
3097                         struct mii_softc *miisc;
3098
3099                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3100                                 mii_phy_reset(miisc);
3101                 }
3102                 mii_mediachg(mii);
3103
3104                 /*
3105                  * Force an interrupt so that we will call bnx_link_upd
3106                  * if needed and clear any pending link state attention.
3107                  * Without this we are not getting any further interrupts
3108                  * for link state changes and thus will not UP the link and
3109                  * not be able to send in bnx_start.  The only way to get
3110                  * things working was to receive a packet and get an RX
3111                  * intr.
3112                  *
3113                  * bnx_tick should help for fiber cards and we might not
3114                  * need to do this here if BNX_FLAG_TBI is set but as
3115                  * we poll for fiber anyway it should not harm.
3116                  */
3117                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3118         }
3119         return(0);
3120 }
3121
3122 /*
3123  * Report current media status.
3124  */
3125 static void
3126 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3127 {
3128         struct bnx_softc *sc = ifp->if_softc;
3129
3130         if (sc->bnx_flags & BNX_FLAG_TBI) {
3131                 ifmr->ifm_status = IFM_AVALID;
3132                 ifmr->ifm_active = IFM_ETHER;
3133                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3134                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3135                         ifmr->ifm_status |= IFM_ACTIVE;
3136                 } else {
3137                         ifmr->ifm_active |= IFM_NONE;
3138                         return;
3139                 }
3140
3141                 ifmr->ifm_active |= IFM_1000_SX;
3142                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3143                         ifmr->ifm_active |= IFM_HDX;
3144                 else
3145                         ifmr->ifm_active |= IFM_FDX;
3146         } else {
3147                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3148
3149                 mii_pollstat(mii);
3150                 ifmr->ifm_active = mii->mii_media_active;
3151                 ifmr->ifm_status = mii->mii_media_status;
3152         }
3153 }
3154
3155 static int
3156 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3157 {
3158         struct bnx_softc *sc = ifp->if_softc;
3159         struct ifreq *ifr = (struct ifreq *)data;
3160         int mask, error = 0;
3161
3162         ASSERT_SERIALIZED(ifp->if_serializer);
3163
3164         switch (command) {
3165         case SIOCSIFMTU:
3166                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3167                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3168                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3169                         error = EINVAL;
3170                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3171                         ifp->if_mtu = ifr->ifr_mtu;
3172                         if (ifp->if_flags & IFF_RUNNING)
3173                                 bnx_init(sc);
3174                 }
3175                 break;
3176         case SIOCSIFFLAGS:
3177                 if (ifp->if_flags & IFF_UP) {
3178                         if (ifp->if_flags & IFF_RUNNING) {
3179                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3180
3181                                 /*
3182                                  * If only the state of the PROMISC flag
3183                                  * changed, then just use the 'set promisc
3184                                  * mode' command instead of reinitializing
3185                                  * the entire NIC. Doing a full re-init
3186                                  * means reloading the firmware and waiting
3187                                  * for it to start up, which may take a
3188                                  * second or two.  Similarly for ALLMULTI.
3189                                  */
3190                                 if (mask & IFF_PROMISC)
3191                                         bnx_setpromisc(sc);
3192                                 if (mask & IFF_ALLMULTI)
3193                                         bnx_setmulti(sc);
3194                         } else {
3195                                 bnx_init(sc);
3196                         }
3197                 } else if (ifp->if_flags & IFF_RUNNING) {
3198                         bnx_stop(sc);
3199                 }
3200                 sc->bnx_if_flags = ifp->if_flags;
3201                 break;
3202         case SIOCADDMULTI:
3203         case SIOCDELMULTI:
3204                 if (ifp->if_flags & IFF_RUNNING)
3205                         bnx_setmulti(sc);
3206                 break;
3207         case SIOCSIFMEDIA:
3208         case SIOCGIFMEDIA:
3209                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3210                         error = ifmedia_ioctl(ifp, ifr,
3211                             &sc->bnx_ifmedia, command);
3212                 } else {
3213                         struct mii_data *mii;
3214
3215                         mii = device_get_softc(sc->bnx_miibus);
3216                         error = ifmedia_ioctl(ifp, ifr,
3217                                               &mii->mii_media, command);
3218                 }
3219                 break;
3220         case SIOCSIFCAP:
3221                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3222                 if (mask & IFCAP_HWCSUM) {
3223                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3224                         if (IFCAP_HWCSUM & ifp->if_capenable)
3225                                 ifp->if_hwassist = BNX_CSUM_FEATURES;
3226                         else
3227                                 ifp->if_hwassist = 0;
3228                 }
3229                 break;
3230         default:
3231                 error = ether_ioctl(ifp, command, data);
3232                 break;
3233         }
3234         return error;
3235 }
3236
3237 static void
3238 bnx_watchdog(struct ifnet *ifp)
3239 {
3240         struct bnx_softc *sc = ifp->if_softc;
3241
3242         if_printf(ifp, "watchdog timeout -- resetting\n");
3243
3244         bnx_init(sc);
3245
3246         ifp->if_oerrors++;
3247
3248         if (!ifq_is_empty(&ifp->if_snd))
3249                 if_devstart(ifp);
3250 }
3251
3252 /*
3253  * Stop the adapter and free any mbufs allocated to the
3254  * RX and TX lists.
3255  */
3256 static void
3257 bnx_stop(struct bnx_softc *sc)
3258 {
3259         struct ifnet *ifp = &sc->arpcom.ac_if;
3260
3261         ASSERT_SERIALIZED(ifp->if_serializer);
3262
3263         callout_stop(&sc->bnx_stat_timer);
3264
3265         /*
3266          * Disable all of the receiver blocks
3267          */
3268         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3269         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3270         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3271         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3272         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3273         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3274
3275         /*
3276          * Disable all of the transmit blocks
3277          */
3278         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3279         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3280         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3281         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3282         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3283         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3284
3285         /*
3286          * Shut down all of the memory managers and related
3287          * state machines.
3288          */
3289         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3290         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3291         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3292         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3293
3294         /* Disable host interrupts. */
3295         bnx_disable_intr(sc);
3296
3297         /*
3298          * Tell firmware we're shutting down.
3299          */
3300         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3301
3302         /* Free the RX lists. */
3303         bnx_free_rx_ring_std(sc);
3304
3305         /* Free jumbo RX list. */
3306         if (BNX_IS_JUMBO_CAPABLE(sc))
3307                 bnx_free_rx_ring_jumbo(sc);
3308
3309         /* Free TX buffers. */
3310         bnx_free_tx_ring(sc);
3311
3312         sc->bnx_status_tag = 0;
3313         sc->bnx_link = 0;
3314         sc->bnx_coal_chg = 0;
3315
3316         sc->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
3317
3318         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3319         ifp->if_timer = 0;
3320 }
3321
3322 /*
3323  * Stop all chip I/O so that the kernel's probe routines don't
3324  * get confused by errant DMAs when rebooting.
3325  */
3326 static void
3327 bnx_shutdown(device_t dev)
3328 {
3329         struct bnx_softc *sc = device_get_softc(dev);
3330         struct ifnet *ifp = &sc->arpcom.ac_if;
3331
3332         lwkt_serialize_enter(ifp->if_serializer);
3333         bnx_stop(sc);
3334         bnx_reset(sc);
3335         lwkt_serialize_exit(ifp->if_serializer);
3336 }
3337
3338 static int
3339 bnx_suspend(device_t dev)
3340 {
3341         struct bnx_softc *sc = device_get_softc(dev);
3342         struct ifnet *ifp = &sc->arpcom.ac_if;
3343
3344         lwkt_serialize_enter(ifp->if_serializer);
3345         bnx_stop(sc);
3346         lwkt_serialize_exit(ifp->if_serializer);
3347
3348         return 0;
3349 }
3350
3351 static int
3352 bnx_resume(device_t dev)
3353 {
3354         struct bnx_softc *sc = device_get_softc(dev);
3355         struct ifnet *ifp = &sc->arpcom.ac_if;
3356
3357         lwkt_serialize_enter(ifp->if_serializer);
3358
3359         if (ifp->if_flags & IFF_UP) {
3360                 bnx_init(sc);
3361
3362                 if (!ifq_is_empty(&ifp->if_snd))
3363                         if_devstart(ifp);
3364         }
3365
3366         lwkt_serialize_exit(ifp->if_serializer);
3367
3368         return 0;
3369 }
3370
3371 static void
3372 bnx_setpromisc(struct bnx_softc *sc)
3373 {
3374         struct ifnet *ifp = &sc->arpcom.ac_if;
3375
3376         if (ifp->if_flags & IFF_PROMISC)
3377                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3378         else
3379                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3380 }
3381
3382 static void
3383 bnx_dma_free(struct bnx_softc *sc)
3384 {
3385         int i;
3386
3387         /* Destroy RX mbuf DMA stuffs. */
3388         if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3389                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3390                         bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3391                             sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3392                 }
3393                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3394                                    sc->bnx_cdata.bnx_rx_tmpmap);
3395                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3396         }
3397
3398         /* Destroy TX mbuf DMA stuffs. */
3399         if (sc->bnx_cdata.bnx_tx_mtag != NULL) {
3400                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3401                         bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3402                             sc->bnx_cdata.bnx_tx_dmamap[i]);
3403                 }
3404                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3405         }
3406
3407         /* Destroy standard RX ring */
3408         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3409                            sc->bnx_cdata.bnx_rx_std_ring_map,
3410                            sc->bnx_ldata.bnx_rx_std_ring);
3411
3412         if (BNX_IS_JUMBO_CAPABLE(sc))
3413                 bnx_free_jumbo_mem(sc);
3414
3415         /* Destroy RX return ring */
3416         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3417                            sc->bnx_cdata.bnx_rx_return_ring_map,
3418                            sc->bnx_ldata.bnx_rx_return_ring);
3419
3420         /* Destroy TX ring */
3421         bnx_dma_block_free(sc->bnx_cdata.bnx_tx_ring_tag,
3422                            sc->bnx_cdata.bnx_tx_ring_map,
3423                            sc->bnx_ldata.bnx_tx_ring);
3424
3425         /* Destroy status block */
3426         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3427                            sc->bnx_cdata.bnx_status_map,
3428                            sc->bnx_ldata.bnx_status_block);
3429
3430         /* Destroy the parent tag */
3431         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3432                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3433 }
3434
3435 static int
3436 bnx_dma_alloc(struct bnx_softc *sc)
3437 {
3438         struct ifnet *ifp = &sc->arpcom.ac_if;
3439         int i, error;
3440
3441         /*
3442          * Allocate the parent bus DMA tag appropriate for PCI.
3443          *
3444          * All of the NetExtreme/NetLink controllers have 4GB boundary
3445          * DMA bug.
3446          * Whenever an address crosses a multiple of the 4GB boundary
3447          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3448          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3449          * state machine will lockup and cause the device to hang.
3450          */
3451         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3452                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3453                                    NULL, NULL,
3454                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3455                                    BUS_SPACE_MAXSIZE_32BIT,
3456                                    0, &sc->bnx_cdata.bnx_parent_tag);
3457         if (error) {
3458                 if_printf(ifp, "could not allocate parent dma tag\n");
3459                 return error;
3460         }
3461
3462         /*
3463          * Create DMA tag and maps for RX mbufs.
3464          */
3465         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3466                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3467                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3468                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3469                                    &sc->bnx_cdata.bnx_rx_mtag);
3470         if (error) {
3471                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3472                 return error;
3473         }
3474
3475         error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3476                                   BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3477         if (error) {
3478                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3479                 sc->bnx_cdata.bnx_rx_mtag = NULL;
3480                 return error;
3481         }
3482
3483         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3484                 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3485                                           BUS_DMA_WAITOK,
3486                                           &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3487                 if (error) {
3488                         int j;
3489
3490                         for (j = 0; j < i; ++j) {
3491                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3492                                         sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3493                         }
3494                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3495                         sc->bnx_cdata.bnx_rx_mtag = NULL;
3496
3497                         if_printf(ifp, "could not create DMA map for RX\n");
3498                         return error;
3499                 }
3500         }
3501
3502         /*
3503          * Create DMA tag and maps for TX mbufs.
3504          */
3505         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3506                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3507                                    NULL, NULL,
3508                                    BNX_JUMBO_FRAMELEN, BNX_NSEG_NEW, MCLBYTES,
3509                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3510                                    BUS_DMA_ONEBPAGE,
3511                                    &sc->bnx_cdata.bnx_tx_mtag);
3512         if (error) {
3513                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3514                 return error;
3515         }
3516
3517         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3518                 error = bus_dmamap_create(sc->bnx_cdata.bnx_tx_mtag,
3519                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3520                                           &sc->bnx_cdata.bnx_tx_dmamap[i]);
3521                 if (error) {
3522                         int j;
3523
3524                         for (j = 0; j < i; ++j) {
3525                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3526                                         sc->bnx_cdata.bnx_tx_dmamap[j]);
3527                         }
3528                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3529                         sc->bnx_cdata.bnx_tx_mtag = NULL;
3530
3531                         if_printf(ifp, "could not create DMA map for TX\n");
3532                         return error;
3533                 }
3534         }
3535
3536         /*
3537          * Create DMA stuffs for standard RX ring.
3538          */
3539         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3540                                     &sc->bnx_cdata.bnx_rx_std_ring_tag,
3541                                     &sc->bnx_cdata.bnx_rx_std_ring_map,
3542                                     (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3543                                     &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3544         if (error) {
3545                 if_printf(ifp, "could not create std RX ring\n");
3546                 return error;
3547         }
3548
3549         /*
3550          * Create jumbo buffer pool.
3551          */
3552         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3553                 error = bnx_alloc_jumbo_mem(sc);
3554                 if (error) {
3555                         if_printf(ifp, "could not create jumbo buffer pool\n");
3556                         return error;
3557                 }
3558         }
3559
3560         /*
3561          * Create DMA stuffs for RX return ring.
3562          */
3563         error = bnx_dma_block_alloc(sc,
3564             BGE_RX_RTN_RING_SZ(sc->bnx_return_ring_cnt),
3565             &sc->bnx_cdata.bnx_rx_return_ring_tag,
3566             &sc->bnx_cdata.bnx_rx_return_ring_map,
3567             (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3568             &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3569         if (error) {
3570                 if_printf(ifp, "could not create RX ret ring\n");
3571                 return error;
3572         }
3573
3574         /*
3575          * Create DMA stuffs for TX ring.
3576          */
3577         error = bnx_dma_block_alloc(sc, BGE_TX_RING_SZ,
3578                                     &sc->bnx_cdata.bnx_tx_ring_tag,
3579                                     &sc->bnx_cdata.bnx_tx_ring_map,
3580                                     (void *)&sc->bnx_ldata.bnx_tx_ring,
3581                                     &sc->bnx_ldata.bnx_tx_ring_paddr);
3582         if (error) {
3583                 if_printf(ifp, "could not create TX ring\n");
3584                 return error;
3585         }
3586
3587         /*
3588          * Create DMA stuffs for status block.
3589          */
3590         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3591                                     &sc->bnx_cdata.bnx_status_tag,
3592                                     &sc->bnx_cdata.bnx_status_map,
3593                                     (void *)&sc->bnx_ldata.bnx_status_block,
3594                                     &sc->bnx_ldata.bnx_status_block_paddr);
3595         if (error) {
3596                 if_printf(ifp, "could not create status block\n");
3597                 return error;
3598         }
3599
3600         return 0;
3601 }
3602
3603 static int
3604 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3605                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3606 {
3607         bus_dmamem_t dmem;
3608         int error;
3609
3610         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3611                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3612                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3613         if (error)
3614                 return error;
3615
3616         *tag = dmem.dmem_tag;
3617         *map = dmem.dmem_map;
3618         *addr = dmem.dmem_addr;
3619         *paddr = dmem.dmem_busaddr;
3620
3621         return 0;
3622 }
3623
3624 static void
3625 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3626 {
3627         if (tag != NULL) {
3628                 bus_dmamap_unload(tag, map);
3629                 bus_dmamem_free(tag, addr, map);
3630                 bus_dma_tag_destroy(tag);
3631         }
3632 }
3633
3634 static void
3635 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3636 {
3637         struct ifnet *ifp = &sc->arpcom.ac_if;
3638
3639 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3640
3641         /*
3642          * Sometimes PCS encoding errors are detected in
3643          * TBI mode (on fiber NICs), and for some reason
3644          * the chip will signal them as link changes.
3645          * If we get a link change event, but the 'PCS
3646          * encoding error' bit in the MAC status register
3647          * is set, don't bother doing a link check.
3648          * This avoids spurious "gigabit link up" messages
3649          * that sometimes appear on fiber NICs during
3650          * periods of heavy traffic.
3651          */
3652         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3653                 if (!sc->bnx_link) {
3654                         sc->bnx_link++;
3655                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3656                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3657                                     BGE_MACMODE_TBI_SEND_CFGS);
3658                         }
3659                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3660
3661                         if (bootverbose)
3662                                 if_printf(ifp, "link UP\n");
3663
3664                         ifp->if_link_state = LINK_STATE_UP;
3665                         if_link_state_change(ifp);
3666                 }
3667         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3668                 if (sc->bnx_link) {
3669                         sc->bnx_link = 0;
3670
3671                         if (bootverbose)
3672                                 if_printf(ifp, "link DOWN\n");
3673
3674                         ifp->if_link_state = LINK_STATE_DOWN;
3675                         if_link_state_change(ifp);
3676                 }
3677         }
3678
3679 #undef PCS_ENCODE_ERR
3680
3681         /* Clear the attention. */
3682         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3683             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3684             BGE_MACSTAT_LINK_CHANGED);
3685 }
3686
3687 static void
3688 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3689 {
3690         struct ifnet *ifp = &sc->arpcom.ac_if;
3691         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3692
3693         mii_pollstat(mii);
3694         bnx_miibus_statchg(sc->bnx_dev);
3695
3696         if (bootverbose) {
3697                 if (sc->bnx_link)
3698                         if_printf(ifp, "link UP\n");
3699                 else
3700                         if_printf(ifp, "link DOWN\n");
3701         }
3702
3703         /* Clear the attention. */
3704         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3705             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3706             BGE_MACSTAT_LINK_CHANGED);
3707 }
3708
3709 static void
3710 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3711 {
3712         struct ifnet *ifp = &sc->arpcom.ac_if;
3713         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3714
3715         mii_pollstat(mii);
3716
3717         if (!sc->bnx_link &&
3718             (mii->mii_media_status & IFM_ACTIVE) &&
3719             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3720                 sc->bnx_link++;
3721                 if (bootverbose)
3722                         if_printf(ifp, "link UP\n");
3723         } else if (sc->bnx_link &&
3724             (!(mii->mii_media_status & IFM_ACTIVE) ||
3725             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3726                 sc->bnx_link = 0;
3727                 if (bootverbose)
3728                         if_printf(ifp, "link DOWN\n");
3729         }
3730
3731         /* Clear the attention. */
3732         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3733             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3734             BGE_MACSTAT_LINK_CHANGED);
3735 }
3736
3737 static int
3738 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3739 {
3740         struct bnx_softc *sc = arg1;
3741
3742         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3743             &sc->bnx_rx_coal_ticks,
3744             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3745             BNX_RX_COAL_TICKS_CHG);
3746 }
3747
3748 static int
3749 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3750 {
3751         struct bnx_softc *sc = arg1;
3752
3753         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3754             &sc->bnx_tx_coal_ticks,
3755             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3756             BNX_TX_COAL_TICKS_CHG);
3757 }
3758
3759 static int
3760 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3761 {
3762         struct bnx_softc *sc = arg1;
3763
3764         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3765             &sc->bnx_rx_coal_bds,
3766             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3767             BNX_RX_COAL_BDS_CHG);
3768 }
3769
3770 static int
3771 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3772 {
3773         struct bnx_softc *sc = arg1;
3774
3775         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3776             &sc->bnx_tx_coal_bds,
3777             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3778             BNX_TX_COAL_BDS_CHG);
3779 }
3780
3781 static int
3782 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3783 {
3784         struct bnx_softc *sc = arg1;
3785
3786         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3787             &sc->bnx_rx_coal_bds_int,
3788             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3789             BNX_RX_COAL_BDS_INT_CHG);
3790 }
3791
3792 static int
3793 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3794 {
3795         struct bnx_softc *sc = arg1;
3796
3797         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3798             &sc->bnx_tx_coal_bds_int,
3799             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3800             BNX_TX_COAL_BDS_INT_CHG);
3801 }
3802
3803 static int
3804 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3805     int coal_min, int coal_max, uint32_t coal_chg_mask)
3806 {
3807         struct bnx_softc *sc = arg1;
3808         struct ifnet *ifp = &sc->arpcom.ac_if;
3809         int error = 0, v;
3810
3811         lwkt_serialize_enter(ifp->if_serializer);
3812
3813         v = *coal;
3814         error = sysctl_handle_int(oidp, &v, 0, req);
3815         if (!error && req->newptr != NULL) {
3816                 if (v < coal_min || v > coal_max) {
3817                         error = EINVAL;
3818                 } else {
3819                         *coal = v;
3820                         sc->bnx_coal_chg |= coal_chg_mask;
3821                 }
3822         }
3823
3824         lwkt_serialize_exit(ifp->if_serializer);
3825         return error;
3826 }
3827
3828 static void
3829 bnx_coal_change(struct bnx_softc *sc)
3830 {
3831         struct ifnet *ifp = &sc->arpcom.ac_if;
3832         uint32_t val;
3833
3834         ASSERT_SERIALIZED(ifp->if_serializer);
3835
3836         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3837                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3838                             sc->bnx_rx_coal_ticks);
3839                 DELAY(10);
3840                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3841
3842                 if (bootverbose) {
3843                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3844                                   sc->bnx_rx_coal_ticks);
3845                 }
3846         }
3847
3848         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3849                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3850                             sc->bnx_tx_coal_ticks);
3851                 DELAY(10);
3852                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3853
3854                 if (bootverbose) {
3855                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3856                                   sc->bnx_tx_coal_ticks);
3857                 }
3858         }
3859
3860         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3861                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3862                             sc->bnx_rx_coal_bds);
3863                 DELAY(10);
3864                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3865
3866                 if (bootverbose) {
3867                         if_printf(ifp, "rx_coal_bds -> %u\n",
3868                                   sc->bnx_rx_coal_bds);
3869                 }
3870         }
3871
3872         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3873                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3874                             sc->bnx_tx_coal_bds);
3875                 DELAY(10);
3876                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3877
3878                 if (bootverbose) {
3879                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3880                                   sc->bnx_tx_coal_bds);
3881                 }
3882         }
3883
3884         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3885                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3886                     sc->bnx_rx_coal_bds_int);
3887                 DELAY(10);
3888                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3889
3890                 if (bootverbose) {
3891                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
3892                             sc->bnx_rx_coal_bds_int);
3893                 }
3894         }
3895
3896         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3897                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3898                     sc->bnx_tx_coal_bds_int);
3899                 DELAY(10);
3900                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3901
3902                 if (bootverbose) {
3903                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
3904                             sc->bnx_tx_coal_bds_int);
3905                 }
3906         }
3907
3908         sc->bnx_coal_chg = 0;
3909 }
3910
3911 static void
3912 bnx_enable_intr(struct bnx_softc *sc)
3913 {
3914         struct ifnet *ifp = &sc->arpcom.ac_if;
3915
3916         lwkt_serialize_handler_enable(ifp->if_serializer);
3917
3918         /*
3919          * Enable interrupt.
3920          */
3921         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3922         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3923                 /* XXX Linux driver */
3924                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3925         }
3926
3927         /*
3928          * Unmask the interrupt when we stop polling.
3929          */
3930         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3931             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3932
3933         /*
3934          * Trigger another interrupt, since above writing
3935          * to interrupt mailbox0 may acknowledge pending
3936          * interrupt.
3937          */
3938         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3939 }
3940
3941 static void
3942 bnx_disable_intr(struct bnx_softc *sc)
3943 {
3944         struct ifnet *ifp = &sc->arpcom.ac_if;
3945
3946         /*
3947          * Mask the interrupt when we start polling.
3948          */
3949         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3950             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3951
3952         /*
3953          * Acknowledge possible asserted interrupt.
3954          */
3955         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3956
3957         lwkt_serialize_handler_disable(ifp->if_serializer);
3958 }
3959
3960 static int
3961 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
3962 {
3963         uint32_t mac_addr;
3964         int ret = 1;
3965
3966         mac_addr = bnx_readmem_ind(sc, 0x0c14);
3967         if ((mac_addr >> 16) == 0x484b) {
3968                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3969                 ether_addr[1] = (uint8_t)mac_addr;
3970                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
3971                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3972                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3973                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3974                 ether_addr[5] = (uint8_t)mac_addr;
3975                 ret = 0;
3976         }
3977         return ret;
3978 }
3979
3980 static int
3981 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
3982 {
3983         int mac_offset = BGE_EE_MAC_OFFSET;
3984
3985         if (BNX_IS_5717_PLUS(sc)) {
3986                 int f;
3987
3988                 f = pci_get_function(sc->bnx_dev);
3989                 if (f & 1)
3990                         mac_offset = BGE_EE_MAC_OFFSET_5717;
3991                 if (f > 1)
3992                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
3993         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
3994                 mac_offset = BGE_EE_MAC_OFFSET_5906;
3995         }
3996
3997         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
3998 }
3999
4000 static int
4001 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4002 {
4003         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4004                 return 1;
4005
4006         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4007                                ETHER_ADDR_LEN);
4008 }
4009
4010 static int
4011 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4012 {
4013         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4014                 /* NOTE: Order is critical */
4015                 bnx_get_eaddr_mem,
4016                 bnx_get_eaddr_nvram,
4017                 bnx_get_eaddr_eeprom,
4018                 NULL
4019         };
4020         const bnx_eaddr_fcn_t *func;
4021
4022         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4023                 if ((*func)(sc, eaddr) == 0)
4024                         break;
4025         }
4026         return (*func == NULL ? ENXIO : 0);
4027 }
4028
4029 /*
4030  * NOTE: 'm' is not freed upon failure
4031  */
4032 struct mbuf *
4033 bnx_defrag_shortdma(struct mbuf *m)
4034 {
4035         struct mbuf *n;
4036         int found;
4037
4038         /*
4039          * If device receive two back-to-back send BDs with less than
4040          * or equal to 8 total bytes then the device may hang.  The two
4041          * back-to-back send BDs must in the same frame for this failure
4042          * to occur.  Scan mbuf chains and see whether two back-to-back
4043          * send BDs are there.  If this is the case, allocate new mbuf
4044          * and copy the frame to workaround the silicon bug.
4045          */
4046         for (n = m, found = 0; n != NULL; n = n->m_next) {
4047                 if (n->m_len < 8) {
4048                         found++;
4049                         if (found > 1)
4050                                 break;
4051                         continue;
4052                 }
4053                 found = 0;
4054         }
4055
4056         if (found > 1)
4057                 n = m_defrag(m, MB_DONTWAIT);
4058         else
4059                 n = m;
4060         return n;
4061 }
4062
4063 static void
4064 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4065 {
4066         int i;
4067
4068         BNX_CLRBIT(sc, reg, bit);
4069         for (i = 0; i < BNX_TIMEOUT; i++) {
4070                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4071                         return;
4072                 DELAY(100);
4073         }
4074 }
4075
4076 static void
4077 bnx_link_poll(struct bnx_softc *sc)
4078 {
4079         uint32_t status;
4080
4081         status = CSR_READ_4(sc, BGE_MAC_STS);
4082         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4083                 sc->bnx_link_evt = 0;
4084                 sc->bnx_link_upd(sc, status);
4085         }
4086 }
4087
4088 static void
4089 bnx_enable_msi(struct bnx_softc *sc)
4090 {
4091         uint32_t msi_mode;
4092
4093         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4094         msi_mode |= BGE_MSIMODE_ENABLE;
4095         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4096                 /*
4097                  * NOTE:
4098                  * 5718-PG105-R says that "one shot" mode
4099                  * does not work if MSI is used, however,
4100                  * it obviously works.
4101                  */
4102                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4103         }
4104         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4105 }
4106
4107 static uint32_t
4108 bnx_dma_swap_options(struct bnx_softc *sc)
4109 {
4110         uint32_t dma_options;
4111
4112         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4113             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4114 #if BYTE_ORDER == BIG_ENDIAN
4115         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4116 #endif
4117         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
4118                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4119                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4120                     BGE_MODECTL_HTX2B_ENABLE;
4121         }
4122         return dma_options;
4123 }