| 1 | /* |
| 2 | * Copyright (c) 2005 The DragonFly Project. All rights reserved. |
| 3 | * Copyright (c) 1991 The Regents of the University of California. |
| 4 | * All rights reserved. |
| 5 | * |
| 6 | * This code is derived from software contributed to The DragonFly Project |
| 7 | * by Matthew Dillon <dillon@backplane.com> |
| 8 | * |
| 9 | * This code is derived from software contributed to Berkeley by |
| 10 | * William Jolitz. |
| 11 | * |
| 12 | * Redistribution and use in source and binary forms, with or without |
| 13 | * modification, are permitted provided that the following conditions |
| 14 | * are met: |
| 15 | * |
| 16 | * 1. Redistributions of source code must retain the above copyright |
| 17 | * notice, this list of conditions and the following disclaimer. |
| 18 | * 2. Redistributions in binary form must reproduce the above copyright |
| 19 | * notice, this list of conditions and the following disclaimer in |
| 20 | * the documentation and/or other materials provided with the |
| 21 | * distribution. |
| 22 | * 3. Neither the name of The DragonFly Project nor the names of its |
| 23 | * contributors may be used to endorse or promote products derived |
| 24 | * from this software without specific, prior written permission. |
| 25 | * |
| 26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 27 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 28 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 29 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 30 | * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 31 | * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 32 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 33 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 34 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 35 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 36 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 37 | * SUCH DAMAGE. |
| 38 | * |
| 39 | * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $ |
| 40 | */ |
| 41 | |
| 42 | #include <sys/param.h> |
| 43 | #include <sys/systm.h> |
| 44 | #include <sys/kernel.h> |
| 45 | #include <sys/machintr.h> |
| 46 | #include <sys/interrupt.h> |
| 47 | #include <sys/rman.h> |
| 48 | #include <sys/bus.h> |
| 49 | |
| 50 | #include <machine/segments.h> |
| 51 | #include <machine/md_var.h> |
| 52 | #include <machine/intr_machdep.h> |
| 53 | #include <machine/globaldata.h> |
| 54 | #include <machine/smp.h> |
| 55 | #include <machine/msi_var.h> |
| 56 | |
| 57 | #include <sys/thread2.h> |
| 58 | |
| 59 | #include <machine_base/icu/elcr_var.h> |
| 60 | |
| 61 | #include <machine_base/icu/icu.h> |
| 62 | #include <machine_base/icu/icu_ipl.h> |
| 63 | #include <machine_base/apic/ioapic.h> |
| 64 | |
| 65 | extern inthand_t |
| 66 | IDTVEC(icu_intr0), IDTVEC(icu_intr1), |
| 67 | IDTVEC(icu_intr2), IDTVEC(icu_intr3), |
| 68 | IDTVEC(icu_intr4), IDTVEC(icu_intr5), |
| 69 | IDTVEC(icu_intr6), IDTVEC(icu_intr7), |
| 70 | IDTVEC(icu_intr8), IDTVEC(icu_intr9), |
| 71 | IDTVEC(icu_intr10), IDTVEC(icu_intr11), |
| 72 | IDTVEC(icu_intr12), IDTVEC(icu_intr13), |
| 73 | IDTVEC(icu_intr14), IDTVEC(icu_intr15); |
| 74 | |
| 75 | static inthand_t *icu_intr[ICU_HWI_VECTORS] = { |
| 76 | &IDTVEC(icu_intr0), &IDTVEC(icu_intr1), |
| 77 | &IDTVEC(icu_intr2), &IDTVEC(icu_intr3), |
| 78 | &IDTVEC(icu_intr4), &IDTVEC(icu_intr5), |
| 79 | &IDTVEC(icu_intr6), &IDTVEC(icu_intr7), |
| 80 | &IDTVEC(icu_intr8), &IDTVEC(icu_intr9), |
| 81 | &IDTVEC(icu_intr10), &IDTVEC(icu_intr11), |
| 82 | &IDTVEC(icu_intr12), &IDTVEC(icu_intr13), |
| 83 | &IDTVEC(icu_intr14), &IDTVEC(icu_intr15) |
| 84 | }; |
| 85 | |
| 86 | static struct icu_irqmap { |
| 87 | int im_type; /* ICU_IMT_ */ |
| 88 | enum intr_trigger im_trig; |
| 89 | int im_msi_base; |
| 90 | } icu_irqmaps[MAXCPU][IDT_HWI_VECTORS]; |
| 91 | |
| 92 | static struct lwkt_token icu_irqmap_tok = |
| 93 | LWKT_TOKEN_INITIALIZER(icu_irqmap_token); |
| 94 | |
| 95 | #define ICU_IMT_UNUSED 0 /* KEEP THIS */ |
| 96 | #define ICU_IMT_RESERVED 1 |
| 97 | #define ICU_IMT_LEGACY 2 |
| 98 | #define ICU_IMT_SYSCALL 3 |
| 99 | #define ICU_IMT_SHADOW 4 |
| 100 | #define ICU_IMT_MSI 5 |
| 101 | |
| 102 | #define ICU_IMT_ISHWI(map) ((map)->im_type != ICU_IMT_RESERVED && \ |
| 103 | (map)->im_type != ICU_IMT_SYSCALL && \ |
| 104 | (map)->im_type != ICU_IMT_SHADOW) |
| 105 | |
| 106 | extern void ICU_INTREN(int); |
| 107 | extern void ICU_INTRDIS(int); |
| 108 | |
| 109 | extern int imcr_present; |
| 110 | |
| 111 | static void icu_abi_intr_enable(int); |
| 112 | static void icu_abi_intr_disable(int); |
| 113 | static void icu_abi_intr_setup(int, int); |
| 114 | static void icu_abi_intr_teardown(int); |
| 115 | static void icu_abi_intr_config(int, enum intr_trigger, enum intr_polarity); |
| 116 | static int icu_abi_intr_cpuid(int); |
| 117 | |
| 118 | static int icu_abi_msi_alloc(int [], int, int); |
| 119 | static void icu_abi_msi_release(const int [], int, int); |
| 120 | static void icu_abi_msi_map(int, uint64_t *, uint32_t *, int); |
| 121 | |
| 122 | static void icu_abi_finalize(void); |
| 123 | static void icu_abi_cleanup(void); |
| 124 | static void icu_abi_setdefault(void); |
| 125 | static void icu_abi_stabilize(void); |
| 126 | static void icu_abi_initmap(void); |
| 127 | static void icu_abi_rman_setup(struct rman *); |
| 128 | |
| 129 | struct machintr_abi MachIntrABI_ICU = { |
| 130 | MACHINTR_ICU, |
| 131 | .intr_disable = icu_abi_intr_disable, |
| 132 | .intr_enable = icu_abi_intr_enable, |
| 133 | .intr_setup = icu_abi_intr_setup, |
| 134 | .intr_teardown = icu_abi_intr_teardown, |
| 135 | .intr_config = icu_abi_intr_config, |
| 136 | .intr_cpuid = icu_abi_intr_cpuid, |
| 137 | |
| 138 | .msi_alloc = icu_abi_msi_alloc, |
| 139 | .msi_release = icu_abi_msi_release, |
| 140 | .msi_map = icu_abi_msi_map, |
| 141 | |
| 142 | .finalize = icu_abi_finalize, |
| 143 | .cleanup = icu_abi_cleanup, |
| 144 | .setdefault = icu_abi_setdefault, |
| 145 | .stabilize = icu_abi_stabilize, |
| 146 | .initmap = icu_abi_initmap, |
| 147 | .rman_setup = icu_abi_rman_setup |
| 148 | }; |
| 149 | |
| 150 | static int icu_abi_msi_start; /* NOTE: for testing only */ |
| 151 | |
| 152 | /* |
| 153 | * WARNING! SMP builds can use the ICU now so this code must be MP safe. |
| 154 | */ |
| 155 | |
| 156 | static void |
| 157 | icu_abi_intr_enable(int irq) |
| 158 | { |
| 159 | const struct icu_irqmap *map; |
| 160 | |
| 161 | KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS, |
| 162 | ("icu enable, invalid irq %d\n", irq)); |
| 163 | |
| 164 | map = &icu_irqmaps[mycpuid][irq]; |
| 165 | KASSERT(ICU_IMT_ISHWI(map), |
| 166 | ("icu enable, not hwi irq %d, type %d, cpu%d\n", |
| 167 | irq, map->im_type, mycpuid)); |
| 168 | if (map->im_type != ICU_IMT_LEGACY) |
| 169 | return; |
| 170 | |
| 171 | ICU_INTREN(irq); |
| 172 | } |
| 173 | |
| 174 | static void |
| 175 | icu_abi_intr_disable(int irq) |
| 176 | { |
| 177 | const struct icu_irqmap *map; |
| 178 | |
| 179 | KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS, |
| 180 | ("icu disable, invalid irq %d\n", irq)); |
| 181 | |
| 182 | map = &icu_irqmaps[mycpuid][irq]; |
| 183 | KASSERT(ICU_IMT_ISHWI(map), |
| 184 | ("icu disable, not hwi irq %d, type %d, cpu%d\n", |
| 185 | irq, map->im_type, mycpuid)); |
| 186 | if (map->im_type != ICU_IMT_LEGACY) |
| 187 | return; |
| 188 | |
| 189 | ICU_INTRDIS(irq); |
| 190 | } |
| 191 | |
| 192 | /* |
| 193 | * Called before interrupts are physically enabled |
| 194 | */ |
| 195 | static void |
| 196 | icu_abi_stabilize(void) |
| 197 | { |
| 198 | int intr; |
| 199 | |
| 200 | for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) |
| 201 | ICU_INTRDIS(intr); |
| 202 | ICU_INTREN(ICU_IRQ_SLAVE); |
| 203 | } |
| 204 | |
| 205 | /* |
| 206 | * Called after interrupts physically enabled but before the |
| 207 | * critical section is released. |
| 208 | */ |
| 209 | static void |
| 210 | icu_abi_cleanup(void) |
| 211 | { |
| 212 | bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending)); |
| 213 | } |
| 214 | |
| 215 | /* |
| 216 | * Called after stablize and cleanup; critical section is not |
| 217 | * held and interrupts are not physically disabled. |
| 218 | */ |
| 219 | static void |
| 220 | icu_abi_finalize(void) |
| 221 | { |
| 222 | KKASSERT(MachIntrABI.type == MACHINTR_ICU); |
| 223 | KKASSERT(!ioapic_enable); |
| 224 | |
| 225 | /* |
| 226 | * If an IMCR is present, programming bit 0 disconnects the 8259 |
| 227 | * from the BSP. The 8259 may still be connected to LINT0 on the |
| 228 | * BSP's LAPIC. |
| 229 | * |
| 230 | * If we are running SMP the LAPIC is active, try to use virtual |
| 231 | * wire mode so we can use other interrupt sources within the LAPIC |
| 232 | * in addition to the 8259. |
| 233 | */ |
| 234 | if (imcr_present) { |
| 235 | outb(0x22, 0x70); |
| 236 | outb(0x23, 0x01); |
| 237 | } |
| 238 | } |
| 239 | |
| 240 | static void |
| 241 | icu_abi_intr_setup(int intr, int flags __unused) |
| 242 | { |
| 243 | const struct icu_irqmap *map; |
| 244 | u_long ef; |
| 245 | |
| 246 | KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, |
| 247 | ("icu setup, invalid irq %d\n", intr)); |
| 248 | |
| 249 | map = &icu_irqmaps[mycpuid][intr]; |
| 250 | KASSERT(ICU_IMT_ISHWI(map), |
| 251 | ("icu setup, not hwi irq %d, type %d, cpu%d\n", |
| 252 | intr, map->im_type, mycpuid)); |
| 253 | if (map->im_type != ICU_IMT_LEGACY) |
| 254 | return; |
| 255 | |
| 256 | ef = read_eflags(); |
| 257 | cpu_disable_intr(); |
| 258 | |
| 259 | ICU_INTREN(intr); |
| 260 | |
| 261 | write_eflags(ef); |
| 262 | } |
| 263 | |
| 264 | static void |
| 265 | icu_abi_intr_teardown(int intr) |
| 266 | { |
| 267 | const struct icu_irqmap *map; |
| 268 | u_long ef; |
| 269 | |
| 270 | KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, |
| 271 | ("icu teardown, invalid irq %d\n", intr)); |
| 272 | |
| 273 | map = &icu_irqmaps[mycpuid][intr]; |
| 274 | KASSERT(ICU_IMT_ISHWI(map), |
| 275 | ("icu teardown, not hwi irq %d, type %d, cpu%d\n", |
| 276 | intr, map->im_type, mycpuid)); |
| 277 | if (map->im_type != ICU_IMT_LEGACY) |
| 278 | return; |
| 279 | |
| 280 | ef = read_eflags(); |
| 281 | cpu_disable_intr(); |
| 282 | |
| 283 | ICU_INTRDIS(intr); |
| 284 | |
| 285 | write_eflags(ef); |
| 286 | } |
| 287 | |
| 288 | static void |
| 289 | icu_abi_setdefault(void) |
| 290 | { |
| 291 | int intr; |
| 292 | |
| 293 | for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) { |
| 294 | if (intr == ICU_IRQ_SLAVE) |
| 295 | continue; |
| 296 | setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT, |
| 297 | SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); |
| 298 | } |
| 299 | } |
| 300 | |
| 301 | static void |
| 302 | icu_abi_initmap(void) |
| 303 | { |
| 304 | int cpu; |
| 305 | |
| 306 | kgetenv_int("hw.icu.msi_start", &icu_abi_msi_start); |
| 307 | icu_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */ |
| 308 | |
| 309 | /* |
| 310 | * NOTE: ncpus is not ready yet |
| 311 | */ |
| 312 | for (cpu = 0; cpu < MAXCPU; ++cpu) { |
| 313 | int i; |
| 314 | |
| 315 | if (cpu != 0) { |
| 316 | for (i = 0; i < ICU_HWI_VECTORS; ++i) |
| 317 | icu_irqmaps[cpu][i].im_type = ICU_IMT_RESERVED; |
| 318 | } else { |
| 319 | for (i = 0; i < ICU_HWI_VECTORS; ++i) |
| 320 | icu_irqmaps[cpu][i].im_type = ICU_IMT_LEGACY; |
| 321 | icu_irqmaps[cpu][ICU_IRQ_SLAVE].im_type = |
| 322 | ICU_IMT_RESERVED; |
| 323 | |
| 324 | if (elcr_found) { |
| 325 | for (i = 0; i < ICU_HWI_VECTORS; ++i) { |
| 326 | icu_irqmaps[cpu][i].im_trig = |
| 327 | elcr_read_trigger(i); |
| 328 | } |
| 329 | } else { |
| 330 | /* |
| 331 | * NOTE: Trigger mode does not matter at all |
| 332 | */ |
| 333 | for (i = 0; i < ICU_HWI_VECTORS; ++i) { |
| 334 | icu_irqmaps[cpu][i].im_trig = |
| 335 | INTR_TRIGGER_EDGE; |
| 336 | } |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | for (i = 0; i < IDT_HWI_VECTORS; ++i) |
| 341 | icu_irqmaps[cpu][i].im_msi_base = -1; |
| 342 | |
| 343 | icu_irqmaps[cpu][IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = |
| 344 | ICU_IMT_SYSCALL; |
| 345 | } |
| 346 | } |
| 347 | |
| 348 | static void |
| 349 | icu_abi_intr_config(int irq, enum intr_trigger trig, |
| 350 | enum intr_polarity pola __unused) |
| 351 | { |
| 352 | struct icu_irqmap *map; |
| 353 | |
| 354 | KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL); |
| 355 | |
| 356 | KKASSERT(irq >= 0 && irq < IDT_HWI_VECTORS); |
| 357 | map = &icu_irqmaps[0][irq]; |
| 358 | |
| 359 | KKASSERT(map->im_type == ICU_IMT_LEGACY); |
| 360 | |
| 361 | /* TODO: Check whether it is configured or not */ |
| 362 | |
| 363 | if (trig == map->im_trig) |
| 364 | return; |
| 365 | |
| 366 | if (bootverbose) { |
| 367 | kprintf("ICU: irq %d, %s -> %s\n", irq, |
| 368 | intr_str_trigger(map->im_trig), |
| 369 | intr_str_trigger(trig)); |
| 370 | } |
| 371 | map->im_trig = trig; |
| 372 | |
| 373 | if (!elcr_found) { |
| 374 | if (bootverbose) |
| 375 | kprintf("ICU: no ELCR, skip irq %d config\n", irq); |
| 376 | return; |
| 377 | } |
| 378 | elcr_write_trigger(irq, map->im_trig); |
| 379 | } |
| 380 | |
| 381 | static int |
| 382 | icu_abi_intr_cpuid(int irq __unused) |
| 383 | { |
| 384 | return 0; |
| 385 | } |
| 386 | |
| 387 | static void |
| 388 | icu_abi_rman_setup(struct rman *rm) |
| 389 | { |
| 390 | int start, end, i; |
| 391 | |
| 392 | KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU, |
| 393 | ("invalid rman cpuid %d", rm->rm_cpuid)); |
| 394 | |
| 395 | start = end = -1; |
| 396 | for (i = 0; i < IDT_HWI_VECTORS; ++i) { |
| 397 | const struct icu_irqmap *map = &icu_irqmaps[rm->rm_cpuid][i]; |
| 398 | |
| 399 | if (start < 0) { |
| 400 | if (ICU_IMT_ISHWI(map)) |
| 401 | start = end = i; |
| 402 | } else { |
| 403 | if (ICU_IMT_ISHWI(map)) { |
| 404 | end = i; |
| 405 | } else { |
| 406 | KKASSERT(end >= 0); |
| 407 | if (bootverbose) { |
| 408 | kprintf("ICU: rman cpu%d %d - %d\n", |
| 409 | rm->rm_cpuid, start, end); |
| 410 | } |
| 411 | if (rman_manage_region(rm, start, end)) { |
| 412 | panic("rman_manage_region" |
| 413 | "(cpu%d %d - %d)", rm->rm_cpuid, |
| 414 | start, end); |
| 415 | } |
| 416 | start = end = -1; |
| 417 | } |
| 418 | } |
| 419 | } |
| 420 | if (start >= 0) { |
| 421 | KKASSERT(end >= 0); |
| 422 | if (bootverbose) { |
| 423 | kprintf("ICU: rman cpu%d %d - %d\n", |
| 424 | rm->rm_cpuid, start, end); |
| 425 | } |
| 426 | if (rman_manage_region(rm, start, end)) { |
| 427 | panic("rman_manage_region(cpu%d %d - %d)", |
| 428 | rm->rm_cpuid, start, end); |
| 429 | } |
| 430 | } |
| 431 | } |
| 432 | |
| 433 | static int |
| 434 | icu_abi_msi_alloc(int intrs[], int count, int cpuid) |
| 435 | { |
| 436 | int i, error; |
| 437 | |
| 438 | KASSERT(cpuid >= 0 && cpuid < ncpus, |
| 439 | ("invalid cpuid %d", cpuid)); |
| 440 | |
| 441 | KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count)); |
| 442 | KASSERT((count & (count - 1)) == 0, |
| 443 | ("count %d is not power of 2\n", count)); |
| 444 | |
| 445 | lwkt_gettoken(&icu_irqmap_tok); |
| 446 | |
| 447 | /* |
| 448 | * NOTE: |
| 449 | * Since IDT_OFFSET is 32, which is the maximum valid 'count', |
| 450 | * we do not need to find out the first properly aligned |
| 451 | * interrupt vector. |
| 452 | */ |
| 453 | |
| 454 | error = EMSGSIZE; |
| 455 | for (i = icu_abi_msi_start; i < IDT_HWI_VECTORS; i += count) { |
| 456 | int j; |
| 457 | |
| 458 | if (icu_irqmaps[cpuid][i].im_type != ICU_IMT_UNUSED) |
| 459 | continue; |
| 460 | |
| 461 | for (j = 1; j < count; ++j) { |
| 462 | if (icu_irqmaps[cpuid][i + j].im_type != ICU_IMT_UNUSED) |
| 463 | break; |
| 464 | } |
| 465 | if (j != count) |
| 466 | continue; |
| 467 | |
| 468 | for (j = 0; j < count; ++j) { |
| 469 | int intr = i + j, cpu; |
| 470 | |
| 471 | for (cpu = 0; cpu < ncpus; ++cpu) { |
| 472 | struct icu_irqmap *map; |
| 473 | |
| 474 | map = &icu_irqmaps[cpu][intr]; |
| 475 | KASSERT(map->im_msi_base < 0, |
| 476 | ("intr %d cpu%d, stale MSI-base %d\n", |
| 477 | intr, cpu, map->im_msi_base)); |
| 478 | KASSERT(map->im_type == ICU_IMT_UNUSED, |
| 479 | ("intr %d cpu%d, already allocated\n", |
| 480 | intr, cpu)); |
| 481 | |
| 482 | if (cpu == cpuid) { |
| 483 | map->im_type = ICU_IMT_MSI; |
| 484 | map->im_msi_base = i; |
| 485 | } else { |
| 486 | map->im_type = ICU_IMT_SHADOW; |
| 487 | } |
| 488 | } |
| 489 | |
| 490 | intrs[j] = intr; |
| 491 | msi_setup(intr); |
| 492 | |
| 493 | if (bootverbose) { |
| 494 | kprintf("alloc MSI intr %d on cpu%d\n", |
| 495 | intr, cpuid); |
| 496 | } |
| 497 | } |
| 498 | error = 0; |
| 499 | break; |
| 500 | } |
| 501 | |
| 502 | lwkt_reltoken(&icu_irqmap_tok); |
| 503 | |
| 504 | return error; |
| 505 | } |
| 506 | |
| 507 | static void |
| 508 | icu_abi_msi_release(const int intrs[], int count, int cpuid) |
| 509 | { |
| 510 | int i, msi_base = -1, intr_next = -1, mask; |
| 511 | |
| 512 | KASSERT(cpuid >= 0 && cpuid < ncpus, |
| 513 | ("invalid cpuid %d", cpuid)); |
| 514 | |
| 515 | KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count)); |
| 516 | |
| 517 | mask = count - 1; |
| 518 | KASSERT((count & mask) == 0, ("count %d is not power of 2\n", count)); |
| 519 | |
| 520 | lwkt_gettoken(&icu_irqmap_tok); |
| 521 | |
| 522 | for (i = 0; i < count; ++i) { |
| 523 | int intr = intrs[i], cpu; |
| 524 | |
| 525 | KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, |
| 526 | ("invalid intr %d\n", intr)); |
| 527 | |
| 528 | for (cpu = 0; cpu < ncpus; ++cpu) { |
| 529 | struct icu_irqmap *map; |
| 530 | |
| 531 | map = &icu_irqmaps[cpu][intr]; |
| 532 | |
| 533 | if (cpu == cpuid) { |
| 534 | KASSERT(map->im_type == ICU_IMT_MSI, |
| 535 | ("try release non-MSI intr %d cpu%d, " |
| 536 | "type %d\n", intr, cpu, map->im_type)); |
| 537 | KASSERT(map->im_msi_base >= 0 && |
| 538 | map->im_msi_base <= intr, |
| 539 | ("intr %d cpu%d, invalid MSI-base %d\n", |
| 540 | intr, cpu, map->im_msi_base)); |
| 541 | KASSERT((map->im_msi_base & mask) == 0, |
| 542 | ("intr %d cpu%d, MSI-base %d is " |
| 543 | "not proper aligned %d\n", |
| 544 | intr, cpu, map->im_msi_base, count)); |
| 545 | |
| 546 | if (msi_base < 0) { |
| 547 | msi_base = map->im_msi_base; |
| 548 | } else { |
| 549 | KASSERT(map->im_msi_base == msi_base, |
| 550 | ("intr %d cpu%d, " |
| 551 | "inconsistent MSI-base, " |
| 552 | "was %d, now %d\n", |
| 553 | intr, cpu, |
| 554 | msi_base, map->im_msi_base)); |
| 555 | } |
| 556 | map->im_msi_base = -1; |
| 557 | } else { |
| 558 | KASSERT(map->im_type == ICU_IMT_SHADOW, |
| 559 | ("try release non-MSIsh intr %d cpu%d, " |
| 560 | "type %d\n", intr, cpu, map->im_type)); |
| 561 | KASSERT(map->im_msi_base < 0, |
| 562 | ("intr %d cpu%d, invalid MSIsh-base %d\n", |
| 563 | intr, cpu, map->im_msi_base)); |
| 564 | } |
| 565 | map->im_type = ICU_IMT_UNUSED; |
| 566 | } |
| 567 | |
| 568 | if (intr_next < intr) |
| 569 | intr_next = intr; |
| 570 | |
| 571 | if (bootverbose) |
| 572 | kprintf("release MSI intr %d on cpu%d\n", intr, cpuid); |
| 573 | } |
| 574 | |
| 575 | KKASSERT(intr_next > 0); |
| 576 | KKASSERT(msi_base >= 0); |
| 577 | |
| 578 | ++intr_next; |
| 579 | if (intr_next < IDT_HWI_VECTORS) { |
| 580 | int cpu; |
| 581 | |
| 582 | for (cpu = 0; cpu < ncpus; ++cpu) { |
| 583 | const struct icu_irqmap *map = |
| 584 | &icu_irqmaps[cpu][intr_next]; |
| 585 | |
| 586 | if (map->im_type == ICU_IMT_MSI) { |
| 587 | KASSERT(map->im_msi_base != msi_base, |
| 588 | ("more than %d MSI was allocated\n", count)); |
| 589 | } |
| 590 | } |
| 591 | } |
| 592 | |
| 593 | lwkt_reltoken(&icu_irqmap_tok); |
| 594 | } |
| 595 | |
| 596 | static void |
| 597 | icu_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid) |
| 598 | { |
| 599 | const struct icu_irqmap *map; |
| 600 | |
| 601 | KASSERT(cpuid >= 0 && cpuid < ncpus, |
| 602 | ("invalid cpuid %d", cpuid)); |
| 603 | |
| 604 | KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, |
| 605 | ("invalid intr %d\n", intr)); |
| 606 | |
| 607 | lwkt_gettoken(&icu_irqmap_tok); |
| 608 | |
| 609 | map = &icu_irqmaps[cpuid][intr]; |
| 610 | KASSERT(map->im_type == ICU_IMT_MSI, |
| 611 | ("try map non-MSI intr %d, type %d\n", intr, map->im_type)); |
| 612 | KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr, |
| 613 | ("intr %d, invalid MSI-base %d\n", intr, map->im_msi_base)); |
| 614 | |
| 615 | msi_map(map->im_msi_base, addr, data, cpuid); |
| 616 | |
| 617 | if (bootverbose) |
| 618 | kprintf("map MSI intr %d on cpu%d\n", intr, cpuid); |
| 619 | |
| 620 | lwkt_reltoken(&icu_irqmap_tok); |
| 621 | } |