| 1 | /* |
| 2 | * Copyright (c) 1997, Stefan Esser <se@freebsd.org> |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * 1. Redistributions of source code must retain the above copyright |
| 9 | * notice unmodified, this list of conditions, and the following |
| 10 | * disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 25 | * |
| 26 | * $FreeBSD: src/sys/pci/pcivar.h,v 1.48 2000/09/28 00:37:32 peter Exp $ |
| 27 | * $DragonFly: src/sys/bus/pci/pcivar.h,v 1.13 2007/11/25 04:08:42 sephe Exp $ |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | #ifndef _PCIVAR_H_ |
| 32 | #define _PCIVAR_H_ |
| 33 | |
| 34 | #include <sys/queue.h> |
| 35 | |
| 36 | /* some PCI bus constants */ |
| 37 | |
| 38 | #define PCI_BUSMAX 255 /* highest supported bus number */ |
| 39 | #define PCI_SLOTMAX 31 /* highest supported slot number */ |
| 40 | #define PCI_FUNCMAX 7 /* highest supported function number */ |
| 41 | #define PCI_REGMAX 255 /* highest supported config register addr. */ |
| 42 | |
| 43 | #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ |
| 44 | #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ |
| 45 | #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ |
| 46 | |
| 47 | /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ |
| 48 | |
| 49 | #ifdef PCI_A64 |
| 50 | typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ |
| 51 | #else |
| 52 | typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ |
| 53 | #endif |
| 54 | |
| 55 | /* config values for PCI power management capability */ |
| 56 | struct pcicfg_pmgt { |
| 57 | u_int16_t pp_cap; /* PCI power management capabilities */ |
| 58 | u_int8_t pp_status; /* config space address of PCI power status reg */ |
| 59 | u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ |
| 60 | u_int8_t pp_data; /* config space address of PCI power data reg */ |
| 61 | }; |
| 62 | |
| 63 | /* config values for PCI Express capability */ |
| 64 | struct pcicfg_expr { |
| 65 | uint8_t expr_ptr; /* capability ptr */ |
| 66 | uint16_t expr_cap; /* capabilities */ |
| 67 | uint32_t expr_slotcap; /* slot capabilities */ |
| 68 | }; |
| 69 | |
| 70 | /* config header information common to all header types */ |
| 71 | |
| 72 | typedef struct pcicfg { |
| 73 | struct device *dev; /* device which owns this */ |
| 74 | void *hdrspec; /* pointer to header type specific data */ |
| 75 | |
| 76 | u_int16_t subvendor; /* card vendor ID */ |
| 77 | u_int16_t subdevice; /* card device ID, assigned by card vendor */ |
| 78 | u_int16_t vendor; /* chip vendor ID */ |
| 79 | u_int16_t device; /* chip device ID, assigned by chip vendor */ |
| 80 | |
| 81 | u_int16_t cmdreg; /* disable/enable chip and PCI options */ |
| 82 | u_int16_t statreg; /* supported PCI features and error state */ |
| 83 | |
| 84 | u_int8_t baseclass; /* chip PCI class */ |
| 85 | u_int8_t subclass; /* chip PCI subclass */ |
| 86 | u_int8_t progif; /* chip PCI programming interface */ |
| 87 | u_int8_t revid; /* chip revision ID */ |
| 88 | |
| 89 | u_int8_t hdrtype; /* chip config header type */ |
| 90 | u_int8_t cachelnsz; /* cache line size in 4byte units */ |
| 91 | u_int8_t intpin; /* PCI interrupt pin */ |
| 92 | u_int8_t intline; /* interrupt line (IRQ for PC arch) */ |
| 93 | |
| 94 | u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ |
| 95 | u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ |
| 96 | u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ |
| 97 | |
| 98 | u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ |
| 99 | u_int8_t nummaps; /* actual number of PCI maps used */ |
| 100 | |
| 101 | u_int8_t bus; /* config space bus address */ |
| 102 | u_int8_t slot; /* config space slot address */ |
| 103 | u_int8_t func; /* config space function number */ |
| 104 | |
| 105 | u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ |
| 106 | u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ |
| 107 | |
| 108 | struct pcicfg_pmgt pmgt; /* power management capability */ |
| 109 | struct pcicfg_expr expr; /* PCI Express capability */ |
| 110 | } pcicfgregs; |
| 111 | |
| 112 | /* additional type 1 device config header information (PCI to PCI bridge) */ |
| 113 | |
| 114 | #ifdef PCI_A64 |
| 115 | #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) |
| 116 | #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) |
| 117 | #else |
| 118 | #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) |
| 119 | #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) |
| 120 | #endif /* PCI_A64 */ |
| 121 | |
| 122 | #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) |
| 123 | #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) |
| 124 | |
| 125 | typedef struct { |
| 126 | pci_addr_t pmembase; /* base address of prefetchable memory */ |
| 127 | pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ |
| 128 | u_int32_t membase; /* base address of memory window */ |
| 129 | u_int32_t memlimit; /* topmost address of memory window */ |
| 130 | u_int32_t iobase; /* base address of port window */ |
| 131 | u_int32_t iolimit; /* topmost address of port window */ |
| 132 | u_int16_t secstat; /* secondary bus status register */ |
| 133 | u_int16_t bridgectl; /* bridge control register */ |
| 134 | u_int8_t seclat; /* CardBus latency timer */ |
| 135 | } pcih1cfgregs; |
| 136 | |
| 137 | /* additional type 2 device config header information (CardBus bridge) */ |
| 138 | |
| 139 | typedef struct { |
| 140 | u_int32_t membase0; /* base address of memory window */ |
| 141 | u_int32_t memlimit0; /* topmost address of memory window */ |
| 142 | u_int32_t membase1; /* base address of memory window */ |
| 143 | u_int32_t memlimit1; /* topmost address of memory window */ |
| 144 | u_int32_t iobase0; /* base address of port window */ |
| 145 | u_int32_t iolimit0; /* topmost address of port window */ |
| 146 | u_int32_t iobase1; /* base address of port window */ |
| 147 | u_int32_t iolimit1; /* topmost address of port window */ |
| 148 | u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ |
| 149 | u_int16_t secstat; /* secondary bus status register */ |
| 150 | u_int16_t bridgectl; /* bridge control register */ |
| 151 | u_int8_t seclat; /* CardBus latency timer */ |
| 152 | } pcih2cfgregs; |
| 153 | |
| 154 | extern u_int32_t pci_numdevs; |
| 155 | extern const char *pcib_owner; /* arbitrate who owns the pci device arch */ |
| 156 | |
| 157 | /* Only if the prerequisites are present */ |
| 158 | #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) |
| 159 | struct pci_devinfo { |
| 160 | STAILQ_ENTRY(pci_devinfo) pci_links; |
| 161 | struct resource_list resources; |
| 162 | pcicfgregs cfg; |
| 163 | struct pci_conf conf; |
| 164 | }; |
| 165 | #endif |
| 166 | |
| 167 | /* externally visible functions */ |
| 168 | |
| 169 | const char *pci_ata_match(struct device *dev); |
| 170 | const char *pci_usb_match(struct device *dev); |
| 171 | const char *pci_vga_match(struct device *dev); |
| 172 | const char *pci_chip_match(struct device *dev); |
| 173 | |
| 174 | /* low level PCI config register functions provided by pcibus.c */ |
| 175 | |
| 176 | int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); |
| 177 | void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); |
| 178 | |
| 179 | /* low level devlist operations for the 2.2 compatibility code in pci.c */ |
| 180 | pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); |
| 181 | |
| 182 | #ifdef _SYS_BUS_H_ |
| 183 | |
| 184 | #include "pci_if.h" |
| 185 | |
| 186 | /* |
| 187 | * Define pci-specific resource flags for accessing memory via dense |
| 188 | * or bwx memory spaces. These flags are ignored on i386. |
| 189 | */ |
| 190 | #define PCI_RF_DENSE 0x10000 |
| 191 | #define PCI_RF_BWX 0x20000 |
| 192 | |
| 193 | enum pci_device_ivars { |
| 194 | PCI_IVAR_SUBVENDOR, |
| 195 | PCI_IVAR_SUBDEVICE, |
| 196 | PCI_IVAR_VENDOR, |
| 197 | PCI_IVAR_DEVICE, |
| 198 | PCI_IVAR_DEVID, |
| 199 | PCI_IVAR_CLASS, |
| 200 | PCI_IVAR_SUBCLASS, |
| 201 | PCI_IVAR_PROGIF, |
| 202 | PCI_IVAR_REVID, |
| 203 | PCI_IVAR_INTPIN, |
| 204 | PCI_IVAR_IRQ, |
| 205 | PCI_IVAR_BUS, |
| 206 | PCI_IVAR_SLOT, |
| 207 | PCI_IVAR_FUNCTION, |
| 208 | PCI_IVAR_SECONDARYBUS, |
| 209 | PCI_IVAR_SUBORDINATEBUS, |
| 210 | PCI_IVAR_ETHADDR, |
| 211 | }; |
| 212 | |
| 213 | /* |
| 214 | * Simplified accessors for pci devices |
| 215 | * |
| 216 | * The PCI device passed in actually represents a PCI function number |
| 217 | * for the current slot. The parent of dev is the "pci" slot device. |
| 218 | * Each function number has its own set of ivars. |
| 219 | */ |
| 220 | #define PCI_ACCESSOR(A, B, T) \ |
| 221 | \ |
| 222 | static __inline T pci_get_ ## A(device_t dev) \ |
| 223 | { \ |
| 224 | uintptr_t v; \ |
| 225 | BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ |
| 226 | return (T) v; \ |
| 227 | } \ |
| 228 | \ |
| 229 | static __inline void pci_set_ ## A(device_t dev, T t) \ |
| 230 | { \ |
| 231 | uintptr_t v = (uintptr_t) t; \ |
| 232 | BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ |
| 233 | } |
| 234 | |
| 235 | PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) |
| 236 | PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) |
| 237 | PCI_ACCESSOR(vendor, VENDOR, u_int16_t) |
| 238 | PCI_ACCESSOR(device, DEVICE, u_int16_t) |
| 239 | PCI_ACCESSOR(devid, DEVID, u_int32_t) |
| 240 | PCI_ACCESSOR(class, CLASS, u_int8_t) |
| 241 | PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) |
| 242 | PCI_ACCESSOR(progif, PROGIF, u_int8_t) |
| 243 | PCI_ACCESSOR(revid, REVID, u_int8_t) |
| 244 | PCI_ACCESSOR(intpin, INTPIN, u_int8_t) |
| 245 | PCI_ACCESSOR(irq, IRQ, u_int8_t) |
| 246 | PCI_ACCESSOR(bus, BUS, u_int8_t) |
| 247 | PCI_ACCESSOR(slot, SLOT, u_int8_t) |
| 248 | PCI_ACCESSOR(function, FUNCTION, u_int8_t) |
| 249 | PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) |
| 250 | PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) |
| 251 | PCI_ACCESSOR(ether, ETHADDR, uint8_t *) |
| 252 | |
| 253 | #undef PCI_ACCESSOR |
| 254 | |
| 255 | static __inline u_int32_t |
| 256 | pci_read_config(device_t dev, int reg, int width) |
| 257 | { |
| 258 | return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); |
| 259 | } |
| 260 | |
| 261 | static __inline void |
| 262 | pci_write_config(device_t dev, int reg, u_int32_t val, int width) |
| 263 | { |
| 264 | PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); |
| 265 | } |
| 266 | |
| 267 | /* |
| 268 | * Convenience functions. |
| 269 | * |
| 270 | * These should be used in preference to manually manipulating |
| 271 | * configuration space. |
| 272 | */ |
| 273 | static __inline void |
| 274 | pci_enable_busmaster(device_t dev) |
| 275 | { |
| 276 | PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev); |
| 277 | } |
| 278 | |
| 279 | static __inline void |
| 280 | pci_disable_busmaster(device_t dev) |
| 281 | { |
| 282 | PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev); |
| 283 | } |
| 284 | |
| 285 | static __inline void |
| 286 | pci_enable_io(device_t dev, int space) |
| 287 | { |
| 288 | PCI_ENABLE_IO(device_get_parent(dev), dev, space); |
| 289 | } |
| 290 | |
| 291 | static __inline void |
| 292 | pci_disable_io(device_t dev, int space) |
| 293 | { |
| 294 | PCI_DISABLE_IO(device_get_parent(dev), dev, space); |
| 295 | } |
| 296 | |
| 297 | /* |
| 298 | * PCI power states are as defined by ACPI: |
| 299 | * |
| 300 | * D0 State in which device is on and running. It is receiving full |
| 301 | * power from the system and delivering full functionality to the user. |
| 302 | * D1 Class-specific low-power state in which device context may or may not |
| 303 | * be lost. Buses in D1 cannot do anything to the bus that would force |
| 304 | * devices on that bus to loose context. |
| 305 | * D2 Class-specific low-power state in which device context may or may |
| 306 | * not be lost. Attains greater power savings than D1. Buses in D2 |
| 307 | * can cause devices on that bus to loose some context. Devices in D2 |
| 308 | * must be prepared for the bus to be in D2 or higher. |
| 309 | * D3 State in which the device is off and not running. Device context is |
| 310 | * lost. Power can be removed from the device. |
| 311 | */ |
| 312 | #define PCI_POWERSTATE_D0 0 |
| 313 | #define PCI_POWERSTATE_D1 1 |
| 314 | #define PCI_POWERSTATE_D2 2 |
| 315 | #define PCI_POWERSTATE_D3 3 |
| 316 | #define PCI_POWERSTATE_UNKNOWN -1 |
| 317 | |
| 318 | static __inline int |
| 319 | pci_set_powerstate(device_t dev, int state) |
| 320 | { |
| 321 | return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); |
| 322 | } |
| 323 | |
| 324 | static __inline int |
| 325 | pci_get_powerstate(device_t dev) |
| 326 | { |
| 327 | return PCI_GET_POWERSTATE(device_get_parent(dev), dev); |
| 328 | } |
| 329 | |
| 330 | /* |
| 331 | * Ivars for pci bridges. |
| 332 | * |
| 333 | * Whereas PCI devices are arranged [pciX]->[pciX.Y] with the pci driver |
| 334 | * functions in [pciX] but the individual ivars in [pciX.Y], PCI bridges |
| 335 | * are installed in [pciX.Y] and store their ivars in a softc. This |
| 336 | * is why the accessor functions for a bridge do not call device_get_parent(). |
| 337 | */ |
| 338 | /*typedef enum pci_device_ivars pcib_device_ivars;*/ |
| 339 | enum pcib_device_ivars { |
| 340 | PCIB_IVAR_BUS, |
| 341 | }; |
| 342 | |
| 343 | #define PCIB_ACCESSOR(A, B, T) \ |
| 344 | \ |
| 345 | static __inline T pcib_get_ ## A(device_t dev) \ |
| 346 | { \ |
| 347 | uintptr_t v; \ |
| 348 | BUS_READ_IVAR(dev, dev, PCIB_IVAR_ ## B, &v); \ |
| 349 | return (T) v; \ |
| 350 | } \ |
| 351 | \ |
| 352 | static __inline void pcib_set_ ## A(device_t dev, T t) \ |
| 353 | { \ |
| 354 | uintptr_t v = (uintptr_t) t; \ |
| 355 | BUS_WRITE_IVAR(dev, dev, PCIB_IVAR_ ## B, v); \ |
| 356 | } |
| 357 | |
| 358 | PCIB_ACCESSOR(bus, BUS, u_int32_t) |
| 359 | |
| 360 | #undef PCIB_ACCESSOR |
| 361 | |
| 362 | device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t); |
| 363 | device_t pci_find_device(u_int16_t, u_int16_t); |
| 364 | #endif |
| 365 | |
| 366 | /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ |
| 367 | |
| 368 | #if defined(_KERNEL) && !defined(KLD_MODULE) |
| 369 | #include "opt_compat_oldpci.h" |
| 370 | #endif |
| 371 | |
| 372 | #ifdef COMPAT_OLDPCI |
| 373 | /* all this is going some day */ |
| 374 | |
| 375 | typedef pcicfgregs *pcici_t; |
| 376 | typedef unsigned pcidi_t; |
| 377 | typedef void pci_inthand_t(void *arg); |
| 378 | |
| 379 | #define pci_max_burst_len (3) |
| 380 | |
| 381 | /* just copied from old PCI code for now ... */ |
| 382 | |
| 383 | struct pci_device { |
| 384 | char* pd_name; |
| 385 | const char* (*pd_probe ) (pcici_t tag, pcidi_t type); |
| 386 | void (*pd_attach) (pcici_t tag, int unit); |
| 387 | u_long *pd_count; |
| 388 | int (*pd_shutdown) (int, int); |
| 389 | }; |
| 390 | |
| 391 | #ifdef __i386__ |
| 392 | typedef u_short pci_port_t; |
| 393 | #else |
| 394 | typedef u_int pci_port_t; |
| 395 | #endif |
| 396 | |
| 397 | u_long pci_conf_read (pcici_t tag, u_long reg); |
| 398 | void pci_conf_write (pcici_t tag, u_long reg, u_long data); |
| 399 | int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); |
| 400 | int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); |
| 401 | int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg); |
| 402 | int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, |
| 403 | u_int flags); |
| 404 | int pci_unmap_int (pcici_t tag); |
| 405 | |
| 406 | pcici_t pci_get_parent_from_tag(pcici_t tag); |
| 407 | int pci_get_bus_from_tag(pcici_t tag); |
| 408 | |
| 409 | struct module; |
| 410 | int compat_pci_handler (struct module *, int, void *); |
| 411 | #define COMPAT_PCI_DRIVER(name, pcidata) \ |
| 412 | static moduledata_t name##_mod = { \ |
| 413 | #name, \ |
| 414 | compat_pci_handler, \ |
| 415 | &pcidata \ |
| 416 | }; \ |
| 417 | DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) |
| 418 | |
| 419 | |
| 420 | #endif /* COMPAT_OLDPCI */ |
| 421 | #endif /* _PCIVAR_H_ */ |