| 1 | /*- |
| 2 | * Copyright (c) 1990 William Jolitz. |
| 3 | * Copyright (c) 1991 The Regents of the University of California. |
| 4 | * All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. All advertising materials mentioning features or use of this software |
| 15 | * must display the following acknowledgement: |
| 16 | * This product includes software developed by the University of |
| 17 | * California, Berkeley and its contributors. |
| 18 | * 4. Neither the name of the University nor the names of its contributors |
| 19 | * may be used to endorse or promote products derived from this software |
| 20 | * without specific prior written permission. |
| 21 | * |
| 22 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
| 23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 25 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 28 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 29 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 30 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 31 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 32 | * SUCH DAMAGE. |
| 33 | * |
| 34 | * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 |
| 35 | * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $ |
| 36 | */ |
| 37 | |
| 38 | #include "opt_cpu.h" |
| 39 | #include "opt_debug_npx.h" |
| 40 | #include "opt_math_emulate.h" |
| 41 | |
| 42 | #include <sys/param.h> |
| 43 | #include <sys/systm.h> |
| 44 | #include <sys/bus.h> |
| 45 | #include <sys/kernel.h> |
| 46 | #include <sys/malloc.h> |
| 47 | #include <sys/module.h> |
| 48 | #include <sys/sysctl.h> |
| 49 | #include <sys/proc.h> |
| 50 | #include <machine/bus.h> |
| 51 | #include <sys/rman.h> |
| 52 | #ifdef NPX_DEBUG |
| 53 | #include <sys/syslog.h> |
| 54 | #endif |
| 55 | #include <sys/signalvar.h> |
| 56 | |
| 57 | #ifndef SMP |
| 58 | #include <machine/asmacros.h> |
| 59 | #endif |
| 60 | #include <machine/cputypes.h> |
| 61 | #include <machine/frame.h> |
| 62 | #include <machine/ipl.h> |
| 63 | #include <machine/md_var.h> |
| 64 | #include <machine/pcb.h> |
| 65 | #include <machine/psl.h> |
| 66 | #ifndef SMP |
| 67 | #include <machine/clock.h> |
| 68 | #endif |
| 69 | #include <machine/resource.h> |
| 70 | #include <machine/specialreg.h> |
| 71 | #include <machine/segments.h> |
| 72 | |
| 73 | #ifndef SMP |
| 74 | #include <i386/isa/icu.h> |
| 75 | #include <i386/isa/intr_machdep.h> |
| 76 | #include <i386/isa/isa.h> |
| 77 | #endif |
| 78 | |
| 79 | /* |
| 80 | * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. |
| 81 | */ |
| 82 | |
| 83 | /* Configuration flags. */ |
| 84 | #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) |
| 85 | #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) |
| 86 | #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) |
| 87 | #define NPX_PREFER_EMULATOR (1 << 3) |
| 88 | |
| 89 | #ifdef __GNUC__ |
| 90 | |
| 91 | #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) |
| 92 | #define fnclex() __asm("fnclex") |
| 93 | #define fninit() __asm("fninit") |
| 94 | #define fnop() __asm("fnop") |
| 95 | #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) |
| 96 | #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) |
| 97 | #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) |
| 98 | #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") |
| 99 | #define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) |
| 100 | #ifdef CPU_ENABLE_SSE |
| 101 | #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) |
| 102 | #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) |
| 103 | #endif |
| 104 | #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ |
| 105 | : : "n" (CR0_TS) : "ax") |
| 106 | #define stop_emulating() __asm("clts") |
| 107 | |
| 108 | #else /* not __GNUC__ */ |
| 109 | |
| 110 | void fldcw __P((caddr_t addr)); |
| 111 | void fnclex __P((void)); |
| 112 | void fninit __P((void)); |
| 113 | void fnop __P((void)); |
| 114 | void fnsave __P((caddr_t addr)); |
| 115 | void fnstcw __P((caddr_t addr)); |
| 116 | void fnstsw __P((caddr_t addr)); |
| 117 | void fp_divide_by_0 __P((void)); |
| 118 | void frstor __P((caddr_t addr)); |
| 119 | #ifdef CPU_ENABLE_SSE |
| 120 | void fxsave __P((caddr_t addr)); |
| 121 | void fxrstor __P((caddr_t addr)); |
| 122 | #endif |
| 123 | void start_emulating __P((void)); |
| 124 | void stop_emulating __P((void)); |
| 125 | |
| 126 | #endif /* __GNUC__ */ |
| 127 | |
| 128 | #ifdef CPU_ENABLE_SSE |
| 129 | #define GET_FPU_EXSW_PTR(pcb) \ |
| 130 | (cpu_fxsr ? \ |
| 131 | &(pcb)->pcb_save.sv_xmm.sv_ex_sw : \ |
| 132 | &(pcb)->pcb_save.sv_87.sv_ex_sw) |
| 133 | #else /* CPU_ENABLE_SSE */ |
| 134 | #define GET_FPU_EXSW_PTR(pcb) \ |
| 135 | (&(pcb)->pcb_save.sv_87.sv_ex_sw) |
| 136 | #endif /* CPU_ENABLE_SSE */ |
| 137 | |
| 138 | typedef u_char bool_t; |
| 139 | |
| 140 | static int npx_attach __P((device_t dev)); |
| 141 | void npx_intr __P((void *)); |
| 142 | static void npx_identify __P((driver_t *driver, device_t parent)); |
| 143 | static int npx_probe __P((device_t dev)); |
| 144 | static int npx_probe1 __P((device_t dev)); |
| 145 | static void fpusave __P((union savefpu *)); |
| 146 | static void fpurstor __P((union savefpu *)); |
| 147 | #ifdef I586_CPU |
| 148 | static long timezero __P((const char *funcname, |
| 149 | void (*func)(void *buf, size_t len))); |
| 150 | #endif /* I586_CPU */ |
| 151 | |
| 152 | int hw_float; /* XXX currently just alias for npx_exists */ |
| 153 | |
| 154 | SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, |
| 155 | CTLFLAG_RD, &hw_float, 0, |
| 156 | "Floatingpoint instructions executed in hardware"); |
| 157 | |
| 158 | #ifndef SMP |
| 159 | static u_int npx0_imask = SWI_CLOCK_MASK; |
| 160 | static struct gate_descriptor npx_idt_probeintr; |
| 161 | static int npx_intrno; |
| 162 | static volatile u_int npx_intrs_while_probing; |
| 163 | static volatile u_int npx_traps_while_probing; |
| 164 | #endif |
| 165 | |
| 166 | static bool_t npx_ex16; |
| 167 | static bool_t npx_exists; |
| 168 | static bool_t npx_irq13; |
| 169 | static int npx_irq; /* irq number */ |
| 170 | |
| 171 | #ifndef SMP |
| 172 | /* |
| 173 | * Special interrupt handlers. Someday intr0-intr15 will be used to count |
| 174 | * interrupts. We'll still need a special exception 16 handler. The busy |
| 175 | * latch stuff in probeintr() can be moved to npxprobe(). |
| 176 | */ |
| 177 | inthand_t probeintr; |
| 178 | __asm(" \n\ |
| 179 | .text \n\ |
| 180 | .p2align 2,0x90 \n\ |
| 181 | .type " __XSTRING(CNAME(probeintr)) ",@function \n\ |
| 182 | " __XSTRING(CNAME(probeintr)) ": \n\ |
| 183 | ss \n\ |
| 184 | incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\ |
| 185 | pushl %eax \n\ |
| 186 | movb $0x20,%al # EOI (asm in strings loses cpp features) \n\ |
| 187 | outb %al,$0xa0 # IO_ICU2 \n\ |
| 188 | outb %al,$0x20 # IO_ICU1 \n\ |
| 189 | movb $0,%al \n\ |
| 190 | outb %al,$0xf0 # clear BUSY# latch \n\ |
| 191 | popl %eax \n\ |
| 192 | iret \n\ |
| 193 | "); |
| 194 | |
| 195 | inthand_t probetrap; |
| 196 | __asm(" \n\ |
| 197 | .text \n\ |
| 198 | .p2align 2,0x90 \n\ |
| 199 | .type " __XSTRING(CNAME(probetrap)) ",@function \n\ |
| 200 | " __XSTRING(CNAME(probetrap)) ": \n\ |
| 201 | ss \n\ |
| 202 | incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ |
| 203 | fnclex \n\ |
| 204 | iret \n\ |
| 205 | "); |
| 206 | #endif /* SMP */ |
| 207 | |
| 208 | /* |
| 209 | * Identify routine. Create a connection point on our parent for probing. |
| 210 | */ |
| 211 | static void |
| 212 | npx_identify(driver, parent) |
| 213 | driver_t *driver; |
| 214 | device_t parent; |
| 215 | { |
| 216 | device_t child; |
| 217 | |
| 218 | child = BUS_ADD_CHILD(parent, 0, "npx", 0); |
| 219 | if (child == NULL) |
| 220 | panic("npx_identify"); |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * Probe routine. Initialize cr0 to give correct behaviour for [f]wait |
| 225 | * whether the device exists or not (XXX should be elsewhere). Set flags |
| 226 | * to tell npxattach() what to do. Modify device struct if npx doesn't |
| 227 | * need to use interrupts. Return 1 if device exists. |
| 228 | */ |
| 229 | static int |
| 230 | npx_probe(dev) |
| 231 | device_t dev; |
| 232 | { |
| 233 | #ifdef SMP |
| 234 | |
| 235 | if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) |
| 236 | npx_irq = 13; |
| 237 | return npx_probe1(dev); |
| 238 | |
| 239 | #else /* SMP */ |
| 240 | |
| 241 | int result; |
| 242 | u_long save_eflags; |
| 243 | u_char save_icu1_mask; |
| 244 | u_char save_icu2_mask; |
| 245 | struct gate_descriptor save_idt_npxintr; |
| 246 | struct gate_descriptor save_idt_npxtrap; |
| 247 | /* |
| 248 | * This routine is now just a wrapper for npxprobe1(), to install |
| 249 | * special npx interrupt and trap handlers, to enable npx interrupts |
| 250 | * and to disable other interrupts. Someday isa_configure() will |
| 251 | * install suitable handlers and run with interrupts enabled so we |
| 252 | * won't need to do so much here. |
| 253 | */ |
| 254 | if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) |
| 255 | npx_irq = 13; |
| 256 | npx_intrno = NRSVIDT + npx_irq; |
| 257 | save_eflags = read_eflags(); |
| 258 | disable_intr(); |
| 259 | save_icu1_mask = inb(IO_ICU1 + 1); |
| 260 | save_icu2_mask = inb(IO_ICU2 + 1); |
| 261 | save_idt_npxintr = idt[npx_intrno]; |
| 262 | save_idt_npxtrap = idt[16]; |
| 263 | outb(IO_ICU1 + 1, ~IRQ_SLAVE); |
| 264 | outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8))); |
| 265 | setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); |
| 266 | setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); |
| 267 | npx_idt_probeintr = idt[npx_intrno]; |
| 268 | enable_intr(); |
| 269 | result = npx_probe1(dev); |
| 270 | disable_intr(); |
| 271 | outb(IO_ICU1 + 1, save_icu1_mask); |
| 272 | outb(IO_ICU2 + 1, save_icu2_mask); |
| 273 | idt[npx_intrno] = save_idt_npxintr; |
| 274 | idt[16] = save_idt_npxtrap; |
| 275 | write_eflags(save_eflags); |
| 276 | return (result); |
| 277 | |
| 278 | #endif /* SMP */ |
| 279 | } |
| 280 | |
| 281 | static int |
| 282 | npx_probe1(dev) |
| 283 | device_t dev; |
| 284 | { |
| 285 | #ifndef SMP |
| 286 | u_short control; |
| 287 | u_short status; |
| 288 | #endif |
| 289 | |
| 290 | /* |
| 291 | * Partially reset the coprocessor, if any. Some BIOS's don't reset |
| 292 | * it after a warm boot. |
| 293 | */ |
| 294 | outb(0xf1, 0); /* full reset on some systems, NOP on others */ |
| 295 | outb(0xf0, 0); /* clear BUSY# latch */ |
| 296 | /* |
| 297 | * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT |
| 298 | * instructions. We must set the CR0_MP bit and use the CR0_TS |
| 299 | * bit to control the trap, because setting the CR0_EM bit does |
| 300 | * not cause WAIT instructions to trap. It's important to trap |
| 301 | * WAIT instructions - otherwise the "wait" variants of no-wait |
| 302 | * control instructions would degenerate to the "no-wait" variants |
| 303 | * after FP context switches but work correctly otherwise. It's |
| 304 | * particularly important to trap WAITs when there is no NPX - |
| 305 | * otherwise the "wait" variants would always degenerate. |
| 306 | * |
| 307 | * Try setting CR0_NE to get correct error reporting on 486DX's. |
| 308 | * Setting it should fail or do nothing on lesser processors. |
| 309 | */ |
| 310 | load_cr0(rcr0() | CR0_MP | CR0_NE); |
| 311 | /* |
| 312 | * But don't trap while we're probing. |
| 313 | */ |
| 314 | stop_emulating(); |
| 315 | /* |
| 316 | * Finish resetting the coprocessor, if any. If there is an error |
| 317 | * pending, then we may get a bogus IRQ13, but probeintr() will handle |
| 318 | * it OK. Bogus halts have never been observed, but we enabled |
| 319 | * IRQ13 and cleared the BUSY# latch early to handle them anyway. |
| 320 | */ |
| 321 | fninit(); |
| 322 | |
| 323 | #ifdef SMP |
| 324 | /* |
| 325 | * Exception 16 MUST work for SMP. |
| 326 | */ |
| 327 | npx_irq13 = 0; |
| 328 | npx_ex16 = hw_float = npx_exists = 1; |
| 329 | device_set_desc(dev, "math processor"); |
| 330 | return (0); |
| 331 | |
| 332 | #else /* !SMP */ |
| 333 | device_set_desc(dev, "math processor"); |
| 334 | |
| 335 | /* |
| 336 | * Don't use fwait here because it might hang. |
| 337 | * Don't use fnop here because it usually hangs if there is no FPU. |
| 338 | */ |
| 339 | DELAY(1000); /* wait for any IRQ13 */ |
| 340 | #ifdef DIAGNOSTIC |
| 341 | if (npx_intrs_while_probing != 0) |
| 342 | printf("fninit caused %u bogus npx interrupt(s)\n", |
| 343 | npx_intrs_while_probing); |
| 344 | if (npx_traps_while_probing != 0) |
| 345 | printf("fninit caused %u bogus npx trap(s)\n", |
| 346 | npx_traps_while_probing); |
| 347 | #endif |
| 348 | /* |
| 349 | * Check for a status of mostly zero. |
| 350 | */ |
| 351 | status = 0x5a5a; |
| 352 | fnstsw(&status); |
| 353 | if ((status & 0xb8ff) == 0) { |
| 354 | /* |
| 355 | * Good, now check for a proper control word. |
| 356 | */ |
| 357 | control = 0x5a5a; |
| 358 | fnstcw(&control); |
| 359 | if ((control & 0x1f3f) == 0x033f) { |
| 360 | hw_float = npx_exists = 1; |
| 361 | /* |
| 362 | * We have an npx, now divide by 0 to see if exception |
| 363 | * 16 works. |
| 364 | */ |
| 365 | control &= ~(1 << 2); /* enable divide by 0 trap */ |
| 366 | fldcw(&control); |
| 367 | npx_traps_while_probing = npx_intrs_while_probing = 0; |
| 368 | fp_divide_by_0(); |
| 369 | if (npx_traps_while_probing != 0) { |
| 370 | /* |
| 371 | * Good, exception 16 works. |
| 372 | */ |
| 373 | npx_ex16 = 1; |
| 374 | return (0); |
| 375 | } |
| 376 | if (npx_intrs_while_probing != 0) { |
| 377 | int rid; |
| 378 | struct resource *r; |
| 379 | void *intr; |
| 380 | /* |
| 381 | * Bad, we are stuck with IRQ13. |
| 382 | */ |
| 383 | npx_irq13 = 1; |
| 384 | /* |
| 385 | * npxattach would be too late to set npx0_imask |
| 386 | */ |
| 387 | npx0_imask |= (1 << npx_irq); |
| 388 | |
| 389 | /* |
| 390 | * We allocate these resources permanently, |
| 391 | * so there is no need to keep track of them. |
| 392 | */ |
| 393 | rid = 0; |
| 394 | r = bus_alloc_resource(dev, SYS_RES_IOPORT, |
| 395 | &rid, IO_NPX, IO_NPX, |
| 396 | IO_NPXSIZE, RF_ACTIVE); |
| 397 | if (r == 0) |
| 398 | panic("npx: can't get ports"); |
| 399 | rid = 0; |
| 400 | r = bus_alloc_resource(dev, SYS_RES_IRQ, |
| 401 | &rid, npx_irq, npx_irq, |
| 402 | 1, RF_ACTIVE); |
| 403 | if (r == 0) |
| 404 | panic("npx: can't get IRQ"); |
| 405 | BUS_SETUP_INTR(device_get_parent(dev), |
| 406 | dev, r, INTR_TYPE_MISC, |
| 407 | npx_intr, 0, &intr); |
| 408 | if (intr == 0) |
| 409 | panic("npx: can't create intr"); |
| 410 | |
| 411 | return (0); |
| 412 | } |
| 413 | /* |
| 414 | * Worse, even IRQ13 is broken. Use emulator. |
| 415 | */ |
| 416 | } |
| 417 | } |
| 418 | /* |
| 419 | * Probe failed, but we want to get to npxattach to initialize the |
| 420 | * emulator and say that it has been installed. XXX handle devices |
| 421 | * that aren't really devices better. |
| 422 | */ |
| 423 | return (0); |
| 424 | #endif /* SMP */ |
| 425 | } |
| 426 | |
| 427 | /* |
| 428 | * Attach routine - announce which it is, and wire into system |
| 429 | */ |
| 430 | int |
| 431 | npx_attach(dev) |
| 432 | device_t dev; |
| 433 | { |
| 434 | int flags; |
| 435 | |
| 436 | if (resource_int_value("npx", 0, "flags", &flags) != 0) |
| 437 | flags = 0; |
| 438 | |
| 439 | if (flags) |
| 440 | device_printf(dev, "flags 0x%x ", flags); |
| 441 | if (npx_irq13) { |
| 442 | device_printf(dev, "using IRQ 13 interface\n"); |
| 443 | } else { |
| 444 | #if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) |
| 445 | if (npx_ex16) { |
| 446 | if (!(flags & NPX_PREFER_EMULATOR)) |
| 447 | device_printf(dev, "INT 16 interface\n"); |
| 448 | else { |
| 449 | device_printf(dev, "FPU exists, but flags request " |
| 450 | "emulator\n"); |
| 451 | hw_float = npx_exists = 0; |
| 452 | } |
| 453 | } else if (npx_exists) { |
| 454 | device_printf(dev, "error reporting broken; using 387 emulator\n"); |
| 455 | hw_float = npx_exists = 0; |
| 456 | } else |
| 457 | device_printf(dev, "387 emulator\n"); |
| 458 | #else |
| 459 | if (npx_ex16) { |
| 460 | device_printf(dev, "INT 16 interface\n"); |
| 461 | if (flags & NPX_PREFER_EMULATOR) { |
| 462 | device_printf(dev, "emulator requested, but none compiled " |
| 463 | "into kernel, using FPU\n"); |
| 464 | } |
| 465 | } else |
| 466 | device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); |
| 467 | #endif |
| 468 | } |
| 469 | npxinit(__INITIAL_NPXCW__); |
| 470 | |
| 471 | #ifdef I586_CPU |
| 472 | if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && |
| 473 | timezero("i586_bzero()", i586_bzero) < |
| 474 | timezero("bzero()", bzero) * 4 / 5) { |
| 475 | if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { |
| 476 | bcopy_vector = i586_bcopy; |
| 477 | ovbcopy_vector = i586_bcopy; |
| 478 | } |
| 479 | if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) |
| 480 | bzero = i586_bzero; |
| 481 | if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { |
| 482 | copyin_vector = i586_copyin; |
| 483 | copyout_vector = i586_copyout; |
| 484 | } |
| 485 | } |
| 486 | #endif |
| 487 | |
| 488 | return (0); /* XXX unused */ |
| 489 | } |
| 490 | |
| 491 | /* |
| 492 | * Initialize floating point unit. |
| 493 | */ |
| 494 | void |
| 495 | npxinit(control) |
| 496 | u_short control; |
| 497 | { |
| 498 | static union savefpu dummy; |
| 499 | |
| 500 | if (!npx_exists) |
| 501 | return; |
| 502 | /* |
| 503 | * fninit has the same h/w bugs as fnsave. Use the detoxified |
| 504 | * fnsave to throw away any junk in the fpu. npxsave() initializes |
| 505 | * the fpu and sets npxproc = NULL as important side effects. |
| 506 | */ |
| 507 | npxsave(&dummy); |
| 508 | stop_emulating(); |
| 509 | #ifdef CPU_ENABLE_SSE |
| 510 | /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ |
| 511 | if (cpu_fxsr) |
| 512 | fninit(); |
| 513 | #endif |
| 514 | fldcw(&control); |
| 515 | if (curpcb != NULL) |
| 516 | fpusave(&curpcb->pcb_save); |
| 517 | start_emulating(); |
| 518 | } |
| 519 | |
| 520 | /* |
| 521 | * Free coprocessor (if we have it). |
| 522 | */ |
| 523 | void |
| 524 | npxexit(p) |
| 525 | struct proc *p; |
| 526 | { |
| 527 | |
| 528 | if (p == npxproc) |
| 529 | npxsave(&curpcb->pcb_save); |
| 530 | #ifdef NPX_DEBUG |
| 531 | if (npx_exists) { |
| 532 | u_int masked_exceptions; |
| 533 | |
| 534 | masked_exceptions = curpcb->pcb_save.sv_87.sv_env.en_cw |
| 535 | & curpcb->pcb_save.sv_87.sv_env.en_sw & 0x7f; |
| 536 | /* |
| 537 | * Log exceptions that would have trapped with the old |
| 538 | * control word (overflow, divide by 0, and invalid operand). |
| 539 | */ |
| 540 | if (masked_exceptions & 0x0d) |
| 541 | log(LOG_ERR, |
| 542 | "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", |
| 543 | p->p_pid, p->p_comm, masked_exceptions); |
| 544 | } |
| 545 | #endif |
| 546 | } |
| 547 | |
| 548 | /* |
| 549 | * The following mechanism is used to ensure that the FPE_... value |
| 550 | * that is passed as a trapcode to the signal handler of the user |
| 551 | * process does not have more than one bit set. |
| 552 | * |
| 553 | * Multiple bits may be set if the user process modifies the control |
| 554 | * word while a status word bit is already set. While this is a sign |
| 555 | * of bad coding, we have no choise than to narrow them down to one |
| 556 | * bit, since we must not send a trapcode that is not exactly one of |
| 557 | * the FPE_ macros. |
| 558 | * |
| 559 | * The mechanism has a static table with 127 entries. Each combination |
| 560 | * of the 7 FPU status word exception bits directly translates to a |
| 561 | * position in this table, where a single FPE_... value is stored. |
| 562 | * This FPE_... value stored there is considered the "most important" |
| 563 | * of the exception bits and will be sent as the signal code. The |
| 564 | * precedence of the bits is based upon Intel Document "Numerical |
| 565 | * Applications", Chapter "Special Computational Situations". |
| 566 | * |
| 567 | * The macro to choose one of these values does these steps: 1) Throw |
| 568 | * away status word bits that cannot be masked. 2) Throw away the bits |
| 569 | * currently masked in the control word, assuming the user isn't |
| 570 | * interested in them anymore. 3) Reinsert status word bit 7 (stack |
| 571 | * fault) if it is set, which cannot be masked but must be presered. |
| 572 | * 4) Use the remaining bits to point into the trapcode table. |
| 573 | * |
| 574 | * The 6 maskable bits in order of their preference, as stated in the |
| 575 | * above referenced Intel manual: |
| 576 | * 1 Invalid operation (FP_X_INV) |
| 577 | * 1a Stack underflow |
| 578 | * 1b Stack overflow |
| 579 | * 1c Operand of unsupported format |
| 580 | * 1d SNaN operand. |
| 581 | * 2 QNaN operand (not an exception, irrelavant here) |
| 582 | * 3 Any other invalid-operation not mentioned above or zero divide |
| 583 | * (FP_X_INV, FP_X_DZ) |
| 584 | * 4 Denormal operand (FP_X_DNML) |
| 585 | * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) |
| 586 | * 6 Inexact result (FP_X_IMP) |
| 587 | */ |
| 588 | static char fpetable[128] = { |
| 589 | 0, |
| 590 | FPE_FLTINV, /* 1 - INV */ |
| 591 | FPE_FLTUND, /* 2 - DNML */ |
| 592 | FPE_FLTINV, /* 3 - INV | DNML */ |
| 593 | FPE_FLTDIV, /* 4 - DZ */ |
| 594 | FPE_FLTINV, /* 5 - INV | DZ */ |
| 595 | FPE_FLTDIV, /* 6 - DNML | DZ */ |
| 596 | FPE_FLTINV, /* 7 - INV | DNML | DZ */ |
| 597 | FPE_FLTOVF, /* 8 - OFL */ |
| 598 | FPE_FLTINV, /* 9 - INV | OFL */ |
| 599 | FPE_FLTUND, /* A - DNML | OFL */ |
| 600 | FPE_FLTINV, /* B - INV | DNML | OFL */ |
| 601 | FPE_FLTDIV, /* C - DZ | OFL */ |
| 602 | FPE_FLTINV, /* D - INV | DZ | OFL */ |
| 603 | FPE_FLTDIV, /* E - DNML | DZ | OFL */ |
| 604 | FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ |
| 605 | FPE_FLTUND, /* 10 - UFL */ |
| 606 | FPE_FLTINV, /* 11 - INV | UFL */ |
| 607 | FPE_FLTUND, /* 12 - DNML | UFL */ |
| 608 | FPE_FLTINV, /* 13 - INV | DNML | UFL */ |
| 609 | FPE_FLTDIV, /* 14 - DZ | UFL */ |
| 610 | FPE_FLTINV, /* 15 - INV | DZ | UFL */ |
| 611 | FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ |
| 612 | FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ |
| 613 | FPE_FLTOVF, /* 18 - OFL | UFL */ |
| 614 | FPE_FLTINV, /* 19 - INV | OFL | UFL */ |
| 615 | FPE_FLTUND, /* 1A - DNML | OFL | UFL */ |
| 616 | FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ |
| 617 | FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ |
| 618 | FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ |
| 619 | FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ |
| 620 | FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ |
| 621 | FPE_FLTRES, /* 20 - IMP */ |
| 622 | FPE_FLTINV, /* 21 - INV | IMP */ |
| 623 | FPE_FLTUND, /* 22 - DNML | IMP */ |
| 624 | FPE_FLTINV, /* 23 - INV | DNML | IMP */ |
| 625 | FPE_FLTDIV, /* 24 - DZ | IMP */ |
| 626 | FPE_FLTINV, /* 25 - INV | DZ | IMP */ |
| 627 | FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ |
| 628 | FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ |
| 629 | FPE_FLTOVF, /* 28 - OFL | IMP */ |
| 630 | FPE_FLTINV, /* 29 - INV | OFL | IMP */ |
| 631 | FPE_FLTUND, /* 2A - DNML | OFL | IMP */ |
| 632 | FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ |
| 633 | FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ |
| 634 | FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ |
| 635 | FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ |
| 636 | FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ |
| 637 | FPE_FLTUND, /* 30 - UFL | IMP */ |
| 638 | FPE_FLTINV, /* 31 - INV | UFL | IMP */ |
| 639 | FPE_FLTUND, /* 32 - DNML | UFL | IMP */ |
| 640 | FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ |
| 641 | FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ |
| 642 | FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ |
| 643 | FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ |
| 644 | FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ |
| 645 | FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ |
| 646 | FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ |
| 647 | FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ |
| 648 | FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ |
| 649 | FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ |
| 650 | FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ |
| 651 | FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ |
| 652 | FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ |
| 653 | FPE_FLTSUB, /* 40 - STK */ |
| 654 | FPE_FLTSUB, /* 41 - INV | STK */ |
| 655 | FPE_FLTUND, /* 42 - DNML | STK */ |
| 656 | FPE_FLTSUB, /* 43 - INV | DNML | STK */ |
| 657 | FPE_FLTDIV, /* 44 - DZ | STK */ |
| 658 | FPE_FLTSUB, /* 45 - INV | DZ | STK */ |
| 659 | FPE_FLTDIV, /* 46 - DNML | DZ | STK */ |
| 660 | FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ |
| 661 | FPE_FLTOVF, /* 48 - OFL | STK */ |
| 662 | FPE_FLTSUB, /* 49 - INV | OFL | STK */ |
| 663 | FPE_FLTUND, /* 4A - DNML | OFL | STK */ |
| 664 | FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ |
| 665 | FPE_FLTDIV, /* 4C - DZ | OFL | STK */ |
| 666 | FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ |
| 667 | FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ |
| 668 | FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ |
| 669 | FPE_FLTUND, /* 50 - UFL | STK */ |
| 670 | FPE_FLTSUB, /* 51 - INV | UFL | STK */ |
| 671 | FPE_FLTUND, /* 52 - DNML | UFL | STK */ |
| 672 | FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ |
| 673 | FPE_FLTDIV, /* 54 - DZ | UFL | STK */ |
| 674 | FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ |
| 675 | FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ |
| 676 | FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ |
| 677 | FPE_FLTOVF, /* 58 - OFL | UFL | STK */ |
| 678 | FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ |
| 679 | FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ |
| 680 | FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ |
| 681 | FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ |
| 682 | FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ |
| 683 | FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ |
| 684 | FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ |
| 685 | FPE_FLTRES, /* 60 - IMP | STK */ |
| 686 | FPE_FLTSUB, /* 61 - INV | IMP | STK */ |
| 687 | FPE_FLTUND, /* 62 - DNML | IMP | STK */ |
| 688 | FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ |
| 689 | FPE_FLTDIV, /* 64 - DZ | IMP | STK */ |
| 690 | FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ |
| 691 | FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ |
| 692 | FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ |
| 693 | FPE_FLTOVF, /* 68 - OFL | IMP | STK */ |
| 694 | FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ |
| 695 | FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ |
| 696 | FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ |
| 697 | FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ |
| 698 | FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ |
| 699 | FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ |
| 700 | FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ |
| 701 | FPE_FLTUND, /* 70 - UFL | IMP | STK */ |
| 702 | FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ |
| 703 | FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ |
| 704 | FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ |
| 705 | FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ |
| 706 | FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ |
| 707 | FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ |
| 708 | FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ |
| 709 | FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ |
| 710 | FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ |
| 711 | FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ |
| 712 | FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ |
| 713 | FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ |
| 714 | FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ |
| 715 | FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ |
| 716 | FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ |
| 717 | }; |
| 718 | |
| 719 | /* |
| 720 | * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. |
| 721 | * |
| 722 | * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now |
| 723 | * depend on longjmp() restoring a usable state. Restoring the state |
| 724 | * or examining it might fail if we didn't clear exceptions. |
| 725 | * |
| 726 | * The error code chosen will be one of the FPE_... macros. It will be |
| 727 | * sent as the second argument to old BSD-style signal handlers and as |
| 728 | * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. |
| 729 | * |
| 730 | * XXX the FP state is not preserved across signal handlers. So signal |
| 731 | * handlers cannot afford to do FP unless they preserve the state or |
| 732 | * longjmp() out. Both preserving the state and longjmp()ing may be |
| 733 | * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable |
| 734 | * solution for signals other than SIGFPE. |
| 735 | */ |
| 736 | void |
| 737 | npx_intr(dummy) |
| 738 | void *dummy; |
| 739 | { |
| 740 | int code; |
| 741 | u_short control; |
| 742 | struct intrframe *frame; |
| 743 | u_long *exstat; |
| 744 | |
| 745 | if (npxproc == NULL || !npx_exists) { |
| 746 | printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", |
| 747 | npxproc, curproc, npx_exists); |
| 748 | panic("npxintr from nowhere"); |
| 749 | } |
| 750 | if (npxproc != curproc) { |
| 751 | printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", |
| 752 | npxproc, curproc, npx_exists); |
| 753 | panic("npxintr from non-current process"); |
| 754 | } |
| 755 | |
| 756 | exstat = GET_FPU_EXSW_PTR(curpcb); |
| 757 | outb(0xf0, 0); |
| 758 | fnstsw(exstat); |
| 759 | fnstcw(&control); |
| 760 | fnclex(); |
| 761 | |
| 762 | /* |
| 763 | * Pass exception to process. |
| 764 | */ |
| 765 | frame = (struct intrframe *)&dummy; /* XXX */ |
| 766 | if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) { |
| 767 | /* |
| 768 | * Interrupt is essentially a trap, so we can afford to call |
| 769 | * the SIGFPE handler (if any) as soon as the interrupt |
| 770 | * returns. |
| 771 | * |
| 772 | * XXX little or nothing is gained from this, and plenty is |
| 773 | * lost - the interrupt frame has to contain the trap frame |
| 774 | * (this is otherwise only necessary for the rescheduling trap |
| 775 | * in doreti, and the frame for that could easily be set up |
| 776 | * just before it is used). |
| 777 | */ |
| 778 | curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame); |
| 779 | /* |
| 780 | * Encode the appropriate code for detailed information on |
| 781 | * this exception. |
| 782 | */ |
| 783 | code = |
| 784 | fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)]; |
| 785 | trapsignal(curproc, SIGFPE, code); |
| 786 | } else { |
| 787 | /* |
| 788 | * Nested interrupt. These losers occur when: |
| 789 | * o an IRQ13 is bogusly generated at a bogus time, e.g.: |
| 790 | * o immediately after an fnsave or frstor of an |
| 791 | * error state. |
| 792 | * o a couple of 386 instructions after |
| 793 | * "fstpl _memvar" causes a stack overflow. |
| 794 | * These are especially nasty when combined with a |
| 795 | * trace trap. |
| 796 | * o an IRQ13 occurs at the same time as another higher- |
| 797 | * priority interrupt. |
| 798 | * |
| 799 | * Treat them like a true async interrupt. |
| 800 | */ |
| 801 | psignal(curproc, SIGFPE); |
| 802 | } |
| 803 | } |
| 804 | |
| 805 | /* |
| 806 | * Implement device not available (DNA) exception |
| 807 | * |
| 808 | * It would be better to switch FP context here (if curproc != npxproc) |
| 809 | * and not necessarily for every context switch, but it is too hard to |
| 810 | * access foreign pcb's. |
| 811 | */ |
| 812 | int |
| 813 | npxdna() |
| 814 | { |
| 815 | u_long *exstat; |
| 816 | |
| 817 | if (!npx_exists) |
| 818 | return (0); |
| 819 | if (npxproc != NULL) { |
| 820 | printf("npxdna: npxproc = %p, curproc = %p\n", |
| 821 | npxproc, curproc); |
| 822 | panic("npxdna"); |
| 823 | } |
| 824 | stop_emulating(); |
| 825 | /* |
| 826 | * Record new context early in case frstor causes an IRQ13. |
| 827 | */ |
| 828 | npxproc = curproc; |
| 829 | exstat = GET_FPU_EXSW_PTR(curpcb); |
| 830 | *exstat = 0; |
| 831 | /* |
| 832 | * The following frstor may cause an IRQ13 when the state being |
| 833 | * restored has a pending error. The error will appear to have been |
| 834 | * triggered by the current (npx) user instruction even when that |
| 835 | * instruction is a no-wait instruction that should not trigger an |
| 836 | * error (e.g., fnclex). On at least one 486 system all of the |
| 837 | * no-wait instructions are broken the same as frstor, so our |
| 838 | * treatment does not amplify the breakage. On at least one |
| 839 | * 386/Cyrix 387 system, fnclex works correctly while frstor and |
| 840 | * fnsave are broken, so our treatment breaks fnclex if it is the |
| 841 | * first FPU instruction after a context switch. |
| 842 | */ |
| 843 | fpurstor(&curpcb->pcb_save); |
| 844 | |
| 845 | return (1); |
| 846 | } |
| 847 | |
| 848 | /* |
| 849 | * Wrapper for fnsave instruction to handle h/w bugs. If there is an error |
| 850 | * pending, then fnsave generates a bogus IRQ13 on some systems. Force |
| 851 | * any IRQ13 to be handled immediately, and then ignore it. This routine is |
| 852 | * often called at splhigh so it must not use many system services. In |
| 853 | * particular, it's much easier to install a special handler than to |
| 854 | * guarantee that it's safe to use npxintr() and its supporting code. |
| 855 | */ |
| 856 | void |
| 857 | npxsave(addr) |
| 858 | union savefpu *addr; |
| 859 | { |
| 860 | #if defined(SMP) || defined(CPU_ENABLE_SSE) |
| 861 | |
| 862 | stop_emulating(); |
| 863 | fpusave(addr); |
| 864 | |
| 865 | /* fnop(); */ |
| 866 | start_emulating(); |
| 867 | npxproc = NULL; |
| 868 | |
| 869 | #else /* SMP or CPU_ENABLE_SSE */ |
| 870 | |
| 871 | u_char icu1_mask; |
| 872 | u_char icu2_mask; |
| 873 | u_char old_icu1_mask; |
| 874 | u_char old_icu2_mask; |
| 875 | struct gate_descriptor save_idt_npxintr; |
| 876 | |
| 877 | disable_intr(); |
| 878 | old_icu1_mask = inb(IO_ICU1 + 1); |
| 879 | old_icu2_mask = inb(IO_ICU2 + 1); |
| 880 | save_idt_npxintr = idt[npx_intrno]; |
| 881 | outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); |
| 882 | outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); |
| 883 | idt[npx_intrno] = npx_idt_probeintr; |
| 884 | enable_intr(); |
| 885 | stop_emulating(); |
| 886 | fnsave(addr); |
| 887 | fnop(); |
| 888 | start_emulating(); |
| 889 | npxproc = NULL; |
| 890 | disable_intr(); |
| 891 | icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ |
| 892 | icu2_mask = inb(IO_ICU2 + 1); |
| 893 | outb(IO_ICU1 + 1, |
| 894 | (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); |
| 895 | outb(IO_ICU2 + 1, |
| 896 | (icu2_mask & ~(npx0_imask >> 8)) |
| 897 | | (old_icu2_mask & (npx0_imask >> 8))); |
| 898 | idt[npx_intrno] = save_idt_npxintr; |
| 899 | enable_intr(); /* back to usual state */ |
| 900 | |
| 901 | #endif /* SMP */ |
| 902 | } |
| 903 | |
| 904 | static void |
| 905 | fpusave(addr) |
| 906 | union savefpu *addr; |
| 907 | { |
| 908 | |
| 909 | #ifdef CPU_ENABLE_SSE |
| 910 | if (cpu_fxsr) |
| 911 | fxsave(addr); |
| 912 | else |
| 913 | #endif |
| 914 | fnsave(addr); |
| 915 | } |
| 916 | |
| 917 | static void |
| 918 | fpurstor(addr) |
| 919 | union savefpu *addr; |
| 920 | { |
| 921 | |
| 922 | #ifdef CPU_ENABLE_SSE |
| 923 | if (cpu_fxsr) |
| 924 | fxrstor(addr); |
| 925 | else |
| 926 | #endif |
| 927 | frstor(addr); |
| 928 | } |
| 929 | |
| 930 | #ifdef I586_CPU |
| 931 | static long |
| 932 | timezero(funcname, func) |
| 933 | const char *funcname; |
| 934 | void (*func) __P((void *buf, size_t len)); |
| 935 | |
| 936 | { |
| 937 | void *buf; |
| 938 | #define BUFSIZE 1000000 |
| 939 | long usec; |
| 940 | struct timeval finish, start; |
| 941 | |
| 942 | buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); |
| 943 | if (buf == NULL) |
| 944 | return (BUFSIZE); |
| 945 | microtime(&start); |
| 946 | (*func)(buf, BUFSIZE); |
| 947 | microtime(&finish); |
| 948 | usec = 1000000 * (finish.tv_sec - start.tv_sec) + |
| 949 | finish.tv_usec - start.tv_usec; |
| 950 | if (usec <= 0) |
| 951 | usec = 1; |
| 952 | if (bootverbose) |
| 953 | printf("%s bandwidth = %ld bytes/sec\n", |
| 954 | funcname, (long)(BUFSIZE * (int64_t)1000000 / usec)); |
| 955 | free(buf, M_TEMP); |
| 956 | return (usec); |
| 957 | } |
| 958 | #endif /* I586_CPU */ |
| 959 | |
| 960 | static device_method_t npx_methods[] = { |
| 961 | /* Device interface */ |
| 962 | DEVMETHOD(device_identify, npx_identify), |
| 963 | DEVMETHOD(device_probe, npx_probe), |
| 964 | DEVMETHOD(device_attach, npx_attach), |
| 965 | DEVMETHOD(device_detach, bus_generic_detach), |
| 966 | DEVMETHOD(device_shutdown, bus_generic_shutdown), |
| 967 | DEVMETHOD(device_suspend, bus_generic_suspend), |
| 968 | DEVMETHOD(device_resume, bus_generic_resume), |
| 969 | |
| 970 | { 0, 0 } |
| 971 | }; |
| 972 | |
| 973 | static driver_t npx_driver = { |
| 974 | "npx", |
| 975 | npx_methods, |
| 976 | 1, /* no softc */ |
| 977 | }; |
| 978 | |
| 979 | static devclass_t npx_devclass; |
| 980 | |
| 981 | /* |
| 982 | * We prefer to attach to the root nexus so that the usual case (exception 16) |
| 983 | * doesn't describe the processor as being `on isa'. |
| 984 | */ |
| 985 | DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); |