| 1 | /*- |
| 2 | * Copyright (c) 1991 The Regents of the University of California. |
| 3 | * Copyright (c) 2008 The DragonFly Project. |
| 4 | * All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 4. Neither the name of the University nor the names of its contributors |
| 15 | * may be used to endorse or promote products derived from this software |
| 16 | * without specific prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
| 19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
| 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 28 | * SUCH DAMAGE. |
| 29 | * |
| 30 | * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 |
| 31 | * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.39 2007/05/31 11:26:44 des Exp $ |
| 32 | * $DragonFly: src/sys/cpu/amd64/include/specialreg.h,v 1.2 2008/08/29 17:07:06 dillon Exp $ |
| 33 | */ |
| 34 | |
| 35 | #ifndef _CPU_SPECIALREG_H_ |
| 36 | #define _CPU_SPECIALREG_H_ |
| 37 | |
| 38 | /* |
| 39 | * Bits in 386 special registers: |
| 40 | */ |
| 41 | #define CR0_PE 0x00000001 /* Protected mode Enable */ |
| 42 | #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ |
| 43 | #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ |
| 44 | #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ |
| 45 | #define CR0_PG 0x80000000 /* PaGing enable */ |
| 46 | |
| 47 | /* |
| 48 | * Bits in 486 special registers: |
| 49 | */ |
| 50 | #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ |
| 51 | #define CR0_WP 0x00010000 /* Write Protect (honor page protect in |
| 52 | all modes) */ |
| 53 | #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ |
| 54 | #define CR0_NW 0x20000000 /* Not Write-through */ |
| 55 | #define CR0_CD 0x40000000 /* Cache Disable */ |
| 56 | |
| 57 | /* |
| 58 | * Bits in PPro special registers |
| 59 | */ |
| 60 | #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ |
| 61 | #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ |
| 62 | #define CR4_TSD 0x00000004 /* Time stamp disable */ |
| 63 | #define CR4_DE 0x00000008 /* Debugging extensions */ |
| 64 | #define CR4_PSE 0x00000010 /* Page size extensions */ |
| 65 | #define CR4_PAE 0x00000020 /* Physical address extension */ |
| 66 | #define CR4_MCE 0x00000040 /* Machine check enable */ |
| 67 | #define CR4_PGE 0x00000080 /* Page global enable */ |
| 68 | #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ |
| 69 | #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ |
| 70 | #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ |
| 71 | |
| 72 | /* |
| 73 | * Bits in AMD64 special registers. EFER is 64 bits wide. |
| 74 | */ |
| 75 | #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ |
| 76 | #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ |
| 77 | #define EFER_LMA 0x000000400 /* Long mode active (R) */ |
| 78 | #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ |
| 79 | |
| 80 | /* |
| 81 | * CPUID instruction features register |
| 82 | */ |
| 83 | #define CPUID_FPU 0x00000001 |
| 84 | #define CPUID_VME 0x00000002 |
| 85 | #define CPUID_DE 0x00000004 |
| 86 | #define CPUID_PSE 0x00000008 |
| 87 | #define CPUID_TSC 0x00000010 |
| 88 | #define CPUID_MSR 0x00000020 |
| 89 | #define CPUID_PAE 0x00000040 |
| 90 | #define CPUID_MCE 0x00000080 |
| 91 | #define CPUID_CX8 0x00000100 |
| 92 | #define CPUID_APIC 0x00000200 |
| 93 | #define CPUID_B10 0x00000400 |
| 94 | #define CPUID_SEP 0x00000800 |
| 95 | #define CPUID_MTRR 0x00001000 |
| 96 | #define CPUID_PGE 0x00002000 |
| 97 | #define CPUID_MCA 0x00004000 |
| 98 | #define CPUID_CMOV 0x00008000 |
| 99 | #define CPUID_PAT 0x00010000 |
| 100 | #define CPUID_PSE36 0x00020000 |
| 101 | #define CPUID_PSN 0x00040000 |
| 102 | #define CPUID_CLFSH 0x00080000 |
| 103 | #define CPUID_B20 0x00100000 |
| 104 | #define CPUID_DS 0x00200000 |
| 105 | #define CPUID_ACPI 0x00400000 |
| 106 | #define CPUID_MMX 0x00800000 |
| 107 | #define CPUID_FXSR 0x01000000 |
| 108 | #define CPUID_SSE 0x02000000 |
| 109 | #define CPUID_XMM 0x02000000 |
| 110 | #define CPUID_SSE2 0x04000000 |
| 111 | #define CPUID_SS 0x08000000 |
| 112 | #define CPUID_HTT 0x10000000 |
| 113 | #define CPUID_TM 0x20000000 |
| 114 | #define CPUID_IA64 0x40000000 |
| 115 | #define CPUID_PBE 0x80000000 |
| 116 | |
| 117 | #define CPUID2_SSE3 0x00000001 |
| 118 | #define CPUID2_MON 0x00000008 |
| 119 | #define CPUID2_DS_CPL 0x00000010 |
| 120 | #define CPUID2_VMX 0x00000020 |
| 121 | #define CPUID2_SMX 0x00000040 |
| 122 | #define CPUID2_EST 0x00000080 |
| 123 | #define CPUID2_TM2 0x00000100 |
| 124 | #define CPUID2_SSSE3 0x00000200 |
| 125 | #define CPUID2_CNXTID 0x00000400 |
| 126 | #define CPUID2_CX16 0x00002000 |
| 127 | #define CPUID2_XTPR 0x00004000 |
| 128 | #define CPUID2_PDCM 0x00008000 |
| 129 | #define CPUID2_DCA 0x00040000 |
| 130 | |
| 131 | /* |
| 132 | * Important bits in the AMD extended cpuid flags |
| 133 | */ |
| 134 | #define AMDID_SYSCALL 0x00000800 |
| 135 | #define AMDID_MP 0x00080000 |
| 136 | #define AMDID_NX 0x00100000 |
| 137 | #define AMDID_EXT_MMX 0x00400000 |
| 138 | #define AMDID_FFXSR 0x01000000 |
| 139 | #define AMDID_PAGE1GB 0x04000000 |
| 140 | #define AMDID_RDTSCP 0x08000000 |
| 141 | #define AMDID_LM 0x20000000 |
| 142 | #define AMDID_EXT_3DNOW 0x40000000 |
| 143 | #define AMDID_3DNOW 0x80000000 |
| 144 | |
| 145 | #define AMDID2_LAHF 0x00000001 |
| 146 | #define AMDID2_CMP 0x00000002 |
| 147 | #define AMDID2_SVM 0x00000004 |
| 148 | #define AMDID2_EXT_APIC 0x00000008 |
| 149 | #define AMDID2_CR8 0x00000010 |
| 150 | #define AMDID2_PREFETCH 0x00000100 |
| 151 | |
| 152 | /* |
| 153 | * CPUID instruction 1 ebx info |
| 154 | */ |
| 155 | #define CPUID_BRAND_INDEX 0x000000ff |
| 156 | #define CPUID_CLFUSH_SIZE 0x0000ff00 |
| 157 | #define CPUID_HTT_CORES 0x00ff0000 |
| 158 | #define CPUID_LOCAL_APIC_ID 0xff000000 |
| 159 | |
| 160 | /* |
| 161 | * AMD extended function 8000_0008h ecx info |
| 162 | */ |
| 163 | #define AMDID_CMP_CORES 0x000000ff |
| 164 | |
| 165 | /* |
| 166 | * Model-specific registers for the i386 family |
| 167 | */ |
| 168 | #define MSR_P5_MC_ADDR 0x000 |
| 169 | #define MSR_P5_MC_TYPE 0x001 |
| 170 | #define MSR_TSC 0x010 |
| 171 | #define MSR_P5_CESR 0x011 |
| 172 | #define MSR_P5_CTR0 0x012 |
| 173 | #define MSR_P5_CTR1 0x013 |
| 174 | #define MSR_IA32_PLATFORM_ID 0x017 |
| 175 | #define MSR_APICBASE 0x01b |
| 176 | #define MSR_EBL_CR_POWERON 0x02a |
| 177 | #define MSR_TEST_CTL 0x033 |
| 178 | #define MSR_BIOS_UPDT_TRIG 0x079 |
| 179 | #define MSR_BBL_CR_D0 0x088 |
| 180 | #define MSR_BBL_CR_D1 0x089 |
| 181 | #define MSR_BBL_CR_D2 0x08a |
| 182 | #define MSR_BIOS_SIGN 0x08b |
| 183 | #define MSR_PERFCTR0 0x0c1 |
| 184 | #define MSR_PERFCTR1 0x0c2 |
| 185 | #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ |
| 186 | #define MSR_MTRRcap 0x0fe |
| 187 | #define MSR_BBL_CR_ADDR 0x116 |
| 188 | #define MSR_BBL_CR_DECC 0x118 |
| 189 | #define MSR_BBL_CR_CTL 0x119 |
| 190 | #define MSR_BBL_CR_TRIG 0x11a |
| 191 | #define MSR_BBL_CR_BUSY 0x11b |
| 192 | #define MSR_BBL_CR_CTL3 0x11e |
| 193 | #define MSR_SYSENTER_CS_MSR 0x174 |
| 194 | #define MSR_SYSENTER_ESP_MSR 0x175 |
| 195 | #define MSR_SYSENTER_EIP_MSR 0x176 |
| 196 | #define MSR_MCG_CAP 0x179 |
| 197 | #define MSR_MCG_STATUS 0x17a |
| 198 | #define MSR_MCG_CTL 0x17b |
| 199 | #define MSR_EVNTSEL0 0x186 |
| 200 | #define MSR_EVNTSEL1 0x187 |
| 201 | #define MSR_THERM_CONTROL 0x19a |
| 202 | #define MSR_THERM_INTERRUPT 0x19b |
| 203 | #define MSR_THERM_STATUS 0x19c |
| 204 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
| 205 | #define MSR_DEBUGCTLMSR 0x1d9 |
| 206 | #define MSR_LASTBRANCHFROMIP 0x1db |
| 207 | #define MSR_LASTBRANCHTOIP 0x1dc |
| 208 | #define MSR_LASTINTFROMIP 0x1dd |
| 209 | #define MSR_LASTINTTOIP 0x1de |
| 210 | #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 |
| 211 | #define MSR_MTRRVarBase 0x200 |
| 212 | #define MSR_MTRR64kBase 0x250 |
| 213 | #define MSR_MTRR16kBase 0x258 |
| 214 | #define MSR_MTRR4kBase 0x268 |
| 215 | #define MSR_PAT 0x277 |
| 216 | #define MSR_MTRRdefType 0x2ff |
| 217 | #define MSR_MC0_CTL 0x400 |
| 218 | #define MSR_MC0_STATUS 0x401 |
| 219 | #define MSR_MC0_ADDR 0x402 |
| 220 | #define MSR_MC0_MISC 0x403 |
| 221 | #define MSR_MC1_CTL 0x404 |
| 222 | #define MSR_MC1_STATUS 0x405 |
| 223 | #define MSR_MC1_ADDR 0x406 |
| 224 | #define MSR_MC1_MISC 0x407 |
| 225 | #define MSR_MC2_CTL 0x408 |
| 226 | #define MSR_MC2_STATUS 0x409 |
| 227 | #define MSR_MC2_ADDR 0x40a |
| 228 | #define MSR_MC2_MISC 0x40b |
| 229 | #define MSR_MC3_CTL 0x40c |
| 230 | #define MSR_MC3_STATUS 0x40d |
| 231 | #define MSR_MC3_ADDR 0x40e |
| 232 | #define MSR_MC3_MISC 0x40f |
| 233 | #define MSR_MC4_CTL 0x410 |
| 234 | #define MSR_MC4_STATUS 0x411 |
| 235 | #define MSR_MC4_ADDR 0x412 |
| 236 | #define MSR_MC4_MISC 0x413 |
| 237 | |
| 238 | /* |
| 239 | * Constants related to MSR's. |
| 240 | */ |
| 241 | #define APICBASE_RESERVED 0x000006ff |
| 242 | #define APICBASE_BSP 0x00000100 |
| 243 | #define APICBASE_ENABLED 0x00000800 |
| 244 | #define APICBASE_ADDRESS 0xfffff000 |
| 245 | |
| 246 | /* |
| 247 | * PAT modes. |
| 248 | */ |
| 249 | #define PAT_UNCACHEABLE 0x00 |
| 250 | #define PAT_WRITE_COMBINING 0x01 |
| 251 | #define PAT_WRITE_THROUGH 0x04 |
| 252 | #define PAT_WRITE_PROTECTED 0x05 |
| 253 | #define PAT_WRITE_BACK 0x06 |
| 254 | #define PAT_UNCACHED 0x07 |
| 255 | #define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) |
| 256 | #define PAT_MASK(i) PAT_VALUE(i, 0xff) |
| 257 | |
| 258 | /* |
| 259 | * Constants related to MTRRs |
| 260 | */ |
| 261 | #define MTRR_N64K 8 /* numbers of fixed-size entries */ |
| 262 | #define MTRR_N16K 16 |
| 263 | #define MTRR_N4K 64 |
| 264 | |
| 265 | /* Performance Control Register (5x86 only). */ |
| 266 | #define PCR0 0x20 |
| 267 | #define PCR0_RSTK 0x01 /* Enables return stack */ |
| 268 | #define PCR0_BTB 0x02 /* Enables branch target buffer */ |
| 269 | #define PCR0_LOOP 0x04 /* Enables loop */ |
| 270 | #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to |
| 271 | serialize pipe. */ |
| 272 | #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ |
| 273 | #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ |
| 274 | #define PCR0_LSSER 0x80 /* Disable reorder */ |
| 275 | |
| 276 | /* Device Identification Registers */ |
| 277 | #define DIR0 0xfe |
| 278 | #define DIR1 0xff |
| 279 | |
| 280 | /* |
| 281 | * The following four 3-byte registers control the non-cacheable regions. |
| 282 | * These registers must be written as three separate bytes. |
| 283 | * |
| 284 | * NCRx+0: A31-A24 of starting address |
| 285 | * NCRx+1: A23-A16 of starting address |
| 286 | * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. |
| 287 | * |
| 288 | * The non-cacheable region's starting address must be aligned to the |
| 289 | * size indicated by the NCR_SIZE_xx field. |
| 290 | */ |
| 291 | #define NCR1 0xc4 |
| 292 | #define NCR2 0xc7 |
| 293 | #define NCR3 0xca |
| 294 | #define NCR4 0xcd |
| 295 | |
| 296 | #define NCR_SIZE_0K 0 |
| 297 | #define NCR_SIZE_4K 1 |
| 298 | #define NCR_SIZE_8K 2 |
| 299 | #define NCR_SIZE_16K 3 |
| 300 | #define NCR_SIZE_32K 4 |
| 301 | #define NCR_SIZE_64K 5 |
| 302 | #define NCR_SIZE_128K 6 |
| 303 | #define NCR_SIZE_256K 7 |
| 304 | #define NCR_SIZE_512K 8 |
| 305 | #define NCR_SIZE_1M 9 |
| 306 | #define NCR_SIZE_2M 10 |
| 307 | #define NCR_SIZE_4M 11 |
| 308 | #define NCR_SIZE_8M 12 |
| 309 | #define NCR_SIZE_16M 13 |
| 310 | #define NCR_SIZE_32M 14 |
| 311 | #define NCR_SIZE_4G 15 |
| 312 | |
| 313 | /* |
| 314 | * The address region registers are used to specify the location and |
| 315 | * size for the eight address regions. |
| 316 | * |
| 317 | * ARRx + 0: A31-A24 of start address |
| 318 | * ARRx + 1: A23-A16 of start address |
| 319 | * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx |
| 320 | */ |
| 321 | #define ARR0 0xc4 |
| 322 | #define ARR1 0xc7 |
| 323 | #define ARR2 0xca |
| 324 | #define ARR3 0xcd |
| 325 | #define ARR4 0xd0 |
| 326 | #define ARR5 0xd3 |
| 327 | #define ARR6 0xd6 |
| 328 | #define ARR7 0xd9 |
| 329 | |
| 330 | #define ARR_SIZE_0K 0 |
| 331 | #define ARR_SIZE_4K 1 |
| 332 | #define ARR_SIZE_8K 2 |
| 333 | #define ARR_SIZE_16K 3 |
| 334 | #define ARR_SIZE_32K 4 |
| 335 | #define ARR_SIZE_64K 5 |
| 336 | #define ARR_SIZE_128K 6 |
| 337 | #define ARR_SIZE_256K 7 |
| 338 | #define ARR_SIZE_512K 8 |
| 339 | #define ARR_SIZE_1M 9 |
| 340 | #define ARR_SIZE_2M 10 |
| 341 | #define ARR_SIZE_4M 11 |
| 342 | #define ARR_SIZE_8M 12 |
| 343 | #define ARR_SIZE_16M 13 |
| 344 | #define ARR_SIZE_32M 14 |
| 345 | #define ARR_SIZE_4G 15 |
| 346 | |
| 347 | /* |
| 348 | * The region control registers specify the attributes associated with |
| 349 | * the ARRx addres regions. |
| 350 | */ |
| 351 | #define RCR0 0xdc |
| 352 | #define RCR1 0xdd |
| 353 | #define RCR2 0xde |
| 354 | #define RCR3 0xdf |
| 355 | #define RCR4 0xe0 |
| 356 | #define RCR5 0xe1 |
| 357 | #define RCR6 0xe2 |
| 358 | #define RCR7 0xe3 |
| 359 | |
| 360 | #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ |
| 361 | #define RCR_RCE 0x01 /* Enables caching for ARR7. */ |
| 362 | #define RCR_WWO 0x02 /* Weak write ordering. */ |
| 363 | #define RCR_WL 0x04 /* Weak locking. */ |
| 364 | #define RCR_WG 0x08 /* Write gathering. */ |
| 365 | #define RCR_WT 0x10 /* Write-through. */ |
| 366 | #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ |
| 367 | |
| 368 | /* AMD Write Allocate Top-Of-Memory and Control Register */ |
| 369 | #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ |
| 370 | #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ |
| 371 | #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ |
| 372 | |
| 373 | /* AMD64 MSR's */ |
| 374 | #define MSR_EFER 0xc0000080 /* extended features */ |
| 375 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ |
| 376 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ |
| 377 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ |
| 378 | #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ |
| 379 | #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ |
| 380 | #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ |
| 381 | #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ |
| 382 | #define MSR_PERFEVSEL0 0xc0010000 |
| 383 | #define MSR_PERFEVSEL1 0xc0010001 |
| 384 | #define MSR_PERFEVSEL2 0xc0010002 |
| 385 | #define MSR_PERFEVSEL3 0xc0010003 |
| 386 | #undef MSR_PERFCTR0 |
| 387 | #undef MSR_PERFCTR1 |
| 388 | #define MSR_PERFCTR0 0xc0010004 |
| 389 | #define MSR_PERFCTR1 0xc0010005 |
| 390 | #define MSR_PERFCTR2 0xc0010006 |
| 391 | #define MSR_PERFCTR3 0xc0010007 |
| 392 | #define MSR_SYSCFG 0xc0010010 |
| 393 | #define MSR_IORRBASE0 0xc0010016 |
| 394 | #define MSR_IORRMASK0 0xc0010017 |
| 395 | #define MSR_IORRBASE1 0xc0010018 |
| 396 | #define MSR_IORRMASK1 0xc0010019 |
| 397 | #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ |
| 398 | #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ |
| 399 | |
| 400 | #endif /* !_CPU_SPECIALREG_H_ */ |