| 1 | /* |
| 2 | * Copyright (c) 1996, by Steve Passe |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * 1. Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * 2. The name of the developer may NOT be used to endorse or promote products |
| 11 | * derived from this software without specific prior written permission. |
| 12 | * |
| 13 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 14 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 16 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 17 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 18 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 19 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 21 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 22 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 23 | * SUCH DAMAGE. |
| 24 | * |
| 25 | * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $ |
| 26 | * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.3 2003/07/04 00:32:24 dillon Exp $ |
| 27 | */ |
| 28 | |
| 29 | #include <sys/param.h> |
| 30 | #include <sys/systm.h> |
| 31 | #include <machine/smptests.h> /** TEST_TEST1, GRAB_LOPRIO */ |
| 32 | #include <machine/globaldata.h> |
| 33 | #include <machine/smp.h> |
| 34 | #include <machine/mpapic.h> |
| 35 | #include <machine/segments.h> |
| 36 | |
| 37 | #include <i386/isa/intr_machdep.h> /* Xspuriousint() */ |
| 38 | |
| 39 | /* EISA Edge/Level trigger control registers */ |
| 40 | #define ELCR0 0x4d0 /* eisa irq 0-7 */ |
| 41 | #define ELCR1 0x4d1 /* eisa irq 8-15 */ |
| 42 | |
| 43 | /* |
| 44 | * pointers to pmapped apic hardware. |
| 45 | */ |
| 46 | |
| 47 | #if defined(APIC_IO) |
| 48 | volatile ioapic_t **ioapic; |
| 49 | #endif /* APIC_IO */ |
| 50 | |
| 51 | /* |
| 52 | * Enable APIC, configure interrupts. |
| 53 | */ |
| 54 | void |
| 55 | apic_initialize(void) |
| 56 | { |
| 57 | u_int temp; |
| 58 | |
| 59 | /* setup LVT1 as ExtINT */ |
| 60 | temp = lapic.lvt_lint0; |
| 61 | temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM); |
| 62 | if (mycpu->gd_cpuid == 0) |
| 63 | temp |= 0x00000700; /* process ExtInts */ |
| 64 | else |
| 65 | temp |= 0x00010700; /* mask ExtInts */ |
| 66 | lapic.lvt_lint0 = temp; |
| 67 | |
| 68 | /* setup LVT2 as NMI, masked till later... */ |
| 69 | temp = lapic.lvt_lint1; |
| 70 | temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM); |
| 71 | temp |= 0x00010400; /* masked, edge trigger, active hi */ |
| 72 | lapic.lvt_lint1 = temp; |
| 73 | |
| 74 | /* set the Task Priority Register as needed */ |
| 75 | temp = lapic.tpr; |
| 76 | temp &= ~APIC_TPR_PRIO; /* clear priority field */ |
| 77 | #ifdef GRAB_LOPRIO |
| 78 | /* Leave the BSP at TPR 0 during boot to make sure it gets interrupts */ |
| 79 | if (mycpu->gd_cpuid != 0) |
| 80 | temp |= LOPRIO_LEVEL; /* allow INT arbitration */ |
| 81 | #endif |
| 82 | lapic.tpr = temp; |
| 83 | |
| 84 | /* enable the local APIC */ |
| 85 | temp = lapic.svr; |
| 86 | temp |= APIC_SVR_SWEN; /* software enable APIC */ |
| 87 | temp &= ~APIC_SVR_FOCUS; /* enable 'focus processor' */ |
| 88 | |
| 89 | /* set the 'spurious INT' vector */ |
| 90 | if ((XSPURIOUSINT_OFFSET & APIC_SVR_VEC_FIX) != APIC_SVR_VEC_FIX) |
| 91 | panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET); |
| 92 | temp &= ~APIC_SVR_VEC_PROG; /* clear (programmable) vector field */ |
| 93 | temp |= (XSPURIOUSINT_OFFSET & APIC_SVR_VEC_PROG); |
| 94 | |
| 95 | #if defined(TEST_TEST1) |
| 96 | if (cpuid == GUARD_CPU) { |
| 97 | temp &= ~APIC_SVR_SWEN; /* software DISABLE APIC */ |
| 98 | } |
| 99 | #endif /** TEST_TEST1 */ |
| 100 | |
| 101 | lapic.svr = temp; |
| 102 | |
| 103 | if (bootverbose) |
| 104 | apic_dump("apic_initialize()"); |
| 105 | } |
| 106 | |
| 107 | |
| 108 | /* |
| 109 | * dump contents of local APIC registers |
| 110 | */ |
| 111 | void |
| 112 | apic_dump(char* str) |
| 113 | { |
| 114 | printf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str); |
| 115 | printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", |
| 116 | lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr); |
| 117 | } |
| 118 | |
| 119 | |
| 120 | #if defined(APIC_IO) |
| 121 | |
| 122 | /* |
| 123 | * IO APIC code, |
| 124 | */ |
| 125 | |
| 126 | #define IOAPIC_ISA_INTS 16 |
| 127 | #define REDIRCNT_IOAPIC(A) \ |
| 128 | ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1) |
| 129 | |
| 130 | static int trigger __P((int apic, int pin, u_int32_t * flags)); |
| 131 | static void polarity __P((int apic, int pin, u_int32_t * flags, int level)); |
| 132 | |
| 133 | #define DEFAULT_FLAGS \ |
| 134 | ((u_int32_t) \ |
| 135 | (IOART_INTMSET | \ |
| 136 | IOART_DESTPHY | \ |
| 137 | IOART_DELLOPRI)) |
| 138 | |
| 139 | #define DEFAULT_ISA_FLAGS \ |
| 140 | ((u_int32_t) \ |
| 141 | (IOART_INTMSET | \ |
| 142 | IOART_TRGREDG | \ |
| 143 | IOART_INTAHI | \ |
| 144 | IOART_DESTPHY | \ |
| 145 | IOART_DELLOPRI)) |
| 146 | |
| 147 | void |
| 148 | io_apic_set_id(int apic, int id) |
| 149 | { |
| 150 | u_int32_t ux; |
| 151 | |
| 152 | ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */ |
| 153 | if (((ux & APIC_ID_MASK) >> 24) != id) { |
| 154 | printf("Changing APIC ID for IO APIC #%d" |
| 155 | " from %d to %d on chip\n", |
| 156 | apic, ((ux & APIC_ID_MASK) >> 24), id); |
| 157 | ux &= ~APIC_ID_MASK; /* clear the ID field */ |
| 158 | ux |= (id << 24); |
| 159 | io_apic_write(apic, IOAPIC_ID, ux); /* write new value */ |
| 160 | ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */ |
| 161 | if (((ux & APIC_ID_MASK) >> 24) != id) |
| 162 | panic("can't control IO APIC #%d ID, reg: 0x%08x", |
| 163 | apic, ux); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | |
| 168 | int |
| 169 | io_apic_get_id(int apic) |
| 170 | { |
| 171 | return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24; |
| 172 | } |
| 173 | |
| 174 | |
| 175 | |
| 176 | /* |
| 177 | * Setup the IO APIC. |
| 178 | */ |
| 179 | |
| 180 | extern int apic_pin_trigger; /* 'opaque' */ |
| 181 | |
| 182 | void |
| 183 | io_apic_setup_intpin(int apic, int pin) |
| 184 | { |
| 185 | int bus, bustype, irq; |
| 186 | u_char select; /* the select register is 8 bits */ |
| 187 | u_int32_t flags; /* the window register is 32 bits */ |
| 188 | u_int32_t target; /* the window register is 32 bits */ |
| 189 | u_int32_t vector; /* the window register is 32 bits */ |
| 190 | int level; |
| 191 | u_int eflags; |
| 192 | |
| 193 | target = IOART_DEST; |
| 194 | |
| 195 | select = pin * 2 + IOAPIC_REDTBL0; /* register */ |
| 196 | /* |
| 197 | * Always disable interrupts, and by default map |
| 198 | * pin X to IRQX because the disable doesn't stick |
| 199 | * and the uninitialize vector will get translated |
| 200 | * into a panic. |
| 201 | * |
| 202 | * This is correct for IRQs 1 and 3-15. In the other cases, |
| 203 | * any robust driver will handle the spurious interrupt, and |
| 204 | * the effective NOP beats a panic. |
| 205 | * |
| 206 | * A dedicated "bogus interrupt" entry in the IDT would |
| 207 | * be a nicer hack, although some one should find out |
| 208 | * why some systems are generating interrupts when they |
| 209 | * shouldn't and stop the carnage. |
| 210 | */ |
| 211 | vector = NRSVIDT + pin; /* IDT vec */ |
| 212 | eflags = read_eflags(); |
| 213 | __asm __volatile("cli" : : : "memory"); |
| 214 | s_lock(&imen_lock); |
| 215 | io_apic_write(apic, select, |
| 216 | (io_apic_read(apic, select) & ~IOART_INTMASK |
| 217 | & ~0xff)|IOART_INTMSET|vector); |
| 218 | s_unlock(&imen_lock); |
| 219 | write_eflags(eflags); |
| 220 | |
| 221 | /* we only deal with vectored INTs here */ |
| 222 | if (apic_int_type(apic, pin) != 0) |
| 223 | return; |
| 224 | |
| 225 | irq = apic_irq(apic, pin); |
| 226 | if (irq < 0) |
| 227 | return; |
| 228 | |
| 229 | /* determine the bus type for this pin */ |
| 230 | bus = apic_src_bus_id(apic, pin); |
| 231 | if (bus == -1) |
| 232 | return; |
| 233 | bustype = apic_bus_type(bus); |
| 234 | |
| 235 | if ((bustype == ISA) && |
| 236 | (pin < IOAPIC_ISA_INTS) && |
| 237 | (irq == pin) && |
| 238 | (apic_polarity(apic, pin) == 0x1) && |
| 239 | (apic_trigger(apic, pin) == 0x3)) { |
| 240 | /* |
| 241 | * A broken BIOS might describe some ISA |
| 242 | * interrupts as active-high level-triggered. |
| 243 | * Use default ISA flags for those interrupts. |
| 244 | */ |
| 245 | flags = DEFAULT_ISA_FLAGS; |
| 246 | } else { |
| 247 | /* |
| 248 | * Program polarity and trigger mode according to |
| 249 | * interrupt entry. |
| 250 | */ |
| 251 | flags = DEFAULT_FLAGS; |
| 252 | level = trigger(apic, pin, &flags); |
| 253 | if (level == 1) |
| 254 | apic_pin_trigger |= (1 << irq); |
| 255 | polarity(apic, pin, &flags, level); |
| 256 | } |
| 257 | |
| 258 | /* program the appropriate registers */ |
| 259 | if (apic != 0 || pin != irq) |
| 260 | printf("IOAPIC #%d intpin %d -> irq %d\n", |
| 261 | apic, pin, irq); |
| 262 | vector = NRSVIDT + irq; /* IDT vec */ |
| 263 | eflags = read_eflags(); |
| 264 | __asm __volatile("cli" : : : "memory"); |
| 265 | s_lock(&imen_lock); |
| 266 | io_apic_write(apic, select, flags | vector); |
| 267 | io_apic_write(apic, select + 1, target); |
| 268 | s_unlock(&imen_lock); |
| 269 | write_eflags(eflags); |
| 270 | } |
| 271 | |
| 272 | int |
| 273 | io_apic_setup(int apic) |
| 274 | { |
| 275 | int maxpin; |
| 276 | int pin; |
| 277 | |
| 278 | if (apic == 0) |
| 279 | apic_pin_trigger = 0; /* default to edge-triggered */ |
| 280 | |
| 281 | maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */ |
| 282 | printf("Programming %d pins in IOAPIC #%d\n", maxpin, apic); |
| 283 | |
| 284 | for (pin = 0; pin < maxpin; ++pin) { |
| 285 | io_apic_setup_intpin(apic, pin); |
| 286 | } |
| 287 | |
| 288 | /* return GOOD status */ |
| 289 | return 0; |
| 290 | } |
| 291 | #undef DEFAULT_ISA_FLAGS |
| 292 | #undef DEFAULT_FLAGS |
| 293 | |
| 294 | |
| 295 | #define DEFAULT_EXTINT_FLAGS \ |
| 296 | ((u_int32_t) \ |
| 297 | (IOART_INTMSET | \ |
| 298 | IOART_TRGREDG | \ |
| 299 | IOART_INTAHI | \ |
| 300 | IOART_DESTPHY | \ |
| 301 | IOART_DELLOPRI)) |
| 302 | |
| 303 | /* |
| 304 | * Setup the source of External INTerrupts. |
| 305 | */ |
| 306 | int |
| 307 | ext_int_setup(int apic, int intr) |
| 308 | { |
| 309 | u_char select; /* the select register is 8 bits */ |
| 310 | u_int32_t flags; /* the window register is 32 bits */ |
| 311 | u_int32_t target; /* the window register is 32 bits */ |
| 312 | u_int32_t vector; /* the window register is 32 bits */ |
| 313 | |
| 314 | if (apic_int_type(apic, intr) != 3) |
| 315 | return -1; |
| 316 | |
| 317 | target = IOART_DEST; |
| 318 | select = IOAPIC_REDTBL0 + (2 * intr); |
| 319 | vector = NRSVIDT + intr; |
| 320 | flags = DEFAULT_EXTINT_FLAGS; |
| 321 | |
| 322 | io_apic_write(apic, select, flags | vector); |
| 323 | io_apic_write(apic, select + 1, target); |
| 324 | |
| 325 | return 0; |
| 326 | } |
| 327 | #undef DEFAULT_EXTINT_FLAGS |
| 328 | |
| 329 | |
| 330 | /* |
| 331 | * Set the trigger level for an IO APIC pin. |
| 332 | */ |
| 333 | static int |
| 334 | trigger(int apic, int pin, u_int32_t * flags) |
| 335 | { |
| 336 | int id; |
| 337 | int eirq; |
| 338 | int level; |
| 339 | static int intcontrol = -1; |
| 340 | |
| 341 | switch (apic_trigger(apic, pin)) { |
| 342 | |
| 343 | case 0x00: |
| 344 | break; |
| 345 | |
| 346 | case 0x01: |
| 347 | *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */ |
| 348 | return 0; |
| 349 | |
| 350 | case 0x03: |
| 351 | *flags |= IOART_TRGRLVL; |
| 352 | return 1; |
| 353 | |
| 354 | case -1: |
| 355 | default: |
| 356 | goto bad; |
| 357 | } |
| 358 | |
| 359 | if ((id = apic_src_bus_id(apic, pin)) == -1) |
| 360 | goto bad; |
| 361 | |
| 362 | switch (apic_bus_type(id)) { |
| 363 | case ISA: |
| 364 | *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */ |
| 365 | return 0; |
| 366 | |
| 367 | case EISA: |
| 368 | eirq = apic_src_bus_irq(apic, pin); |
| 369 | |
| 370 | if (eirq < 0 || eirq > 15) { |
| 371 | printf("EISA IRQ %d?!?!\n", eirq); |
| 372 | goto bad; |
| 373 | } |
| 374 | |
| 375 | if (intcontrol == -1) { |
| 376 | intcontrol = inb(ELCR1) << 8; |
| 377 | intcontrol |= inb(ELCR0); |
| 378 | printf("EISA INTCONTROL = %08x\n", intcontrol); |
| 379 | } |
| 380 | |
| 381 | /* Use ELCR settings to determine level or edge mode */ |
| 382 | level = (intcontrol >> eirq) & 1; |
| 383 | |
| 384 | /* |
| 385 | * Note that on older Neptune chipset based systems, any |
| 386 | * pci interrupts often show up here and in the ELCR as well |
| 387 | * as level sensitive interrupts attributed to the EISA bus. |
| 388 | */ |
| 389 | |
| 390 | if (level) |
| 391 | *flags |= IOART_TRGRLVL; |
| 392 | else |
| 393 | *flags &= ~IOART_TRGRLVL; |
| 394 | |
| 395 | return level; |
| 396 | |
| 397 | case PCI: |
| 398 | *flags |= IOART_TRGRLVL; |
| 399 | return 1; |
| 400 | |
| 401 | case -1: |
| 402 | default: |
| 403 | goto bad; |
| 404 | } |
| 405 | |
| 406 | bad: |
| 407 | panic("bad APIC IO INT flags"); |
| 408 | } |
| 409 | |
| 410 | |
| 411 | /* |
| 412 | * Set the polarity value for an IO APIC pin. |
| 413 | */ |
| 414 | static void |
| 415 | polarity(int apic, int pin, u_int32_t * flags, int level) |
| 416 | { |
| 417 | int id; |
| 418 | |
| 419 | switch (apic_polarity(apic, pin)) { |
| 420 | |
| 421 | case 0x00: |
| 422 | break; |
| 423 | |
| 424 | case 0x01: |
| 425 | *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */ |
| 426 | return; |
| 427 | |
| 428 | case 0x03: |
| 429 | *flags |= IOART_INTALO; |
| 430 | return; |
| 431 | |
| 432 | case -1: |
| 433 | default: |
| 434 | goto bad; |
| 435 | } |
| 436 | |
| 437 | if ((id = apic_src_bus_id(apic, pin)) == -1) |
| 438 | goto bad; |
| 439 | |
| 440 | switch (apic_bus_type(id)) { |
| 441 | case ISA: |
| 442 | *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */ |
| 443 | return; |
| 444 | |
| 445 | case EISA: |
| 446 | /* polarity converter always gives active high */ |
| 447 | *flags &= ~IOART_INTALO; |
| 448 | return; |
| 449 | |
| 450 | case PCI: |
| 451 | *flags |= IOART_INTALO; |
| 452 | return; |
| 453 | |
| 454 | case -1: |
| 455 | default: |
| 456 | goto bad; |
| 457 | } |
| 458 | |
| 459 | bad: |
| 460 | panic("bad APIC IO INT flags"); |
| 461 | } |
| 462 | |
| 463 | |
| 464 | /* |
| 465 | * Print contents of apic_imen. |
| 466 | */ |
| 467 | extern u_int apic_imen; /* keep apic_imen 'opaque' */ |
| 468 | void |
| 469 | imen_dump(void) |
| 470 | { |
| 471 | int x; |
| 472 | |
| 473 | printf("SMP: enabled INTs: "); |
| 474 | for (x = 0; x < 24; ++x) |
| 475 | if ((apic_imen & (1 << x)) == 0) |
| 476 | printf("%d, ", x); |
| 477 | printf("apic_imen: 0x%08x\n", apic_imen); |
| 478 | } |
| 479 | |
| 480 | |
| 481 | /* |
| 482 | * Inter Processor Interrupt functions. |
| 483 | */ |
| 484 | |
| 485 | |
| 486 | /* |
| 487 | * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'. |
| 488 | * |
| 489 | * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF |
| 490 | * vector is any valid SYSTEM INT vector |
| 491 | * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO |
| 492 | */ |
| 493 | #define DETECT_DEADLOCK |
| 494 | int |
| 495 | apic_ipi(int dest_type, int vector, int delivery_mode) |
| 496 | { |
| 497 | u_long icr_lo; |
| 498 | |
| 499 | #if defined(DETECT_DEADLOCK) |
| 500 | #define MAX_SPIN1 10000000 |
| 501 | #define MAX_SPIN2 1000 |
| 502 | int x; |
| 503 | |
| 504 | /* "lazy delivery", ie we only barf if they stack up on us... */ |
| 505 | for (x = MAX_SPIN1; x; --x) { |
| 506 | if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0) |
| 507 | break; |
| 508 | } |
| 509 | if (x == 0) |
| 510 | panic("apic_ipi was stuck"); |
| 511 | #endif /* DETECT_DEADLOCK */ |
| 512 | |
| 513 | /* build IRC_LOW */ |
| 514 | icr_lo = (lapic.icr_lo & APIC_RESV2_MASK) |
| 515 | | dest_type | delivery_mode | vector; |
| 516 | |
| 517 | /* write APIC ICR */ |
| 518 | lapic.icr_lo = icr_lo; |
| 519 | |
| 520 | /* wait for pending status end */ |
| 521 | #if defined(DETECT_DEADLOCK) |
| 522 | for (x = MAX_SPIN2; x; --x) { |
| 523 | if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0) |
| 524 | break; |
| 525 | } |
| 526 | #ifdef needsattention |
| 527 | /* |
| 528 | * XXX FIXME: |
| 529 | * The above loop waits for the message to actually be delivered. |
| 530 | * It breaks out after an arbitrary timout on the theory that it eventually |
| 531 | * will be delivered and we will catch a real failure on the next entry to |
| 532 | * this function, which would panic(). |
| 533 | * We could skip this wait entirely, EXCEPT it probably protects us from |
| 534 | * other "less robust" routines that assume the message was delivered and |
| 535 | * acted upon when this function returns. TLB shootdowns are one such |
| 536 | * "less robust" function. |
| 537 | */ |
| 538 | if (x == 0) |
| 539 | printf("apic_ipi might be stuck\n"); |
| 540 | #endif |
| 541 | #undef MAX_SPIN2 |
| 542 | #undef MAX_SPIN1 |
| 543 | #else |
| 544 | while (lapic.icr_lo & APIC_DELSTAT_MASK) |
| 545 | /* spin */ ; |
| 546 | #endif /* DETECT_DEADLOCK */ |
| 547 | |
| 548 | /** XXX FIXME: return result */ |
| 549 | return 0; |
| 550 | } |
| 551 | |
| 552 | static int |
| 553 | apic_ipi_singledest(int cpu, int vector, int delivery_mode) |
| 554 | { |
| 555 | u_long icr_lo; |
| 556 | u_long icr_hi; |
| 557 | u_long eflags; |
| 558 | |
| 559 | #if defined(DETECT_DEADLOCK) |
| 560 | #define MAX_SPIN1 10000000 |
| 561 | #define MAX_SPIN2 1000 |
| 562 | int x; |
| 563 | |
| 564 | /* "lazy delivery", ie we only barf if they stack up on us... */ |
| 565 | for (x = MAX_SPIN1; x; --x) { |
| 566 | if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0) |
| 567 | break; |
| 568 | } |
| 569 | if (x == 0) |
| 570 | panic("apic_ipi was stuck"); |
| 571 | #endif /* DETECT_DEADLOCK */ |
| 572 | |
| 573 | eflags = read_eflags(); |
| 574 | __asm __volatile("cli" : : : "memory"); |
| 575 | icr_hi = lapic.icr_hi & ~APIC_ID_MASK; |
| 576 | icr_hi |= (CPU_TO_ID(cpu) << 24); |
| 577 | lapic.icr_hi = icr_hi; |
| 578 | |
| 579 | /* build IRC_LOW */ |
| 580 | icr_lo = (lapic.icr_lo & APIC_RESV2_MASK) |
| 581 | | APIC_DEST_DESTFLD | delivery_mode | vector; |
| 582 | |
| 583 | /* write APIC ICR */ |
| 584 | lapic.icr_lo = icr_lo; |
| 585 | write_eflags(eflags); |
| 586 | |
| 587 | /* wait for pending status end */ |
| 588 | #if defined(DETECT_DEADLOCK) |
| 589 | for (x = MAX_SPIN2; x; --x) { |
| 590 | if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0) |
| 591 | break; |
| 592 | } |
| 593 | #ifdef needsattention |
| 594 | /* |
| 595 | * XXX FIXME: |
| 596 | * The above loop waits for the message to actually be delivered. |
| 597 | * It breaks out after an arbitrary timout on the theory that it eventually |
| 598 | * will be delivered and we will catch a real failure on the next entry to |
| 599 | * this function, which would panic(). |
| 600 | * We could skip this wait entirely, EXCEPT it probably protects us from |
| 601 | * other "less robust" routines that assume the message was delivered and |
| 602 | * acted upon when this function returns. TLB shootdowns are one such |
| 603 | * "less robust" function. |
| 604 | */ |
| 605 | if (x == 0) |
| 606 | printf("apic_ipi might be stuck\n"); |
| 607 | #endif |
| 608 | #undef MAX_SPIN2 |
| 609 | #undef MAX_SPIN1 |
| 610 | #else |
| 611 | while (lapic.icr_lo & APIC_DELSTAT_MASK) |
| 612 | /* spin */ ; |
| 613 | #endif /* DETECT_DEADLOCK */ |
| 614 | |
| 615 | /** XXX FIXME: return result */ |
| 616 | return 0; |
| 617 | } |
| 618 | |
| 619 | |
| 620 | /* |
| 621 | * Send APIC IPI 'vector' to 'target's via 'delivery_mode'. |
| 622 | * |
| 623 | * target contains a bitfield with a bit set for selected APICs. |
| 624 | * vector is any valid SYSTEM INT vector |
| 625 | * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO |
| 626 | */ |
| 627 | int |
| 628 | selected_apic_ipi(u_int target, int vector, int delivery_mode) |
| 629 | { |
| 630 | int x; |
| 631 | int status; |
| 632 | |
| 633 | if (target & ~0x7fff) |
| 634 | return -1; /* only 15 targets allowed */ |
| 635 | |
| 636 | for (status = 0, x = 0; x <= 14; ++x) |
| 637 | if (target & (1 << x)) { |
| 638 | |
| 639 | /* send the IPI */ |
| 640 | if (apic_ipi_singledest(x, vector, |
| 641 | delivery_mode) == -1) |
| 642 | status |= (1 << x); |
| 643 | } |
| 644 | return status; |
| 645 | } |
| 646 | |
| 647 | |
| 648 | #if defined(READY) |
| 649 | /* |
| 650 | * Send an IPI INTerrupt containing 'vector' to CPU 'target' |
| 651 | * NOTE: target is a LOGICAL APIC ID |
| 652 | */ |
| 653 | int |
| 654 | selected_proc_ipi(int target, int vector) |
| 655 | { |
| 656 | u_long icr_lo; |
| 657 | u_long icr_hi; |
| 658 | |
| 659 | /* write the destination field for the target AP */ |
| 660 | icr_hi = (lapic.icr_hi & ~APIC_ID_MASK) | |
| 661 | (cpu_num_to_apic_id[target] << 24); |
| 662 | lapic.icr_hi = icr_hi; |
| 663 | |
| 664 | /* write command */ |
| 665 | icr_lo = (lapic.icr_lo & APIC_RESV2_MASK) | |
| 666 | APIC_DEST_DESTFLD | APIC_DELMODE_FIXED | vector; |
| 667 | lapic.icr_lo = icr_lo; |
| 668 | |
| 669 | /* wait for pending status end */ |
| 670 | while (lapic.icr_lo & APIC_DELSTAT_MASK) |
| 671 | /* spin */ ; |
| 672 | |
| 673 | return 0; /** XXX FIXME: return result */ |
| 674 | } |
| 675 | #endif /* READY */ |
| 676 | |
| 677 | #endif /* APIC_IO */ |
| 678 | |
| 679 | |
| 680 | /* |
| 681 | * Timer code, in development... |
| 682 | * - suggested by rgrimes@gndrsh.aac.dev.com |
| 683 | */ |
| 684 | |
| 685 | /** XXX FIXME: temp hack till we can determin bus clock */ |
| 686 | #ifndef BUS_CLOCK |
| 687 | #define BUS_CLOCK 66000000 |
| 688 | #define bus_clock() 66000000 |
| 689 | #endif |
| 690 | |
| 691 | #if defined(READY) |
| 692 | int acquire_apic_timer __P((void)); |
| 693 | int release_apic_timer __P((void)); |
| 694 | |
| 695 | /* |
| 696 | * Acquire the APIC timer for exclusive use. |
| 697 | */ |
| 698 | int |
| 699 | acquire_apic_timer(void) |
| 700 | { |
| 701 | #if 1 |
| 702 | return 0; |
| 703 | #else |
| 704 | /** XXX FIXME: make this really do something */ |
| 705 | panic("APIC timer in use when attempting to aquire"); |
| 706 | #endif |
| 707 | } |
| 708 | |
| 709 | |
| 710 | /* |
| 711 | * Return the APIC timer. |
| 712 | */ |
| 713 | int |
| 714 | release_apic_timer(void) |
| 715 | { |
| 716 | #if 1 |
| 717 | return 0; |
| 718 | #else |
| 719 | /** XXX FIXME: make this really do something */ |
| 720 | panic("APIC timer was already released"); |
| 721 | #endif |
| 722 | } |
| 723 | #endif /* READY */ |
| 724 | |
| 725 | |
| 726 | /* |
| 727 | * Load a 'downcount time' in uSeconds. |
| 728 | */ |
| 729 | void |
| 730 | set_apic_timer(int value) |
| 731 | { |
| 732 | u_long lvtt; |
| 733 | long ticks_per_microsec; |
| 734 | |
| 735 | /* |
| 736 | * Calculate divisor and count from value: |
| 737 | * |
| 738 | * timeBase == CPU bus clock divisor == [1,2,4,8,16,32,64,128] |
| 739 | * value == time in uS |
| 740 | */ |
| 741 | lapic.dcr_timer = APIC_TDCR_1; |
| 742 | ticks_per_microsec = bus_clock() / 1000000; |
| 743 | |
| 744 | /* configure timer as one-shot */ |
| 745 | lvtt = lapic.lvt_timer; |
| 746 | lvtt &= ~(APIC_LVTT_VECTOR | APIC_LVTT_DS | APIC_LVTT_M | APIC_LVTT_TM); |
| 747 | lvtt |= APIC_LVTT_M; /* no INT, one-shot */ |
| 748 | lapic.lvt_timer = lvtt; |
| 749 | |
| 750 | /* */ |
| 751 | lapic.icr_timer = value * ticks_per_microsec; |
| 752 | } |
| 753 | |
| 754 | |
| 755 | /* |
| 756 | * Read remaining time in timer. |
| 757 | */ |
| 758 | int |
| 759 | read_apic_timer(void) |
| 760 | { |
| 761 | #if 0 |
| 762 | /** XXX FIXME: we need to return the actual remaining time, |
| 763 | * for now we just return the remaining count. |
| 764 | */ |
| 765 | #else |
| 766 | return lapic.ccr_timer; |
| 767 | #endif |
| 768 | } |
| 769 | |
| 770 | |
| 771 | /* |
| 772 | * Spin-style delay, set delay time in uS, spin till it drains. |
| 773 | */ |
| 774 | void |
| 775 | u_sleep(int count) |
| 776 | { |
| 777 | set_apic_timer(count); |
| 778 | while (read_apic_timer()) |
| 779 | /* spin */ ; |
| 780 | } |