2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/i386/isa/pci_cfgreg.c,v 1.1.2.7 2001/11/28 05:47:03 imp Exp $
29 * $DragonFly: src/sys/bus/pci/amd64/pci_cfgreg.c,v 1.1 2008/08/02 05:22:19 dillon Exp $
33 #include <sys/param.h> /* XXX trim includes */
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/malloc.h>
39 #include <sys/sysctl.h>
42 #include <machine/md_var.h>
43 #include <machine/clock.h>
44 #include <bus/pci/pcivar.h>
45 #include <bus/pci/pcireg.h>
46 #include <bus/isa/isavar.h>
47 #include "pci_cfgreg.h"
48 #include <machine/segments.h>
49 #include <machine/pc/bios.h>
50 #include <machine/smp.h>
52 #define PRVERB(a) do { \
57 static int pci_disable_bios_route = 0;
58 SYSCTL_INT(_hw, OID_AUTO, pci_disable_bios_route, CTLFLAG_RD,
59 &pci_disable_bios_route, 0, "disable interrupt routing via PCI-BIOS");
60 TUNABLE_INT("hw.pci_disable_bios_route", &pci_disable_bios_route);
66 static int pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq);
67 static int pci_cfgintr_unique(struct PIR_entry *pe, int pin);
68 static int pci_cfgintr_linked(struct PIR_entry *pe, int pin);
69 static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin);
70 static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
73 static void pci_print_irqmask(u_int16_t irqs);
75 static void pci_print_route_table(struct PIR_table *prt, int size);
77 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
78 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
79 static int pcireg_cfgopen(void);
81 static struct PIR_table *pci_route_table;
82 static int pci_route_count;
85 * Some BIOS writers seem to want to ignore the spec and put
86 * 0 in the intline rather than 255 to indicate none. Some use
87 * numbers in the range 128-254 to indicate something strange and
88 * apparently undocumented anywhere. Assume these are completely bogus
89 * and map them to 255, which means "none".
92 pci_map_intline(int line)
94 if (line == 0 || line >= 128)
95 return (PCI_INVALID_IRQ);
102 pcibios_get_version(void)
104 struct bios_regs args;
106 if (PCIbios.ventry == 0) {
107 PRVERB(("pcibios: No call entry point\n"));
110 args.eax = PCIBIOS_BIOS_PRESENT;
111 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
112 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
115 if (args.edx != 0x20494350) {
116 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
119 return (args.ebx & 0xffff);
125 * Initialise access to PCI configuration space
130 static int opened = 0;
132 static struct PIR_table *pt;
140 if (pcireg_cfgopen() == 0)
144 v = pcibios_get_version();
146 kprintf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
149 * Look for the interrupt routing table.
151 * We use PCI BIOS's PIR table if it's available $PIR is the
152 * standard way to do this. Sadly some machines are not
153 * standards conforming and have _PIR instead. We shrug and cope
154 * by looking for both.
156 if (pcibios_get_version() >= 0x0210 && pt == NULL) {
157 sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0);
159 sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0);
161 pt = (struct PIR_table *)(uintptr_t)
162 BIOS_PADDRTOVADDR(sigaddr);
163 for (cv = (u_int8_t *)pt, ck = 0, i = 0;
164 i < (pt->pt_header.ph_length); i++)
166 if (ck == 0 && pt->pt_header.ph_length >
167 sizeof(struct PIR_header)) {
168 pci_route_table = pt;
169 pci_route_count = (pt->pt_header.ph_length -
170 sizeof(struct PIR_header)) /
171 sizeof(struct PIR_entry);
172 kprintf("Using $PIR table, %d entries at %p\n",
173 pci_route_count, pci_route_table);
175 pci_print_route_table(pci_route_table,
186 * Read configuration space register
189 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
196 * If we are using the APIC, the contents of the intline
197 * register will probably be wrong (since they are set up for
198 * use with the PIC. Rather than rewrite these registers
199 * (maybe that would be smarter) we trap attempts to read them
200 * and translate to our private vector numbers.
202 if ((reg == PCIR_INTLINE) && (bytes == 1)) {
204 pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1);
205 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
210 airq = pci_apic_irq(bus, slot, pin);
212 /* PCI specific entry found in MP table */
214 undirect_pci_irq(line);
218 * PCI interrupts might be redirected to the
219 * ISA bus according to some MP tables. Use the
220 * same methods as used by the ISA devices
221 * devices to find the proper IOAPIC int pin.
223 airq = isa_apic_irq(line);
224 if ((airq >= 0) && (airq != line)) {
225 /* XXX: undirect_pci_irq() ? */
226 undirect_isa_irq(line);
235 * Some BIOS writers seem to want to ignore the spec and put
236 * 0 in the intline rather than 255 to indicate none. The rest of
237 * the code uses 255 as an invalid IRQ.
239 if (reg == PCIR_INTLINE && bytes == 1) {
240 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
241 return pci_map_intline(line);
244 return (pcireg_cfgread(bus, slot, func, reg, bytes));
248 * Write configuration space register
251 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
253 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
257 pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
259 return (pci_cfgregread(cfg->bus, cfg->slot, cfg->func, reg, bytes));
263 pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
265 pci_cfgregwrite(cfg->bus, cfg->slot, cfg->func, reg, data, bytes);
272 pci_cfgintr(int bus, int device, int pin, int oldirq)
274 return (PCI_INVALID_IRQ);
280 * Route a PCI interrupt
283 pci_cfgintr(int bus, int device, int pin, int oldirq)
285 struct PIR_entry *pe;
287 struct bios_regs args;
293 v = pcibios_get_version();
296 "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n",
297 (v & 0xff00) >> 8, v & 0xff));
298 return (PCI_INVALID_IRQ);
300 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
301 (pin < 1) || (pin > 4))
302 return (PCI_INVALID_IRQ);
305 * Scan the entry table for a contender
307 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count;
309 if ((bus != pe->pe_bus) || (device != pe->pe_device))
313 * A link of 0 means that this intpin is not connected to
314 * any other device's interrupt pins and is not connected to
315 * any of the Interrupt Router's interrupt pins, so we can't
318 if (pe->pe_intpin[pin - 1].link == 0)
321 if (pci_cfgintr_valid(pe, pin, oldirq)) {
322 kprintf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus,
323 device, 'A' + pin - 1, oldirq);
328 * We try to find a linked interrupt, then we look to see
329 * if the interrupt is uniquely routed, then we look for
330 * a virgin interrupt. The virgin interrupt should return
331 * an interrupt we can route, but if that fails, maybe we
332 * should try harder to route a different interrupt.
333 * However, experience has shown that that's rarely the
334 * failure mode we see.
336 irq = pci_cfgintr_linked(pe, pin);
337 if (irq != PCI_INVALID_IRQ)
339 if (irq == PCI_INVALID_IRQ) {
340 irq = pci_cfgintr_unique(pe, pin);
341 if (irq != PCI_INVALID_IRQ)
344 if (irq == PCI_INVALID_IRQ)
345 irq = pci_cfgintr_virgin(pe, pin);
347 if (irq == PCI_INVALID_IRQ)
350 if (pci_disable_bios_route != 0)
353 * Ask the BIOS to route the interrupt. If we picked an
354 * interrupt that failed, we should really try other
355 * choices that the BIOS offers us.
357 * For uniquely routed interrupts, we need to try
358 * to route them on some machines. Yet other machines
359 * fail to route, so we have to pretend that in that
360 * case it worked. Isn't PC hardware fun?
362 * NOTE: if we want to whack hardware to do this, then
363 * I think the right way to do that would be to have
364 * bridge drivers that do this. I'm not sure that the
365 * $PIR table would be valid for those interrupt
368 args.eax = PCIBIOS_ROUTE_INTERRUPT;
369 args.ebx = (bus << 8) | (device << 3);
370 /* pin value is 0xa - 0xd */
371 args.ecx = (irq << 8) | (0xa + pin -1);
373 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)) &&
375 PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n"));
376 return (PCI_INVALID_IRQ);
378 kprintf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus,
379 device, 'A' + pin - 1, irq);
383 PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c oldirq=%d\n", bus,
384 device, 'A' + pin - 1, oldirq));
385 return (PCI_INVALID_IRQ);
389 * Check to see if an existing IRQ setting is valid.
392 pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq)
396 if (!PCI_INTERRUPT_VALID(irq))
398 irqmask = pe->pe_intpin[pin - 1].irqs;
399 if (irqmask & (1 << irq)) {
400 PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq));
407 * Look to see if the routing table claims this pin is uniquely routed.
410 pci_cfgintr_unique(struct PIR_entry *pe, int pin)
415 irqmask = pe->pe_intpin[pin - 1].irqs;
416 if(irqmask != 0 && powerof2(irqmask)) {
417 irq = ffs(irqmask) - 1;
418 PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
421 return (PCI_INVALID_IRQ);
425 * Look for another device which shares the same link byte and
426 * already has a unique IRQ, or which has had one routed already.
429 pci_cfgintr_linked(struct PIR_entry *pe, int pin)
431 struct PIR_entry *oe;
432 struct PIR_intpin *pi;
438 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count;
440 /* scan interrupt pins */
441 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) {
443 /* don't look at the entry we're trying to match */
444 if ((pe == oe) && (i == (pin - 1)))
446 /* compare link bytes */
447 if (pi->link != pe->pe_intpin[pin - 1].link)
449 /* link destination mapped to a unique interrupt? */
450 if (pi->irqs != 0 && powerof2(pi->irqs)) {
451 irq = ffs(pi->irqs) - 1;
452 PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
458 * look for the real PCI device that matches this
461 irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device,
463 if (irq != PCI_INVALID_IRQ)
467 return (PCI_INVALID_IRQ);
471 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
472 * see if it has already been assigned an interrupt.
475 pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin)
477 devclass_t pci_devclass;
478 device_t *pci_devices;
480 device_t *pci_children;
482 device_t *busp, *childp;
486 * Find all the PCI busses.
489 if ((pci_devclass = devclass_find("pci")) != NULL)
490 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
493 * Scan all the PCI busses/devices looking for this one.
495 irq = PCI_INVALID_IRQ;
496 for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ);
499 device_get_children(*busp, &pci_children, &pci_childcount);
501 for (j = 0, childp = pci_children; j < pci_childcount; j++,
503 if ((pci_get_bus(*childp) == bus) &&
504 (pci_get_slot(*childp) == device) &&
505 (pci_get_intpin(*childp) == matchpin)) {
506 irq = pci_map_intline(pci_get_irq(*childp));
507 if (irq != PCI_INVALID_IRQ)
508 PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
509 pe->pe_intpin[pin - 1].link, irq,
510 pci_get_bus(*childp),
511 pci_get_slot(*childp),
512 pci_get_function(*childp)));
516 if (pci_children != NULL)
517 kfree(pci_children, M_TEMP);
519 if (pci_devices != NULL)
520 kfree(pci_devices, M_TEMP);
525 * Pick a suitable IRQ from those listed as routable to this device.
528 pci_cfgintr_virgin(struct PIR_entry *pe, int pin)
533 * first scan the set of PCI-only interrupts and see if any of these
536 for (irq = 0; irq < 16; irq++) {
539 /* can we use this interrupt? */
540 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) &&
541 (pe->pe_intpin[pin - 1].irqs & ibit)) {
542 PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq));
547 /* life is tough, so just pick an interrupt */
548 for (irq = 0; irq < 16; irq++) {
551 if (pe->pe_intpin[pin - 1].irqs & ibit) {
552 PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq));
556 return (PCI_INVALID_IRQ);
560 pci_print_irqmask(u_int16_t irqs)
569 for (i = 0; i < 16; i++, irqs >>= 1)
580 * Dump the contents of a PCI BIOS Interrupt Routing Table to the console.
583 pci_print_route_table(struct PIR_table *ptr, int size)
585 struct PIR_entry *entry;
586 struct PIR_intpin *intpin;
589 kprintf("PCI-Only Interrupts: ");
590 pci_print_irqmask(ptr->pt_header.ph_pci_irqs);
591 kprintf("\nLocation Bus Device Pin Link IRQs\n");
592 entry = &ptr->pt_entry[0];
593 for (i = 0; i < size; i++, entry++) {
594 intpin = &entry->pe_intpin[0];
595 for (pin = 0; pin < 4; pin++, intpin++)
596 if (intpin->link != 0) {
597 if (entry->pe_slot == 0)
598 kprintf("embedded ");
600 kprintf("slot %-3d ", entry->pe_slot);
601 kprintf(" %3d %3d %c 0x%02x ",
602 entry->pe_bus, entry->pe_device,
603 'A' + pin, intpin->link);
604 pci_print_irqmask(intpin->irqs);
611 * See if any interrupts for a given PCI bus are routed in the PIR. Don't
612 * even bother looking if the BIOS doesn't support routing anyways.
615 pci_probe_route_table(int bus)
620 v = pcibios_get_version();
623 for (i = 0; i < pci_route_count; i++)
624 if (pci_route_table->pt_entry[i].pe_bus == bus)
632 * Configuration space access using direct register operations
635 /* enable configuration space accesses and return data port address */
637 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
641 if (bus <= PCI_BUSMAX
643 && func <= PCI_FUNCMAX
646 && (unsigned) bytes <= 4
647 && (reg & (bytes - 1)) == 0) {
650 outl(CONF1_ADDR_PORT, (1 << 31)
651 | (bus << 16) | (slot << 11)
652 | (func << 8) | (reg & ~0x03));
653 dataport = CONF1_DATA_PORT + (reg & 0x03);
656 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
657 outb(CONF2_FORWARD_PORT, bus);
658 dataport = 0xc000 | (slot << 8) | reg;
665 /* disable configuration space accesses */
671 outl(CONF1_ADDR_PORT, 0);
674 outb(CONF2_ENABLE_PORT, 0);
675 outb(CONF2_FORWARD_PORT, 0);
681 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
686 port = pci_cfgenable(bus, slot, func, reg, bytes);
705 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
709 port = pci_cfgenable(bus, slot, func, reg, bytes);
726 /* check whether the configuration mechanism has been correctly identified */
728 pci_cfgcheck(int maxdev)
736 kprintf("pci_cfgcheck:\tdevice ");
738 for (device = 0; device < maxdev; device++) {
740 kprintf("%d ", device);
742 port = pci_cfgenable(0, device, 0, 0, 4);
744 if (id == 0 || id == 0xffffffff)
747 port = pci_cfgenable(0, device, 0, 8, 4);
748 class = inl(port) >> 8;
750 kprintf("[class=%06x] ", class);
751 if (class == 0 || (class & 0xf870ff) != 0)
754 port = pci_cfgenable(0, device, 0, 14, 1);
757 kprintf("[hdr=%02x] ", header);
758 if ((header & 0x7e) != 0)
762 kprintf("is there (id=%08x)\n", id);
768 kprintf("-- nothing found\n");
777 uint32_t mode1res,oldval1;
778 uint8_t mode2res,oldval2;
780 oldval1 = inl(CONF1_ADDR_PORT);
783 kprintf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
787 if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
792 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
794 mode1res = inl(CONF1_ADDR_PORT);
795 outl(CONF1_ADDR_PORT, oldval1);
798 kprintf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n",
799 mode1res, CONF1_ENABLE_CHK);
802 if (pci_cfgcheck(32))
806 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
807 mode1res = inl(CONF1_ADDR_PORT);
808 outl(CONF1_ADDR_PORT, oldval1);
811 kprintf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n",
812 mode1res, CONF1_ENABLE_CHK1);
814 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
815 if (pci_cfgcheck(32))
820 oldval2 = inb(CONF2_ENABLE_PORT);
823 kprintf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
827 if ((oldval2 & 0xf0) == 0) {
832 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
833 mode2res = inb(CONF2_ENABLE_PORT);
834 outb(CONF2_ENABLE_PORT, oldval2);
837 kprintf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
838 mode2res, CONF2_ENABLE_CHK);
840 if (mode2res == CONF2_ENABLE_RES) {
842 kprintf("pci_open(2a):\tnow trying mechanism 2\n");
844 if (pci_cfgcheck(16))