2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2006 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5211/ar5211_misc.c 188974 2009-02-24 00:12:16Z sam $
23 #include "ah_internal.h"
25 #include "ar5211/ar5211.h"
26 #include "ar5211/ar5211reg.h"
27 #include "ar5211/ar5211phy.h"
29 #include "ah_eeprom_v3.h"
31 #define AR_NUM_GPIO 6 /* 6 GPIO bits */
32 #define AR_GPIOD_MASK 0x2f /* 6-bit mask */
35 ar5211GetMacAddress(struct ath_hal *ah, uint8_t *mac)
37 struct ath_hal_5211 *ahp = AH5211(ah);
39 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
43 ar5211SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
45 struct ath_hal_5211 *ahp = AH5211(ah);
47 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
52 ar5211GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
54 static const uint8_t ones[IEEE80211_ADDR_LEN] =
55 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
56 OS_MEMCPY(mask, ones, IEEE80211_ADDR_LEN);
60 ar5211SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
66 * Read 16 bits of data from the specified EEPROM offset.
69 ar5211EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)
71 OS_REG_WRITE(ah, AR_EEPROM_ADDR, off);
72 OS_REG_WRITE(ah, AR_EEPROM_CMD, AR_EEPROM_CMD_READ);
74 if (!ath_hal_wait(ah, AR_EEPROM_STS,
75 AR_EEPROM_STS_READ_COMPLETE | AR_EEPROM_STS_READ_ERROR,
76 AR_EEPROM_STS_READ_COMPLETE)) {
77 HALDEBUG(ah, HAL_DEBUG_ANY,
78 "%s: read failed for entry 0x%x\n", __func__, off);
81 *data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;
85 #ifdef AH_SUPPORT_WRITE_EEPROM
87 * Write 16 bits of data to the specified EEPROM offset.
90 ar5211EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)
94 #endif /* AH_SUPPORT_WRITE_EEPROM */
97 * Attempt to change the cards operating regulatory domain to the given value
100 ar5211SetRegulatoryDomain(struct ath_hal *ah,
101 uint16_t regDomain, HAL_STATUS *status)
105 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
110 * Check if EEPROM is configured to allow this; must
111 * be a proper version and the protection bits must
112 * permit re-writing that segment of the EEPROM.
114 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
118 #ifdef AH_SUPPORT_WRITE_REGDOMAIN
119 if (ar5211EepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
120 HALDEBUG(ah, HAL_DEBUG_ANY,
121 "%s: set regulatory domain to %u (0x%x)\n",
122 __func__, regDomain, regDomain);
123 AH_PRIVATE(ah)->ah_currentRD = regDomain;
135 * Return the wireless modes (a,b,g,t) supported by hardware.
137 * This value is what is actually supported by the hardware
138 * and is unaffected by regulatory/country code settings.
142 ar5211GetWirelessModes(struct ath_hal *ah)
146 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
148 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
149 mode |= HAL_MODE_TURBO | HAL_MODE_108A;
151 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
152 mode |= HAL_MODE_11B;
158 ar5211GetTurboDisable(struct ath_hal *ah)
160 return (AH5211(ah)->ah_turboDisable != 0);
165 * Called if RfKill is supported (according to EEPROM). Set the interrupt and
166 * GPIO values so the ISR and can disable RF on a switch signal
169 ar5211EnableRfKill(struct ath_hal *ah)
171 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
172 int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
173 int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
176 * Configure the desired GPIO port for input
177 * and enable baseband rf silence.
179 ar5211GpioCfgInput(ah, select);
180 OS_REG_SET_BIT(ah, AR_PHY_BASE, 0x00002000);
182 * If radio disable switch connection to GPIO bit x is enabled
183 * program GPIO interrupt.
184 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
185 * verified that it is a later version of eeprom, it has a place for
186 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
187 * connection is present.
189 ar5211GpioSetIntr(ah, select, (ar5211GpioGet(ah, select) != polarity));
193 * Configure GPIO Output lines
196 ar5211GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
200 HALASSERT(gpio < AR_NUM_GPIO);
202 reg = OS_REG_READ(ah, AR_GPIOCR);
203 reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));
204 reg |= AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT);
206 OS_REG_WRITE(ah, AR_GPIOCR, reg);
211 * Configure GPIO Input lines
214 ar5211GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
218 HALASSERT(gpio < AR_NUM_GPIO);
220 reg = OS_REG_READ(ah, AR_GPIOCR);
221 reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));
222 reg |= AR_GPIOCR_0_CR_N << (gpio * AR_GPIOCR_CR_SHIFT);
224 OS_REG_WRITE(ah, AR_GPIOCR, reg);
229 * Once configured for I/O - set output lines
232 ar5211GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
236 HALASSERT(gpio < AR_NUM_GPIO);
238 reg = OS_REG_READ(ah, AR_GPIODO);
240 reg |= (val&1) << gpio;
242 OS_REG_WRITE(ah, AR_GPIODO, reg);
247 * Once configured for I/O - get input lines
250 ar5211GpioGet(struct ath_hal *ah, uint32_t gpio)
252 if (gpio < AR_NUM_GPIO) {
253 uint32_t val = OS_REG_READ(ah, AR_GPIODI);
254 val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
262 * Set the GPIO 0 Interrupt (gpio is ignored)
265 ar5211GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
267 uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
269 /* Clear the bits that we will modify. */
270 val &= ~(AR_GPIOCR_INT_SEL0 | AR_GPIOCR_INT_SELH | AR_GPIOCR_INT_ENA |
273 val |= AR_GPIOCR_INT_SEL0 | AR_GPIOCR_INT_ENA;
275 val |= AR_GPIOCR_INT_SELH;
277 /* Don't need to change anything for low level interrupt. */
278 OS_REG_WRITE(ah, AR_GPIOCR, val);
280 /* Change the interrupt mask. */
281 ar5211SetInterrupts(ah, AH5211(ah)->ah_maskReg | HAL_INT_GPIO);
285 * Change the LED blinking pattern to correspond to the connectivity
288 ar5211SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
290 static const uint32_t ledbits[8] = {
291 AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_PROP, /* HAL_LED_INIT */
292 AR_PCICFG_LEDCTL_PEND|AR_PCICFG_LEDMODE_PROP, /* HAL_LED_SCAN */
293 AR_PCICFG_LEDCTL_PEND|AR_PCICFG_LEDMODE_PROP, /* HAL_LED_AUTH */
294 AR_PCICFG_LEDCTL_ASSOC|AR_PCICFG_LEDMODE_PROP,/* HAL_LED_ASSOC*/
295 AR_PCICFG_LEDCTL_ASSOC|AR_PCICFG_LEDMODE_PROP,/* HAL_LED_RUN */
296 AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_RAND,
297 AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_RAND,
298 AR_PCICFG_LEDCTL_NONE|AR_PCICFG_LEDMODE_RAND,
300 OS_REG_WRITE(ah, AR_PCICFG,
301 (OS_REG_READ(ah, AR_PCICFG) &~
302 (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE))
303 | ledbits[state & 0x7]
308 * Change association related fields programmed into the hardware.
309 * Writing a valid BSSID to the hardware effectively enables the hardware
310 * to synchronize its TSF to the correct beacons and receive frames coming
311 * from that BSSID. It is called by the SME JOIN operation.
314 ar5211WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
316 struct ath_hal_5211 *ahp = AH5211(ah);
318 /* XXX save bssid for possible re-use on reset */
319 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
320 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
321 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
322 ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
326 * Get the current hardware tsf for stamlme.
329 ar5211GetTsf64(struct ath_hal *ah)
331 uint32_t low1, low2, u32;
333 /* sync multi-word read */
334 low1 = OS_REG_READ(ah, AR_TSF_L32);
335 u32 = OS_REG_READ(ah, AR_TSF_U32);
336 low2 = OS_REG_READ(ah, AR_TSF_L32);
337 if (low2 < low1) { /* roll over */
339 * If we are not preempted this will work. If we are
340 * then we re-reading AR_TSF_U32 does no good as the
341 * low bits will be meaningless. Likewise reading
342 * L32, U32, U32, then comparing the last two reads
343 * to check for rollover doesn't help if preempted--so
344 * we take this approach as it costs one less PCI
345 * read which can be noticeable when doing things
346 * like timestamping packets in monitor mode.
350 return (((uint64_t) u32) << 32) | ((uint64_t) low2);
354 * Get the current hardware tsf for stamlme.
357 ar5211GetTsf32(struct ath_hal *ah)
359 return OS_REG_READ(ah, AR_TSF_L32);
363 * Reset the current hardware tsf for stamlme
366 ar5211ResetTsf(struct ath_hal *ah)
368 uint32_t val = OS_REG_READ(ah, AR_BEACON);
370 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
374 * Grab a semi-random value from hardware registers - may not
378 ar5211GetRandomSeed(struct ath_hal *ah)
382 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
384 nf = 0 - ((nf ^ 0x1ff) + 1);
385 return (OS_REG_READ(ah, AR_TSF_U32) ^
386 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
390 * Detect if our card is present
393 ar5211DetectCardPresent(struct ath_hal *ah)
395 uint16_t macVersion, macRev;
399 * Read the Silicon Revision register and compare that
400 * to what we read at attach time. If the same, we say
401 * a card/device is present.
403 v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID_M;
404 macVersion = v >> AR_SREV_ID_S;
405 macRev = v & AR_SREV_REVISION_M;
406 return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
407 AH_PRIVATE(ah)->ah_macRev == macRev);
411 * Update MIB Counters
414 ar5211UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)
416 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
417 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
418 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
419 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
420 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
424 ar5211SetSifsTime(struct ath_hal *ah, u_int us)
426 struct ath_hal_5211 *ahp = AH5211(ah);
428 if (us > ath_hal_mac_usec(ah, 0xffff)) {
429 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
431 ahp->ah_sifstime = (u_int) -1; /* restore default handling */
434 /* convert to system clocks */
435 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us));
436 ahp->ah_slottime = us;
442 ar5211GetSifsTime(struct ath_hal *ah)
444 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
445 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
449 ar5211SetSlotTime(struct ath_hal *ah, u_int us)
451 struct ath_hal_5211 *ahp = AH5211(ah);
453 if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {
454 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
456 ahp->ah_slottime = us; /* restore default handling */
459 /* convert to system clocks */
460 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
461 ahp->ah_slottime = us;
467 ar5211GetSlotTime(struct ath_hal *ah)
469 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
470 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
474 ar5211SetAckTimeout(struct ath_hal *ah, u_int us)
476 struct ath_hal_5211 *ahp = AH5211(ah);
478 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
479 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
481 ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
484 /* convert to system clocks */
485 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
486 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
487 ahp->ah_acktimeout = us;
493 ar5211GetAckTimeout(struct ath_hal *ah)
495 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
496 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
500 ar5211GetAckCTSRate(struct ath_hal *ah)
502 return ((AH5211(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
506 ar5211SetAckCTSRate(struct ath_hal *ah, u_int high)
508 struct ath_hal_5211 *ahp = AH5211(ah);
511 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
512 ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
514 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
515 ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
521 ar5211SetCTSTimeout(struct ath_hal *ah, u_int us)
523 struct ath_hal_5211 *ahp = AH5211(ah);
525 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
526 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
528 ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
531 /* convert to system clocks */
532 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
533 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
534 ahp->ah_ctstimeout = us;
540 ar5211GetCTSTimeout(struct ath_hal *ah)
542 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
543 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
547 ar5211SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
554 ar5211SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
559 * Control Adaptive Noise Immunity Parameters
562 ar5211AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
568 ar5211AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
569 const struct ieee80211_channel *chan)
574 ar5211MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)
579 * Get the rssi of frame curently being received.
582 ar5211GetCurRssi(struct ath_hal *ah)
584 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
588 ar5211GetDefAntenna(struct ath_hal *ah)
590 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
594 ar5211SetDefAntenna(struct ath_hal *ah, u_int antenna)
596 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
600 ar5211GetAntennaSwitch(struct ath_hal *ah)
602 return AH5211(ah)->ah_diversityControl;
606 ar5211SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
608 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
610 if (chan == AH_NULL) {
611 AH5211(ah)->ah_diversityControl = settings;
614 return ar5211SetAntennaSwitchInternal(ah, settings, chan);
618 ar5211GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
619 uint32_t capability, uint32_t *result)
623 case HAL_CAP_CIPHER: /* cipher handled in hardware */
624 switch (capability) {
625 case HAL_CIPHER_AES_OCB:
633 return ath_hal_getcapability(ah, type, capability, result);
638 ar5211SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
639 uint32_t capability, uint32_t setting, HAL_STATUS *status)
642 case HAL_CAP_DIAG: /* hardware diagnostic support */
644 * NB: could split this up into virtual capabilities,
645 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
646 * seems worth the additional complexity.
649 AH_PRIVATE(ah)->ah_diagreg = setting;
651 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
653 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
656 return ath_hal_setcapability(ah, type, capability,
662 ar5211GetDiagState(struct ath_hal *ah, int request,
663 const void *args, uint32_t argsize,
664 void **result, uint32_t *resultsize)
666 struct ath_hal_5211 *ahp = AH5211(ah);
669 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
672 case HAL_DIAG_EEPROM:
673 return ath_hal_eepromDiag(ah, request,
674 args, argsize, result, resultsize);
675 case HAL_DIAG_RFGAIN:
676 *result = &ahp->ah_gainValues;
677 *resultsize = sizeof(GAIN_VALUES);
679 case HAL_DIAG_RFGAIN_CURSTEP:
680 *result = __DECONST(void *, ahp->ah_gainValues.currStep);
681 *resultsize = (*result == AH_NULL) ?
682 0 : sizeof(GAIN_OPTIMIZATION_STEP);