1 /* $OpenBSD: blambert $ */
2 /* $NetBSD: nsclpcsio_isa.c,v 1.5 2002/10/22 16:18:26 drochner Exp $ */
5 * Copyright (c) 2002 Matthias Drochner. All rights reserved.
6 * Copyright (c) 2004 Markus Friedl. All rights reserved.
7 * Copyright (c) 2004 Alexander Yurchenko. All rights reserved.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * National Semiconductor PC87366 LPC Super I/O.
33 * Supported logical devices: GPIO, TMS, VLM.
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/device.h>
41 #include <sys/kernel.h>
42 #include <sys/sensors.h>
43 #include <sys/module.h>
45 #include <sys/cdefs.h>
46 #include <sys/systm.h>
50 #include <bus/isa/isareg.h>
51 #include <bus/isa/isavar.h>
53 #include <dev/misc/gpio/gpio.h>
55 #if defined(NSC_LPC_SIO_DEBUG)
56 #define DPRINTF(x) do { kprintf x; } while (0)
61 #define SIO_REG_SID 0x20 /* Super I/O ID */
62 #define SIO_SID_PC87366 0xE9 /* PC87366 is identified by 0xE9.*/
64 #define SIO_REG_SRID 0x27 /* Super I/O Revision */
66 #define SIO_REG_LDN 0x07 /* Logical Device Number */
67 #define SIO_LDN_FDC 0x00 /* Floppy Disk Controller (FDC) */
68 #define SIO_LDN_PP 0x01 /* Parallel Port (PP) */
69 #define SIO_LDN_SP2 0x02 /* Serial Port 2 with IR (SP2) */
70 #define SIO_LDN_SP1 0x03 /* Serial Port 1 (SP1) */
71 #define SIO_LDN_SWC 0x04 /* System Wake-Up Control (SWC) */
72 #define SIO_LDN_KBCM 0x05 /* Mouse Controller (KBC) */
73 #define SIO_LDN_KBCK 0x06 /* Keyboard Controller (KBC) */
74 #define SIO_LDN_GPIO 0x07 /* General-Purpose I/O (GPIO) Ports */
75 #define SIO_LDN_ACB 0x08 /* ACCESS.bus Interface (ACB) */
76 #define SIO_LDN_FSCM 0x09 /* Fan Speed Control and Monitor (FSCM) */
77 #define SIO_LDN_WDT 0x0A /* WATCHDOG Timer (WDT) */
78 #define SIO_LDN_GMP 0x0B /* Game Port (GMP) */
79 #define SIO_LDN_MIDI 0x0C /* Musical Instrument Digital Interface */
80 #define SIO_LDN_VLM 0x0D /* Voltage Level Monitor (VLM) */
81 #define SIO_LDN_TMS 0x0E /* Temperature Sensor (TMS) */
83 #define SIO_REG_ACTIVE 0x30 /* Logical Device Activate Register */
84 #define SIO_ACTIVE_EN 0x01 /* enabled */
86 #define SIO_REG_IO_MSB 0x60 /* I/O Port Base, bits 15-8 */
87 #define SIO_REG_IO_LSB 0x61 /* I/O Port Base, bits 7-0 */
89 #define SIO_LDNUM 15 /* total number of logical devices */
91 /* Supported logical devices description */
97 { "GPIO", SIO_LDN_GPIO, 16 },
98 { "VLM", SIO_LDN_VLM, 16 },
99 { "TMS", SIO_LDN_TMS, 16 },
103 #define SIO_GPIO_PINSEL 0xf0
104 #define SIO_GPIO_PINCFG 0xf1
105 #define SIO_GPIO_PINEV 0xf2
107 #define SIO_GPIO_CONF_OUTPUTEN (1 << 0)
108 #define SIO_GPIO_CONF_PUSHPULL (1 << 1)
109 #define SIO_GPIO_CONF_PULLUP (1 << 2)
111 #define SIO_GPDO0 0x00
112 #define SIO_GPDI0 0x01
113 #define SIO_GPEVEN0 0x02
114 #define SIO_GPEVST0 0x03
115 #define SIO_GPDO1 0x04
116 #define SIO_GPDI1 0x05
117 #define SIO_GPEVEN1 0x06
118 #define SIO_GPEVST1 0x07
119 #define SIO_GPDO2 0x08
120 #define SIO_GPDI2 0x09
121 #define SIO_GPDO3 0x0a
122 #define SIO_GPDI3 0x0b
124 #define SIO_GPIO_NPINS 29
127 #define SIO_TEVSTS 0x00 /* Temperature Event Status */
128 #define SIO_TEVSMI 0x02 /* Temperature Event to SMI */
129 #define SIO_TEVIRQ 0x04 /* Temperature Event to IRQ */
130 #define SIO_TMSCFG 0x08 /* TMS Configuration */
131 #define SIO_TMSBS 0x09 /* TMS Bank Select */
132 #define SIO_TCHCFST 0x0A /* Temperature Channel Config and Status */
133 #define SIO_RDCHT 0x0B /* Read Channel Temperature */
134 #define SIO_CHTH 0x0C /* Channel Temperature High Limit */
135 #define SIO_CHTL 0x0D /* Channel Temperature Low Limit */
136 #define SIO_CHOTL 0x0E /* Channel Overtemperature Limit */
139 #define SIO_VEVSTS0 0x00 /* Voltage Event Status 0 */
140 #define SIO_VEVSTS1 0x01 /* Voltage Event Status 1 */
141 #define SIO_VEVSMI0 0x02 /* Voltage Event to SMI 0 */
142 #define SIO_VEVSMI1 0x03 /* Voltage Event to SMI 1 */
143 #define SIO_VEVIRQ0 0x04 /* Voltage Event to IRQ 0 */
144 #define SIO_VEVIRQ1 0x05 /* Voltage Event to IRQ 1 */
145 #define SIO_VID 0x06 /* Voltage ID */
146 #define SIO_VCNVR 0x07 /* Voltage Conversion Rate */
147 #define SIO_VLMCFG 0x08 /* VLM Configuration */
148 #define SIO_VLMBS 0x09 /* VLM Bank Select */
149 #define SIO_VCHCFST 0x0A /* Voltage Channel Config and Status */
150 #define SIO_RDCHV 0x0B /* Read Channel Voltage */
151 #define SIO_CHVH 0x0C /* Channel Voltage High Limit */
152 #define SIO_CHVL 0x0D /* Channel Voltage Low Limit */
153 #define SIO_OTSL 0x0E /* Overtemperature Shutdown Limit */
155 #define SIO_REG_SIOCF1 0x21
156 #define SIO_REG_SIOCF2 0x22
157 #define SIO_REG_SIOCF3 0x23
158 #define SIO_REG_SIOCF4 0x24
159 #define SIO_REG_SIOCF5 0x25
160 #define SIO_REG_SIOCF8 0x28
161 #define SIO_REG_SIOCFA 0x2A
162 #define SIO_REG_SIOCFB 0x2B
163 #define SIO_REG_SIOCFC 0x2C
164 #define SIO_REG_SIOCFD 0x2D
166 #define SIO_NUM_SENSORS (3+14)
167 #define SIO_VLM_OFF 3
168 #define SIO_VREF 1235 /* 1000.0 * VREF */
170 struct nsclpcsio_softc {
171 struct device* sc_dev;
172 struct resource *sc_iores;
174 bus_space_tag_t sc_iot;
175 bus_space_handle_t sc_ioh;
177 bus_space_handle_t sc_ld_ioh[SIO_LDNUM];
178 int sc_ld_en[SIO_LDNUM];
181 struct gpio sc_gpio_gc;
182 struct gpio_pin sc_gpio_pins[SIO_GPIO_NPINS];
186 struct ksensor sensors[SIO_NUM_SENSORS];
187 struct ksensordev sensordev;
190 #define GPIO_READ(sc, reg) \
191 bus_space_read_1((sc)->sc_iot, \
192 (sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg))
193 #define GPIO_WRITE(sc, reg, val) \
194 bus_space_write_1((sc)->sc_iot, \
195 (sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg), (val))
196 #define TMS_WRITE(sc, reg, val) \
197 bus_space_write_1((sc)->sc_iot, \
198 (sc)->sc_ld_ioh[SIO_LDN_TMS], (reg), (val))
199 #define TMS_READ(sc, reg) \
200 bus_space_read_1((sc)->sc_iot, \
201 (sc)->sc_ld_ioh[SIO_LDN_TMS], (reg))
202 #define VLM_WRITE(sc, reg, val) \
203 bus_space_write_1((sc)->sc_iot, \
204 (sc)->sc_ld_ioh[SIO_LDN_VLM], (reg), (val))
205 #define VLM_READ(sc, reg) \
206 bus_space_read_1((sc)->sc_iot, \
207 (sc)->sc_ld_ioh[SIO_LDN_VLM], (reg))
209 int nsclpcsio_isa_probe(struct device *);
210 int nsclpcsio_isa_attach(struct device *);
213 static device_method_t nsclpcsio_isa_methods[] = {
214 DEVMETHOD(device_probe, nsclpcsio_isa_probe),
215 DEVMETHOD(device_attach, nsclpcsio_isa_attach),
219 static driver_t nsclpcsio_isa_driver = {
221 nsclpcsio_isa_methods,
222 sizeof (struct nsclpcsio_softc)
225 static devclass_t nsclpcsio_devclass;
227 DRIVER_MODULE(nsclpcsio_isa, isa, nsclpcsio_isa_driver, nsclpcsio_devclass, NULL, NULL);
231 static u_int8_t nsread(bus_space_tag_t, bus_space_handle_t, int);
232 static void nswrite(bus_space_tag_t, bus_space_handle_t, int, u_int8_t);
235 void nsclpcsio_gpio_init(struct nsclpcsio_softc *);
236 int nsclpcsio_gpio_pin_read(void *, int);
237 void nsclpcsio_gpio_pin_write(void *, int, int);
238 void nsclpcsio_gpio_pin_ctl(void *, int, int);
241 void nsclpcsio_tms_init(struct nsclpcsio_softc *);
242 void nsclpcsio_vlm_init(struct nsclpcsio_softc *);
243 void nsclpcsio_tms_update(struct nsclpcsio_softc *);
244 void nsclpcsio_vlm_update(struct nsclpcsio_softc *);
245 void nsclpcsio_refresh(void *);
248 nsread(bus_space_tag_t iot, bus_space_handle_t ioh, int idx)
250 bus_space_write_1(iot, ioh, 0, idx);
251 return (bus_space_read_1(iot, ioh, 1));
255 nswrite(bus_space_tag_t iot, bus_space_handle_t ioh, int idx, u_int8_t data)
257 bus_space_write_1(iot, ioh, 0, idx);
258 bus_space_write_1(iot, ioh, 1, data);
262 nsclpcsio_isa_probe(struct device *dev)
264 struct resource *iores;
267 bus_space_handle_t ioh;
270 iores = bus_alloc_resource(dev, SYS_RES_IOPORT, &iorid, 0ul, ~0ul, 8, RF_ACTIVE);
274 iot = rman_get_bustag(iores);
275 ioh = rman_get_bushandle(iores);
277 if (nsread(iot, ioh, SIO_REG_SID) == SIO_SID_PC87366)
280 bus_release_resource(dev, SYS_RES_IOPORT, iorid, iores);
289 nsclpcsio_isa_attach(struct device *dev)
291 struct resource *iores;
294 struct nsclpcsio_softc *sc = device_get_softc(dev);
298 sc->sc_iores = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->sc_iorid, 0ul, ~0ul, 8, RF_ACTIVE);
299 if (sc->sc_iores == NULL) {
302 sc->sc_iot = rman_get_bustag(sc->sc_iores);
303 sc->sc_ioh = rman_get_bushandle(sc->sc_iores);
305 kprintf("%s: NSC PC87366 rev %d:", device_get_nameunit(sc->sc_dev),
306 nsread(sc->sc_iot, sc->sc_ioh, SIO_REG_SRID));
308 /* Configure all supported logical devices */
309 for (i = 0; i < sizeof(sio_ld) / sizeof(sio_ld[0]); i++) {
310 sc->sc_ld_en[sio_ld[i].ld_num] = 0;
312 /* Select the device and check if it's activated */
313 nswrite(sc->sc_iot, sc->sc_ioh, SIO_REG_LDN, sio_ld[i].ld_num);
314 if ((nsread(sc->sc_iot, sc->sc_ioh,
315 SIO_REG_ACTIVE) & SIO_ACTIVE_EN) == 0)
318 /* Map I/O space if necessary */
319 if (sio_ld[i].ld_iosize != 0) {
321 iobase = (nsread(sc->sc_iot, sc->sc_ioh,
322 SIO_REG_IO_MSB) << 8);
324 iobase |= nsread(sc->sc_iot, sc->sc_ioh,
327 /* XXX: Not elegant without alloc_resource, but works */
328 kprintf("debugging: iobase = %x\n", iobase);
329 iores = bus_alloc_resource(dev, SYS_RES_IOPORT, &iorid,
330 iobase, sio_ld[i].ld_iosize, sio_ld[i].ld_iosize, RF_ACTIVE);
332 kprintf("messed up alloc3\n");
335 /* XXX: if implemented, also use the rman get handle stuff */
337 sc->sc_ld_ioh[sio_ld[i].ld_num] = iobase;
340 sc->sc_ld_en[sio_ld[i].ld_num] = 1;
341 kprintf(" %s", sio_ld[i].ld_name);
346 nsclpcsio_gpio_init(sc);
348 nsclpcsio_tms_init(sc);
349 nsclpcsio_vlm_init(sc);
351 /* Hook into hw.sensors sysctl */
352 strlcpy(sc->sensordev.xname, device_get_nameunit(sc->sc_dev),
353 sizeof(sc->sensordev.xname));
354 for (i = 0; i < SIO_NUM_SENSORS; i++) {
355 if (i < SIO_VLM_OFF && !sc->sc_ld_en[SIO_LDN_TMS])
357 if (i >= SIO_VLM_OFF && !sc->sc_ld_en[SIO_LDN_VLM])
359 sensor_attach(&sc->sensordev, &sc->sensors[i]);
361 sensordev_install(&sc->sensordev);
362 if (sc->sc_ld_en[SIO_LDN_TMS] || sc->sc_ld_en[SIO_LDN_VLM]) {
363 sensor_task_register(sc, nsclpcsio_refresh, 2);
367 /* Attach GPIO framework */
368 if (sc->sc_ld_en[SIO_LDN_GPIO]) {
369 sc->sc_gpio_gc.driver_name = "pc83766";
370 sc->sc_gpio_gc.arg = sc;
371 sc->sc_gpio_gc.pin_read = nsclpcsio_gpio_pin_read;
372 sc->sc_gpio_gc.pin_write = nsclpcsio_gpio_pin_write;
373 sc->sc_gpio_gc.pin_ctl = nsclpcsio_gpio_pin_ctl;
374 sc->sc_gpio_gc.pins = sc->sc_gpio_pins;
375 sc->sc_gpio_gc.npins = SIO_GPIO_NPINS;
376 gpio_register(&sc->sc_gpio_gc);
384 nsclpcsio_refresh(void *arg)
386 struct nsclpcsio_softc *sc = (struct nsclpcsio_softc *)arg;
388 if (sc->sc_ld_en[SIO_LDN_TMS])
389 nsclpcsio_tms_update(sc);
390 if (sc->sc_ld_en[SIO_LDN_VLM])
391 nsclpcsio_vlm_update(sc);
395 nsclpcsio_tms_init(struct nsclpcsio_softc *sc)
399 /* Initialisation, PC87366.pdf, page 208 */
400 TMS_WRITE(sc, 0x08, 0x00);
401 TMS_WRITE(sc, 0x09, 0x0f);
402 TMS_WRITE(sc, 0x0a, 0x08);
403 TMS_WRITE(sc, 0x0b, 0x04);
404 TMS_WRITE(sc, 0x0c, 0x35);
405 TMS_WRITE(sc, 0x0d, 0x05);
406 TMS_WRITE(sc, 0x0e, 0x05);
408 TMS_WRITE(sc, SIO_TMSCFG, 0x00);
410 /* Enable the sensors */
411 for (i = 0; i < 3; i++) {
412 TMS_WRITE(sc, SIO_TMSBS, i);
413 TMS_WRITE(sc, SIO_TCHCFST, 0x01);
415 sc->sensors[i].type = SENSOR_TEMP;
418 strlcpy(sc->sensors[0].desc, "Remote", sizeof(sc->sensors[0].desc));
419 strlcpy(sc->sensors[1].desc, "Remote", sizeof(sc->sensors[1].desc));
420 strlcpy(sc->sensors[2].desc, "Local", sizeof(sc->sensors[2].desc));
422 nsclpcsio_tms_update(sc);
426 nsclpcsio_tms_update(struct nsclpcsio_softc *sc)
432 for (i = 0; i < 3; i++) {
433 TMS_WRITE(sc, SIO_TMSBS, i);
434 status = TMS_READ(sc, SIO_TCHCFST);
435 if (!(status & 0x01)) {
436 DPRINTF(("%s: status %d: disabled\n",
437 sc->sensors[i].desc, status));
438 sc->sensors[i].value = 0;
441 sdata = TMS_READ(sc, SIO_RDCHT);
442 DPRINTF(("%s: status %d C %d\n", sc->sensors[i].desc,
444 sc->sensors[i].value = sdata * 1000000 + 273150000;
449 nsclpcsio_vlm_init(struct nsclpcsio_softc *sc)
454 VLM_WRITE(sc, SIO_VLMCFG, 0x00);
456 /* Enable the sensors */
457 for (i = 0; i < 14; i++) {
458 VLM_WRITE(sc, SIO_VLMBS, i);
459 VLM_WRITE(sc, SIO_VCHCFST, 0x01);
485 /* only init .desc if we have something meaningful to say */
487 strlcpy(sc->sensors[SIO_VLM_OFF + i].desc, desc,
488 sizeof(sc->sensors[SIO_VLM_OFF + i].desc));
489 sc->sensors[SIO_VLM_OFF + i].type = SENSOR_VOLTS_DC;
492 nsclpcsio_vlm_update(sc);
496 nsclpcsio_vlm_update(struct nsclpcsio_softc *sc)
502 for (i = 0; i < 14; i++) {
503 VLM_WRITE(sc, SIO_VLMBS, i);
504 status = VLM_READ(sc, SIO_VCHCFST);
505 if (!(status & 0x01)) {
506 DPRINTF(("%s: status %d: disabled\n",
507 sc->sensors[SIO_VLM_OFF + i].desc, status));
508 sc->sensors[SIO_VLM_OFF + i].value = 0;
511 data = VLM_READ(sc, SIO_RDCHV);
512 DPRINTF(("%s: status %d V %d\n",
513 sc->sensors[SIO_VLM_OFF + i].desc, status, data));
523 /* Vi = (2.45±0.05)*VREF *RDCHVi / 256 */
524 rfact = 10 * scale * ((245 * SIO_VREF) >> 8);
525 sc->sensors[SIO_VLM_OFF + i].value = data * rfact;
531 nsclpcsio_gpio_pin_select(struct nsclpcsio_softc *sc, int pin)
538 data = (port << 4) | shift;
540 nswrite(sc->sc_iot, sc->sc_ioh, SIO_REG_LDN, SIO_LDN_GPIO);
541 nswrite(sc->sc_iot, sc->sc_ioh, SIO_GPIO_PINSEL, data);
545 nsclpcsio_gpio_init(struct nsclpcsio_softc *sc)
549 for (i = 0; i < SIO_GPIO_NPINS; i++) {
550 sc->sc_gpio_pins[i].pin_num = i;
551 sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT |
552 GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN |
553 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE |
556 /* Read initial state */
557 sc->sc_gpio_pins[i].pin_state = nsclpcsio_gpio_pin_read(sc,
558 i) ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
563 nsclpcsio_gpio_pin_read(void *arg, int pin)
565 struct nsclpcsio_softc *sc = arg;
566 int port, shift, reg;
589 data = GPIO_READ(sc, reg);
591 return ((data >> shift) & 0x1);
595 nsclpcsio_gpio_pin_write(void *arg, int pin, int value)
597 struct nsclpcsio_softc *sc = arg;
598 int port, shift, reg;
621 data = GPIO_READ(sc, reg);
623 data &= ~(1 << shift);
625 data |= (1 << shift);
627 GPIO_WRITE(sc, reg, data);
631 nsclpcsio_gpio_pin_ctl(void *arg, int pin, int flags)
633 struct nsclpcsio_softc *sc = arg;
636 nswrite(sc->sc_iot, sc->sc_ioh, SIO_REG_LDN, SIO_LDN_GPIO);
637 nsclpcsio_gpio_pin_select(sc, pin);
638 conf = nsread(sc->sc_iot, sc->sc_ioh, SIO_GPIO_PINCFG);
640 conf &= ~(SIO_GPIO_CONF_OUTPUTEN | SIO_GPIO_CONF_PUSHPULL |
641 SIO_GPIO_CONF_PULLUP);
642 if ((flags & GPIO_PIN_TRISTATE) == 0)
643 conf |= SIO_GPIO_CONF_OUTPUTEN;
644 if (flags & GPIO_PIN_PUSHPULL)
645 conf |= SIO_GPIO_CONF_PUSHPULL;
646 if (flags & GPIO_PIN_PULLUP)
647 conf |= SIO_GPIO_CONF_PULLUP;
649 nswrite(sc->sc_iot, sc->sc_ioh, SIO_GPIO_PINCFG, conf);