2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.22 2005/05/24 16:46:26 joerg Exp $
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
54 * http://www.national.com/ds/DP/DP83861.pdf
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
73 * There are two bugs/misfeatures in the 83820/83821 that I have
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/socket.h>
100 #include <net/ifq_var.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
105 #include <net/if_types.h>
106 #include <net/vlan/if_vlan_var.h>
110 #include <vm/vm.h> /* for vtophys */
111 #include <vm/pmap.h> /* for vtophys */
112 #include <machine/bus.h>
113 #include <machine/resource.h>
115 #include <sys/rman.h>
117 #include <dev/netif/mii_layer/mii.h>
118 #include <dev/netif/mii_layer/miivar.h>
120 #include <bus/pci/pcireg.h>
121 #include <bus/pci/pcivar.h>
123 #define NGE_USEIOSPACE
125 #include "if_ngereg.h"
128 /* "controller miibus0" required. See GENERIC if you get errors here. */
129 #include "miibus_if.h"
131 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
134 * Various supported device vendors/types and their names.
136 static struct nge_type nge_devs[] = {
137 { NGE_VENDORID, NGE_DEVICEID,
138 "National Semiconductor Gigabit Ethernet" },
142 static int nge_probe(device_t);
143 static int nge_attach(device_t);
144 static int nge_detach(device_t);
146 static int nge_alloc_jumbo_mem(struct nge_softc *);
147 static void nge_free_jumbo_mem(struct nge_softc *);
148 static void *nge_jalloc(struct nge_softc *);
149 static void nge_jfree(caddr_t, u_int);
150 static void nge_jref(caddr_t, u_int);
152 static int nge_newbuf(struct nge_softc *,
153 struct nge_desc *, struct mbuf *);
154 static int nge_encap(struct nge_softc *,
155 struct mbuf *, uint32_t *);
156 static void nge_rxeof(struct nge_softc *);
157 static void nge_txeof(struct nge_softc *);
158 static void nge_intr(void *);
159 static void nge_tick(void *);
160 static void nge_start(struct ifnet *);
161 static int nge_ioctl(struct ifnet *, u_long, caddr_t,
163 static void nge_init(void *);
164 static void nge_stop(struct nge_softc *);
165 static void nge_watchdog(struct ifnet *);
166 static void nge_shutdown(device_t);
167 static int nge_ifmedia_upd(struct ifnet *);
168 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
170 static void nge_delay(struct nge_softc *);
171 static void nge_eeprom_idle(struct nge_softc *);
172 static void nge_eeprom_putbyte(struct nge_softc *, int);
173 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
174 static void nge_read_eeprom(struct nge_softc *, void *, int, int);
176 static void nge_mii_sync(struct nge_softc *);
177 static void nge_mii_send(struct nge_softc *, uint32_t, int);
178 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
179 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
181 static int nge_miibus_readreg(device_t, int, int);
182 static int nge_miibus_writereg(device_t, int, int, int);
183 static void nge_miibus_statchg(device_t);
185 static void nge_setmulti(struct nge_softc *);
186 static void nge_reset(struct nge_softc *);
187 static int nge_list_rx_init(struct nge_softc *);
188 static int nge_list_tx_init(struct nge_softc *);
190 #ifdef NGE_USEIOSPACE
191 #define NGE_RES SYS_RES_IOPORT
192 #define NGE_RID NGE_PCI_LOIO
194 #define NGE_RES SYS_RES_MEMORY
195 #define NGE_RID NGE_PCI_LOMEM
198 static device_method_t nge_methods[] = {
199 /* Device interface */
200 DEVMETHOD(device_probe, nge_probe),
201 DEVMETHOD(device_attach, nge_attach),
202 DEVMETHOD(device_detach, nge_detach),
203 DEVMETHOD(device_shutdown, nge_shutdown),
206 DEVMETHOD(bus_print_child, bus_generic_print_child),
207 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
210 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
211 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
212 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
217 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
218 static devclass_t nge_devclass;
220 DECLARE_DUMMY_MODULE(if_nge);
221 MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
222 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0);
223 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
225 #define NGE_SETBIT(sc, reg, x) \
226 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
228 #define NGE_CLRBIT(sc, reg, x) \
229 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
232 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
235 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
238 nge_delay(struct nge_softc *sc)
242 for (idx = (300 / 33) + 1; idx > 0; idx--)
243 CSR_READ_4(sc, NGE_CSR);
247 nge_eeprom_idle(struct nge_softc *sc)
251 SIO_SET(NGE_MEAR_EE_CSEL);
253 SIO_SET(NGE_MEAR_EE_CLK);
256 for (i = 0; i < 25; i++) {
257 SIO_CLR(NGE_MEAR_EE_CLK);
259 SIO_SET(NGE_MEAR_EE_CLK);
263 SIO_CLR(NGE_MEAR_EE_CLK);
265 SIO_CLR(NGE_MEAR_EE_CSEL);
267 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
271 * Send a read command and address to the EEPROM, check for ACK.
274 nge_eeprom_putbyte(struct nge_softc *sc, int addr)
278 d = addr | NGE_EECMD_READ;
281 * Feed in each bit and stobe the clock.
283 for (i = 0x400; i; i >>= 1) {
285 SIO_SET(NGE_MEAR_EE_DIN);
287 SIO_CLR(NGE_MEAR_EE_DIN);
289 SIO_SET(NGE_MEAR_EE_CLK);
291 SIO_CLR(NGE_MEAR_EE_CLK);
297 * Read a word of data stored in the EEPROM at address 'addr.'
300 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
305 /* Force EEPROM to idle state. */
308 /* Enter EEPROM access mode. */
310 SIO_CLR(NGE_MEAR_EE_CLK);
312 SIO_SET(NGE_MEAR_EE_CSEL);
316 * Send address of word we want to read.
318 nge_eeprom_putbyte(sc, addr);
321 * Start reading bits from EEPROM.
323 for (i = 0x8000; i; i >>= 1) {
324 SIO_SET(NGE_MEAR_EE_CLK);
326 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
329 SIO_CLR(NGE_MEAR_EE_CLK);
333 /* Turn off EEPROM access mode. */
340 * Read a sequence of words from the EEPROM.
343 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
346 uint16_t word = 0, *ptr;
348 for (i = 0; i < cnt; i++) {
349 nge_eeprom_getword(sc, off + i, &word);
350 ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
356 * Sync the PHYs by setting data bit and strobing the clock 32 times.
359 nge_mii_sync(struct nge_softc *sc)
363 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
365 for (i = 0; i < 32; i++) {
366 SIO_SET(NGE_MEAR_MII_CLK);
368 SIO_CLR(NGE_MEAR_MII_CLK);
374 * Clock a series of bits through the MII.
377 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
381 SIO_CLR(NGE_MEAR_MII_CLK);
383 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
385 SIO_SET(NGE_MEAR_MII_DATA);
387 SIO_CLR(NGE_MEAR_MII_DATA);
389 SIO_CLR(NGE_MEAR_MII_CLK);
391 SIO_SET(NGE_MEAR_MII_CLK);
396 * Read an PHY register through the MII.
399 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
406 * Set up frame for RX.
408 frame->mii_stdelim = NGE_MII_STARTDELIM;
409 frame->mii_opcode = NGE_MII_READOP;
410 frame->mii_turnaround = 0;
413 CSR_WRITE_4(sc, NGE_MEAR, 0);
418 SIO_SET(NGE_MEAR_MII_DIR);
423 * Send command/address info.
425 nge_mii_send(sc, frame->mii_stdelim, 2);
426 nge_mii_send(sc, frame->mii_opcode, 2);
427 nge_mii_send(sc, frame->mii_phyaddr, 5);
428 nge_mii_send(sc, frame->mii_regaddr, 5);
431 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
433 SIO_SET(NGE_MEAR_MII_CLK);
437 SIO_CLR(NGE_MEAR_MII_DIR);
439 SIO_CLR(NGE_MEAR_MII_CLK);
441 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
442 SIO_SET(NGE_MEAR_MII_CLK);
446 * Now try reading data bits. If the ack failed, we still
447 * need to clock through 16 cycles to keep the PHY(s) in sync.
450 for(i = 0; i < 16; i++) {
451 SIO_CLR(NGE_MEAR_MII_CLK);
453 SIO_SET(NGE_MEAR_MII_CLK);
459 for (i = 0x8000; i; i >>= 1) {
460 SIO_CLR(NGE_MEAR_MII_CLK);
463 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
464 frame->mii_data |= i;
467 SIO_SET(NGE_MEAR_MII_CLK);
472 SIO_CLR(NGE_MEAR_MII_CLK);
474 SIO_SET(NGE_MEAR_MII_CLK);
485 * Write to a PHY register through the MII.
488 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
494 * Set up frame for TX.
497 frame->mii_stdelim = NGE_MII_STARTDELIM;
498 frame->mii_opcode = NGE_MII_WRITEOP;
499 frame->mii_turnaround = NGE_MII_TURNAROUND;
502 * Turn on data output.
504 SIO_SET(NGE_MEAR_MII_DIR);
508 nge_mii_send(sc, frame->mii_stdelim, 2);
509 nge_mii_send(sc, frame->mii_opcode, 2);
510 nge_mii_send(sc, frame->mii_phyaddr, 5);
511 nge_mii_send(sc, frame->mii_regaddr, 5);
512 nge_mii_send(sc, frame->mii_turnaround, 2);
513 nge_mii_send(sc, frame->mii_data, 16);
516 SIO_SET(NGE_MEAR_MII_CLK);
518 SIO_CLR(NGE_MEAR_MII_CLK);
524 SIO_CLR(NGE_MEAR_MII_DIR);
532 nge_miibus_readreg(device_t dev, int phy, int reg)
534 struct nge_softc *sc = device_get_softc(dev);
535 struct nge_mii_frame frame;
537 bzero((char *)&frame, sizeof(frame));
539 frame.mii_phyaddr = phy;
540 frame.mii_regaddr = reg;
541 nge_mii_readreg(sc, &frame);
543 return(frame.mii_data);
547 nge_miibus_writereg(device_t dev, int phy, int reg, int data)
549 struct nge_softc *sc = device_get_softc(dev);
550 struct nge_mii_frame frame;
552 bzero((char *)&frame, sizeof(frame));
554 frame.mii_phyaddr = phy;
555 frame.mii_regaddr = reg;
556 frame.mii_data = data;
557 nge_mii_writereg(sc, &frame);
563 nge_miibus_statchg(device_t dev)
565 struct nge_softc *sc = device_get_softc(dev);
566 struct mii_data *mii;
570 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
572 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
573 if (status == 0 || status & NGE_TBIANAR_FDX) {
574 NGE_SETBIT(sc, NGE_TX_CFG,
575 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
576 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
578 NGE_CLRBIT(sc, NGE_TX_CFG,
579 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
580 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
582 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
584 NGE_CLRBIT(sc, NGE_TX_CFG,
585 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
586 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
588 NGE_SETBIT(sc, NGE_TX_CFG,
589 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
590 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
593 mii = device_get_softc(sc->nge_miibus);
595 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
596 NGE_SETBIT(sc, NGE_TX_CFG,
597 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
598 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
600 NGE_CLRBIT(sc, NGE_TX_CFG,
601 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
602 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
605 /* If we have a 1000Mbps link, set the mode_1000 bit. */
606 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
607 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
608 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
610 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
616 nge_setmulti(struct nge_softc *sc)
618 struct ifnet *ifp = &sc->arpcom.ac_if;
619 struct ifmultiaddr *ifma;
620 uint32_t filtsave, h = 0, i;
623 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
624 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
625 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
626 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
631 * We have to explicitly enable the multicast hash table
632 * on the NatSemi chip if we want to use it, which we do.
633 * We also have to tell it that we don't want to use the
634 * hash table for matching unicast addresses.
636 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
637 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
638 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
640 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
642 /* first, zot all the existing hash bits */
643 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
644 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
645 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
649 * From the 11 bits returned by the crc routine, the top 7
650 * bits represent the 16-bit word in the mcast hash table
651 * that needs to be updated, and the lower 4 bits represent
652 * which bit within that byte needs to be set.
654 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
655 if (ifma->ifma_addr->sa_family != AF_LINK)
657 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
658 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
659 index = (h >> 4) & 0x7F;
661 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
662 NGE_FILTADDR_MCAST_LO + (index * 2));
663 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
666 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
670 nge_reset(struct nge_softc *sc)
674 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
676 for (i = 0; i < NGE_TIMEOUT; i++) {
677 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
681 if (i == NGE_TIMEOUT)
682 printf("nge%d: reset never completed\n", sc->nge_unit);
684 /* Wait a little while for the chip to get its brains in order. */
688 * If this is a NetSemi chip, make sure to clear
691 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
692 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
696 * Probe for an NatSemi chip. Check the PCI vendor and device
697 * IDs against our list and return a device name if we find a match.
700 nge_probe(device_t dev)
703 uint16_t vendor, product;
705 vendor = pci_get_vendor(dev);
706 product = pci_get_device(dev);
708 for (t = nge_devs; t->nge_name != NULL; t++) {
709 if (vendor == t->nge_vid && product == t->nge_did) {
710 device_set_desc(dev, t->nge_name);
719 * Attach the interface. Allocate softc structures, do ifmedia
720 * setup and ethernet/BPF attach.
723 nge_attach(device_t dev)
725 struct nge_softc *sc;
727 uint8_t eaddr[ETHER_ADDR_LEN];
729 int error = 0, rid, s, unit;
730 const char *sep = "";
734 sc = device_get_softc(dev);
735 unit = device_get_unit(dev);
736 callout_init(&sc->nge_stat_timer);
739 * Handle power management nonsense.
741 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
742 if (command == 0x01) {
743 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
744 if (command & NGE_PSTATE_MASK) {
745 uint32_t iobase, membase, irq;
747 /* Save important PCI config data. */
748 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
749 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
750 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
752 /* Reset the power state. */
753 printf("nge%d: chip is in D%d power mode "
754 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
755 command &= 0xFFFFFFFC;
756 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
758 /* Restore PCI config data. */
759 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
760 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
761 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
766 * Map control/status registers.
768 command = pci_read_config(dev, PCIR_COMMAND, 4);
769 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
770 pci_write_config(dev, PCIR_COMMAND, command, 4);
771 command = pci_read_config(dev, PCIR_COMMAND, 4);
773 #ifdef NGE_USEIOSPACE
774 if (!(command & PCIM_CMD_PORTEN)) {
775 printf("nge%d: failed to enable I/O ports!\n", unit);
780 if (!(command & PCIM_CMD_MEMEN)) {
781 printf("nge%d: failed to enable memory mapping!\n", unit);
788 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
790 if (sc->nge_res == NULL) {
791 printf("nge%d: couldn't map ports/memory\n", unit);
796 sc->nge_btag = rman_get_bustag(sc->nge_res);
797 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
799 /* Allocate interrupt */
801 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
802 RF_SHAREABLE | RF_ACTIVE);
804 if (sc->nge_irq == NULL) {
805 printf("nge%d: couldn't map interrupt\n", unit);
806 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
811 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET,
812 nge_intr, sc, &sc->nge_intrhand);
815 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
816 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
817 printf("nge%d: couldn't set up irq\n", unit);
821 /* Reset the adapter. */
825 * Get station address from the EEPROM.
827 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
828 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
829 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
833 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
834 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
836 if (sc->nge_ldata == NULL) {
837 printf("nge%d: no memory for list buffers!\n", unit);
838 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
839 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
840 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
844 bzero(sc->nge_ldata, sizeof(struct nge_list_data));
846 /* Try to allocate memory for jumbo buffers. */
847 if (nge_alloc_jumbo_mem(sc)) {
848 printf("nge%d: jumbo buffer allocation failed\n",
850 contigfree(sc->nge_ldata,
851 sizeof(struct nge_list_data), M_DEVBUF);
852 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
853 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
854 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
859 ifp = &sc->arpcom.ac_if;
861 if_initname(ifp, "nge", unit);
862 ifp->if_mtu = ETHERMTU;
863 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
864 ifp->if_ioctl = nge_ioctl;
865 ifp->if_start = nge_start;
866 ifp->if_watchdog = nge_watchdog;
867 ifp->if_init = nge_init;
868 ifp->if_baudrate = 1000000000;
869 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
870 ifq_set_ready(&ifp->if_snd);
871 ifp->if_hwassist = NGE_CSUM_FEATURES;
872 ifp->if_capabilities = IFCAP_HWCSUM;
873 ifp->if_capenable = ifp->if_capabilities;
878 if (mii_phy_probe(dev, &sc->nge_miibus,
879 nge_ifmedia_upd, nge_ifmedia_sts)) {
880 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
882 device_printf(dev, "Using TBI\n");
884 sc->nge_miibus = dev;
886 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
888 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
889 #define PRINT(s) printf("%s%s", sep, s); sep = ", "
890 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
891 device_printf(dev, " ");
892 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
894 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
895 PRINT("1000baseSX-FDX");
896 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
902 ifmedia_set(&sc->nge_ifmedia,
903 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
905 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
907 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
908 | NGE_GPIO_GP3_OUTENB
909 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
912 printf("nge%d: MII without any PHY!\n", sc->nge_unit);
913 nge_free_jumbo_mem(sc);
914 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
915 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
916 bus_release_resource(dev, NGE_RES, NGE_RID,
924 * Call MI attach routine.
926 ether_ifattach(ifp, eaddr);
935 nge_detach(device_t dev)
937 struct nge_softc *sc;
943 sc = device_get_softc(dev);
944 ifp = &sc->arpcom.ac_if;
950 bus_generic_detach(dev);
952 device_delete_child(dev, sc->nge_miibus);
954 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
955 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
956 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
958 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
959 nge_free_jumbo_mem(sc);
967 * Initialize the transmit descriptors.
970 nge_list_tx_init(struct nge_softc *sc)
972 struct nge_list_data *ld;
973 struct nge_ring_data *cd;
979 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
980 if (i == (NGE_TX_LIST_CNT - 1)) {
981 ld->nge_tx_list[i].nge_nextdesc =
983 ld->nge_tx_list[i].nge_next =
984 vtophys(&ld->nge_tx_list[0]);
986 ld->nge_tx_list[i].nge_nextdesc =
987 &ld->nge_tx_list[i + 1];
988 ld->nge_tx_list[i].nge_next =
989 vtophys(&ld->nge_tx_list[i + 1]);
991 ld->nge_tx_list[i].nge_mbuf = NULL;
992 ld->nge_tx_list[i].nge_ptr = 0;
993 ld->nge_tx_list[i].nge_ctl = 0;
996 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
1003 * Initialize the RX descriptors and allocate mbufs for them. Note that
1004 * we arrange the descriptors in a closed ring, so that the last descriptor
1005 * points back to the first.
1008 nge_list_rx_init(struct nge_softc *sc)
1010 struct nge_list_data *ld;
1011 struct nge_ring_data *cd;
1015 cd = &sc->nge_cdata;
1017 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1018 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1020 if (i == (NGE_RX_LIST_CNT - 1)) {
1021 ld->nge_rx_list[i].nge_nextdesc =
1022 &ld->nge_rx_list[0];
1023 ld->nge_rx_list[i].nge_next =
1024 vtophys(&ld->nge_rx_list[0]);
1026 ld->nge_rx_list[i].nge_nextdesc =
1027 &ld->nge_rx_list[i + 1];
1028 ld->nge_rx_list[i].nge_next =
1029 vtophys(&ld->nge_rx_list[i + 1]);
1033 cd->nge_rx_prod = 0;
1039 * Initialize an RX descriptor and attach an MBUF cluster.
1042 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
1044 struct mbuf *m_new = NULL;
1045 caddr_t *buf = NULL;
1048 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1049 if (m_new == NULL) {
1050 printf("nge%d: no memory for rx list "
1051 "-- packet dropped!\n", sc->nge_unit);
1055 /* Allocate the jumbo buffer */
1056 buf = nge_jalloc(sc);
1059 printf("nge%d: jumbo allocation failed "
1060 "-- packet dropped!\n", sc->nge_unit);
1065 /* Attach the buffer to the mbuf */
1066 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
1067 m_new->m_flags |= M_EXT | M_EXT_OLD;
1068 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1069 m_new->m_len = NGE_MCLBYTES;
1070 m_new->m_ext.ext_nfree.old = nge_jfree;
1071 m_new->m_ext.ext_nref.old = nge_jref;
1074 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES;
1075 m_new->m_data = m_new->m_ext.ext_buf;
1078 m_adj(m_new, sizeof(uint64_t));
1080 c->nge_mbuf = m_new;
1081 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1082 c->nge_ctl = m_new->m_len;
1089 nge_alloc_jumbo_mem(struct nge_softc *sc)
1093 struct nge_jpool_entry *entry;
1095 /* Grab a big chunk o' storage. */
1096 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
1097 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1099 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1100 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1104 SLIST_INIT(&sc->nge_jfree_listhead);
1105 SLIST_INIT(&sc->nge_jinuse_listhead);
1108 * Now divide it up into 9K pieces and save the addresses
1111 ptr = sc->nge_cdata.nge_jumbo_buf;
1112 for (i = 0; i < NGE_JSLOTS; i++) {
1114 aptr = (uint64_t **)ptr;
1115 aptr[0] = (uint64_t *)sc;
1116 ptr += sizeof(uint64_t);
1117 sc->nge_cdata.nge_jslots[i].nge_buf = ptr;
1118 sc->nge_cdata.nge_jslots[i].nge_inuse = 0;
1119 ptr += NGE_MCLBYTES;
1120 entry = malloc(sizeof(struct nge_jpool_entry),
1121 M_DEVBUF, M_WAITOK);
1122 if (entry == NULL) {
1123 printf("nge%d: no memory for jumbo "
1124 "buffer queue!\n", sc->nge_unit);
1128 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1129 entry, jpool_entries);
1136 nge_free_jumbo_mem(struct nge_softc *sc)
1139 struct nge_jpool_entry *entry;
1141 for (i = 0; i < NGE_JSLOTS; i++) {
1142 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1143 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
1144 free(entry, M_DEVBUF);
1147 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
1151 * Allocate a jumbo buffer.
1154 nge_jalloc(struct nge_softc *sc)
1156 struct nge_jpool_entry *entry;
1158 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1160 if (entry == NULL) {
1162 printf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1167 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
1168 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries);
1169 sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1;
1170 return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf);
1174 * Adjust usage count on a jumbo buffer. In general this doesn't
1175 * get used much because our jumbo buffers don't get passed around
1176 * a lot, but it's implemented for correctness.
1179 nge_jref(caddr_t buf, u_int size)
1181 struct nge_softc *sc;
1185 /* Extract the softc struct pointer. */
1186 aptr = (uint64_t **)(buf - sizeof(uint64_t));
1187 sc = (struct nge_softc *)(aptr[0]);
1190 panic("nge_jref: can't find softc pointer!");
1192 if (size != NGE_MCLBYTES)
1193 panic("nge_jref: adjusting refcount of buf of wrong size!");
1195 /* calculate the slot this buffer belongs to */
1197 i = ((vm_offset_t)aptr
1198 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN;
1200 if ((i < 0) || (i >= NGE_JSLOTS))
1201 panic("nge_jref: asked to reference buffer "
1202 "that we don't manage!");
1203 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0)
1204 panic("nge_jref: buffer already free!");
1206 sc->nge_cdata.nge_jslots[i].nge_inuse++;
1210 * Release a jumbo buffer.
1213 nge_jfree(caddr_t buf, u_int size)
1215 struct nge_softc *sc;
1218 struct nge_jpool_entry *entry;
1220 /* Extract the softc struct pointer. */
1221 aptr = (uint64_t **)(buf - sizeof(uint64_t));
1222 sc = (struct nge_softc *)(aptr[0]);
1225 panic("nge_jfree: can't find softc pointer!");
1227 if (size != NGE_MCLBYTES)
1228 panic("nge_jfree: freeing buffer of wrong size!");
1230 /* calculate the slot this buffer belongs to */
1232 i = ((vm_offset_t)aptr
1233 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN;
1235 if ((i < 0) || (i >= NGE_JSLOTS))
1236 panic("nge_jfree: asked to free buffer that we don't manage!");
1237 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0)
1238 panic("nge_jfree: buffer already free!");
1240 sc->nge_cdata.nge_jslots[i].nge_inuse--;
1241 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) {
1242 entry = SLIST_FIRST(&sc->nge_jinuse_listhead);
1244 panic("nge_jfree: buffer not in use!");
1246 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead,
1248 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1249 entry, jpool_entries);
1254 * A frame has been uploaded: pass the resulting mbuf chain up to
1255 * the higher level protocols.
1258 nge_rxeof(struct nge_softc *sc)
1261 struct ifnet *ifp = &sc->arpcom.ac_if;
1262 struct nge_desc *cur_rx;
1263 int i, total_len = 0;
1266 i = sc->nge_cdata.nge_rx_prod;
1268 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1269 struct mbuf *m0 = NULL;
1272 #ifdef DEVICE_POLLING
1273 if (ifp->if_flags & IFF_POLLING) {
1274 if (sc->rxcycles <= 0)
1278 #endif /* DEVICE_POLLING */
1280 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1281 rxstat = cur_rx->nge_rxstat;
1282 extsts = cur_rx->nge_extsts;
1283 m = cur_rx->nge_mbuf;
1284 cur_rx->nge_mbuf = NULL;
1285 total_len = NGE_RXBYTES(cur_rx);
1286 NGE_INC(i, NGE_RX_LIST_CNT);
1288 * If an error occurs, update stats, clear the
1289 * status word and leave the mbuf cluster in place:
1290 * it should simply get re-used next time this descriptor
1291 * comes up in the ring.
1293 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
1295 nge_newbuf(sc, cur_rx, m);
1300 * Ok. NatSemi really screwed up here. This is the
1301 * only gigE chip I know of with alignment constraints
1302 * on receive buffers. RX buffers must be 64-bit aligned.
1306 * By popular demand, ignore the alignment problems
1307 * on the Intel x86 platform. The performance hit
1308 * incurred due to unaligned accesses is much smaller
1309 * than the hit produced by forcing buffer copies all
1310 * the time, especially with jumbo frames. We still
1311 * need to fix up the alignment everywhere else though.
1313 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1315 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1316 total_len + ETHER_ALIGN, 0, ifp, NULL);
1317 nge_newbuf(sc, cur_rx, m);
1319 printf("nge%d: no receive buffers "
1320 "available -- packet dropped!\n",
1325 m_adj(m0, ETHER_ALIGN);
1329 m->m_pkthdr.rcvif = ifp;
1330 m->m_pkthdr.len = m->m_len = total_len;
1336 /* Do IP checksum checking. */
1337 if (extsts & NGE_RXEXTSTS_IPPKT)
1338 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1339 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1340 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1341 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1342 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
1343 (extsts & NGE_RXEXTSTS_UDPPKT &&
1344 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
1345 m->m_pkthdr.csum_flags |=
1346 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1347 m->m_pkthdr.csum_data = 0xffff;
1351 * If we received a packet with a vlan tag, pass it
1352 * to vlan_input() instead of ether_input().
1354 if (extsts & NGE_RXEXTSTS_VLANPKT)
1355 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI);
1357 (*ifp->if_input)(ifp, m);
1360 sc->nge_cdata.nge_rx_prod = i;
1364 * A frame was downloaded to the chip. It's safe for us to clean up
1368 nge_txeof(struct nge_softc *sc)
1370 struct ifnet *ifp = &sc->arpcom.ac_if;
1371 struct nge_desc *cur_tx = NULL;
1374 /* Clear the timeout timer. */
1378 * Go through our tx list and free mbufs for those
1379 * frames that have been transmitted.
1381 idx = sc->nge_cdata.nge_tx_cons;
1382 while (idx != sc->nge_cdata.nge_tx_prod) {
1383 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1385 if (NGE_OWNDESC(cur_tx))
1388 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1389 sc->nge_cdata.nge_tx_cnt--;
1390 NGE_INC(idx, NGE_TX_LIST_CNT);
1394 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1396 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1397 ifp->if_collisions++;
1398 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1399 ifp->if_collisions++;
1402 ifp->if_collisions +=
1403 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1406 if (cur_tx->nge_mbuf != NULL) {
1407 m_freem(cur_tx->nge_mbuf);
1408 cur_tx->nge_mbuf = NULL;
1411 sc->nge_cdata.nge_tx_cnt--;
1412 NGE_INC(idx, NGE_TX_LIST_CNT);
1416 sc->nge_cdata.nge_tx_cons = idx;
1419 ifp->if_flags &= ~IFF_OACTIVE;
1425 struct nge_softc *sc = xsc;
1426 struct ifnet *ifp = &sc->arpcom.ac_if;
1427 struct mii_data *mii;
1433 if (sc->nge_link == 0) {
1434 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1435 & NGE_TBIBMSR_ANEG_DONE) {
1436 printf("nge%d: gigabit link up\n",
1438 nge_miibus_statchg(sc->nge_miibus);
1440 if (!ifq_is_empty(&ifp->if_snd))
1445 mii = device_get_softc(sc->nge_miibus);
1448 if (sc->nge_link == 0) {
1449 if (mii->mii_media_status & IFM_ACTIVE &&
1450 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1452 if (IFM_SUBTYPE(mii->mii_media_active)
1454 printf("nge%d: gigabit link up\n",
1456 if (!ifq_is_empty(&ifp->if_snd))
1461 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1466 #ifdef DEVICE_POLLING
1467 static poll_handler_t nge_poll;
1470 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1472 struct nge_softc *sc = ifp->if_softc;
1474 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1475 CSR_WRITE_4(sc, NGE_IER, 1);
1480 * On the nge, reading the status register also clears it.
1481 * So before returning to intr mode we must make sure that all
1482 * possible pending sources of interrupts have been served.
1483 * In practice this means run to completion the *eof routines,
1484 * and then call the interrupt routine
1486 sc->rxcycles = count;
1489 if (!ifq_is_empty(&ifp->if_snd))
1492 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1495 /* Reading the ISR register clears all interrupts. */
1496 status = CSR_READ_4(sc, NGE_ISR);
1498 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1501 if (status & (NGE_ISR_RX_IDLE))
1502 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1504 if (status & NGE_ISR_SYSERR) {
1510 #endif /* DEVICE_POLLING */
1515 struct nge_softc *sc = arg;
1516 struct ifnet *ifp = &sc->arpcom.ac_if;
1519 #ifdef DEVICE_POLLING
1520 if (ifp->if_flags & IFF_POLLING)
1522 if (ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */
1523 CSR_WRITE_4(sc, NGE_IER, 0);
1524 nge_poll(ifp, 0, 1);
1527 #endif /* DEVICE_POLLING */
1529 /* Supress unwanted interrupts */
1530 if (!(ifp->if_flags & IFF_UP)) {
1535 /* Disable interrupts. */
1536 CSR_WRITE_4(sc, NGE_IER, 0);
1538 /* Data LED on for TBI mode */
1540 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1541 | NGE_GPIO_GP3_OUT);
1544 /* Reading the ISR register clears all interrupts. */
1545 status = CSR_READ_4(sc, NGE_ISR);
1547 if ((status & NGE_INTRS) == 0)
1550 if ((status & NGE_ISR_TX_DESC_OK) ||
1551 (status & NGE_ISR_TX_ERR) ||
1552 (status & NGE_ISR_TX_OK) ||
1553 (status & NGE_ISR_TX_IDLE))
1556 if ((status & NGE_ISR_RX_DESC_OK) ||
1557 (status & NGE_ISR_RX_ERR) ||
1558 (status & NGE_ISR_RX_OFLOW) ||
1559 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1560 (status & NGE_ISR_RX_IDLE) ||
1561 (status & NGE_ISR_RX_OK))
1564 if ((status & NGE_ISR_RX_IDLE))
1565 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1567 if (status & NGE_ISR_SYSERR) {
1569 ifp->if_flags &= ~IFF_RUNNING;
1574 /* mii_tick should only be called once per second */
1575 if (status & NGE_ISR_PHY_INTR) {
1582 /* Re-enable interrupts. */
1583 CSR_WRITE_4(sc, NGE_IER, 1);
1585 if (!ifq_is_empty(&ifp->if_snd))
1588 /* Data LED off for TBI mode */
1591 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1592 & ~NGE_GPIO_GP3_OUT);
1596 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1597 * pointers to the fragment pointers.
1600 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1602 struct nge_desc *f = NULL;
1604 int frag, cur, cnt = 0;
1605 struct ifvlan *ifv = NULL;
1607 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1608 m_head->m_pkthdr.rcvif != NULL &&
1609 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1610 ifv = m_head->m_pkthdr.rcvif->if_softc;
1613 * Start packing the mbufs in this chain into
1614 * the fragment pointers. Stop when we run out
1615 * of fragments or hit the end of the mbuf chain.
1618 cur = frag = *txidx;
1620 for (m = m_head; m != NULL; m = m->m_next) {
1621 if (m->m_len != 0) {
1622 if ((NGE_TX_LIST_CNT -
1623 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1625 f = &sc->nge_ldata->nge_tx_list[frag];
1626 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1627 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1629 f->nge_ctl |= NGE_CMDSTS_OWN;
1631 NGE_INC(frag, NGE_TX_LIST_CNT);
1639 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1640 if (m_head->m_pkthdr.csum_flags) {
1641 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1642 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1643 NGE_TXEXTSTS_IPCSUM;
1644 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1645 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1646 NGE_TXEXTSTS_TCPCSUM;
1647 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1648 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1649 NGE_TXEXTSTS_UDPCSUM;
1653 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1654 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag);
1657 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1658 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1659 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1660 sc->nge_cdata.nge_tx_cnt += cnt;
1667 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1668 * to the mbuf data regions directly in the transmit lists. We also save a
1669 * copy of the pointers since the transmit list fragment pointers are
1670 * physical addresses.
1674 nge_start(struct ifnet *ifp)
1676 struct nge_softc *sc = ifp->if_softc;
1677 struct mbuf *m_head = NULL;
1683 idx = sc->nge_cdata.nge_tx_prod;
1685 if (ifp->if_flags & IFF_OACTIVE)
1688 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1689 m_head = ifq_poll(&ifp->if_snd);
1693 if (nge_encap(sc, m_head, &idx)) {
1694 ifp->if_flags |= IFF_OACTIVE;
1697 m_head = ifq_dequeue(&ifp->if_snd);
1699 BPF_MTAP(ifp, m_head);
1703 sc->nge_cdata.nge_tx_prod = idx;
1704 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1707 * Set a timeout in case the chip goes out to lunch.
1715 struct nge_softc *sc = xsc;
1716 struct ifnet *ifp = &sc->arpcom.ac_if;
1717 struct mii_data *mii;
1720 if (ifp->if_flags & IFF_RUNNING)
1726 * Cancel pending I/O and free all RX/TX buffers.
1729 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1734 mii = device_get_softc(sc->nge_miibus);
1736 /* Set MAC address */
1737 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1738 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1739 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1740 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1741 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1742 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1743 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1744 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1745 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1747 /* Init circular RX list. */
1748 if (nge_list_rx_init(sc) == ENOBUFS) {
1749 printf("nge%d: initialization failed: no "
1750 "memory for rx buffers\n", sc->nge_unit);
1757 * Init tx descriptors.
1759 nge_list_tx_init(sc);
1762 * For the NatSemi chip, we have to explicitly enable the
1763 * reception of ARP frames, as well as turn on the 'perfect
1764 * match' filter where we store the station address, otherwise
1765 * we won't receive unicasts meant for this host.
1767 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1768 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1770 /* If we want promiscuous mode, set the allframes bit. */
1771 if (ifp->if_flags & IFF_PROMISC)
1772 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1774 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1777 * Set the capture broadcast bit to capture broadcast frames.
1779 if (ifp->if_flags & IFF_BROADCAST)
1780 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1782 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1785 * Load the multicast filter.
1789 /* Turn the receive filter on */
1790 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1793 * Load the address of the RX and TX lists.
1795 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1796 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1797 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1798 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1800 /* Set RX configuration */
1801 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1803 * Enable hardware checksum validation for all IPv4
1804 * packets, do not reject packets with bad checksums.
1806 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1809 * Tell the chip to detect and strip VLAN tag info from
1810 * received frames. The tag will be provided in the extsts
1811 * field in the RX descriptors.
1813 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1814 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1816 /* Set TX configuration */
1817 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1820 * Enable TX IPv4 checksumming on a per-packet basis.
1822 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1825 * Tell the chip to insert VLAN tags on a per-packet basis as
1826 * dictated by the code in the frame encapsulation routine.
1828 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1830 /* Set full/half duplex mode. */
1832 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1834 NGE_SETBIT(sc, NGE_TX_CFG,
1835 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1836 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1838 NGE_CLRBIT(sc, NGE_TX_CFG,
1839 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1840 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1843 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1844 NGE_SETBIT(sc, NGE_TX_CFG,
1845 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1846 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1848 NGE_CLRBIT(sc, NGE_TX_CFG,
1849 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1850 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1855 * Enable the delivery of PHY interrupts based on
1856 * link/speed/duplex status changes. Also enable the
1857 * extsts field in the DMA descriptors (needed for
1858 * TCP/IP checksum offload on transmit).
1860 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1861 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
1864 * Configure interrupt holdoff (moderation). We can
1865 * have the chip delay interrupt delivery for a certain
1866 * period. Units are in 100us, and the max setting
1867 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1869 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1872 * Enable interrupts.
1874 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1875 #ifdef DEVICE_POLLING
1877 * ... only enable interrupts if we are not polling, make sure
1878 * they are off otherwise.
1880 if (ifp->if_flags & IFF_POLLING)
1881 CSR_WRITE_4(sc, NGE_IER, 0);
1883 #endif /* DEVICE_POLLING */
1884 CSR_WRITE_4(sc, NGE_IER, 1);
1886 /* Enable receiver and transmitter. */
1887 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
1888 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1890 nge_ifmedia_upd(ifp);
1892 ifp->if_flags |= IFF_RUNNING;
1893 ifp->if_flags &= ~IFF_OACTIVE;
1899 * Set media options.
1902 nge_ifmedia_upd(struct ifnet *ifp)
1904 struct nge_softc *sc = ifp->if_softc;
1905 struct mii_data *mii;
1908 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1910 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1911 CSR_READ_4(sc, NGE_TBI_ANAR)
1912 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1913 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1914 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1915 | NGE_TBIBMCR_RESTART_ANEG);
1916 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1917 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1918 & IFM_GMASK) == IFM_FDX) {
1919 NGE_SETBIT(sc, NGE_TX_CFG,
1920 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1921 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1923 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1924 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1926 NGE_CLRBIT(sc, NGE_TX_CFG,
1927 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1928 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1930 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1931 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1934 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1935 & ~NGE_GPIO_GP3_OUT);
1937 mii = device_get_softc(sc->nge_miibus);
1939 if (mii->mii_instance) {
1940 struct mii_softc *miisc;
1941 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1942 miisc = LIST_NEXT(miisc, mii_list))
1943 mii_phy_reset(miisc);
1952 * Report current media status.
1955 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1957 struct nge_softc *sc = ifp->if_softc;
1958 struct mii_data *mii;
1961 ifmr->ifm_status = IFM_AVALID;
1962 ifmr->ifm_active = IFM_ETHER;
1964 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
1965 ifmr->ifm_status |= IFM_ACTIVE;
1966 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1967 ifmr->ifm_active |= IFM_LOOP;
1968 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1969 ifmr->ifm_active |= IFM_NONE;
1970 ifmr->ifm_status = 0;
1973 ifmr->ifm_active |= IFM_1000_SX;
1974 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1976 ifmr->ifm_active |= IFM_AUTO;
1977 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1978 & NGE_TBIANAR_FDX) {
1979 ifmr->ifm_active |= IFM_FDX;
1980 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1981 & NGE_TBIANAR_HDX) {
1982 ifmr->ifm_active |= IFM_HDX;
1984 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1986 ifmr->ifm_active |= IFM_FDX;
1988 ifmr->ifm_active |= IFM_HDX;
1991 mii = device_get_softc(sc->nge_miibus);
1993 ifmr->ifm_active = mii->mii_media_active;
1994 ifmr->ifm_status = mii->mii_media_status;
1999 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2001 struct nge_softc *sc = ifp->if_softc;
2002 struct ifreq *ifr = (struct ifreq *) data;
2003 struct mii_data *mii;
2011 error = ether_ioctl(ifp, command, data);
2014 if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
2017 ifp->if_mtu = ifr->ifr_mtu;
2019 * Workaround: if the MTU is larger than
2020 * 8152 (TX FIFO size minus 64 minus 18), turn off
2021 * TX checksum offloading.
2023 if (ifr->ifr_mtu >= 8152)
2024 ifp->if_hwassist = 0;
2026 ifp->if_hwassist = NGE_CSUM_FEATURES;
2030 if (ifp->if_flags & IFF_UP) {
2031 if (ifp->if_flags & IFF_RUNNING &&
2032 ifp->if_flags & IFF_PROMISC &&
2033 !(sc->nge_if_flags & IFF_PROMISC)) {
2034 NGE_SETBIT(sc, NGE_RXFILT_CTL,
2035 NGE_RXFILTCTL_ALLPHYS|
2036 NGE_RXFILTCTL_ALLMULTI);
2037 } else if (ifp->if_flags & IFF_RUNNING &&
2038 !(ifp->if_flags & IFF_PROMISC) &&
2039 sc->nge_if_flags & IFF_PROMISC) {
2040 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2041 NGE_RXFILTCTL_ALLPHYS);
2042 if (!(ifp->if_flags & IFF_ALLMULTI))
2043 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2044 NGE_RXFILTCTL_ALLMULTI);
2046 ifp->if_flags &= ~IFF_RUNNING;
2050 if (ifp->if_flags & IFF_RUNNING)
2053 sc->nge_if_flags = ifp->if_flags;
2064 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2067 mii = device_get_softc(sc->nge_miibus);
2068 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2083 nge_watchdog(struct ifnet *ifp)
2085 struct nge_softc *sc = ifp->if_softc;
2088 printf("nge%d: watchdog timeout\n", sc->nge_unit);
2092 ifp->if_flags &= ~IFF_RUNNING;
2095 if (!ifq_is_empty(&ifp->if_snd))
2100 * Stop the adapter and free any mbufs allocated to the
2104 nge_stop(struct nge_softc *sc)
2106 struct ifnet *ifp = &sc->arpcom.ac_if;
2107 struct ifmedia_entry *ifm;
2108 struct mii_data *mii;
2115 mii = device_get_softc(sc->nge_miibus);
2117 callout_stop(&sc->nge_stat_timer);
2118 #ifdef DEVICE_POLLING
2119 ether_poll_deregister(ifp);
2121 CSR_WRITE_4(sc, NGE_IER, 0);
2122 CSR_WRITE_4(sc, NGE_IMR, 0);
2123 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2125 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2126 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2129 * Isolate/power down the PHY, but leave the media selection
2130 * unchanged so that things will be put back to normal when
2131 * we bring the interface back up.
2133 itmp = ifp->if_flags;
2134 ifp->if_flags |= IFF_UP;
2137 ifm = sc->nge_ifmedia.ifm_cur;
2139 ifm = mii->mii_media.ifm_cur;
2141 mtmp = ifm->ifm_media;
2142 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2146 ifm->ifm_media = mtmp;
2147 ifp->if_flags = itmp;
2152 * Free data in the RX lists.
2154 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2155 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2156 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2157 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2160 bzero(&sc->nge_ldata->nge_rx_list,
2161 sizeof(sc->nge_ldata->nge_rx_list));
2164 * Free the TX list buffers.
2166 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2167 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2168 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2169 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2173 bzero(&sc->nge_ldata->nge_tx_list,
2174 sizeof(sc->nge_ldata->nge_tx_list));
2176 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2180 * Stop all chip I/O so that the kernel's probe routines don't
2181 * get confused by errant DMAs when rebooting.
2184 nge_shutdown(device_t dev)
2186 struct nge_softc *sc = device_get_softc(dev);