sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 /*
  37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  38  *
  39  * Written by Bill Paul <wpaul@windriver.com>
  40  * Senior Engineer, Wind River Systems
  41  */
  42
  43 /*
  44  * The Broadcom BCM5700 is based on technology originally developed by
  45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  49  * frames, highly configurable RX filtering, and 16 RX and TX queues
  50  * (which, along with RX filter rules, can be used for QOS applications).
  51  * Other features, such as TCP segmentation, may be available as part
  52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  53  * firmware images can be stored in hardware and need not be compiled
  54  * into the driver.
  55  *
  56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  58  *
  59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  61  * does not support external SSRAM.
  62  *
  63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  64  * brand name, which is functionally similar but lacks PCI-X support.
  65  *
  66  * Without external SSRAM, you can only have at most 4 TX rings,
  67  * and the use of the mini RX ring is disabled. This seems to imply
  68  * that these features are simply not available on the BCM5701. As a
  69  * result, this driver does not implement any support for the mini RX
  70  * ring.
  71  */
  72
  73 #include "opt_polling.h"
  74
  75 #include <sys/param.h>
  76 #include <sys/bus.h>
  77 #include <sys/endian.h>
  78 #include <sys/kernel.h>
  79 #include <sys/ktr.h>
  80 #include <sys/interrupt.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <net/bpf.h>
  91 #include <net/ethernet.h>
  92 #include <net/if.h>
  93 #include <net/if_arp.h>
  94 #include <net/if_dl.h>
  95 #include <net/if_media.h>
  96 #include <net/if_types.h>
  97 #include <net/ifq_var.h>
  98 #include <net/vlan/if_vlan_var.h>
  99 #include <net/vlan/if_vlan_ether.h>
 100
 101 #include <dev/netif/mii_layer/mii.h>
 102 #include <dev/netif/mii_layer/miivar.h>
 103 #include <dev/netif/mii_layer/brgphyreg.h>
 104
 105 #include <bus/pci/pcidevs.h>
 106 #include <bus/pci/pcireg.h>
 107 #include <bus/pci/pcivar.h>
 108
 109 #include <dev/netif/bge/if_bgereg.h>
 110
 111 /* "device miibus" required.  See GENERIC if you get errors here. */
 112 #include "miibus_if.h"
 113
 114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 115 #define BGE_MIN_FRAME           60
 116
 117 static const struct bge_type bge_devs[] = {
 118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 119                 "3COM 3C996 Gigabit Ethernet" },
 120
 121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 122                 "Alteon BCM5700 Gigabit Ethernet" },
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 124                 "Alteon BCM5701 Gigabit Ethernet" },
 125
 126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 127                 "Altima AC1000 Gigabit Ethernet" },
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 129                 "Altima AC1002 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 131                 "Altima AC9100 Gigabit Ethernet" },
 132
 133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 134                 "Apple BCM5701 Gigabit Ethernet" },
 135
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 141                 "Broadcom BCM5702 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 143                 "Broadcom BCM5702X Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 145                 "Broadcom BCM5702 Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 149                 "Broadcom BCM5703X Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 151                 "Broadcom BCM5703 Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 159                 "Broadcom BCM5705 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 161                 "Broadcom BCM5705F Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 163                 "Broadcom BCM5705K Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 165                 "Broadcom BCM5705M Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 169                 "Broadcom BCM5714C Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 171                 "Broadcom BCM5714S Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 173                 "Broadcom BCM5715 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 175                 "Broadcom BCM5715S Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 177                 "Broadcom BCM5720 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 179                 "Broadcom BCM5721 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 181                 "Broadcom BCM5722 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
 183                 "Broadcom BCM5723 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
 215                 "Broadcom BCM5761 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
 217                 "Broadcom BCM5761E Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
 219                 "Broadcom BCM5761S Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
 221                 "Broadcom BCM5761SE Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
 223                 "Broadcom BCM5764 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 225                 "Broadcom BCM5780 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 227                 "Broadcom BCM5780S Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 229                 "Broadcom BCM5781 Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 231                 "Broadcom BCM5782 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
 233                 "Broadcom BCM5784 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
 235                 "Broadcom BCM5785F Gigabit Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
 237                 "Broadcom BCM5785G Gigabit Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 239                 "Broadcom BCM5786 Gigabit Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 241                 "Broadcom BCM5787 Gigabit Ethernet" },
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 243                 "Broadcom BCM5787F Gigabit Ethernet" },
 244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 245                 "Broadcom BCM5787M Gigabit Ethernet" },
 246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 247                 "Broadcom BCM5788 Gigabit Ethernet" },
 248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 249                 "Broadcom BCM5789 Gigabit Ethernet" },
 250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 251                 "Broadcom BCM5901 Fast Ethernet" },
 252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 253                 "Broadcom BCM5901A2 Fast Ethernet" },
 254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 255                 "Broadcom BCM5903M Fast Ethernet" },
 256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 257                 "Broadcom BCM5906 Fast Ethernet"},
 258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 259                 "Broadcom BCM5906M Fast Ethernet"},
 260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
 261                 "Broadcom BCM57760 Gigabit Ethernet"},
 262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
 263                 "Broadcom BCM57780 Gigabit Ethernet"},
 264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
 265                 "Broadcom BCM57788 Gigabit Ethernet"},
 266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
 267                 "Broadcom BCM57790 Gigabit Ethernet"},
 268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 269                 "SysKonnect Gigabit Ethernet" },
 270
 271         { 0, 0, NULL }
 272 };
 273
 274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 280
 281 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 282
 283 static int      bge_probe(device_t);
 284 static int      bge_attach(device_t);
 285 static int      bge_detach(device_t);
 286 static void     bge_txeof(struct bge_softc *);
 287 static void     bge_rxeof(struct bge_softc *);
 288
 289 static void     bge_tick(void *);
 290 static void     bge_stats_update(struct bge_softc *);
 291 static void     bge_stats_update_regs(struct bge_softc *);
 292 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 293
 294 #ifdef DEVICE_POLLING
 295 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 296 #endif
 297 static void     bge_intr(void *);
 298 static void     bge_enable_intr(struct bge_softc *);
 299 static void     bge_disable_intr(struct bge_softc *);
 300 static void     bge_start(struct ifnet *);
 301 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 302 static void     bge_init(void *);
 303 static void     bge_stop(struct bge_softc *);
 304 static void     bge_watchdog(struct ifnet *);
 305 static void     bge_shutdown(device_t);
 306 static int      bge_suspend(device_t);
 307 static int      bge_resume(device_t);
 308 static int      bge_ifmedia_upd(struct ifnet *);
 309 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 310
 311 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 312 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 313
 314 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 315 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 316
 317 static void     bge_setmulti(struct bge_softc *);
 318 static void     bge_setpromisc(struct bge_softc *);
 319
 320 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 321 static void     bge_free_jumbo_mem(struct bge_softc *);
 322 static struct bge_jslot
 323                 *bge_jalloc(struct bge_softc *);
 324 static void     bge_jfree(void *);
 325 static void     bge_jref(void *);
 326 static int      bge_newbuf_std(struct bge_softc *, int, int);
 327 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
 328 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
 329 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
 330 static int      bge_init_rx_ring_std(struct bge_softc *);
 331 static void     bge_free_rx_ring_std(struct bge_softc *);
 332 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 333 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 334 static void     bge_free_tx_ring(struct bge_softc *);
 335 static int      bge_init_tx_ring(struct bge_softc *);
 336
 337 static int      bge_chipinit(struct bge_softc *);
 338 static int      bge_blockinit(struct bge_softc *);
 339
 340 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 341 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 342 #ifdef notdef
 343 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 344 #endif
 345 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 346 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 347 static void     bge_writembx(struct bge_softc *, int, int);
 348
 349 static int      bge_miibus_readreg(device_t, int, int);
 350 static int      bge_miibus_writereg(device_t, int, int, int);
 351 static void     bge_miibus_statchg(device_t);
 352 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 353 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 354 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 355
 356 static void     bge_reset(struct bge_softc *);
 357
 358 static int      bge_dma_alloc(struct bge_softc *);
 359 static void     bge_dma_free(struct bge_softc *);
 360 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 361                                     bus_dma_tag_t *, bus_dmamap_t *,
 362                                     void **, bus_addr_t *);
 363 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 364
 365 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 366 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 367 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 368 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 369
 370 static void     bge_coal_change(struct bge_softc *);
 371 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 372 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 373 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 374 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 375 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 376
 377 /*
 378  * Set following tunable to 1 for some IBM blade servers with the DNLK
 379  * switch module. Auto negotiation is broken for those configurations.
 380  */
 381 static int      bge_fake_autoneg = 0;
 382 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 383
 384 /* Interrupt moderation control variables. */
 385 static int      bge_rx_coal_ticks = 100;        /* usec */
 386 static int      bge_tx_coal_ticks = 1023;       /* usec */
 387 static int      bge_rx_max_coal_bds = 80;
 388 static int      bge_tx_max_coal_bds = 128;
 389
 390 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 391 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 392 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 393 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 394
 395 #if !defined(KTR_IF_BGE)
 396 #define KTR_IF_BGE      KTR_ALL
 397 #endif
 398 KTR_INFO_MASTER(if_bge);
 399 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
 400 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
 401 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
 402 #define logif(name)     KTR_LOG(if_bge_ ## name)
 403
 404 static device_method_t bge_methods[] = {
 405         /* Device interface */
 406         DEVMETHOD(device_probe,         bge_probe),
 407         DEVMETHOD(device_attach,        bge_attach),
 408         DEVMETHOD(device_detach,        bge_detach),
 409         DEVMETHOD(device_shutdown,      bge_shutdown),
 410         DEVMETHOD(device_suspend,       bge_suspend),
 411         DEVMETHOD(device_resume,        bge_resume),
 412
 413         /* bus interface */
 414         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 415         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 416
 417         /* MII interface */
 418         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 419         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 420         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 421
 422         { 0, 0 }
 423 };
 424
 425 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 426 static devclass_t bge_devclass;
 427
 428 DECLARE_DUMMY_MODULE(if_bge);
 429 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
 430 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
 431
 432 static uint32_t
 433 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 434 {
 435         device_t dev = sc->bge_dev;
 436         uint32_t val;
 437
 438         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 439         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 440         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 441         return (val);
 442 }
 443
 444 static void
 445 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 446 {
 447         device_t dev = sc->bge_dev;
 448
 449         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 450         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 451         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 452 }
 453
 454 #ifdef notdef
 455 static uint32_t
 456 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 457 {
 458         device_t dev = sc->bge_dev;
 459
 460         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 461         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 462 }
 463 #endif
 464
 465 static void
 466 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 467 {
 468         device_t dev = sc->bge_dev;
 469
 470         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 471         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 472 }
 473
 474 static void
 475 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 476 {
 477         CSR_WRITE_4(sc, off, val);
 478 }
 479
 480 static void
 481 bge_writembx(struct bge_softc *sc, int off, int val)
 482 {
 483         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 484                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 485
 486         CSR_WRITE_4(sc, off, val);
 487 }
 488
 489 static uint8_t
 490 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 491 {
 492         uint32_t access, byte = 0;
 493         int i;
 494
 495         /* Lock. */
 496         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 497         for (i = 0; i < 8000; i++) {
 498                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 499                         break;
 500                 DELAY(20);
 501         }
 502         if (i == 8000)
 503                 return (1);
 504
 505         /* Enable access. */
 506         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 507         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 508
 509         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 510         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 511         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 512                 DELAY(10);
 513                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 514                         DELAY(10);
 515                         break;
 516                 }
 517         }
 518
 519         if (i == BGE_TIMEOUT * 10) {
 520                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 521                 return (1);
 522         }
 523
 524         /* Get result. */
 525         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 526
 527         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 528
 529         /* Disable access. */
 530         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 531
 532         /* Unlock. */
 533         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 534         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 535
 536         return (0);
 537 }
 538
 539 /*
 540  * Read a sequence of bytes from NVRAM.
 541  */
 542 static int
 543 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 544 {
 545         int err = 0, i;
 546         uint8_t byte = 0;
 547
 548         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 549                 return (1);
 550
 551         for (i = 0; i < cnt; i++) {
 552                 err = bge_nvram_getbyte(sc, off + i, &byte);
 553                 if (err)
 554                         break;
 555                 *(dest + i) = byte;
 556         }
 557
 558         return (err ? 1 : 0);
 559 }
 560
 561 /*
 562  * Read a byte of data stored in the EEPROM at address 'addr.' The
 563  * BCM570x supports both the traditional bitbang interface and an
 564  * auto access interface for reading the EEPROM. We use the auto
 565  * access method.
 566  */
 567 static uint8_t
 568 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 569 {
 570         int i;
 571         uint32_t byte = 0;
 572
 573         /*
 574          * Enable use of auto EEPROM access so we can avoid
 575          * having to use the bitbang method.
 576          */
 577         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 578
 579         /* Reset the EEPROM, load the clock period. */
 580         CSR_WRITE_4(sc, BGE_EE_ADDR,
 581             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 582         DELAY(20);
 583
 584         /* Issue the read EEPROM command. */
 585         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 586
 587         /* Wait for completion */
 588         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 589                 DELAY(10);
 590                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 591                         break;
 592         }
 593
 594         if (i == BGE_TIMEOUT) {
 595                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 596                 return(1);
 597         }
 598
 599         /* Get result. */
 600         byte = CSR_READ_4(sc, BGE_EE_DATA);
 601
 602         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 603
 604         return(0);
 605 }
 606
 607 /*
 608  * Read a sequence of bytes from the EEPROM.
 609  */
 610 static int
 611 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 612 {
 613         size_t i;
 614         int err;
 615         uint8_t byte;
 616
 617         for (byte = 0, err = 0, i = 0; i < len; i++) {
 618                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 619                 if (err)
 620                         break;
 621                 *(dest + i) = byte;
 622         }
 623
 624         return(err ? 1 : 0);
 625 }
 626
 627 static int
 628 bge_miibus_readreg(device_t dev, int phy, int reg)
 629 {
 630         struct bge_softc *sc = device_get_softc(dev);
 631         struct ifnet *ifp = &sc->arpcom.ac_if;
 632         uint32_t val, autopoll;
 633         int i;
 634
 635         /*
 636          * Broadcom's own driver always assumes the internal
 637          * PHY is at GMII address 1. On some chips, the PHY responds
 638          * to accesses at all addresses, which could cause us to
 639          * bogusly attach the PHY 32 times at probe type. Always
 640          * restricting the lookup to address 1 is simpler than
 641          * trying to figure out which chips revisions should be
 642          * special-cased.
 643          */
 644         if (phy != 1)
 645                 return(0);
 646
 647         /* Reading with autopolling on may trigger PCI errors */
 648         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 649         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 650                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 651                 DELAY(40);
 652         }
 653
 654         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 655             BGE_MIPHY(phy)|BGE_MIREG(reg));
 656
 657         for (i = 0; i < BGE_TIMEOUT; i++) {
 658                 DELAY(10);
 659                 val = CSR_READ_4(sc, BGE_MI_COMM);
 660                 if (!(val & BGE_MICOMM_BUSY))
 661                         break;
 662         }
 663
 664         if (i == BGE_TIMEOUT) {
 665                 if_printf(ifp, "PHY read timed out "
 666                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 667                 val = 0;
 668                 goto done;
 669         }
 670
 671         DELAY(5);
 672         val = CSR_READ_4(sc, BGE_MI_COMM);
 673
 674 done:
 675         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 676                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 677                 DELAY(40);
 678         }
 679
 680         if (val & BGE_MICOMM_READFAIL)
 681                 return(0);
 682
 683         return(val & 0xFFFF);
 684 }
 685
 686 static int
 687 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 688 {
 689         struct bge_softc *sc = device_get_softc(dev);
 690         uint32_t autopoll;
 691         int i;
 692
 693         /*
 694          * See the related comment in bge_miibus_readreg()
 695          */
 696         if (phy != 1)
 697                 return(0);
 698
 699         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 700             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 701                return(0);
 702
 703         /* Reading with autopolling on may trigger PCI errors */
 704         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 705         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 706                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 707                 DELAY(40);
 708         }
 709
 710         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 711             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 712
 713         for (i = 0; i < BGE_TIMEOUT; i++) {
 714                 DELAY(10);
 715                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 716                         DELAY(5);
 717                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 718                         break;
 719                 }
 720         }
 721
 722         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 723                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 724                 DELAY(40);
 725         }
 726
 727         if (i == BGE_TIMEOUT) {
 728                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 729                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
 730                 return(0);
 731         }
 732
 733         return(0);
 734 }
 735
 736 static void
 737 bge_miibus_statchg(device_t dev)
 738 {
 739         struct bge_softc *sc;
 740         struct mii_data *mii;
 741
 742         sc = device_get_softc(dev);
 743         mii = device_get_softc(sc->bge_miibus);
 744
 745         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 746         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 747                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 748         } else {
 749                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 750         }
 751
 752         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 753                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 754         } else {
 755                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 756         }
 757 }
 758
 759 /*
 760  * Memory management for jumbo frames.
 761  */
 762 static int
 763 bge_alloc_jumbo_mem(struct bge_softc *sc)
 764 {
 765         struct ifnet *ifp = &sc->arpcom.ac_if;
 766         struct bge_jslot *entry;
 767         uint8_t *ptr;
 768         bus_addr_t paddr;
 769         int i, error;
 770
 771         /*
 772          * Create tag for jumbo mbufs.
 773          * This is really a bit of a kludge. We allocate a special
 774          * jumbo buffer pool which (thanks to the way our DMA
 775          * memory allocation works) will consist of contiguous
 776          * pages. This means that even though a jumbo buffer might
 777          * be larger than a page size, we don't really need to
 778          * map it into more than one DMA segment. However, the
 779          * default mbuf tag will result in multi-segment mappings,
 780          * so we have to create a special jumbo mbuf tag that
 781          * lets us get away with mapping the jumbo buffers as
 782          * a single segment. I think eventually the driver should
 783          * be changed so that it uses ordinary mbufs and cluster
 784          * buffers, i.e. jumbo frames can span multiple DMA
 785          * descriptors. But that's a project for another day.
 786          */
 787
 788         /*
 789          * Create DMA stuffs for jumbo RX ring.
 790          */
 791         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 792                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 793                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 794                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
 795                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 796         if (error) {
 797                 if_printf(ifp, "could not create jumbo RX ring\n");
 798                 return error;
 799         }
 800
 801         /*
 802          * Create DMA stuffs for jumbo buffer block.
 803          */
 804         error = bge_dma_block_alloc(sc, BGE_JMEM,
 805                                     &sc->bge_cdata.bge_jumbo_tag,
 806                                     &sc->bge_cdata.bge_jumbo_map,
 807                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 808                                     &paddr);
 809         if (error) {
 810                 if_printf(ifp, "could not create jumbo buffer\n");
 811                 return error;
 812         }
 813
 814         SLIST_INIT(&sc->bge_jfree_listhead);
 815
 816         /*
 817          * Now divide it up into 9K pieces and save the addresses
 818          * in an array. Note that we play an evil trick here by using
 819          * the first few bytes in the buffer to hold the the address
 820          * of the softc structure for this interface. This is because
 821          * bge_jfree() needs it, but it is called by the mbuf management
 822          * code which will not pass it to us explicitly.
 823          */
 824         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 825                 entry = &sc->bge_cdata.bge_jslots[i];
 826                 entry->bge_sc = sc;
 827                 entry->bge_buf = ptr;
 828                 entry->bge_paddr = paddr;
 829                 entry->bge_inuse = 0;
 830                 entry->bge_slot = i;
 831                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 832
 833                 ptr += BGE_JLEN;
 834                 paddr += BGE_JLEN;
 835         }
 836         return 0;
 837 }
 838
 839 static void
 840 bge_free_jumbo_mem(struct bge_softc *sc)
 841 {
 842         /* Destroy jumbo RX ring. */
 843         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 844                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 845                            sc->bge_ldata.bge_rx_jumbo_ring);
 846
 847         /* Destroy jumbo buffer block. */
 848         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 849                            sc->bge_cdata.bge_jumbo_map,
 850                            sc->bge_ldata.bge_jumbo_buf);
 851 }
 852
 853 /*
 854  * Allocate a jumbo buffer.
 855  */
 856 static struct bge_jslot *
 857 bge_jalloc(struct bge_softc *sc)
 858 {
 859         struct bge_jslot *entry;
 860
 861         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 862         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 863         if (entry) {
 864                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 865                 entry->bge_inuse = 1;
 866         } else {
 867                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 868         }
 869         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 870         return(entry);
 871 }
 872
 873 /*
 874  * Adjust usage count on a jumbo buffer.
 875  */
 876 static void
 877 bge_jref(void *arg)
 878 {
 879         struct bge_jslot *entry = (struct bge_jslot *)arg;
 880         struct bge_softc *sc = entry->bge_sc;
 881
 882         if (sc == NULL)
 883                 panic("bge_jref: can't find softc pointer!");
 884
 885         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 886                 panic("bge_jref: asked to reference buffer "
 887                     "that we don't manage!");
 888         } else if (entry->bge_inuse == 0) {
 889                 panic("bge_jref: buffer already free!");
 890         } else {
 891                 atomic_add_int(&entry->bge_inuse, 1);
 892         }
 893 }
 894
 895 /*
 896  * Release a jumbo buffer.
 897  */
 898 static void
 899 bge_jfree(void *arg)
 900 {
 901         struct bge_jslot *entry = (struct bge_jslot *)arg;
 902         struct bge_softc *sc = entry->bge_sc;
 903
 904         if (sc == NULL)
 905                 panic("bge_jfree: can't find softc pointer!");
 906
 907         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 908                 panic("bge_jfree: asked to free buffer that we don't manage!");
 909         } else if (entry->bge_inuse == 0) {
 910                 panic("bge_jfree: buffer already free!");
 911         } else {
 912                 /*
 913                  * Possible MP race to 0, use the serializer.  The atomic insn
 914                  * is still needed for races against bge_jref().
 915                  */
 916                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 917                 atomic_subtract_int(&entry->bge_inuse, 1);
 918                 if (entry->bge_inuse == 0) {
 919                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 920                                           entry, jslot_link);
 921                 }
 922                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 923         }
 924 }
 925
 926
 927 /*
 928  * Intialize a standard receive ring descriptor.
 929  */
 930 static int
 931 bge_newbuf_std(struct bge_softc *sc, int i, int init)
 932 {
 933         struct mbuf *m_new = NULL;
 934         bus_dma_segment_t seg;
 935         bus_dmamap_t map;
 936         int error, nsegs;
 937
 938         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 939         if (m_new == NULL)
 940                 return ENOBUFS;
 941         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 942
 943         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 944                 m_adj(m_new, ETHER_ALIGN);
 945
 946         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
 947                         sc->bge_cdata.bge_rx_tmpmap, m_new,
 948                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 949         if (error) {
 950                 m_freem(m_new);
 951                 return error;
 952         }
 953
 954         if (!init) {
 955                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 956                                 sc->bge_cdata.bge_rx_std_dmamap[i],
 957                                 BUS_DMASYNC_POSTREAD);
 958                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 959                         sc->bge_cdata.bge_rx_std_dmamap[i]);
 960         }
 961
 962         map = sc->bge_cdata.bge_rx_tmpmap;
 963         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
 964         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
 965
 966         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
 967         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
 968
 969         bge_setup_rxdesc_std(sc, i);
 970         return 0;
 971 }
 972
 973 static void
 974 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
 975 {
 976         struct bge_rxchain *rc;
 977         struct bge_rx_bd *r;
 978
 979         rc = &sc->bge_cdata.bge_rx_std_chain[i];
 980         r = &sc->bge_ldata.bge_rx_std_ring[i];
 981
 982         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
 983         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
 984         r->bge_len = rc->bge_mbuf->m_len;
 985         r->bge_idx = i;
 986         r->bge_flags = BGE_RXBDFLAG_END;
 987 }
 988
 989 /*
 990  * Initialize a jumbo receive ring descriptor. This allocates
 991  * a jumbo buffer from the pool managed internally by the driver.
 992  */
 993 static int
 994 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
 995 {
 996         struct mbuf *m_new = NULL;
 997         struct bge_jslot *buf;
 998         bus_addr_t paddr;
 999
1000         /* Allocate the mbuf. */
1001         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1002         if (m_new == NULL)
1003                 return ENOBUFS;
1004
1005         /* Allocate the jumbo buffer */
1006         buf = bge_jalloc(sc);
1007         if (buf == NULL) {
1008                 m_freem(m_new);
1009                 return ENOBUFS;
1010         }
1011
1012         /* Attach the buffer to the mbuf. */
1013         m_new->m_ext.ext_arg = buf;
1014         m_new->m_ext.ext_buf = buf->bge_buf;
1015         m_new->m_ext.ext_free = bge_jfree;
1016         m_new->m_ext.ext_ref = bge_jref;
1017         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1018
1019         m_new->m_flags |= M_EXT;
1020
1021         m_new->m_data = m_new->m_ext.ext_buf;
1022         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1023
1024         paddr = buf->bge_paddr;
1025         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1026                 m_adj(m_new, ETHER_ALIGN);
1027                 paddr += ETHER_ALIGN;
1028         }
1029
1030         /* Save necessary information */
1031         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1032         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1033
1034         /* Set up the descriptor. */
1035         bge_setup_rxdesc_jumbo(sc, i);
1036         return 0;
1037 }
1038
1039 static void
1040 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1041 {
1042         struct bge_rx_bd *r;
1043         struct bge_rxchain *rc;
1044
1045         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1046         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1047
1048         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1049         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1050         r->bge_len = rc->bge_mbuf->m_len;
1051         r->bge_idx = i;
1052         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1053 }
1054
1055 static int
1056 bge_init_rx_ring_std(struct bge_softc *sc)
1057 {
1058         int i, error;
1059
1060         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1061                 error = bge_newbuf_std(sc, i, 1);
1062                 if (error)
1063                         return error;
1064         };
1065
1066         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1067         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1068
1069         return(0);
1070 }
1071
1072 static void
1073 bge_free_rx_ring_std(struct bge_softc *sc)
1074 {
1075         int i;
1076
1077         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1078                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1079
1080                 if (rc->bge_mbuf != NULL) {
1081                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1082                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1083                         m_freem(rc->bge_mbuf);
1084                         rc->bge_mbuf = NULL;
1085                 }
1086                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1087                     sizeof(struct bge_rx_bd));
1088         }
1089 }
1090
1091 static int
1092 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1093 {
1094         struct bge_rcb *rcb;
1095         int i, error;
1096
1097         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1098                 error = bge_newbuf_jumbo(sc, i, 1);
1099                 if (error)
1100                         return error;
1101         };
1102
1103         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1104
1105         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1106         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1107         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1108
1109         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1110
1111         return(0);
1112 }
1113
1114 static void
1115 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1116 {
1117         int i;
1118
1119         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1120                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1121
1122                 if (rc->bge_mbuf != NULL) {
1123                         m_freem(rc->bge_mbuf);
1124                         rc->bge_mbuf = NULL;
1125                 }
1126                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1127                     sizeof(struct bge_rx_bd));
1128         }
1129 }
1130
1131 static void
1132 bge_free_tx_ring(struct bge_softc *sc)
1133 {
1134         int i;
1135
1136         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1137                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1138                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1139                                           sc->bge_cdata.bge_tx_dmamap[i]);
1140                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1141                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1142                 }
1143                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1144                     sizeof(struct bge_tx_bd));
1145         }
1146 }
1147
1148 static int
1149 bge_init_tx_ring(struct bge_softc *sc)
1150 {
1151         sc->bge_txcnt = 0;
1152         sc->bge_tx_saved_considx = 0;
1153         sc->bge_tx_prodidx = 0;
1154
1155         /* Initialize transmit producer index for host-memory send ring. */
1156         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1157
1158         /* 5700 b2 errata */
1159         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1160                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1161
1162         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1163         /* 5700 b2 errata */
1164         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1165                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1166
1167         return(0);
1168 }
1169
1170 static void
1171 bge_setmulti(struct bge_softc *sc)
1172 {
1173         struct ifnet *ifp;
1174         struct ifmultiaddr *ifma;
1175         uint32_t hashes[4] = { 0, 0, 0, 0 };
1176         int h, i;
1177
1178         ifp = &sc->arpcom.ac_if;
1179
1180         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1181                 for (i = 0; i < 4; i++)
1182                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1183                 return;
1184         }
1185
1186         /* First, zot all the existing filters. */
1187         for (i = 0; i < 4; i++)
1188                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1189
1190         /* Now program new ones. */
1191         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1192                 if (ifma->ifma_addr->sa_family != AF_LINK)
1193                         continue;
1194                 h = ether_crc32_le(
1195                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1196                     ETHER_ADDR_LEN) & 0x7f;
1197                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1198         }
1199
1200         for (i = 0; i < 4; i++)
1201                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1202 }
1203
1204 /*
1205  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1206  * self-test results.
1207  */
1208 static int
1209 bge_chipinit(struct bge_softc *sc)
1210 {
1211         int i;
1212         uint32_t dma_rw_ctl;
1213
1214         /* Set endian type before we access any non-PCI registers. */
1215         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1216
1217         /* Clear the MAC control register */
1218         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1219
1220         /*
1221          * Clear the MAC statistics block in the NIC's
1222          * internal memory.
1223          */
1224         for (i = BGE_STATS_BLOCK;
1225             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1226                 BGE_MEMWIN_WRITE(sc, i, 0);
1227
1228         for (i = BGE_STATUS_BLOCK;
1229             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1230                 BGE_MEMWIN_WRITE(sc, i, 0);
1231
1232         /* Set up the PCI DMA control register. */
1233         if (sc->bge_flags & BGE_FLAG_PCIE) {
1234                 /* PCI Express */
1235                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1236                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1237                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1238         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1239                 /* PCI-X bus */
1240                 if (BGE_IS_5714_FAMILY(sc)) {
1241                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1242                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1243                         /* XXX magic values, Broadcom-supplied Linux driver */
1244                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1245                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1246                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1247                         } else {
1248                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1249                         }
1250                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1251                         /*
1252                          * The 5704 uses a different encoding of read/write
1253                          * watermarks.
1254                          */
1255                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1256                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1257                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1258                 } else {
1259                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1260                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1261                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1262                             (0x0F);
1263                 }
1264
1265                 /*
1266                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1267                  * for hardware bugs.
1268                  */
1269                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1270                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1271                         uint32_t tmp;
1272
1273                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1274                         if (tmp == 0x6 || tmp == 0x7)
1275                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1276                 }
1277         } else {
1278                 /* Conventional PCI bus */
1279                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1280                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1281                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1282                     (0x0F);
1283         }
1284
1285         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1286             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1287             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1288                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1289         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1290
1291         /*
1292          * Set up general mode register.
1293          */
1294         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1295             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1296             BGE_MODECTL_TX_NO_PHDR_CSUM);
1297
1298         /*
1299          * BCM5701 B5 have a bug causing data corruption when using
1300          * 64-bit DMA reads, which can be terminated early and then
1301          * completed later as 32-bit accesses, in combination with
1302          * certain bridges.
1303          */
1304         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1305             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1306                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1307
1308         /*
1309          * Disable memory write invalidate.  Apparently it is not supported
1310          * properly by these devices.
1311          */
1312         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1313
1314         /* Set the timer prescaler (always 66Mhz) */
1315         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1316
1317         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1318                 DELAY(40);      /* XXX */
1319
1320                 /* Put PHY into ready state */
1321                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1322                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1323                 DELAY(40);
1324         }
1325
1326         return(0);
1327 }
1328
1329 static int
1330 bge_blockinit(struct bge_softc *sc)
1331 {
1332         struct bge_rcb *rcb;
1333         bus_size_t vrcb;
1334         bge_hostaddr taddr;
1335         uint32_t val;
1336         int i;
1337
1338         /*
1339          * Initialize the memory window pointer register so that
1340          * we can access the first 32K of internal NIC RAM. This will
1341          * allow us to set up the TX send ring RCBs and the RX return
1342          * ring RCBs, plus other things which live in NIC memory.
1343          */
1344         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1345
1346         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1347
1348         if (!BGE_IS_5705_PLUS(sc)) {
1349                 /* Configure mbuf memory pool */
1350                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1351                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1352                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1353                 else
1354                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1355
1356                 /* Configure DMA resource pool */
1357                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1358                     BGE_DMA_DESCRIPTORS);
1359                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1360         }
1361
1362         /* Configure mbuf pool watermarks */
1363         if (!BGE_IS_5705_PLUS(sc)) {
1364                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1365                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1366                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1367         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1368                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1369                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1370                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1371         } else {
1372                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1373                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1374                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1375         }
1376
1377         /* Configure DMA resource watermarks */
1378         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1379         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1380
1381         /* Enable buffer manager */
1382         if (!BGE_IS_5705_PLUS(sc)) {
1383                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1384                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1385
1386                 /* Poll for buffer manager start indication */
1387                 for (i = 0; i < BGE_TIMEOUT; i++) {
1388                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1389                                 break;
1390                         DELAY(10);
1391                 }
1392
1393                 if (i == BGE_TIMEOUT) {
1394                         if_printf(&sc->arpcom.ac_if,
1395                                   "buffer manager failed to start\n");
1396                         return(ENXIO);
1397                 }
1398         }
1399
1400         /* Enable flow-through queues */
1401         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1402         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1403
1404         /* Wait until queue initialization is complete */
1405         for (i = 0; i < BGE_TIMEOUT; i++) {
1406                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1407                         break;
1408                 DELAY(10);
1409         }
1410
1411         if (i == BGE_TIMEOUT) {
1412                 if_printf(&sc->arpcom.ac_if,
1413                           "flow-through queue init failed\n");
1414                 return(ENXIO);
1415         }
1416
1417         /* Initialize the standard RX ring control block */
1418         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1419         rcb->bge_hostaddr.bge_addr_lo =
1420             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1421         rcb->bge_hostaddr.bge_addr_hi =
1422             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1423         if (BGE_IS_5705_PLUS(sc))
1424                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1425         else
1426                 rcb->bge_maxlen_flags =
1427                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1428         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1429         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1430         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1431         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1432         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1433
1434         /*
1435          * Initialize the jumbo RX ring control block
1436          * We set the 'ring disabled' bit in the flags
1437          * field until we're actually ready to start
1438          * using this ring (i.e. once we set the MTU
1439          * high enough to require it).
1440          */
1441         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1442                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1443
1444                 rcb->bge_hostaddr.bge_addr_lo =
1445                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1446                 rcb->bge_hostaddr.bge_addr_hi =
1447                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1448                 rcb->bge_maxlen_flags =
1449                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1450                     BGE_RCB_FLAG_RING_DISABLED);
1451                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1452                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1453                     rcb->bge_hostaddr.bge_addr_hi);
1454                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1455                     rcb->bge_hostaddr.bge_addr_lo);
1456                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1457                     rcb->bge_maxlen_flags);
1458                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1459
1460                 /* Set up dummy disabled mini ring RCB */
1461                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1462                 rcb->bge_maxlen_flags =
1463                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1464                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1465                     rcb->bge_maxlen_flags);
1466         }
1467
1468         /*
1469          * Set the BD ring replentish thresholds. The recommended
1470          * values are 1/8th the number of descriptors allocated to
1471          * each ring.
1472          */
1473         if (BGE_IS_5705_PLUS(sc))
1474                 val = 8;
1475         else
1476                 val = BGE_STD_RX_RING_CNT / 8;
1477         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1478         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1479
1480         /*
1481          * Disable all unused send rings by setting the 'ring disabled'
1482          * bit in the flags field of all the TX send ring control blocks.
1483          * These are located in NIC memory.
1484          */
1485         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1486         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1487                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1488                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1489                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1490                 vrcb += sizeof(struct bge_rcb);
1491         }
1492
1493         /* Configure TX RCB 0 (we use only the first ring) */
1494         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1495         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1496         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1497         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1498         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1499             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1500         if (!BGE_IS_5705_PLUS(sc)) {
1501                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1502                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1503         }
1504
1505         /* Disable all unused RX return rings */
1506         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1507         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1508                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1509                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1510                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1511                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1512                     BGE_RCB_FLAG_RING_DISABLED));
1513                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1514                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1515                     (i * (sizeof(uint64_t))), 0);
1516                 vrcb += sizeof(struct bge_rcb);
1517         }
1518
1519         /* Initialize RX ring indexes */
1520         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1521         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1522         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1523
1524         /*
1525          * Set up RX return ring 0
1526          * Note that the NIC address for RX return rings is 0x00000000.
1527          * The return rings live entirely within the host, so the
1528          * nicaddr field in the RCB isn't used.
1529          */
1530         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1531         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1532         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1533         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1534         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1535         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1536             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1537
1538         /* Set random backoff seed for TX */
1539         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1540             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1541             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1542             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1543             BGE_TX_BACKOFF_SEED_MASK);
1544
1545         /* Set inter-packet gap */
1546         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1547
1548         /*
1549          * Specify which ring to use for packets that don't match
1550          * any RX rules.
1551          */
1552         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1553
1554         /*
1555          * Configure number of RX lists. One interrupt distribution
1556          * list, sixteen active lists, one bad frames class.
1557          */
1558         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1559
1560         /* Inialize RX list placement stats mask. */
1561         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1562         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1563
1564         /* Disable host coalescing until we get it set up */
1565         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1566
1567         /* Poll to make sure it's shut down. */
1568         for (i = 0; i < BGE_TIMEOUT; i++) {
1569                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1570                         break;
1571                 DELAY(10);
1572         }
1573
1574         if (i == BGE_TIMEOUT) {
1575                 if_printf(&sc->arpcom.ac_if,
1576                           "host coalescing engine failed to idle\n");
1577                 return(ENXIO);
1578         }
1579
1580         /* Set up host coalescing defaults */
1581         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1582         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1583         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1584         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1585         if (!BGE_IS_5705_PLUS(sc)) {
1586                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1587                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1588         }
1589         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1590         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1591
1592         /* Set up address of statistics block */
1593         if (!BGE_IS_5705_PLUS(sc)) {
1594                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1595                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1596                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1597                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1598
1599                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1600                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1601                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1602         }
1603
1604         /* Set up address of status block */
1605         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1606             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1607         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1608             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1609         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1610         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1611
1612         /* Turn on host coalescing state machine */
1613         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1614
1615         /* Turn on RX BD completion state machine and enable attentions */
1616         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1617             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1618
1619         /* Turn on RX list placement state machine */
1620         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1621
1622         /* Turn on RX list selector state machine. */
1623         if (!BGE_IS_5705_PLUS(sc))
1624                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1625
1626         /* Turn on DMA, clear stats */
1627         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1628             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1629             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1630             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1631             ((sc->bge_flags & BGE_FLAG_TBI) ?
1632              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1633
1634         /* Set misc. local control, enable interrupts on attentions */
1635         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1636
1637 #ifdef notdef
1638         /* Assert GPIO pins for PHY reset */
1639         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1640             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1641         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1642             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1643 #endif
1644
1645         /* Turn on DMA completion state machine */
1646         if (!BGE_IS_5705_PLUS(sc))
1647                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1648
1649         /* Turn on write DMA state machine */
1650         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1651         if (BGE_IS_5755_PLUS(sc)) {
1652                 /* Enable host coalescing bug fix. */
1653                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1654         }
1655         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1656         DELAY(40);
1657
1658         /* Turn on read DMA state machine */
1659         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1660         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1661             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1662             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1663                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1664                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1665                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1666         if (sc->bge_flags & BGE_FLAG_PCIE)
1667                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1668         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1669         DELAY(40);
1670
1671         /* Turn on RX data completion state machine */
1672         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1673
1674         /* Turn on RX BD initiator state machine */
1675         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1676
1677         /* Turn on RX data and RX BD initiator state machine */
1678         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1679
1680         /* Turn on Mbuf cluster free state machine */
1681         if (!BGE_IS_5705_PLUS(sc))
1682                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1683
1684         /* Turn on send BD completion state machine */
1685         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1686
1687         /* Turn on send data completion state machine */
1688         val = BGE_SDCMODE_ENABLE;
1689         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1690                 val |= BGE_SDCMODE_CDELAY;
1691         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1692
1693         /* Turn on send data initiator state machine */
1694         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1695
1696         /* Turn on send BD initiator state machine */
1697         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1698
1699         /* Turn on send BD selector state machine */
1700         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1701
1702         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1703         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1704             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1705
1706         /* ack/clear link change events */
1707         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1708             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1709             BGE_MACSTAT_LINK_CHANGED);
1710         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1711
1712         /* Enable PHY auto polling (for MII/GMII only) */
1713         if (sc->bge_flags & BGE_FLAG_TBI) {
1714                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1715         } else {
1716                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1717                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1718                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1719                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1720                             BGE_EVTENB_MI_INTERRUPT);
1721                 }
1722         }
1723
1724         /*
1725          * Clear any pending link state attention.
1726          * Otherwise some link state change events may be lost until attention
1727          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1728          * It's not necessary on newer BCM chips - perhaps enabling link
1729          * state change attentions implies clearing pending attention.
1730          */
1731         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1732             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1733             BGE_MACSTAT_LINK_CHANGED);
1734
1735         /* Enable link state change attentions. */
1736         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1737
1738         return(0);
1739 }
1740
1741 /*
1742  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1743  * against our list and return its name if we find a match. Note
1744  * that since the Broadcom controller contains VPD support, we
1745  * can get the device name string from the controller itself instead
1746  * of the compiled-in string. This is a little slow, but it guarantees
1747  * we'll always announce the right product name.
1748  */
1749 static int
1750 bge_probe(device_t dev)
1751 {
1752         const struct bge_type *t;
1753         uint16_t product, vendor;
1754
1755         product = pci_get_device(dev);
1756         vendor = pci_get_vendor(dev);
1757
1758         for (t = bge_devs; t->bge_name != NULL; t++) {
1759                 if (vendor == t->bge_vid && product == t->bge_did)
1760                         break;
1761         }
1762         if (t->bge_name == NULL)
1763                 return(ENXIO);
1764
1765         device_set_desc(dev, t->bge_name);
1766         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1767                 struct bge_softc *sc = device_get_softc(dev);
1768                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1769         }
1770         return(0);
1771 }
1772
1773 static int
1774 bge_attach(device_t dev)
1775 {
1776         struct ifnet *ifp;
1777         struct bge_softc *sc;
1778         uint32_t hwcfg = 0;
1779         int error = 0, rid;
1780         uint8_t ether_addr[ETHER_ADDR_LEN];
1781
1782         sc = device_get_softc(dev);
1783         sc->bge_dev = dev;
1784         callout_init(&sc->bge_stat_timer);
1785         lwkt_serialize_init(&sc->bge_jslot_serializer);
1786
1787 #ifndef BURN_BRIDGES
1788         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1789                 uint32_t irq, mem;
1790
1791                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1792                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1793
1794                 device_printf(dev, "chip is in D%d power mode "
1795                     "-- setting to D0\n", pci_get_powerstate(dev));
1796
1797                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1798
1799                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1800                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1801         }
1802 #endif  /* !BURN_BRIDGE */
1803
1804         /*
1805          * Map control/status registers.
1806          */
1807         pci_enable_busmaster(dev);
1808
1809         rid = BGE_PCI_BAR0;
1810         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1811             RF_ACTIVE);
1812
1813         if (sc->bge_res == NULL) {
1814                 device_printf(dev, "couldn't map memory\n");
1815                 return ENXIO;
1816         }
1817
1818         sc->bge_btag = rman_get_bustag(sc->bge_res);
1819         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1820
1821         /* Save various chip information */
1822         sc->bge_chipid =
1823             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1824             BGE_PCIMISCCTL_ASICREV_SHIFT;
1825         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1826                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1827         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1828         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1829
1830         /* Save chipset family. */
1831         switch (sc->bge_asicrev) {
1832         case BGE_ASICREV_BCM5755:
1833         case BGE_ASICREV_BCM5761:
1834         case BGE_ASICREV_BCM5784:
1835         case BGE_ASICREV_BCM5785:
1836         case BGE_ASICREV_BCM5787:
1837         case BGE_ASICREV_BCM57780:
1838             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1839                 BGE_FLAG_5705_PLUS;
1840             break;
1841
1842         case BGE_ASICREV_BCM5700:
1843         case BGE_ASICREV_BCM5701:
1844         case BGE_ASICREV_BCM5703:
1845         case BGE_ASICREV_BCM5704:
1846                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1847                 break;
1848
1849         case BGE_ASICREV_BCM5714_A0:
1850         case BGE_ASICREV_BCM5780:
1851         case BGE_ASICREV_BCM5714:
1852                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1853                 /* Fall through */
1854
1855         case BGE_ASICREV_BCM5750:
1856         case BGE_ASICREV_BCM5752:
1857         case BGE_ASICREV_BCM5906:
1858                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1859                 /* Fall through */
1860
1861         case BGE_ASICREV_BCM5705:
1862                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1863                 break;
1864         }
1865
1866         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1867                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1868
1869         /*
1870          * Set various quirk flags.
1871          */
1872
1873         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1874         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1875             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1876              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1877               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1878             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1879                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1880
1881         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1882             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1883                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1884
1885         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1886             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1887                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1888
1889         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1890                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1891
1892         if (BGE_IS_5705_PLUS(sc)) {
1893                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1894                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1895                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1896                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1897                         uint32_t product = pci_get_device(dev);
1898
1899                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1900                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1901                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1902                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1903                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1904                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1905                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1906                 }
1907         }
1908
1909         /* Allocate interrupt */
1910         rid = 0;
1911
1912         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1913             RF_SHAREABLE | RF_ACTIVE);
1914
1915         if (sc->bge_irq == NULL) {
1916                 device_printf(dev, "couldn't map interrupt\n");
1917                 error = ENXIO;
1918                 goto fail;
1919         }
1920
1921         /*
1922          * Check if this is a PCI-X or PCI Express device.
1923          */
1924         if (BGE_IS_5705_PLUS(sc)) {
1925                 if (pci_is_pcie(dev)) {
1926                         sc->bge_flags |= BGE_FLAG_PCIE;
1927                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1928                 }
1929         } else {
1930                 /*
1931                  * Check if the device is in PCI-X Mode.
1932                  * (This bit is not valid on PCI Express controllers.)
1933                  */
1934                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1935                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1936                         sc->bge_flags |= BGE_FLAG_PCIX;
1937         }
1938
1939         device_printf(dev, "CHIP ID 0x%08x; "
1940                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1941                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1942                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1943                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1944                         "PCI-E" : "PCI"));
1945
1946         /*
1947          * All controllers that are not 5755 or higher have 4GB
1948          * boundary DMA bug.
1949          * Whenever an address crosses a multiple of the 4GB boundary
1950          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
1951          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
1952          * state machine will lockup and cause the device to hang.
1953          */
1954         if (BGE_IS_5755_PLUS(sc) == 0)
1955                 sc->bge_flags |= BGE_FLAG_BOUNDARY_4G;
1956
1957         /*
1958          * The 40bit DMA bug applies to the 5714/5715 controllers and is
1959          * not actually a MAC controller bug but an issue with the embedded
1960          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
1961          */
1962         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
1963                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
1964
1965         ifp = &sc->arpcom.ac_if;
1966         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1967
1968         /* Try to reset the chip. */
1969         bge_reset(sc);
1970
1971         if (bge_chipinit(sc)) {
1972                 device_printf(dev, "chip initialization failed\n");
1973                 error = ENXIO;
1974                 goto fail;
1975         }
1976
1977         /*
1978          * Get station address
1979          */
1980         error = bge_get_eaddr(sc, ether_addr);
1981         if (error) {
1982                 device_printf(dev, "failed to read station address\n");
1983                 goto fail;
1984         }
1985
1986         /* 5705/5750 limits RX return ring to 512 entries. */
1987         if (BGE_IS_5705_PLUS(sc))
1988                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1989         else
1990                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1991
1992         error = bge_dma_alloc(sc);
1993         if (error)
1994                 goto fail;
1995
1996         /* Set default tuneable values. */
1997         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1998         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1999         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2000         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2001         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2002
2003         /* Set up ifnet structure */
2004         ifp->if_softc = sc;
2005         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2006         ifp->if_ioctl = bge_ioctl;
2007         ifp->if_start = bge_start;
2008 #ifdef DEVICE_POLLING
2009         ifp->if_poll = bge_poll;
2010 #endif
2011         ifp->if_watchdog = bge_watchdog;
2012         ifp->if_init = bge_init;
2013         ifp->if_mtu = ETHERMTU;
2014         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2015         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2016         ifq_set_ready(&ifp->if_snd);
2017
2018         /*
2019          * 5700 B0 chips do not support checksumming correctly due
2020          * to hardware bugs.
2021          */
2022         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2023                 ifp->if_capabilities |= IFCAP_HWCSUM;
2024                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2025         }
2026         ifp->if_capenable = ifp->if_capabilities;
2027
2028         /*
2029          * Figure out what sort of media we have by checking the
2030          * hardware config word in the first 32k of NIC internal memory,
2031          * or fall back to examining the EEPROM if necessary.
2032          * Note: on some BCM5700 cards, this value appears to be unset.
2033          * If that's the case, we have to rely on identifying the NIC
2034          * by its PCI subsystem ID, as we do below for the SysKonnect
2035          * SK-9D41.
2036          */
2037         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2038                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2039         else {
2040                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2041                                     sizeof(hwcfg))) {
2042                         device_printf(dev, "failed to read EEPROM\n");
2043                         error = ENXIO;
2044                         goto fail;
2045                 }
2046                 hwcfg = ntohl(hwcfg);
2047         }
2048
2049         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2050                 sc->bge_flags |= BGE_FLAG_TBI;
2051
2052         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2053         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
2054                 sc->bge_flags |= BGE_FLAG_TBI;
2055
2056         if (sc->bge_flags & BGE_FLAG_TBI) {
2057                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2058                     bge_ifmedia_upd, bge_ifmedia_sts);
2059                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2060                 ifmedia_add(&sc->bge_ifmedia,
2061                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2062                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2063                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2064                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2065         } else {
2066                 /*
2067                  * Do transceiver setup.
2068                  */
2069                 if (mii_phy_probe(dev, &sc->bge_miibus,
2070                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2071                         device_printf(dev, "MII without any PHY!\n");
2072                         error = ENXIO;
2073                         goto fail;
2074                 }
2075         }
2076
2077         /*
2078          * When using the BCM5701 in PCI-X mode, data corruption has
2079          * been observed in the first few bytes of some received packets.
2080          * Aligning the packet buffer in memory eliminates the corruption.
2081          * Unfortunately, this misaligns the packet payloads.  On platforms
2082          * which do not support unaligned accesses, we will realign the
2083          * payloads by copying the received packets.
2084          */
2085         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2086             (sc->bge_flags & BGE_FLAG_PCIX))
2087                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2088
2089         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2090             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2091                 sc->bge_link_upd = bge_bcm5700_link_upd;
2092                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2093         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2094                 sc->bge_link_upd = bge_tbi_link_upd;
2095                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2096         } else {
2097                 sc->bge_link_upd = bge_copper_link_upd;
2098                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2099         }
2100
2101         /*
2102          * Create sysctl nodes.
2103          */
2104         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2105         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2106                                               SYSCTL_STATIC_CHILDREN(_hw),
2107                                               OID_AUTO,
2108                                               device_get_nameunit(dev),
2109                                               CTLFLAG_RD, 0, "");
2110         if (sc->bge_sysctl_tree == NULL) {
2111                 device_printf(dev, "can't add sysctl node\n");
2112                 error = ENXIO;
2113                 goto fail;
2114         }
2115
2116         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2117                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2118                         OID_AUTO, "rx_coal_ticks",
2119                         CTLTYPE_INT | CTLFLAG_RW,
2120                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2121                         "Receive coalescing ticks (usec).");
2122         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2123                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2124                         OID_AUTO, "tx_coal_ticks",
2125                         CTLTYPE_INT | CTLFLAG_RW,
2126                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2127                         "Transmit coalescing ticks (usec).");
2128         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2129                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2130                         OID_AUTO, "rx_max_coal_bds",
2131                         CTLTYPE_INT | CTLFLAG_RW,
2132                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2133                         "Receive max coalesced BD count.");
2134         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2135                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2136                         OID_AUTO, "tx_max_coal_bds",
2137                         CTLTYPE_INT | CTLFLAG_RW,
2138                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2139                         "Transmit max coalesced BD count.");
2140
2141         /*
2142          * Call MI attach routine.
2143          */
2144         ether_ifattach(ifp, ether_addr, NULL);
2145
2146         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2147                                bge_intr, sc, &sc->bge_intrhand,
2148                                ifp->if_serializer);
2149         if (error) {
2150                 ether_ifdetach(ifp);
2151                 device_printf(dev, "couldn't set up irq\n");
2152                 goto fail;
2153         }
2154
2155         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2156         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2157
2158         return(0);
2159 fail:
2160         bge_detach(dev);
2161         return(error);
2162 }
2163
2164 static int
2165 bge_detach(device_t dev)
2166 {
2167         struct bge_softc *sc = device_get_softc(dev);
2168
2169         if (device_is_attached(dev)) {
2170                 struct ifnet *ifp = &sc->arpcom.ac_if;
2171
2172                 lwkt_serialize_enter(ifp->if_serializer);
2173                 bge_stop(sc);
2174                 bge_reset(sc);
2175                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2176                 lwkt_serialize_exit(ifp->if_serializer);
2177
2178                 ether_ifdetach(ifp);
2179         }
2180
2181         if (sc->bge_flags & BGE_FLAG_TBI)
2182                 ifmedia_removeall(&sc->bge_ifmedia);
2183         if (sc->bge_miibus)
2184                 device_delete_child(dev, sc->bge_miibus);
2185         bus_generic_detach(dev);
2186
2187         if (sc->bge_irq != NULL)
2188                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2189
2190         if (sc->bge_res != NULL)
2191                 bus_release_resource(dev, SYS_RES_MEMORY,
2192                     BGE_PCI_BAR0, sc->bge_res);
2193
2194         if (sc->bge_sysctl_tree != NULL)
2195                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2196
2197         bge_dma_free(sc);
2198
2199         return 0;
2200 }
2201
2202 static void
2203 bge_reset(struct bge_softc *sc)
2204 {
2205         device_t dev;
2206         uint32_t cachesize, command, pcistate, reset;
2207         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2208         int i, val = 0;
2209
2210         dev = sc->bge_dev;
2211
2212         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2213             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2214                 if (sc->bge_flags & BGE_FLAG_PCIE)
2215                         write_op = bge_writemem_direct;
2216                 else
2217                         write_op = bge_writemem_ind;
2218         } else {
2219                 write_op = bge_writereg_ind;
2220         }
2221
2222         /* Save some important PCI state. */
2223         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2224         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2225         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2226
2227         pci_write_config(dev, BGE_PCI_MISC_CTL,
2228             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2229             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2230
2231         /* Disable fastboot on controllers that support it. */
2232         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2233             BGE_IS_5755_PLUS(sc)) {
2234                 if (bootverbose)
2235                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2236                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2237         }
2238
2239         /*
2240          * Write the magic number to SRAM at offset 0xB50.
2241          * When firmware finishes its initialization it will
2242          * write ~BGE_MAGIC_NUMBER to the same location.
2243          */
2244         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2245
2246         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2247
2248         /* XXX: Broadcom Linux driver. */
2249         if (sc->bge_flags & BGE_FLAG_PCIE) {
2250                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2251                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2252                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2253                         /* Prevent PCIE link training during global reset */
2254                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2255                         reset |= (1<<29);
2256                 }
2257         }
2258
2259         /*
2260          * Set GPHY Power Down Override to leave GPHY
2261          * powered up in D0 uninitialized.
2262          */
2263         if (BGE_IS_5705_PLUS(sc))
2264                 reset |= 0x04000000;
2265
2266         /* Issue global reset */
2267         write_op(sc, BGE_MISC_CFG, reset);
2268
2269         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2270                 uint32_t status, ctrl;
2271
2272                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2273                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2274                     status | BGE_VCPU_STATUS_DRV_RESET);
2275                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2276                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2277                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2278         }
2279
2280         DELAY(1000);
2281
2282         /* XXX: Broadcom Linux driver. */
2283         if (sc->bge_flags & BGE_FLAG_PCIE) {
2284                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2285                         uint32_t v;
2286
2287                         DELAY(500000); /* wait for link training to complete */
2288                         v = pci_read_config(dev, 0xc4, 4);
2289                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2290                 }
2291                 /*
2292                  * Set PCIE max payload size to 128 bytes and
2293                  * clear error status.
2294                  */
2295                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2296         }
2297
2298         /* Reset some of the PCI state that got zapped by reset */
2299         pci_write_config(dev, BGE_PCI_MISC_CTL,
2300             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2301             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2302         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2303         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2304         write_op(sc, BGE_MISC_CFG, (65 << 1));
2305
2306         /* Enable memory arbiter. */
2307         if (BGE_IS_5714_FAMILY(sc)) {
2308                 uint32_t val;
2309
2310                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2311                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2312         } else {
2313                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2314         }
2315
2316         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2317                 for (i = 0; i < BGE_TIMEOUT; i++) {
2318                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2319                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2320                                 break;
2321                         DELAY(100);
2322                 }
2323                 if (i == BGE_TIMEOUT) {
2324                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2325                         return;
2326                 }
2327         } else {
2328                 /*
2329                  * Poll until we see the 1's complement of the magic number.
2330                  * This indicates that the firmware initialization
2331                  * is complete.
2332                  */
2333                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2334                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2335                         if (val == ~BGE_MAGIC_NUMBER)
2336                                 break;
2337                         DELAY(10);
2338                 }
2339                 if (i == BGE_FIRMWARE_TIMEOUT) {
2340                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2341                                   "timed out, found 0x%08x\n", val);
2342                         return;
2343                 }
2344         }
2345
2346         /*
2347          * XXX Wait for the value of the PCISTATE register to
2348          * return to its original pre-reset state. This is a
2349          * fairly good indicator of reset completion. If we don't
2350          * wait for the reset to fully complete, trying to read
2351          * from the device's non-PCI registers may yield garbage
2352          * results.
2353          */
2354         for (i = 0; i < BGE_TIMEOUT; i++) {
2355                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2356                         break;
2357                 DELAY(10);
2358         }
2359
2360         if (sc->bge_flags & BGE_FLAG_PCIE) {
2361                 reset = bge_readmem_ind(sc, 0x7c00);
2362                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2363         }
2364
2365         /* Fix up byte swapping */
2366         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2367             BGE_MODECTL_BYTESWAP_DATA);
2368
2369         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2370
2371         /*
2372          * The 5704 in TBI mode apparently needs some special
2373          * adjustment to insure the SERDES drive level is set
2374          * to 1.2V.
2375          */
2376         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2377             (sc->bge_flags & BGE_FLAG_TBI)) {
2378                 uint32_t serdescfg;
2379
2380                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2381                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2382                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2383         }
2384
2385         /* XXX: Broadcom Linux driver. */
2386         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2387             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2388                 uint32_t v;
2389
2390                 v = CSR_READ_4(sc, 0x7c00);
2391                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2392         }
2393
2394         DELAY(10000);
2395 }
2396
2397 /*
2398  * Frame reception handling. This is called if there's a frame
2399  * on the receive return list.
2400  *
2401  * Note: we have to be able to handle two possibilities here:
2402  * 1) the frame is from the jumbo recieve ring
2403  * 2) the frame is from the standard receive ring
2404  */
2405
2406 static void
2407 bge_rxeof(struct bge_softc *sc)
2408 {
2409         struct ifnet *ifp;
2410         int stdcnt = 0, jumbocnt = 0;
2411
2412         if (sc->bge_rx_saved_considx ==
2413             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2414                 return;
2415
2416         ifp = &sc->arpcom.ac_if;
2417
2418         while (sc->bge_rx_saved_considx !=
2419                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2420                 struct bge_rx_bd        *cur_rx;
2421                 uint32_t                rxidx;
2422                 struct mbuf             *m = NULL;
2423                 uint16_t                vlan_tag = 0;
2424                 int                     have_tag = 0;
2425
2426                 cur_rx =
2427             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2428
2429                 rxidx = cur_rx->bge_idx;
2430                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2431                 logif(rx_pkt);
2432
2433                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2434                         have_tag = 1;
2435                         vlan_tag = cur_rx->bge_vlan_tag;
2436                 }
2437
2438                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2439                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2440                         jumbocnt++;
2441
2442                         if (rxidx != sc->bge_jumbo) {
2443                                 ifp->if_ierrors++;
2444                                 if_printf(ifp, "sw jumbo index(%d) "
2445                                     "and hw jumbo index(%d) mismatch, drop!\n",
2446                                     sc->bge_jumbo, rxidx);
2447                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2448                                 continue;
2449                         }
2450
2451                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2452                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2453                                 ifp->if_ierrors++;
2454                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2455                                 continue;
2456                         }
2457                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2458                                 ifp->if_ierrors++;
2459                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2460                                 continue;
2461                         }
2462                 } else {
2463                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2464                         stdcnt++;
2465
2466                         if (rxidx != sc->bge_std) {
2467                                 ifp->if_ierrors++;
2468                                 if_printf(ifp, "sw std index(%d) "
2469                                     "and hw std index(%d) mismatch, drop!\n",
2470                                     sc->bge_std, rxidx);
2471                                 bge_setup_rxdesc_std(sc, rxidx);
2472                                 continue;
2473                         }
2474
2475                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2476                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2477                                 ifp->if_ierrors++;
2478                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2479                                 continue;
2480                         }
2481                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2482                                 ifp->if_ierrors++;
2483                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2484                                 continue;
2485                         }
2486                 }
2487
2488                 ifp->if_ipackets++;
2489 #ifndef __i386__
2490                 /*
2491                  * The i386 allows unaligned accesses, but for other
2492                  * platforms we must make sure the payload is aligned.
2493                  */
2494                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2495                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2496                             cur_rx->bge_len);
2497                         m->m_data += ETHER_ALIGN;
2498                 }
2499 #endif
2500                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2501                 m->m_pkthdr.rcvif = ifp;
2502
2503                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2504                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2505                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2506                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2507                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2508                         }
2509                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2510                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2511                                 m->m_pkthdr.csum_data =
2512                                         cur_rx->bge_tcp_udp_csum;
2513                                 m->m_pkthdr.csum_flags |=
2514                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2515                         }
2516                 }
2517
2518                 /*
2519                  * If we received a packet with a vlan tag, pass it
2520                  * to vlan_input() instead of ether_input().
2521                  */
2522                 if (have_tag) {
2523                         m->m_flags |= M_VLANTAG;
2524                         m->m_pkthdr.ether_vlantag = vlan_tag;
2525                         have_tag = vlan_tag = 0;
2526                 }
2527                 ifp->if_input(ifp, m);
2528         }
2529
2530         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2531         if (stdcnt)
2532                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2533         if (jumbocnt)
2534                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2535 }
2536
2537 static void
2538 bge_txeof(struct bge_softc *sc)
2539 {
2540         struct bge_tx_bd *cur_tx = NULL;
2541         struct ifnet *ifp;
2542
2543         if (sc->bge_tx_saved_considx ==
2544             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2545                 return;
2546
2547         ifp = &sc->arpcom.ac_if;
2548
2549         /*
2550          * Go through our tx ring and free mbufs for those
2551          * frames that have been sent.
2552          */
2553         while (sc->bge_tx_saved_considx !=
2554                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2555                 uint32_t idx = 0;
2556
2557                 idx = sc->bge_tx_saved_considx;
2558                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2559                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2560                         ifp->if_opackets++;
2561                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2562                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2563                             sc->bge_cdata.bge_tx_dmamap[idx]);
2564                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2565                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2566                 }
2567                 sc->bge_txcnt--;
2568                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2569                 logif(tx_pkt);
2570         }
2571
2572         if (cur_tx != NULL &&
2573             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2574             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2575                 ifp->if_flags &= ~IFF_OACTIVE;
2576
2577         if (sc->bge_txcnt == 0)
2578                 ifp->if_timer = 0;
2579
2580         if (!ifq_is_empty(&ifp->if_snd))
2581                 if_devstart(ifp);
2582 }
2583
2584 #ifdef DEVICE_POLLING
2585
2586 static void
2587 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2588 {
2589         struct bge_softc *sc = ifp->if_softc;
2590         uint32_t status;
2591
2592         switch(cmd) {
2593         case POLL_REGISTER:
2594                 bge_disable_intr(sc);
2595                 break;
2596         case POLL_DEREGISTER:
2597                 bge_enable_intr(sc);
2598                 break;
2599         case POLL_AND_CHECK_STATUS:
2600                 /*
2601                  * Process link state changes.
2602                  */
2603                 status = CSR_READ_4(sc, BGE_MAC_STS);
2604                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2605                         sc->bge_link_evt = 0;
2606                         sc->bge_link_upd(sc, status);
2607                 }
2608                 /* fall through */
2609         case POLL_ONLY:
2610                 if (ifp->if_flags & IFF_RUNNING) {
2611                         bge_rxeof(sc);
2612                         bge_txeof(sc);
2613                 }
2614                 break;
2615         }
2616 }
2617
2618 #endif
2619
2620 static void
2621 bge_intr(void *xsc)
2622 {
2623         struct bge_softc *sc = xsc;
2624         struct ifnet *ifp = &sc->arpcom.ac_if;
2625         uint32_t status;
2626
2627         logif(intr);
2628
2629         /*
2630          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2631          * disable interrupts by writing nonzero like we used to, since with
2632          * our current organization this just gives complications and
2633          * pessimizations for re-enabling interrupts.  We used to have races
2634          * instead of the necessary complications.  Disabling interrupts
2635          * would just reduce the chance of a status update while we are
2636          * running (by switching to the interrupt-mode coalescence
2637          * parameters), but this chance is already very low so it is more
2638          * efficient to get another interrupt than prevent it.
2639          *
2640          * We do the ack first to ensure another interrupt if there is a
2641          * status update after the ack.  We don't check for the status
2642          * changing later because it is more efficient to get another
2643          * interrupt than prevent it, not quite as above (not checking is
2644          * a smaller optimization than not toggling the interrupt enable,
2645          * since checking doesn't involve PCI accesses and toggling require
2646          * the status check).  So toggling would probably be a pessimization
2647          * even with MSI.  It would only be needed for using a task queue.
2648          */
2649         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2650
2651         /*
2652          * Process link state changes.
2653          */
2654         status = CSR_READ_4(sc, BGE_MAC_STS);
2655         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2656                 sc->bge_link_evt = 0;
2657                 sc->bge_link_upd(sc, status);
2658         }
2659
2660         if (ifp->if_flags & IFF_RUNNING) {
2661                 /* Check RX return ring producer/consumer */
2662                 bge_rxeof(sc);
2663
2664                 /* Check TX ring producer/consumer */
2665                 bge_txeof(sc);
2666         }
2667
2668         if (sc->bge_coal_chg)
2669                 bge_coal_change(sc);
2670 }
2671
2672 static void
2673 bge_tick(void *xsc)
2674 {
2675         struct bge_softc *sc = xsc;
2676         struct ifnet *ifp = &sc->arpcom.ac_if;
2677
2678         lwkt_serialize_enter(ifp->if_serializer);
2679
2680         if (BGE_IS_5705_PLUS(sc))
2681                 bge_stats_update_regs(sc);
2682         else
2683                 bge_stats_update(sc);
2684
2685         if (sc->bge_flags & BGE_FLAG_TBI) {
2686                 /*
2687                  * Since in TBI mode auto-polling can't be used we should poll
2688                  * link status manually. Here we register pending link event
2689                  * and trigger interrupt.
2690                  */
2691                 sc->bge_link_evt++;
2692                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2693         } else if (!sc->bge_link) {
2694                 mii_tick(device_get_softc(sc->bge_miibus));
2695         }
2696
2697         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2698
2699         lwkt_serialize_exit(ifp->if_serializer);
2700 }
2701
2702 static void
2703 bge_stats_update_regs(struct bge_softc *sc)
2704 {
2705         struct ifnet *ifp = &sc->arpcom.ac_if;
2706         struct bge_mac_stats_regs stats;
2707         uint32_t *s;
2708         int i;
2709
2710         s = (uint32_t *)&stats;
2711         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2712                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2713                 s++;
2714         }
2715
2716         ifp->if_collisions +=
2717            (stats.dot3StatsSingleCollisionFrames +
2718            stats.dot3StatsMultipleCollisionFrames +
2719            stats.dot3StatsExcessiveCollisions +
2720            stats.dot3StatsLateCollisions) -
2721            ifp->if_collisions;
2722 }
2723
2724 static void
2725 bge_stats_update(struct bge_softc *sc)
2726 {
2727         struct ifnet *ifp = &sc->arpcom.ac_if;
2728         bus_size_t stats;
2729
2730         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2731
2732 #define READ_STAT(sc, stats, stat)      \
2733         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2734
2735         ifp->if_collisions +=
2736            (READ_STAT(sc, stats,
2737                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2738             READ_STAT(sc, stats,
2739                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2740             READ_STAT(sc, stats,
2741                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2742             READ_STAT(sc, stats,
2743                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2744            ifp->if_collisions;
2745
2746 #undef READ_STAT
2747
2748 #ifdef notdef
2749         ifp->if_collisions +=
2750            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2751            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2752            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2753            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2754            ifp->if_collisions;
2755 #endif
2756 }
2757
2758 /*
2759  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2760  * pointers to descriptors.
2761  */
2762 static int
2763 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2764 {
2765         struct bge_tx_bd *d = NULL;
2766         uint16_t csum_flags = 0;
2767         bus_dma_segment_t segs[BGE_NSEG_NEW];
2768         bus_dmamap_t map;
2769         int error, maxsegs, nsegs, idx, i;
2770         struct mbuf *m_head = *m_head0;
2771
2772         if (m_head->m_pkthdr.csum_flags) {
2773                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2774                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2775                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2776                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2777                 if (m_head->m_flags & M_LASTFRAG)
2778                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2779                 else if (m_head->m_flags & M_FRAG)
2780                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2781         }
2782
2783         idx = *txidx;
2784         map = sc->bge_cdata.bge_tx_dmamap[idx];
2785
2786         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2787         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2788                 ("not enough segments %d", maxsegs));
2789
2790         if (maxsegs > BGE_NSEG_NEW)
2791                 maxsegs = BGE_NSEG_NEW;
2792
2793         /*
2794          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2795          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2796          * but when such padded frames employ the bge IP/TCP checksum
2797          * offload, the hardware checksum assist gives incorrect results
2798          * (possibly from incorporating its own padding into the UDP/TCP
2799          * checksum; who knows).  If we pad such runts with zeros, the
2800          * onboard checksum comes out correct.
2801          */
2802         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2803             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2804                 error = m_devpad(m_head, BGE_MIN_FRAME);
2805                 if (error)
2806                         goto back;
2807         }
2808
2809         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
2810                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2811         if (error)
2812                 goto back;
2813
2814         m_head = *m_head0;
2815         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2816
2817         for (i = 0; ; i++) {
2818                 d = &sc->bge_ldata.bge_tx_ring[idx];
2819
2820                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2821                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2822                 d->bge_len = segs[i].ds_len;
2823                 d->bge_flags = csum_flags;
2824
2825                 if (i == nsegs - 1)
2826                         break;
2827                 BGE_INC(idx, BGE_TX_RING_CNT);
2828         }
2829         /* Mark the last segment as end of packet... */
2830         d->bge_flags |= BGE_TXBDFLAG_END;
2831
2832         /* Set vlan tag to the first segment of the packet. */
2833         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2834         if (m_head->m_flags & M_VLANTAG) {
2835                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2836                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2837         } else {
2838                 d->bge_vlan_tag = 0;
2839         }
2840
2841         /*
2842          * Insure that the map for this transmission is placed at
2843          * the array index of the last descriptor in this chain.
2844          */
2845         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2846         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2847         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2848         sc->bge_txcnt += nsegs;
2849
2850         BGE_INC(idx, BGE_TX_RING_CNT);
2851         *txidx = idx;
2852 back:
2853         if (error) {
2854                 m_freem(*m_head0);
2855                 *m_head0 = NULL;
2856         }
2857         return error;
2858 }
2859
2860 /*
2861  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2862  * to the mbuf data regions directly in the transmit descriptors.
2863  */
2864 static void
2865 bge_start(struct ifnet *ifp)
2866 {
2867         struct bge_softc *sc = ifp->if_softc;
2868         struct mbuf *m_head = NULL;
2869         uint32_t prodidx;
2870         int need_trans;
2871
2872         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2873                 return;
2874
2875         prodidx = sc->bge_tx_prodidx;
2876
2877         need_trans = 0;
2878         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2879                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2880                 if (m_head == NULL)
2881                         break;
2882
2883                 /*
2884                  * XXX
2885                  * The code inside the if() block is never reached since we
2886                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2887                  * requests to checksum TCP/UDP in a fragmented packet.
2888                  *
2889                  * XXX
2890                  * safety overkill.  If this is a fragmented packet chain
2891                  * with delayed TCP/UDP checksums, then only encapsulate
2892                  * it if we have enough descriptors to handle the entire
2893                  * chain at once.
2894                  * (paranoia -- may not actually be needed)
2895                  */
2896                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2897                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2898                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2899                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2900                                 ifp->if_flags |= IFF_OACTIVE;
2901                                 ifq_prepend(&ifp->if_snd, m_head);
2902                                 break;
2903                         }
2904                 }
2905
2906                 /*
2907                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2908                  * descriptors of the end of the ring.  Also make
2909                  * sure there are BGE_NSEG_SPARE descriptors for
2910                  * jumbo buffers' defragmentation.
2911                  */
2912                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2913                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2914                         ifp->if_flags |= IFF_OACTIVE;
2915                         ifq_prepend(&ifp->if_snd, m_head);
2916                         break;
2917                 }
2918
2919                 /*
2920                  * Pack the data into the transmit ring. If we
2921                  * don't have room, set the OACTIVE flag and wait
2922                  * for the NIC to drain the ring.
2923                  */
2924                 if (bge_encap(sc, &m_head, &prodidx)) {
2925                         ifp->if_flags |= IFF_OACTIVE;
2926                         ifp->if_oerrors++;
2927                         break;
2928                 }
2929                 need_trans = 1;
2930
2931                 ETHER_BPF_MTAP(ifp, m_head);
2932         }
2933
2934         if (!need_trans)
2935                 return;
2936
2937         /* Transmit */
2938         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2939         /* 5700 b2 errata */
2940         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2941                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2942
2943         sc->bge_tx_prodidx = prodidx;
2944
2945         /*
2946          * Set a timeout in case the chip goes out to lunch.
2947          */
2948         ifp->if_timer = 5;
2949 }
2950
2951 static void
2952 bge_init(void *xsc)
2953 {
2954         struct bge_softc *sc = xsc;
2955         struct ifnet *ifp = &sc->arpcom.ac_if;
2956         uint16_t *m;
2957
2958         ASSERT_SERIALIZED(ifp->if_serializer);
2959
2960         if (ifp->if_flags & IFF_RUNNING)
2961                 return;
2962
2963         /* Cancel pending I/O and flush buffers. */
2964         bge_stop(sc);
2965         bge_reset(sc);
2966         bge_chipinit(sc);
2967
2968         /*
2969          * Init the various state machines, ring
2970          * control blocks and firmware.
2971          */
2972         if (bge_blockinit(sc)) {
2973                 if_printf(ifp, "initialization failure\n");
2974                 bge_stop(sc);
2975                 return;
2976         }
2977
2978         /* Specify MTU. */
2979         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2980             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2981
2982         /* Load our MAC address. */
2983         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2984         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2985         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2986
2987         /* Enable or disable promiscuous mode as needed. */
2988         bge_setpromisc(sc);
2989
2990         /* Program multicast filter. */
2991         bge_setmulti(sc);
2992
2993         /* Init RX ring. */
2994         if (bge_init_rx_ring_std(sc)) {
2995                 if_printf(ifp, "RX ring initialization failed\n");
2996                 bge_stop(sc);
2997                 return;
2998         }
2999
3000         /*
3001          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3002          * memory to insure that the chip has in fact read the first
3003          * entry of the ring.
3004          */
3005         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3006                 uint32_t                v, i;
3007                 for (i = 0; i < 10; i++) {
3008                         DELAY(20);
3009                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3010                         if (v == (MCLBYTES - ETHER_ALIGN))
3011                                 break;
3012                 }
3013                 if (i == 10)
3014                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3015         }
3016
3017         /* Init jumbo RX ring. */
3018         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3019                 if (bge_init_rx_ring_jumbo(sc)) {
3020                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3021                         bge_stop(sc);
3022                         return;
3023                 }
3024         }
3025
3026         /* Init our RX return ring index */
3027         sc->bge_rx_saved_considx = 0;
3028
3029         /* Init TX ring. */
3030         bge_init_tx_ring(sc);
3031
3032         /* Turn on transmitter */
3033         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3034
3035         /* Turn on receiver */
3036         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3037
3038         /* Tell firmware we're alive. */
3039         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3040
3041         /* Enable host interrupts if polling(4) is not enabled. */
3042         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3043 #ifdef DEVICE_POLLING
3044         if (ifp->if_flags & IFF_POLLING)
3045                 bge_disable_intr(sc);
3046         else
3047 #endif
3048         bge_enable_intr(sc);
3049
3050         bge_ifmedia_upd(ifp);
3051
3052         ifp->if_flags |= IFF_RUNNING;
3053         ifp->if_flags &= ~IFF_OACTIVE;
3054
3055         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3056 }
3057
3058 /*
3059  * Set media options.
3060  */
3061 static int
3062 bge_ifmedia_upd(struct ifnet *ifp)
3063 {
3064         struct bge_softc *sc = ifp->if_softc;
3065
3066         /* If this is a 1000baseX NIC, enable the TBI port. */
3067         if (sc->bge_flags & BGE_FLAG_TBI) {
3068                 struct ifmedia *ifm = &sc->bge_ifmedia;
3069
3070                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3071                         return(EINVAL);
3072
3073                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3074                 case IFM_AUTO:
3075                         /*
3076                          * The BCM5704 ASIC appears to have a special
3077                          * mechanism for programming the autoneg
3078                          * advertisement registers in TBI mode.
3079                          */
3080                         if (!bge_fake_autoneg &&
3081                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3082                                 uint32_t sgdig;
3083
3084                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3085                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3086                                 sgdig |= BGE_SGDIGCFG_AUTO |
3087                                          BGE_SGDIGCFG_PAUSE_CAP |
3088                                          BGE_SGDIGCFG_ASYM_PAUSE;
3089                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3090                                             sgdig | BGE_SGDIGCFG_SEND);
3091                                 DELAY(5);
3092                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3093                         }
3094                         break;
3095                 case IFM_1000_SX:
3096                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3097                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3098                                     BGE_MACMODE_HALF_DUPLEX);
3099                         } else {
3100                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3101                                     BGE_MACMODE_HALF_DUPLEX);
3102                         }
3103                         break;
3104                 default:
3105                         return(EINVAL);
3106                 }
3107         } else {
3108                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3109
3110                 sc->bge_link_evt++;
3111                 sc->bge_link = 0;
3112                 if (mii->mii_instance) {
3113                         struct mii_softc *miisc;
3114
3115                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3116                                 mii_phy_reset(miisc);
3117                 }
3118                 mii_mediachg(mii);
3119         }
3120         return(0);
3121 }
3122
3123 /*
3124  * Report current media status.
3125  */
3126 static void
3127 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3128 {
3129         struct bge_softc *sc = ifp->if_softc;
3130
3131         if (sc->bge_flags & BGE_FLAG_TBI) {
3132                 ifmr->ifm_status = IFM_AVALID;
3133                 ifmr->ifm_active = IFM_ETHER;
3134                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3135                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3136                         ifmr->ifm_status |= IFM_ACTIVE;
3137                 } else {
3138                         ifmr->ifm_active |= IFM_NONE;
3139                         return;
3140                 }
3141
3142                 ifmr->ifm_active |= IFM_1000_SX;
3143                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3144                         ifmr->ifm_active |= IFM_HDX;
3145                 else
3146                         ifmr->ifm_active |= IFM_FDX;
3147         } else {
3148                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3149
3150                 mii_pollstat(mii);
3151                 ifmr->ifm_active = mii->mii_media_active;
3152                 ifmr->ifm_status = mii->mii_media_status;
3153         }
3154 }
3155
3156 static int
3157 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3158 {
3159         struct bge_softc *sc = ifp->if_softc;
3160         struct ifreq *ifr = (struct ifreq *)data;
3161         int mask, error = 0;
3162
3163         ASSERT_SERIALIZED(ifp->if_serializer);
3164
3165         switch (command) {
3166         case SIOCSIFMTU:
3167                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3168                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3169                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3170                         error = EINVAL;
3171                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3172                         ifp->if_mtu = ifr->ifr_mtu;
3173                         ifp->if_flags &= ~IFF_RUNNING;
3174                         bge_init(sc);
3175                 }
3176                 break;
3177         case SIOCSIFFLAGS:
3178                 if (ifp->if_flags & IFF_UP) {
3179                         if (ifp->if_flags & IFF_RUNNING) {
3180                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3181
3182                                 /*
3183                                  * If only the state of the PROMISC flag
3184                                  * changed, then just use the 'set promisc
3185                                  * mode' command instead of reinitializing
3186                                  * the entire NIC. Doing a full re-init
3187                                  * means reloading the firmware and waiting
3188                                  * for it to start up, which may take a
3189                                  * second or two.  Similarly for ALLMULTI.
3190                                  */
3191                                 if (mask & IFF_PROMISC)
3192                                         bge_setpromisc(sc);
3193                                 if (mask & IFF_ALLMULTI)
3194                                         bge_setmulti(sc);
3195                         } else {
3196                                 bge_init(sc);
3197                         }
3198                 } else {
3199                         if (ifp->if_flags & IFF_RUNNING)
3200                                 bge_stop(sc);
3201                 }
3202                 sc->bge_if_flags = ifp->if_flags;
3203                 break;
3204         case SIOCADDMULTI:
3205         case SIOCDELMULTI:
3206                 if (ifp->if_flags & IFF_RUNNING)
3207                         bge_setmulti(sc);
3208                 break;
3209         case SIOCSIFMEDIA:
3210         case SIOCGIFMEDIA:
3211                 if (sc->bge_flags & BGE_FLAG_TBI) {
3212                         error = ifmedia_ioctl(ifp, ifr,
3213                             &sc->bge_ifmedia, command);
3214                 } else {
3215                         struct mii_data *mii;
3216
3217                         mii = device_get_softc(sc->bge_miibus);
3218                         error = ifmedia_ioctl(ifp, ifr,
3219                                               &mii->mii_media, command);
3220                 }
3221                 break;
3222         case SIOCSIFCAP:
3223                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3224                 if (mask & IFCAP_HWCSUM) {
3225                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3226                         if (IFCAP_HWCSUM & ifp->if_capenable)
3227                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3228                         else
3229                                 ifp->if_hwassist = 0;
3230                 }
3231                 break;
3232         default:
3233                 error = ether_ioctl(ifp, command, data);
3234                 break;
3235         }
3236         return error;
3237 }
3238
3239 static void
3240 bge_watchdog(struct ifnet *ifp)
3241 {
3242         struct bge_softc *sc = ifp->if_softc;
3243
3244         if_printf(ifp, "watchdog timeout -- resetting\n");
3245
3246         ifp->if_flags &= ~IFF_RUNNING;
3247         bge_init(sc);
3248
3249         ifp->if_oerrors++;
3250
3251         if (!ifq_is_empty(&ifp->if_snd))
3252                 if_devstart(ifp);
3253 }
3254
3255 /*
3256  * Stop the adapter and free any mbufs allocated to the
3257  * RX and TX lists.
3258  */
3259 static void
3260 bge_stop(struct bge_softc *sc)
3261 {
3262         struct ifnet *ifp = &sc->arpcom.ac_if;
3263
3264         ASSERT_SERIALIZED(ifp->if_serializer);
3265
3266         callout_stop(&sc->bge_stat_timer);
3267
3268         /*
3269          * Disable all of the receiver blocks
3270          */
3271         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3272         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3273         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3274         if (!BGE_IS_5705_PLUS(sc))
3275                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3276         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3277         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3278         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3279
3280         /*
3281          * Disable all of the transmit blocks
3282          */
3283         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3284         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3285         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3286         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3287         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3288         if (!BGE_IS_5705_PLUS(sc))
3289                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3290         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3291
3292         /*
3293          * Shut down all of the memory managers and related
3294          * state machines.
3295          */
3296         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3297         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3298         if (!BGE_IS_5705_PLUS(sc))
3299                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3300         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3301         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3302         if (!BGE_IS_5705_PLUS(sc)) {
3303                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3304                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3305         }
3306
3307         /* Disable host interrupts. */
3308         bge_disable_intr(sc);
3309
3310         /*
3311          * Tell firmware we're shutting down.
3312          */
3313         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3314
3315         /* Free the RX lists. */
3316         bge_free_rx_ring_std(sc);
3317
3318         /* Free jumbo RX list. */
3319         if (BGE_IS_JUMBO_CAPABLE(sc))
3320                 bge_free_rx_ring_jumbo(sc);
3321
3322         /* Free TX buffers. */
3323         bge_free_tx_ring(sc);
3324
3325         sc->bge_link = 0;
3326         sc->bge_coal_chg = 0;
3327
3328         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3329
3330         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3331         ifp->if_timer = 0;
3332 }
3333
3334 /*
3335  * Stop all chip I/O so that the kernel's probe routines don't
3336  * get confused by errant DMAs when rebooting.
3337  */
3338 static void
3339 bge_shutdown(device_t dev)
3340 {
3341         struct bge_softc *sc = device_get_softc(dev);
3342         struct ifnet *ifp = &sc->arpcom.ac_if;
3343
3344         lwkt_serialize_enter(ifp->if_serializer);
3345         bge_stop(sc);
3346         bge_reset(sc);
3347         lwkt_serialize_exit(ifp->if_serializer);
3348 }
3349
3350 static int
3351 bge_suspend(device_t dev)
3352 {
3353         struct bge_softc *sc = device_get_softc(dev);
3354         struct ifnet *ifp = &sc->arpcom.ac_if;
3355
3356         lwkt_serialize_enter(ifp->if_serializer);
3357         bge_stop(sc);
3358         lwkt_serialize_exit(ifp->if_serializer);
3359
3360         return 0;
3361 }
3362
3363 static int
3364 bge_resume(device_t dev)
3365 {
3366         struct bge_softc *sc = device_get_softc(dev);
3367         struct ifnet *ifp = &sc->arpcom.ac_if;
3368
3369         lwkt_serialize_enter(ifp->if_serializer);
3370
3371         if (ifp->if_flags & IFF_UP) {
3372                 bge_init(sc);
3373
3374                 if (!ifq_is_empty(&ifp->if_snd))
3375                         if_devstart(ifp);
3376         }
3377
3378         lwkt_serialize_exit(ifp->if_serializer);
3379
3380         return 0;
3381 }
3382
3383 static void
3384 bge_setpromisc(struct bge_softc *sc)
3385 {
3386         struct ifnet *ifp = &sc->arpcom.ac_if;
3387
3388         if (ifp->if_flags & IFF_PROMISC)
3389                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3390         else
3391                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3392 }
3393
3394 static void
3395 bge_dma_free(struct bge_softc *sc)
3396 {
3397         int i;
3398
3399         /* Destroy RX mbuf DMA stuffs. */
3400         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3401                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3402                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3403                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3404                 }
3405                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3406                                    sc->bge_cdata.bge_rx_tmpmap);
3407                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3408         }
3409
3410         /* Destroy TX mbuf DMA stuffs. */
3411         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3412                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3413                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3414                             sc->bge_cdata.bge_tx_dmamap[i]);
3415                 }
3416                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3417         }
3418
3419         /* Destroy standard RX ring */
3420         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3421                            sc->bge_cdata.bge_rx_std_ring_map,
3422                            sc->bge_ldata.bge_rx_std_ring);
3423
3424         if (BGE_IS_JUMBO_CAPABLE(sc))
3425                 bge_free_jumbo_mem(sc);
3426
3427         /* Destroy RX return ring */
3428         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3429                            sc->bge_cdata.bge_rx_return_ring_map,
3430                            sc->bge_ldata.bge_rx_return_ring);
3431
3432         /* Destroy TX ring */
3433         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3434                            sc->bge_cdata.bge_tx_ring_map,
3435                            sc->bge_ldata.bge_tx_ring);
3436
3437         /* Destroy status block */
3438         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3439                            sc->bge_cdata.bge_status_map,
3440                            sc->bge_ldata.bge_status_block);
3441
3442         /* Destroy statistics block */
3443         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3444                            sc->bge_cdata.bge_stats_map,
3445                            sc->bge_ldata.bge_stats);
3446
3447         /* Destroy the parent tag */
3448         if (sc->bge_cdata.bge_parent_tag != NULL)
3449                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3450 }
3451
3452 static int
3453 bge_dma_alloc(struct bge_softc *sc)
3454 {
3455         struct ifnet *ifp = &sc->arpcom.ac_if;
3456         int i, error;
3457         bus_addr_t lowaddr;
3458         bus_size_t boundary;
3459
3460         boundary = 0;
3461         if (sc->bge_flags & BGE_FLAG_BOUNDARY_4G)
3462                 boundary = BGE_DMA_BOUNDARY_4G;
3463
3464         lowaddr = BUS_SPACE_MAXADDR;
3465         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3466                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3467
3468         /*
3469          * Allocate the parent bus DMA tag appropriate for PCI.
3470          */
3471         error = bus_dma_tag_create(NULL, 1, boundary,
3472                                    lowaddr, BUS_SPACE_MAXADDR,
3473                                    NULL, NULL,
3474                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3475                                    BUS_SPACE_MAXSIZE_32BIT,
3476                                    0, &sc->bge_cdata.bge_parent_tag);
3477         if (error) {
3478                 if_printf(ifp, "could not allocate parent dma tag\n");
3479                 return error;
3480         }
3481
3482         /*
3483          * Create DMA tag and maps for RX mbufs.
3484          */
3485         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3486                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3487                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3488                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3489                                    &sc->bge_cdata.bge_rx_mtag);
3490         if (error) {
3491                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3492                 return error;
3493         }
3494
3495         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3496                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3497         if (error) {
3498                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3499                 sc->bge_cdata.bge_rx_mtag = NULL;
3500                 return error;
3501         }
3502
3503         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3504                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3505                                           BUS_DMA_WAITOK,
3506                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3507                 if (error) {
3508                         int j;
3509
3510                         for (j = 0; j < i; ++j) {
3511                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3512                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3513                         }
3514                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3515                         sc->bge_cdata.bge_rx_mtag = NULL;
3516
3517                         if_printf(ifp, "could not create DMA map for RX\n");
3518                         return error;
3519                 }
3520         }
3521
3522         /*
3523          * Create DMA tag and maps for TX mbufs.
3524          */
3525         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3526                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3527                                    NULL, NULL,
3528                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3529                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3530                                    BUS_DMA_ONEBPAGE,
3531                                    &sc->bge_cdata.bge_tx_mtag);
3532         if (error) {
3533                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3534                 return error;
3535         }
3536
3537         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3538                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3539                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3540                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3541                 if (error) {
3542                         int j;
3543
3544                         for (j = 0; j < i; ++j) {
3545                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3546                                         sc->bge_cdata.bge_tx_dmamap[j]);
3547                         }
3548                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3549                         sc->bge_cdata.bge_tx_mtag = NULL;
3550
3551                         if_printf(ifp, "could not create DMA map for TX\n");
3552                         return error;
3553                 }
3554         }
3555
3556         /*
3557          * Create DMA stuffs for standard RX ring.
3558          */
3559         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3560                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3561                                     &sc->bge_cdata.bge_rx_std_ring_map,
3562                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3563                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3564         if (error) {
3565                 if_printf(ifp, "could not create std RX ring\n");
3566                 return error;
3567         }
3568
3569         /*
3570          * Create jumbo buffer pool.
3571          */
3572         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3573                 error = bge_alloc_jumbo_mem(sc);
3574                 if (error) {
3575                         if_printf(ifp, "could not create jumbo buffer pool\n");
3576                         return error;
3577                 }
3578         }
3579
3580         /*
3581          * Create DMA stuffs for RX return ring.
3582          */
3583         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3584                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3585                                     &sc->bge_cdata.bge_rx_return_ring_map,
3586                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3587                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3588         if (error) {
3589                 if_printf(ifp, "could not create RX ret ring\n");
3590                 return error;
3591         }
3592
3593         /*
3594          * Create DMA stuffs for TX ring.
3595          */
3596         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3597                                     &sc->bge_cdata.bge_tx_ring_tag,
3598                                     &sc->bge_cdata.bge_tx_ring_map,
3599                                     (void *)&sc->bge_ldata.bge_tx_ring,
3600                                     &sc->bge_ldata.bge_tx_ring_paddr);
3601         if (error) {
3602                 if_printf(ifp, "could not create TX ring\n");
3603                 return error;
3604         }
3605
3606         /*
3607          * Create DMA stuffs for status block.
3608          */
3609         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3610                                     &sc->bge_cdata.bge_status_tag,
3611                                     &sc->bge_cdata.bge_status_map,
3612                                     (void *)&sc->bge_ldata.bge_status_block,
3613                                     &sc->bge_ldata.bge_status_block_paddr);
3614         if (error) {
3615                 if_printf(ifp, "could not create status block\n");
3616                 return error;
3617         }
3618
3619         /*
3620          * Create DMA stuffs for statistics block.
3621          */
3622         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3623                                     &sc->bge_cdata.bge_stats_tag,
3624                                     &sc->bge_cdata.bge_stats_map,
3625                                     (void *)&sc->bge_ldata.bge_stats,
3626                                     &sc->bge_ldata.bge_stats_paddr);
3627         if (error) {
3628                 if_printf(ifp, "could not create stats block\n");
3629                 return error;
3630         }
3631         return 0;
3632 }
3633
3634 static int
3635 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3636                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3637 {
3638         bus_dmamem_t dmem;
3639         int error;
3640
3641         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3642                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3643                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3644         if (error)
3645                 return error;
3646
3647         *tag = dmem.dmem_tag;
3648         *map = dmem.dmem_map;
3649         *addr = dmem.dmem_addr;
3650         *paddr = dmem.dmem_busaddr;
3651
3652         return 0;
3653 }
3654
3655 static void
3656 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3657 {
3658         if (tag != NULL) {
3659                 bus_dmamap_unload(tag, map);
3660                 bus_dmamem_free(tag, addr, map);
3661                 bus_dma_tag_destroy(tag);
3662         }
3663 }
3664
3665 /*
3666  * Grrr. The link status word in the status block does
3667  * not work correctly on the BCM5700 rev AX and BX chips,
3668  * according to all available information. Hence, we have
3669  * to enable MII interrupts in order to properly obtain
3670  * async link changes. Unfortunately, this also means that
3671  * we have to read the MAC status register to detect link
3672  * changes, thereby adding an additional register access to
3673  * the interrupt handler.
3674  *
3675  * XXX: perhaps link state detection procedure used for
3676  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3677  */
3678 static void
3679 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3680 {
3681         struct ifnet *ifp = &sc->arpcom.ac_if;
3682         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3683
3684         mii_pollstat(mii);
3685
3686         if (!sc->bge_link &&
3687             (mii->mii_media_status & IFM_ACTIVE) &&
3688             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3689                 sc->bge_link++;
3690                 if (bootverbose)
3691                         if_printf(ifp, "link UP\n");
3692         } else if (sc->bge_link &&
3693             (!(mii->mii_media_status & IFM_ACTIVE) ||
3694             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3695                 sc->bge_link = 0;
3696                 if (bootverbose)
3697                         if_printf(ifp, "link DOWN\n");
3698         }
3699
3700         /* Clear the interrupt. */
3701         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3702         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3703         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3704 }
3705
3706 static void
3707 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3708 {
3709         struct ifnet *ifp = &sc->arpcom.ac_if;
3710
3711 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3712
3713         /*
3714          * Sometimes PCS encoding errors are detected in
3715          * TBI mode (on fiber NICs), and for some reason
3716          * the chip will signal them as link changes.
3717          * If we get a link change event, but the 'PCS
3718          * encoding error' bit in the MAC status register
3719          * is set, don't bother doing a link check.
3720          * This avoids spurious "gigabit link up" messages
3721          * that sometimes appear on fiber NICs during
3722          * periods of heavy traffic.
3723          */
3724         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3725                 if (!sc->bge_link) {
3726                         sc->bge_link++;
3727                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3728                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3729                                     BGE_MACMODE_TBI_SEND_CFGS);
3730                         }
3731                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3732
3733                         if (bootverbose)
3734                                 if_printf(ifp, "link UP\n");
3735
3736                         ifp->if_link_state = LINK_STATE_UP;
3737                         if_link_state_change(ifp);
3738                 }
3739         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3740                 if (sc->bge_link) {
3741                         sc->bge_link = 0;
3742
3743                         if (bootverbose)
3744                                 if_printf(ifp, "link DOWN\n");
3745
3746                         ifp->if_link_state = LINK_STATE_DOWN;
3747                         if_link_state_change(ifp);
3748                 }
3749         }
3750
3751 #undef PCS_ENCODE_ERR
3752
3753         /* Clear the attention. */
3754         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3755             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3756             BGE_MACSTAT_LINK_CHANGED);
3757 }
3758
3759 static void
3760 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3761 {
3762         /*
3763          * Check that the AUTOPOLL bit is set before
3764          * processing the event as a real link change.
3765          * Turning AUTOPOLL on and off in the MII read/write
3766          * functions will often trigger a link status
3767          * interrupt for no reason.
3768          */
3769         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3770                 struct ifnet *ifp = &sc->arpcom.ac_if;
3771                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3772
3773                 mii_pollstat(mii);
3774
3775                 if (!sc->bge_link &&
3776                     (mii->mii_media_status & IFM_ACTIVE) &&
3777                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3778                         sc->bge_link++;
3779                         if (bootverbose)
3780                                 if_printf(ifp, "link UP\n");
3781                 } else if (sc->bge_link &&
3782                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3783                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3784                         sc->bge_link = 0;
3785                         if (bootverbose)
3786                                 if_printf(ifp, "link DOWN\n");
3787                 }
3788         }
3789
3790         /* Clear the attention. */
3791         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3792             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3793             BGE_MACSTAT_LINK_CHANGED);
3794 }
3795
3796 static int
3797 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3798 {
3799         struct bge_softc *sc = arg1;
3800
3801         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3802                                    &sc->bge_rx_coal_ticks,
3803                                    BGE_RX_COAL_TICKS_CHG);
3804 }
3805
3806 static int
3807 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3808 {
3809         struct bge_softc *sc = arg1;
3810
3811         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3812                                    &sc->bge_tx_coal_ticks,
3813                                    BGE_TX_COAL_TICKS_CHG);
3814 }
3815
3816 static int
3817 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3818 {
3819         struct bge_softc *sc = arg1;
3820
3821         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3822                                    &sc->bge_rx_max_coal_bds,
3823                                    BGE_RX_MAX_COAL_BDS_CHG);
3824 }
3825
3826 static int
3827 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3828 {
3829         struct bge_softc *sc = arg1;
3830
3831         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3832                                    &sc->bge_tx_max_coal_bds,
3833                                    BGE_TX_MAX_COAL_BDS_CHG);
3834 }
3835
3836 static int
3837 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3838                     uint32_t coal_chg_mask)
3839 {
3840         struct bge_softc *sc = arg1;
3841         struct ifnet *ifp = &sc->arpcom.ac_if;
3842         int error = 0, v;
3843
3844         lwkt_serialize_enter(ifp->if_serializer);
3845
3846         v = *coal;
3847         error = sysctl_handle_int(oidp, &v, 0, req);
3848         if (!error && req->newptr != NULL) {
3849                 if (v < 0) {
3850                         error = EINVAL;
3851                 } else {
3852                         *coal = v;
3853                         sc->bge_coal_chg |= coal_chg_mask;
3854                 }
3855         }
3856
3857         lwkt_serialize_exit(ifp->if_serializer);
3858         return error;
3859 }
3860
3861 static void
3862 bge_coal_change(struct bge_softc *sc)
3863 {
3864         struct ifnet *ifp = &sc->arpcom.ac_if;
3865         uint32_t val;
3866
3867         ASSERT_SERIALIZED(ifp->if_serializer);
3868
3869         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3870                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3871                             sc->bge_rx_coal_ticks);
3872                 DELAY(10);
3873                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3874
3875                 if (bootverbose) {
3876                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3877                                   sc->bge_rx_coal_ticks);
3878                 }
3879         }
3880
3881         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3882                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3883                             sc->bge_tx_coal_ticks);
3884                 DELAY(10);
3885                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3886
3887                 if (bootverbose) {
3888                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3889                                   sc->bge_tx_coal_ticks);
3890                 }
3891         }
3892
3893         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3894                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3895                             sc->bge_rx_max_coal_bds);
3896                 DELAY(10);
3897                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3898
3899                 if (bootverbose) {
3900                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3901                                   sc->bge_rx_max_coal_bds);
3902                 }
3903         }
3904
3905         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3906                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3907                             sc->bge_tx_max_coal_bds);
3908                 DELAY(10);
3909                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3910
3911                 if (bootverbose) {
3912                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3913                                   sc->bge_tx_max_coal_bds);
3914                 }
3915         }
3916
3917         sc->bge_coal_chg = 0;
3918 }
3919
3920 static void
3921 bge_enable_intr(struct bge_softc *sc)
3922 {
3923         struct ifnet *ifp = &sc->arpcom.ac_if;
3924
3925         lwkt_serialize_handler_enable(ifp->if_serializer);
3926
3927         /*
3928          * Enable interrupt.
3929          */
3930         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3931
3932         /*
3933          * Unmask the interrupt when we stop polling.
3934          */
3935         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3936
3937         /*
3938          * Trigger another interrupt, since above writing
3939          * to interrupt mailbox0 may acknowledge pending
3940          * interrupt.
3941          */
3942         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3943 }
3944
3945 static void
3946 bge_disable_intr(struct bge_softc *sc)
3947 {
3948         struct ifnet *ifp = &sc->arpcom.ac_if;
3949
3950         /*
3951          * Mask the interrupt when we start polling.
3952          */
3953         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3954
3955         /*
3956          * Acknowledge possible asserted interrupt.
3957          */
3958         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3959
3960         lwkt_serialize_handler_disable(ifp->if_serializer);
3961 }
3962
3963 static int
3964 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
3965 {
3966         uint32_t mac_addr;
3967         int ret = 1;
3968
3969         mac_addr = bge_readmem_ind(sc, 0x0c14);
3970         if ((mac_addr >> 16) == 0x484b) {
3971                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3972                 ether_addr[1] = (uint8_t)mac_addr;
3973                 mac_addr = bge_readmem_ind(sc, 0x0c18);
3974                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3975                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3976                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3977                 ether_addr[5] = (uint8_t)mac_addr;
3978                 ret = 0;
3979         }
3980         return ret;
3981 }
3982
3983 static int
3984 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
3985 {
3986         int mac_offset = BGE_EE_MAC_OFFSET;
3987
3988         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
3989                 mac_offset = BGE_EE_MAC_OFFSET_5906;
3990
3991         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
3992 }
3993
3994 static int
3995 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
3996 {
3997         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
3998                 return 1;
3999
4000         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4001                                ETHER_ADDR_LEN);
4002 }
4003
4004 static int
4005 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4006 {
4007         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4008                 /* NOTE: Order is critical */
4009                 bge_get_eaddr_mem,
4010                 bge_get_eaddr_nvram,
4011                 bge_get_eaddr_eeprom,
4012                 NULL
4013         };
4014         const bge_eaddr_fcn_t *func;
4015
4016         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4017                 if ((*func)(sc, eaddr) == 0)
4018                         break;
4019         }
4020         return (*func == NULL ? ENXIO : 0);
4021 }