sys/dev/netif/mii_layer/brgphy.c

   1 /*      $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $        */
   2
   3 /*
   4  * Copyright (c) 2000
   5  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $
  35  * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.21 2008/07/22 10:59:16 sephe Exp $
  36  */
  37
  38 /*
  39  * Driver for the Broadcom BCR5400 1000baseT PHY. Speed is always
  40  * 1000mbps; all we need to negotiate here is full or half duplex.
  41  */
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/socket.h>
  47 #include <sys/bus.h>
  48 #include <sys/sysctl.h>
  49
  50 #include <net/ethernet.h>
  51 #include <net/if.h>
  52 #include <net/if_media.h>
  53 #include <net/if_arp.h>
  54
  55 #include "mii.h"
  56 #include "miivar.h"
  57 #include "miidevs.h"
  58
  59 #include "brgphyreg.h"
  60 #include <dev/netif/bge/if_bgereg.h>
  61
  62 #include "miibus_if.h"
  63
  64 static int brgphy_probe(device_t);
  65 static int brgphy_attach(device_t);
  66
  67 static const struct mii_phydesc brgphys[] = {
  68         MII_PHYDESC(xxBROADCOM, BCM5400),
  69         MII_PHYDESC(xxBROADCOM, BCM5401),
  70         MII_PHYDESC(xxBROADCOM, BCM5411),
  71         MII_PHYDESC(xxBROADCOM, BCM5421),
  72         MII_PHYDESC(xxBROADCOM, BCM54K2),
  73         MII_PHYDESC(xxBROADCOM, BCM5462),
  74
  75         MII_PHYDESC(xxBROADCOM, BCM5701),
  76         MII_PHYDESC(xxBROADCOM, BCM5703),
  77         MII_PHYDESC(xxBROADCOM, BCM5704),
  78         MII_PHYDESC(xxBROADCOM, BCM5705),
  79
  80         MII_PHYDESC(xxBROADCOM, BCM5714),
  81         MII_PHYDESC(xxBROADCOM, BCM5750),
  82         MII_PHYDESC(xxBROADCOM, BCM5752),
  83         MII_PHYDESC(xxBROADCOM2,BCM5755),
  84         MII_PHYDESC(xxBROADCOM, BCM5780),
  85         MII_PHYDESC(xxBROADCOM2,BCM5787),
  86
  87         MII_PHYDESC(xxBROADCOM, BCM5706C),
  88         MII_PHYDESC(xxBROADCOM, BCM5708C),
  89
  90         MII_PHYDESC_NULL
  91 };
  92
  93 static device_method_t brgphy_methods[] = {
  94         /* device interface */
  95         DEVMETHOD(device_probe,         brgphy_probe),
  96         DEVMETHOD(device_attach,        brgphy_attach),
  97         DEVMETHOD(device_detach,        ukphy_detach),
  98         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  99         { 0, 0 }
 100 };
 101
 102 static devclass_t brgphy_devclass;
 103
 104 static driver_t brgphy_driver = {
 105         "brgphy",
 106         brgphy_methods,
 107         sizeof(struct mii_softc)
 108 };
 109
 110 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
 111
 112 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
 113 static void     brgphy_status(struct mii_softc *);
 114 static void     brgphy_mii_phy_auto(struct mii_softc *);
 115 static void     brgphy_reset(struct mii_softc *);
 116 static void     brgphy_loop(struct mii_softc *);
 117
 118 static void     brgphy_bcm5401_dspcode(struct mii_softc *);
 119 static void     brgphy_bcm5411_dspcode(struct mii_softc *);
 120 static void     brgphy_bcm5421_dspcode(struct mii_softc *);
 121 static void     brgphy_bcm54k2_dspcode(struct mii_softc *);
 122
 123 static void     brgphy_adc_bug(struct mii_softc *);
 124 static void     brgphy_5704_a0_bug(struct mii_softc *);
 125 static void     brgphy_ber_bug(struct mii_softc *);
 126 static void     brgphy_crc_bug(struct mii_softc *);
 127
 128 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 129 static void     brgphy_eth_wirespeed(struct mii_softc *);
 130
 131 static int
 132 brgphy_probe(device_t dev)
 133 {
 134         struct mii_attach_args *ma = device_get_ivars(dev);
 135         const struct mii_phydesc *mpd;
 136
 137         mpd = mii_phy_match(ma, brgphys);
 138         if (mpd != NULL) {
 139                 device_set_desc(dev, mpd->mpd_name);
 140                 return (0);
 141         }
 142         return(ENXIO);
 143 }
 144
 145 static int
 146 brgphy_attach(device_t dev)
 147 {
 148         struct mii_softc *sc;
 149         struct mii_attach_args *ma;
 150         struct mii_data *mii;
 151
 152         sc = device_get_softc(dev);
 153         ma = device_get_ivars(dev);
 154         mii_softc_init(sc, ma);
 155         sc->mii_dev = device_get_parent(dev);
 156         mii = device_get_softc(sc->mii_dev);
 157         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
 158
 159         sc->mii_inst = mii->mii_instance;
 160         sc->mii_service = brgphy_service;
 161         sc->mii_reset = brgphy_reset;
 162         sc->mii_pdata = mii;
 163
 164         sc->mii_flags |= MIIF_NOISOLATE;
 165         mii->mii_instance++;
 166
 167         brgphy_reset(sc);
 168
 169 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
 170
 171         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
 172             MII_MEDIA_NONE);
 173 #if 0
 174         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
 175             MII_MEDIA_100_TX);
 176 #endif
 177
 178 #undef ADD
 179
 180         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 181         if (sc->mii_capabilities & BMSR_EXTSTAT)
 182                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 183
 184         device_printf(dev, " ");
 185         if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
 186             (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
 187                 mii_phy_add_media(sc);
 188         else
 189                 kprintf("no media present");
 190         kprintf("\n");
 191
 192         MIIBUS_MEDIAINIT(sc->mii_dev);
 193         return(0);
 194 }
 195
 196 static int
 197 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 198 {
 199         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 200         int reg, speed, gig;
 201
 202         switch (cmd) {
 203         case MII_POLLSTAT:
 204                 /*
 205                  * If we're not polling our PHY instance, just return.
 206                  */
 207                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 208                         return (0);
 209                 break;
 210
 211         case MII_MEDIACHG:
 212                 /*
 213                  * If the media indicates a different PHY instance,
 214                  * isolate ourselves.
 215                  */
 216                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 217                         reg = PHY_READ(sc, MII_BMCR);
 218                         PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
 219                         return (0);
 220                 }
 221
 222                 /*
 223                  * If the interface is not up, don't do anything.
 224                  */
 225                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 226                         break;
 227
 228                 brgphy_reset(sc);       /* XXX hardware bug work-around */
 229
 230                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 231                 case IFM_AUTO:
 232 #ifdef foo
 233                         /*
 234                          * If we're already in auto mode, just return.
 235                          */
 236                         if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
 237                                 return (0);
 238 #endif
 239                         brgphy_mii_phy_auto(sc);
 240                         break;
 241                 case IFM_1000_T:
 242                         speed = BRGPHY_S1000;
 243                         goto setit;
 244                 case IFM_100_TX:
 245                         speed = BRGPHY_S100;
 246                         goto setit;
 247                 case IFM_10_T:
 248                         speed = BRGPHY_S10;
 249 setit:
 250                         brgphy_loop(sc);
 251                         if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
 252                                 speed |= BRGPHY_BMCR_FDX;
 253                                 gig = BRGPHY_1000CTL_AFD;
 254                         } else {
 255                                 gig = BRGPHY_1000CTL_AHD;
 256                         }
 257
 258                         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 259                         PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
 260                         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 261
 262                         if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
 263                                 break;
 264
 265                         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 266                         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 267                             speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
 268
 269                         if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
 270                                 break;
 271
 272                         /*
 273                          * When settning the link manually, one side must
 274                          * be the master and the other the slave. However
 275                          * ifmedia doesn't give us a good way to specify
 276                          * this, so we fake it by using one of the LINK
 277                          * flags. If LINK0 is set, we program the PHY to
 278                          * be a master, otherwise it's a slave.
 279                          */
 280                         if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
 281                                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 282                                     gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
 283                         } else {
 284                                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 285                                     gig|BRGPHY_1000CTL_MSE);
 286                         }
 287                         break;
 288 #ifdef foo
 289                 case IFM_NONE:
 290                         PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
 291                         break;
 292 #endif
 293                 case IFM_100_T4:
 294                 default:
 295                         return (EINVAL);
 296                 }
 297                 break;
 298
 299         case MII_TICK:
 300                 /*
 301                  * If we're not currently selected, just return.
 302                  */
 303                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 304                         return (0);
 305
 306                 /*
 307                  * Is the interface even up?
 308                  */
 309                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 310                         return (0);
 311
 312                 /*
 313                  * Only used for autonegotiation.
 314                  */
 315                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
 316                         break;
 317
 318                 /*
 319                  * Check to see if we have link.  If we do, we don't
 320                  * need to restart the autonegotiation process.
 321                  */
 322                 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 323                 if (reg & BRGPHY_AUXSTS_LINK) {
 324                         sc->mii_ticks = 0;
 325                         break;
 326                 }
 327
 328                 /*
 329                  * Only retry autonegotiation every 5 seconds.
 330                  */
 331                 if (++sc->mii_ticks <= sc->mii_anegticks)
 332                         break;
 333
 334                 sc->mii_ticks = 0;
 335                 brgphy_mii_phy_auto(sc);
 336                 break;
 337         }
 338
 339         /* Update the media status. */
 340         brgphy_status(sc);
 341
 342         /*
 343          * Callback if something changed. Note that we need to poke
 344          * the DSP on the Broadcom PHYs if the media changes.
 345          */
 346         if (sc->mii_media_active != mii->mii_media_active ||
 347             sc->mii_media_status != mii->mii_media_status ||
 348             cmd == MII_MEDIACHG) {
 349                 switch (sc->mii_model) {
 350                 case MII_MODEL_xxBROADCOM_BCM5400:
 351                         brgphy_bcm5401_dspcode(sc);
 352                         break;
 353                 case MII_MODEL_xxBROADCOM_BCM5401:
 354                         if (sc->mii_rev == 1 || sc->mii_rev == 3)
 355                                 brgphy_bcm5401_dspcode(sc);
 356                         break;
 357                 case MII_MODEL_xxBROADCOM_BCM5411:
 358                         brgphy_bcm5411_dspcode(sc);
 359                         break;
 360                 }
 361         }
 362         mii_phy_update(sc, cmd);
 363         return (0);
 364 }
 365
 366 static void
 367 brgphy_status(struct mii_softc *sc)
 368 {
 369         struct mii_data *mii = sc->mii_pdata;
 370         int bmcr, aux;
 371
 372         mii->mii_media_status = IFM_AVALID;
 373         mii->mii_media_active = IFM_ETHER;
 374
 375         aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 376         if (aux & BRGPHY_AUXSTS_LINK)
 377                 mii->mii_media_status |= IFM_ACTIVE;
 378
 379         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 380         if (bmcr & BRGPHY_BMCR_LOOP)
 381                 mii->mii_media_active |= IFM_LOOP;
 382
 383         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 384                 if ((PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_ACOMP) == 0) {
 385                         /* Erg, still trying, I guess... */
 386                         mii->mii_media_active |= IFM_NONE;
 387                         return;
 388                 }
 389
 390                 switch (aux & BRGPHY_AUXSTS_AN_RES) {
 391                 case BRGPHY_RES_1000FD:
 392                         mii->mii_media_active |= IFM_1000_T | IFM_FDX;
 393                         break;
 394                 case BRGPHY_RES_1000HD:
 395                         mii->mii_media_active |= IFM_1000_T | IFM_HDX;
 396                         break;
 397                 case BRGPHY_RES_100FD:
 398                         mii->mii_media_active |= IFM_100_TX | IFM_FDX;
 399                         break;
 400                 case BRGPHY_RES_100T4:
 401                         mii->mii_media_active |= IFM_100_T4;
 402                         break;
 403                 case BRGPHY_RES_100HD:
 404                         mii->mii_media_active |= IFM_100_TX | IFM_HDX;
 405                         break;
 406                 case BRGPHY_RES_10FD:
 407                         mii->mii_media_active |= IFM_10_T | IFM_FDX;
 408                         break;
 409                 case BRGPHY_RES_10HD:
 410                         mii->mii_media_active |= IFM_10_T | IFM_HDX;
 411                         break;
 412                 default:
 413                         mii->mii_media_active |= IFM_NONE;
 414                         break;
 415                 }
 416         } else {
 417                 mii->mii_media_active = mii->mii_media.ifm_cur->ifm_media;
 418         }
 419 }
 420
 421
 422 static void
 423 brgphy_mii_phy_auto(struct mii_softc *sc)
 424 {
 425         int ktcr = 0;
 426
 427         brgphy_loop(sc);
 428         brgphy_reset(sc);
 429         ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
 430         if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
 431                 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
 432         PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 433         ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
 434         DELAY(1000);
 435         PHY_WRITE(sc, BRGPHY_MII_ANAR,
 436             BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
 437         DELAY(1000);
 438         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 439             BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 440         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 441 }
 442
 443 static void
 444 brgphy_loop(struct mii_softc *sc)
 445 {
 446         uint32_t bmsr;
 447         int i;
 448
 449         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 450         for (i = 0; i < 15000; i++) {
 451                 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
 452                 if (!(bmsr & BRGPHY_BMSR_LINK))
 453                         break;
 454                 DELAY(10);
 455         }
 456 }
 457
 458 static void
 459 brgphy_reset(struct mii_softc *sc)
 460 {
 461         struct ifnet *ifp;
 462
 463         mii_phy_reset(sc);
 464
 465         switch (sc->mii_model) {
 466         case MII_MODEL_xxBROADCOM_BCM5400:
 467                 brgphy_bcm5401_dspcode(sc);
 468                         break;
 469         case MII_MODEL_xxBROADCOM_BCM5401:
 470                 if (sc->mii_rev == 1 || sc->mii_rev == 3)
 471                         brgphy_bcm5401_dspcode(sc);
 472                 break;
 473         case MII_MODEL_xxBROADCOM_BCM5411:
 474                 brgphy_bcm5411_dspcode(sc);
 475                 break;
 476         case MII_MODEL_xxBROADCOM_BCM5421:
 477                 brgphy_bcm5421_dspcode(sc);
 478                 break;
 479         case MII_MODEL_xxBROADCOM_BCM54K2:
 480                 brgphy_bcm54k2_dspcode(sc);
 481                 break;
 482         }
 483
 484         ifp = sc->mii_pdata->mii_ifp;
 485         if (strncmp(ifp->if_xname, "bge", 3) == 0) {
 486                 struct bge_softc *bge_sc = ifp->if_softc;
 487
 488                 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
 489                         brgphy_adc_bug(sc);
 490                 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
 491                         brgphy_5704_a0_bug(sc);
 492                 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) {
 493                         brgphy_ber_bug(sc);
 494                 } else if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) {
 495                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
 496                         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
 497
 498                         if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) {
 499                                 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
 500                                 PHY_WRITE(sc, BRGPHY_TEST1,
 501                                     BRGPHY_TEST1_TRIM_EN | 0x4);
 502                         } else {
 503                                 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b);
 504                         }
 505
 506                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
 507                 }
 508                 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
 509                         brgphy_crc_bug(sc);
 510
 511                 /* Set Jumbo frame settings in the PHY. */
 512                 brgphy_jumbo_settings(sc, ifp->if_mtu);
 513
 514                 /* Enable Ethernet@Wirespeed */
 515                 if (bge_sc->bge_flags & BGE_FLAG_ETH_WIRESPEED)
 516                         brgphy_eth_wirespeed(sc);
 517
 518                 /* Enable Link LED on Dell boxes */
 519                 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
 520                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 521                         PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
 522                                 & ~BRGPHY_PHY_EXTCTL_3_LED);
 523                 }
 524         } else if (strncmp(ifp->if_xname, "bce", 3) == 0) {
 525                 brgphy_ber_bug(sc);
 526                 brgphy_jumbo_settings(sc, ifp->if_mtu);
 527                 brgphy_eth_wirespeed(sc);
 528         }
 529 }
 530
 531 /* Turn off tap power management on 5401. */
 532 static void
 533 brgphy_bcm5401_dspcode(struct mii_softc *sc)
 534 {
 535         static const struct {
 536                 int             reg;
 537                 uint16_t        val;
 538         } dspcode[] = {
 539                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 540                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 541                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 542                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 543                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 544                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 545                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 546                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 547                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 548                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 549                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 550                 { 0,                            0 },
 551         };
 552         int i;
 553
 554         for (i = 0; dspcode[i].reg != 0; i++)
 555                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 556         DELAY(40);
 557 }
 558
 559 /* Setting some undocumented voltage */
 560 static void
 561 brgphy_bcm5411_dspcode(struct mii_softc *sc)
 562 {
 563         static const struct {
 564                 int             reg;
 565                 uint16_t        val;
 566         } dspcode[] = {
 567                 { 0x1c,                         0x8c23 },
 568                 { 0x1c,                         0x8ca3 },
 569                 { 0x1c,                         0x8c23 },
 570                 { 0,                            0 },
 571         };
 572         int i;
 573
 574         for (i = 0; dspcode[i].reg != 0; i++)
 575                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 576 }
 577
 578 static void
 579 brgphy_bcm5421_dspcode(struct mii_softc *sc)
 580 {
 581         uint16_t data;
 582
 583         /* Set Class A mode */
 584         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
 585         data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 586         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
 587
 588         /* Set FFE gamma override to -0.125 */
 589         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
 590         data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 591         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
 592         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
 593         data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
 594         PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
 595 }
 596
 597 static void
 598 brgphy_bcm54k2_dspcode(struct mii_softc *sc)
 599 {
 600         static const struct {
 601                 int             reg;
 602                 uint16_t        val;
 603         } dspcode[] = {
 604                 { 4,                            0x01e1 },
 605                 { 9,                            0x0300 },
 606                 { 0,                            0 },
 607         };
 608         int i;
 609
 610         for (i = 0; dspcode[i].reg != 0; i++)
 611                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 612 }
 613
 614 static void
 615 brgphy_adc_bug(struct mii_softc *sc)
 616 {
 617         static const struct {
 618                 int             reg;
 619                 uint16_t        val;
 620         } dspcode[] = {
 621                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 622                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 623                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 624                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 625                 { BRGPHY_MII_DSP_RW_PORT,       0x0323 },
 626                 { BRGPHY_MII_AUXCTL,            0x0400 },
 627                 { 0,                            0 },
 628         };
 629         int i;
 630
 631         for (i = 0; dspcode[i].reg != 0; i++)
 632                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 633 }
 634
 635 static void
 636 brgphy_5704_a0_bug(struct mii_softc *sc)
 637 {
 638         static const struct {
 639                 int             reg;
 640                 u_int16_t       val;
 641         } dspcode[] = {
 642                 { 0x1c,                         0x8d68 },
 643                 { 0x1c,                         0x8d68 },
 644                 { 0,                            0 },
 645         };
 646         int i;
 647
 648         for (i = 0; dspcode[i].reg != 0; i++)
 649                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 650 }
 651
 652 static void
 653 brgphy_ber_bug(struct mii_softc *sc)
 654 {
 655         static const struct {
 656                 int             reg;
 657                 uint16_t        val;
 658         } dspcode[] = {
 659                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 660                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 661                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 662                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 663                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 664                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 665                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 666                 { BRGPHY_MII_AUXCTL,            0x0400 },
 667                 { 0,                            0 },
 668         };
 669         int i;
 670
 671         for (i = 0; dspcode[i].reg != 0; i++)
 672                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 673 }
 674
 675 static void
 676 brgphy_crc_bug(struct mii_softc *sc)
 677 {
 678         static const struct {
 679                 int             reg;
 680                 uint16_t        val;
 681         } dspcode[] = {
 682                 { BRGPHY_MII_DSP_ADDR_REG,      0x0a75 },
 683                 { 0x1c,                         0x8c68 },
 684                 { 0x1c,                         0x8d68 },
 685                 { 0x1c,                         0x8c68 },
 686                 { 0,                            0 },
 687         };
 688         int i;
 689
 690         for (i = 0; dspcode[i].reg != 0; i++)
 691                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 692 }
 693
 694 static void
 695 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 696 {
 697         uint32_t val;
 698
 699         /* Set or clear jumbo frame settings in the PHY. */
 700         if (mtu > ETHER_MAX_LEN) {
 701                 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
 702                         /* BCM5401 PHY cannot read-modify-write. */
 703                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 704                 } else {
 705                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 706                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 707                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 708                             val | BRGPHY_AUXCTL_LONG_PKT);
 709                 }
 710
 711                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 712                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 713                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 714         } else {
 715                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 716                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 717                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 718                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 719
 720                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 721                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 722                     val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 723         }
 724 }
 725
 726 static void
 727 brgphy_eth_wirespeed(struct mii_softc *sc)
 728 {
 729         u_int32_t val;
 730
 731         /* Enable Ethernet@Wirespeed */
 732         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 733         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 734         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4)));
 735 }