sys/platform/pc32/i386/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.206 2009/11/12 10:59:00 nyan
  40  */
  41 #include "opt_cpu.h"
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/sysctl.h>
  47 #include <sys/lock.h>
  48
  49 #include <machine/asmacros.h>
  50 #include <machine/clock.h>
  51 #include <machine/cputypes.h>
  52 #include <machine/segments.h>
  53 #include <machine/specialreg.h>
  54 #include <machine/md_var.h>
  55 #include <machine/intr_machdep.h>
  56
  57 #define IDENTBLUE_CYRIX486      0
  58 #define IDENTBLUE_IBMCPU        1
  59 #define IDENTBLUE_CYRIXM2       2
  60
  61 /* XXX - should be in header file: */
  62 void printcpuinfo(void);
  63 void finishidentcpu(void);
  64 void earlysetcpuclass(void);
  65 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  66 void    enable_K5_wt_alloc(void);
  67 void    enable_K6_wt_alloc(void);
  68 void    enable_K6_2_wt_alloc(void);
  69 #endif
  70 void panicifcpuunsupported(void);
  71
  72 static void identifycyrix(void);
  73 static void init_exthigh(void);
  74 static u_int find_cpu_vendor_id(void);
  75 static void print_AMD_info(void);
  76 static void print_INTEL_info(void);
  77 static void print_INTEL_TLB(u_int data);
  78 static void print_AMD_assoc(int i);
  79 static void print_transmeta_info(void);
  80 static void print_via_padlock_info(void);
  81
  82 int     cpu_class;
  83 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
  84 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
  85 char machine[] = MACHINE;
  86 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  87     machine, 0, "Machine class");
  88
  89 static char cpu_model[128];
  90 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
  91     cpu_model, 0, "Machine model");
  92
  93 static int hw_clockrate;
  94 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
  95     &hw_clockrate, 0, "CPU instruction clock rate");
  96
  97 static char cpu_brand[48];
  98
  99 #define MAX_ADDITIONAL_INFO     16
 100
 101 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
 102 static u_int additional_cpu_info_count;
 103
 104 #define MAX_BRAND_INDEX 8
 105
 106 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 107         NULL,                   /* No brand */
 108         "Intel Celeron",
 109         "Intel Pentium III",
 110         "Intel Pentium III Xeon",
 111         NULL,
 112         NULL,
 113         NULL,
 114         NULL,
 115         "Intel Pentium 4"
 116 };
 117
 118 static struct {
 119         char    *cpu_name;
 120         int     cpu_class;
 121 } i386_cpus[] = {
 122         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 123         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 124         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 125         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 126         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 127         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 128         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 129         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 130         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 131         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 132         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 133         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 134         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 135         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 136         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 137         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 138         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 139 };
 140
 141 static struct {
 142         char    *vendor;
 143         u_int   vendor_id;
 144 } cpu_vendors[] = {
 145         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 146         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 147         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 148         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 149         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 150         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 151         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 152         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 153         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 154         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 155 #if 0
 156         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 157         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 158 #endif
 159 };
 160
 161 #ifdef foo
 162 static int cpu_cores;
 163 static int cpu_logical;
 164 #endif
 165
 166 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 167 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
 168 #endif
 169
 170 static void
 171 init_exthigh(void)
 172 {
 173         static int done = 0;
 174         u_int regs[4];
 175
 176         if (done == 0) {
 177                 if (cpu_high > 0 &&
 178                     (cpu_vendor_id == CPU_VENDOR_INTEL ||
 179                     cpu_vendor_id == CPU_VENDOR_AMD ||
 180                     cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 181                     cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 182                     cpu_vendor_id == CPU_VENDOR_NSC)) {
 183                         do_cpuid(0x80000000, regs);
 184                         if (regs[0] >= 0x80000000)
 185                                 cpu_exthigh = regs[0];
 186                 }
 187
 188                 done = 1;
 189         }
 190 }
 191
 192 void
 193 printcpuinfo(void)
 194 {
 195         u_int regs[4], i;
 196         char *brand;
 197
 198         cpu_class = i386_cpus[cpu].cpu_class;
 199         kprintf("CPU: ");
 200         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
 201
 202         /* Check for extended CPUID information and a processor name. */
 203         init_exthigh();
 204         if (cpu_exthigh >= 0x80000004) {
 205                 brand = cpu_brand;
 206                 for (i = 0x80000002; i < 0x80000005; i++) {
 207                         do_cpuid(i, regs);
 208                         memcpy(brand, regs, sizeof(regs));
 209                         brand += sizeof(regs);
 210                 }
 211         }
 212
 213         if (cpu_vendor_id == CPU_VENDOR_INTEL) {
 214                 if ((cpu_id & 0xf00) > 0x300) {
 215                         u_int brand_index;
 216
 217                         cpu_model[0] = '\0';
 218
 219                         switch (cpu_id & 0x3000) {
 220                         case 0x1000:
 221                                 strcpy(cpu_model, "Overdrive ");
 222                                 break;
 223                         case 0x2000:
 224                                 strcpy(cpu_model, "Dual ");
 225                                 break;
 226                         }
 227
 228                         switch (cpu_id & 0xf00) {
 229                         case 0x400:
 230                                 strcat(cpu_model, "i486 ");
 231                                 /* Check the particular flavor of 486 */
 232                                 switch (cpu_id & 0xf0) {
 233                                 case 0x00:
 234                                 case 0x10:
 235                                         strcat(cpu_model, "DX");
 236                                         break;
 237                                 case 0x20:
 238                                         strcat(cpu_model, "SX");
 239                                         break;
 240                                 case 0x30:
 241                                         strcat(cpu_model, "DX2");
 242                                         break;
 243                                 case 0x40:
 244                                         strcat(cpu_model, "SL");
 245                                         break;
 246                                 case 0x50:
 247                                         strcat(cpu_model, "SX2");
 248                                         break;
 249                                 case 0x70:
 250                                         strcat(cpu_model,
 251                                             "DX2 Write-Back Enhanced");
 252                                         break;
 253                                 case 0x80:
 254                                         strcat(cpu_model, "DX4");
 255                                         break;
 256                                 }
 257                                 break;
 258                         case 0x500:
 259                                 /* Check the particular flavor of 586 */
 260                                 strcat(cpu_model, "Pentium");
 261                                 switch (cpu_id & 0xf0) {
 262                                 case 0x00:
 263                                         strcat(cpu_model, " A-step");
 264                                         break;
 265                                 case 0x10:
 266                                         strcat(cpu_model, "/P5");
 267                                         break;
 268                                 case 0x20:
 269                                         strcat(cpu_model, "/P54C");
 270                                         break;
 271                                 case 0x30:
 272                                         strcat(cpu_model, "/P24T");
 273                                         break;
 274                                 case 0x40:
 275                                         strcat(cpu_model, "/P55C");
 276                                         break;
 277                                 case 0x70:
 278                                         strcat(cpu_model, "/P54C");
 279                                         break;
 280                                 case 0x80:
 281                                         strcat(cpu_model, "/P55C (quarter-micron)");
 282                                         break;
 283                                 default:
 284                                         /* nothing */
 285                                         break;
 286                                 }
 287 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 288                                 /*
 289                                  * XXX - If/when Intel fixes the bug, this
 290                                  * should also check the version of the
 291                                  * CPU, not just that it's a Pentium.
 292                                  */
 293                                 has_f00f_bug = 1;
 294 #endif
 295                                 break;
 296                         case 0x600:
 297                                 /* Check the particular flavor of 686 */
 298                                 switch (cpu_id & 0xf0) {
 299                                 case 0x00:
 300                                         strcat(cpu_model, "Pentium Pro A-step");
 301                                         break;
 302                                 case 0x10:
 303                                         strcat(cpu_model, "Pentium Pro");
 304                                         break;
 305                                 case 0x30:
 306                                 case 0x50:
 307                                 case 0x60:
 308                                         strcat(cpu_model,
 309                                 "Pentium II/Pentium II Xeon/Celeron");
 310                                         cpu = CPU_PII;
 311                                         break;
 312                                 case 0x70:
 313                                 case 0x80:
 314                                 case 0xa0:
 315                                 case 0xb0:
 316                                         strcat(cpu_model,
 317                                         "Pentium III/Pentium III Xeon/Celeron");
 318                                         cpu = CPU_PIII;
 319                                         break;
 320                                 default:
 321                                         strcat(cpu_model, "Unknown 80686");
 322                                         break;
 323                                 }
 324                                 break;
 325                         case 0xf00:
 326                                 strcat(cpu_model, "Pentium 4");
 327                                 cpu = CPU_P4;
 328                                 break;
 329                         default:
 330                                 strcat(cpu_model, "unknown");
 331                                 break;
 332                         }
 333
 334                         /*
 335                          * If we didn't get a brand name from the extended
 336                          * CPUID, try to look it up in the brand table.
 337                          */
 338                         if (cpu_high > 0 && *cpu_brand == '\0') {
 339                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 340                                 if (brand_index <= MAX_BRAND_INDEX &&
 341                                     cpu_brandtable[brand_index] != NULL)
 342                                         strcpy(cpu_brand,
 343                                             cpu_brandtable[brand_index]);
 344                         }
 345                 }
 346         } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
 347                 /*
 348                  * Values taken from AMD Processor Recognition
 349                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 350                  * (also describes ``Features'' encodings.
 351                  */
 352                 strcpy(cpu_model, "AMD ");
 353                 switch (cpu_id & 0xFF0) {
 354                 case 0x410:
 355                         strcat(cpu_model, "Standard Am486DX");
 356                         break;
 357                 case 0x430:
 358                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 359                         break;
 360                 case 0x470:
 361                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 362                         break;
 363                 case 0x480:
 364                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 365                         break;
 366                 case 0x490:
 367                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 368                         break;
 369                 case 0x4E0:
 370                         strcat(cpu_model, "Am5x86 Write-Through");
 371                         break;
 372                 case 0x4F0:
 373                         strcat(cpu_model, "Am5x86 Write-Back");
 374                         break;
 375                 case 0x500:
 376                         strcat(cpu_model, "K5 model 0");
 377                         tsc_is_broken = 1;
 378                         break;
 379                 case 0x510:
 380                         strcat(cpu_model, "K5 model 1");
 381                         break;
 382                 case 0x520:
 383                         strcat(cpu_model, "K5 PR166 (model 2)");
 384                         break;
 385                 case 0x530:
 386                         strcat(cpu_model, "K5 PR200 (model 3)");
 387                         break;
 388                 case 0x560:
 389                         strcat(cpu_model, "K6");
 390                         break;
 391                 case 0x570:
 392                         strcat(cpu_model, "K6 266 (model 1)");
 393                         break;
 394                 case 0x580:
 395                         strcat(cpu_model, "K6-2");
 396                         break;
 397                 case 0x590:
 398                         strcat(cpu_model, "K6-III");
 399                         break;
 400                 case 0x5a0:
 401                         strcat(cpu_model, "Geode LX");
 402                         /*
 403                          * Make sure the TSC runs through suspension,
 404                          * otherwise we can't use it as timecounter
 405                          */
 406                         wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
 407                         break;
 408                 default:
 409                         strcat(cpu_model, "Unknown");
 410                         break;
 411                 }
 412 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 413                 if ((cpu_id & 0xf00) == 0x500) {
 414                         if (((cpu_id & 0x0f0) > 0)
 415                             && ((cpu_id & 0x0f0) < 0x60)
 416                             && ((cpu_id & 0x00f) > 3))
 417                                 enable_K5_wt_alloc();
 418                         else if (((cpu_id & 0x0f0) > 0x80)
 419                                  || (((cpu_id & 0x0f0) == 0x80)
 420                                      && (cpu_id & 0x00f) > 0x07))
 421                                 enable_K6_2_wt_alloc();
 422                         else if ((cpu_id & 0x0f0) > 0x50)
 423                                 enable_K6_wt_alloc();
 424                 }
 425 #endif
 426         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 427                 strcpy(cpu_model, "Cyrix ");
 428                 switch (cpu_id & 0xff0) {
 429                 case 0x440:
 430                         strcat(cpu_model, "MediaGX");
 431                         break;
 432                 case 0x520:
 433                         strcat(cpu_model, "6x86");
 434                         break;
 435                 case 0x540:
 436                         cpu_class = CPUCLASS_586;
 437                         strcat(cpu_model, "GXm");
 438                         break;
 439                 case 0x600:
 440                         strcat(cpu_model, "6x86MX");
 441                         break;
 442                 default:
 443                         /*
 444                          * Even though CPU supports the cpuid
 445                          * instruction, it can be disabled.
 446                          * Therefore, this routine supports all Cyrix
 447                          * CPUs.
 448                          */
 449                         switch (cyrix_did & 0xf0) {
 450                         case 0x00:
 451                                 switch (cyrix_did & 0x0f) {
 452                                 case 0x00:
 453                                         strcat(cpu_model, "486SLC");
 454                                         break;
 455                                 case 0x01:
 456                                         strcat(cpu_model, "486DLC");
 457                                         break;
 458                                 case 0x02:
 459                                         strcat(cpu_model, "486SLC2");
 460                                         break;
 461                                 case 0x03:
 462                                         strcat(cpu_model, "486DLC2");
 463                                         break;
 464                                 case 0x04:
 465                                         strcat(cpu_model, "486SRx");
 466                                         break;
 467                                 case 0x05:
 468                                         strcat(cpu_model, "486DRx");
 469                                         break;
 470                                 case 0x06:
 471                                         strcat(cpu_model, "486SRx2");
 472                                         break;
 473                                 case 0x07:
 474                                         strcat(cpu_model, "486DRx2");
 475                                         break;
 476                                 case 0x08:
 477                                         strcat(cpu_model, "486SRu");
 478                                         break;
 479                                 case 0x09:
 480                                         strcat(cpu_model, "486DRu");
 481                                         break;
 482                                 case 0x0a:
 483                                         strcat(cpu_model, "486SRu2");
 484                                         break;
 485                                 case 0x0b:
 486                                         strcat(cpu_model, "486DRu2");
 487                                         break;
 488                                 default:
 489                                         strcat(cpu_model, "Unknown");
 490                                         break;
 491                                 }
 492                                 break;
 493                         case 0x10:
 494                                 switch (cyrix_did & 0x0f) {
 495                                 case 0x00:
 496                                         strcat(cpu_model, "486S");
 497                                         break;
 498                                 case 0x01:
 499                                         strcat(cpu_model, "486S2");
 500                                         break;
 501                                 case 0x02:
 502                                         strcat(cpu_model, "486Se");
 503                                         break;
 504                                 case 0x03:
 505                                         strcat(cpu_model, "486S2e");
 506                                         break;
 507                                 case 0x0a:
 508                                         strcat(cpu_model, "486DX");
 509                                         break;
 510                                 case 0x0b:
 511                                         strcat(cpu_model, "486DX2");
 512                                         break;
 513                                 case 0x0f:
 514                                         strcat(cpu_model, "486DX4");
 515                                         break;
 516                                 default:
 517                                         strcat(cpu_model, "Unknown");
 518                                         break;
 519                                 }
 520                                 break;
 521                         case 0x20:
 522                                 if ((cyrix_did & 0x0f) < 8)
 523                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 524                                 else
 525                                         strcat(cpu_model, "5x86");
 526                                 break;
 527                         case 0x30:
 528                                 strcat(cpu_model, "6x86");
 529                                 break;
 530                         case 0x40:
 531                                 if ((cyrix_did & 0xf000) == 0x3000) {
 532                                         cpu_class = CPUCLASS_586;
 533                                         strcat(cpu_model, "GXm");
 534                                 } else
 535                                         strcat(cpu_model, "MediaGX");
 536                                 break;
 537                         case 0x50:
 538                                 strcat(cpu_model, "6x86MX");
 539                                 break;
 540                         case 0xf0:
 541                                 switch (cyrix_did & 0x0f) {
 542                                 case 0x0d:
 543                                         strcat(cpu_model, "Overdrive CPU");
 544                                         break;
 545                                 case 0x0e:
 546                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 547                                         break;
 548                                 case 0x0f:
 549                                         strcat(cpu_model, "486SLC/DLC");
 550                                         break;
 551                                 default:
 552                                         strcat(cpu_model, "Unknown");
 553                                         break;
 554                                 }
 555                                 break;
 556                         default:
 557                                 strcat(cpu_model, "Unknown");
 558                                 break;
 559                         }
 560                         break;
 561                 }
 562         } else if (cpu_vendor_id == CPU_VENDOR_RISE) {
 563                 strcpy(cpu_model, "Rise ");
 564                 switch (cpu_id & 0xff0) {
 565                 case 0x500:
 566                         strcat(cpu_model, "mP6");
 567                         break;
 568                 default:
 569                         strcat(cpu_model, "Unknown");
 570                 }
 571         } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 572                 switch (cpu_id & 0xff0) {
 573                 case 0x540:
 574                         strcpy(cpu_model, "IDT WinChip C6");
 575                         tsc_is_broken = 1;
 576                         break;
 577                 case 0x580:
 578                         strcpy(cpu_model, "IDT WinChip 2");
 579                         break;
 580                 case 0x660:
 581                         strcpy(cpu_model, "VIA C3 Samuel");
 582                         break;
 583                 case 0x670:
 584                         if (cpu_id & 0x8)
 585                                 strcpy(cpu_model, "VIA C3 Ezra");
 586                         else
 587                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 588                         break;
 589                 case 0x680:
 590                         strcpy(cpu_model, "VIA C3 Ezra-T");
 591                         break;
 592                 case 0x690:
 593                         strcpy(cpu_model, "VIA C3 Nehemiah");
 594                         break;
 595                 case 0x6a0:
 596                 case 0x6d0:
 597                         strcpy(cpu_model, "VIA C7 Esther");
 598                         break;
 599                 case 0x6f0:
 600                         strcpy(cpu_model, "VIA Nano");
 601                         break;
 602                 default:
 603                         strcpy(cpu_model, "VIA/IDT Unknown");
 604                 }
 605         } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
 606                 strcpy(cpu_model, "Blue Lightning CPU");
 607         } else if (cpu_vendor_id == CPU_VENDOR_NSC) {
 608                 switch (cpu_id & 0xfff) {
 609                 case 0x540:
 610                         strcpy(cpu_model, "Geode SC1100");
 611                         cpu = CPU_GEODE1100;
 612                         tsc_is_broken = 1;
 613                         break;
 614                 default:
 615                         strcpy(cpu_model, "Geode/NSC unknown");
 616                         break;
 617                 }
 618         }
 619
 620         /*
 621          * Replace cpu_model with cpu_brand minus leading spaces if
 622          * we have one.
 623          */
 624         brand = cpu_brand;
 625         while (*brand == ' ')
 626                 ++brand;
 627         if (*brand != '\0')
 628                 strcpy(cpu_model, brand);
 629
 630         kprintf("%s (", cpu_model);
 631         switch(cpu_class) {
 632         case CPUCLASS_286:
 633                 kprintf("286");
 634                 break;
 635         case CPUCLASS_386:
 636                 kprintf("386");
 637                 break;
 638 #if defined(I486_CPU)
 639         case CPUCLASS_486:
 640                 kprintf("486");
 641                 break;
 642 #endif
 643 #if defined(I586_CPU)
 644         case CPUCLASS_586:
 645                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
 646                 kprintf("%jd.%02d-MHz ",
 647                        (intmax_t)(tsc_frequency + 4999) / 1000000,
 648                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
 649                 kprintf("586");
 650                 break;
 651 #endif
 652 #if defined(I686_CPU)
 653         case CPUCLASS_686:
 654                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
 655                 kprintf("%jd.%02d-MHz ",
 656                        (intmax_t)(tsc_frequency + 4999) / 1000000,
 657                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
 658                 kprintf("686");
 659                 break;
 660 #endif
 661         default:
 662                 kprintf("Unknown");     /* will panic below... */
 663         }
 664         kprintf("-class CPU)\n");
 665         if(*cpu_vendor)
 666                 kprintf("  Origin = \"%s\"",cpu_vendor);
 667         if(cpu_id)
 668                 kprintf("  Id = 0x%x", cpu_id);
 669
 670         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 671             cpu_vendor_id == CPU_VENDOR_AMD ||
 672             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 673             cpu_vendor_id == CPU_VENDOR_RISE ||
 674             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 675             cpu_vendor_id == CPU_VENDOR_NSC ||
 676                 (cpu_vendor_id == CPU_VENDOR_CYRIX &&
 677                  ((cpu_id & 0xf00) > 0x500))) {
 678                 kprintf("  Stepping = %u", cpu_id & 0xf);
 679                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 680                         kprintf("  DIR=0x%04x", cyrix_did);
 681                 if (cpu_high > 0) {
 682                         u_int cmp = 1, htt = 1;
 683
 684                         /*
 685                          * Here we should probably set up flags indicating
 686                          * whether or not various features are available.
 687                          * The interesting ones are probably VME, PSE, PAE,
 688                          * and PGE.  The code already assumes without bothering
 689                          * to check that all CPUs >= Pentium have a TSC and
 690                          * MSRs.
 691                          */
 692                         kprintf("\n  Features=0x%b", cpu_feature,
 693                         "\020"
 694                         "\001FPU"       /* Integral FPU */
 695                         "\002VME"       /* Extended VM86 mode support */
 696                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 697                         "\004PSE"       /* 4MByte page tables */
 698                         "\005TSC"       /* Timestamp counter */
 699                         "\006MSR"       /* Machine specific registers */
 700                         "\007PAE"       /* Physical address extension */
 701                         "\010MCE"       /* Machine Check support */
 702                         "\011CX8"       /* CMPEXCH8 instruction */
 703                         "\012APIC"      /* SMP local APIC */
 704                         "\013oldMTRR"   /* Previous implementation of MTRR */
 705                         "\014SEP"       /* Fast System Call */
 706                         "\015MTRR"      /* Memory Type Range Registers */
 707                         "\016PGE"       /* PG_G (global bit) support */
 708                         "\017MCA"       /* Machine Check Architecture */
 709                         "\020CMOV"      /* CMOV instruction */
 710                         "\021PAT"       /* Page attributes table */
 711                         "\022PSE36"     /* 36 bit address space support */
 712                         "\023PN"        /* Processor Serial number */
 713                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 714                         "\025<b20>"
 715                         "\026DTS"       /* Debug Trace Store */
 716                         "\027ACPI"      /* ACPI support */
 717                         "\030MMX"       /* MMX instructions */
 718                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 719                         "\032SSE"       /* Streaming SIMD Extensions */
 720                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 721                         "\034SS"        /* Self snoop */
 722                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 723                         "\036TM"        /* Thermal Monitor clock slowdown */
 724                         "\037IA64"      /* CPU can execute IA64 instructions */
 725                         "\040PBE"       /* Pending Break Enable */
 726                         );
 727
 728                         if (cpu_feature2 != 0) {
 729                                 kprintf("\n  Features2=0x%b", cpu_feature2,
 730                                 "\020"
 731                                 "\001SSE3"      /* SSE3 */
 732                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 733                                 "\003DTES64"    /* 64-bit Debug Trace */
 734                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 735                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 736                                 "\006VMX"       /* Virtual Machine Extensions */
 737                                 "\007SMX"       /* Safer Mode Extensions */
 738                                 "\010EST"       /* Enhanced SpeedStep */
 739                                 "\011TM2"       /* Thermal Monitor 2 */
 740                                 "\012SSSE3"     /* SSSE3 */
 741                                 "\013CNXT-ID"   /* L1 context ID available */
 742                                 "\014<b11>"
 743                                 "\015FMA"       /* Fused Multiply Add */
 744                                 "\016CX16"      /* CMPXCHG16B Instruction */
 745                                 "\017xTPR"      /* Send Task Priority Messages */
 746                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 747                                 "\021<b16>"
 748                                 "\022PCID"      /* Process-context Identifiers */
 749                                 "\023DCA"       /* Direct Cache Access */
 750                                 "\024SSE4.1"    /* SSE 4.1 */
 751                                 "\025SSE4.2"    /* SSE 4.2 */
 752                                 "\026x2APIC"    /* xAPIC Extensions */
 753                                 "\027MOVBE"     /* MOVBE Instruction */
 754                                 "\030POPCNT"    /* POPCNT Instruction */
 755                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 756                                 "\032AESNI"     /* AES Crypto */
 757                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 758                                 "\034OSXSAVE"   /* OS-Enabled State Management */
 759                                 "\035AVX"       /* Advanced Vector Extensions */
 760                                 "\036F16C"      /* Half-precision conversions */
 761                                 "\037RDRND"     /* RDRAND RNG function */
 762                                 "\040VMM"       /* Running on a hypervisor */
 763                                 );
 764                         }
 765
 766                         /*
 767                          * AMD64 Architecture Programmer's Manual Volume 3:
 768                          * General-Purpose and System Instructions
 769                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
 770                          *
 771                          * IA-32 Intel Architecture Software Developer's Manual,
 772                          * Volume 2A: Instruction Set Reference, A-M
 773                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
 774                          */
 775                         if (amd_feature != 0) {
 776                                 kprintf("\n  AMD Features=0x%b", amd_feature,
 777                                 "\020"          /* in hex */
 778                                 "\001<s0>"      /* Same */
 779                                 "\002<s1>"      /* Same */
 780                                 "\003<s2>"      /* Same */
 781                                 "\004<s3>"      /* Same */
 782                                 "\005<s4>"      /* Same */
 783                                 "\006<s5>"      /* Same */
 784                                 "\007<s6>"      /* Same */
 785                                 "\010<s7>"      /* Same */
 786                                 "\011<s8>"      /* Same */
 787                                 "\012<s9>"      /* Same */
 788                                 "\013<b10>"     /* Undefined */
 789                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 790                                 "\015<s12>"     /* Same */
 791                                 "\016<s13>"     /* Same */
 792                                 "\017<s14>"     /* Same */
 793                                 "\020<s15>"     /* Same */
 794                                 "\021<s16>"     /* Same */
 795                                 "\022<s17>"     /* Same */
 796                                 "\023<b18>"     /* Reserved, unknown */
 797                                 "\024MP"        /* Multiprocessor Capable */
 798                                 "\025NX"        /* Has EFER.NXE, NX */
 799                                 "\026<b21>"     /* Undefined */
 800                                 "\027MMX+"      /* AMD MMX Extensions */
 801                                 "\030<s23>"     /* Same */
 802                                 "\031<s24>"     /* Same */
 803                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 804                                 "\033Page1GB"   /* 1-GB large page support */
 805                                 "\034RDTSCP"    /* RDTSCP */
 806                                 "\035<b28>"     /* Undefined */
 807                                 "\036LM"        /* 64 bit long mode */
 808                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 809                                 "\0403DNow!"    /* AMD 3DNow! */
 810                                 );
 811                         }
 812
 813                         if (amd_feature2 != 0) {
 814                                 kprintf("\n  AMD Features2=0x%b", amd_feature2,
 815                                 "\020"
 816                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 817                                 "\002CMP"       /* CMP legacy */
 818                                 "\003SVM"       /* Secure Virtual Mode */
 819                                 "\004ExtAPIC"   /* Extended APIC register */
 820                                 "\005CR8"       /* CR8 in legacy mode */
 821                                 "\006ABM"       /* LZCNT instruction */
 822                                 "\007SSE4A"     /* SSE4A */
 823                                 "\010MAS"       /* Misaligned SSE mode */
 824                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 825                                 "\012OSVW"      /* OS visible workaround */
 826                                 "\013IBS"       /* Instruction based sampling */
 827                                 "\014XOP"       /* XOP extended instructions */
 828                                 "\015SKINIT"    /* SKINIT/STGI */
 829                                 "\016WDT"       /* Watchdog timer */
 830                                 "\017<b14>"
 831                                 "\020LWP"       /* Lightweight Profiling */
 832                                 "\021FMA4"      /* 4-operand FMA instructions */
 833                                 "\022TCE"       /* Translation Cache Extension */
 834                                 "\023<b18>"
 835                                 "\024NodeId"    /* NodeId MSR support */
 836                                 "\025<b20>"
 837                                 "\026TBM"       /* Trailing Bit Manipulation */
 838                                 "\027Topology"  /* Topology Extensions */
 839                                 "\030PCX_CORE"  /* Core Performance Counter */
 840                                 "\031PCX_NB"    /* NB Performance Counter */
 841                                 "\032<b25>"
 842                                 "\033<b26>"
 843                                 "\034<b27>"
 844                                 "\035<b28>"
 845                                 "\036<b29>"
 846                                 "\037<b30>"
 847                                 "\040<b31>"
 848                                 );
 849                         }
 850
 851                         if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
 852                                 print_via_padlock_info();
 853
 854                         if ((cpu_feature & CPUID_HTT) &&
 855                             cpu_vendor_id == CPU_VENDOR_AMD)
 856                                 cpu_feature &= ~CPUID_HTT;
 857
 858                         /*
 859                          * If this CPU supports HTT or CMP then mention the
 860                          * number of physical/logical cores it contains.
 861                          */
 862                         if (cpu_feature & CPUID_HTT)
 863                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
 864                         if (cpu_vendor_id == CPU_VENDOR_AMD &&
 865                             (amd_feature2 & AMDID2_CMP))
 866                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
 867                         else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
 868                             (cpu_high >= 4)) {
 869                                 cpuid_count(4, 0, regs);
 870                                 if ((regs[0] & 0x1f) != 0)
 871                                         cmp = ((regs[0] >> 26) & 0x3f) + 1;
 872                         }
 873
 874 #ifdef foo
 875                         /*
 876                          * XXX For Intel CPUs, this is max number of cores per
 877                          * package, not the actual cores per package.
 878                          */
 879                         cpu_cores = cmp;
 880                         cpu_logical = htt / cmp;
 881
 882                         if (cpu_cores > 1)
 883                                 kprintf("\n  Cores per package: %d", cpu_cores);
 884                         if (cpu_logical > 1) {
 885                                 kprintf("\n  Logical CPUs per core: %d",
 886                                     cpu_logical);
 887                         }
 888 #endif
 889
 890 #if 0
 891                         /*
 892                          * If this CPU supports P-state invariant TSC then
 893                          * mention the capability.
 894                          */
 895                         switch (cpu_vendor_id) {
 896                         case CPU_VENDOR_AMD:
 897                                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
 898                                     CPUID_TO_FAMILY(cpu_id) >= 0x10 ||
 899                                     cpu_id == 0x60fb2)
 900                                         tsc_is_invariant = 1;
 901                                 break;
 902                         case CPU_VENDOR_INTEL:
 903                                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
 904                                     (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
 905                                     CPUID_TO_MODEL(cpu_id) >= 0xe) ||
 906                                     (CPUID_TO_FAMILY(cpu_id) == 0xf &&
 907                                     CPUID_TO_MODEL(cpu_id) >= 0x3))
 908                                         tsc_is_invariant = 1;
 909                                 break;
 910                         case CPU_VENDOR_CENTAUR:
 911                                 if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
 912                                     CPUID_TO_MODEL(cpu_id) >= 0xf &&
 913                                     (rdmsr(0x1203) & 0x100000000ULL) == 0)
 914                                         tsc_is_invariant = 1;
 915                                 break;
 916                         }
 917                         if (tsc_is_invariant)
 918                                 kprintf("\n  TSC: P-state invariant");
 919 #endif
 920
 921                 }
 922         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 923                 kprintf("  DIR=0x%04x", cyrix_did);
 924                 kprintf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
 925                 kprintf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
 926 #ifndef CYRIX_CACHE_REALLY_WORKS
 927                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
 928                         kprintf("\n  CPU cache: write-through mode");
 929 #endif
 930         }
 931
 932         /* Avoid ugly blank lines: only print newline when we have to. */
 933         if (*cpu_vendor || cpu_id)
 934                 kprintf("\n");
 935
 936         for (i = 0; i < additional_cpu_info_count; ++i) {
 937                 kprintf("  %s\n", additional_cpu_info_ary[i]);
 938         }
 939
 940         if (!bootverbose)
 941                 return;
 942
 943         if (cpu_vendor_id == CPU_VENDOR_AMD)
 944                 print_AMD_info();
 945         else if (cpu_vendor_id == CPU_VENDOR_INTEL)
 946                 print_INTEL_info();
 947         else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
 948                 print_transmeta_info();
 949
 950 #ifdef CPU_HAS_SSE2
 951         kprintf("Use SSE2 (lfence, mfence)\n");
 952 #endif
 953 }
 954
 955 void
 956 panicifcpuunsupported(void)
 957 {
 958
 959 #if !defined(lint)
 960 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
 961 #error This kernel is not configured for one of the supported CPUs
 962 #endif
 963 #else /* lint */
 964 #endif /* lint */
 965         /*
 966          * Now that we have told the user what they have,
 967          * let them know if that machine type isn't configured.
 968          */
 969         switch (cpu_class) {
 970         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
 971         case CPUCLASS_386:
 972 #if !defined(I486_CPU)
 973         case CPUCLASS_486:
 974 #endif
 975 #if !defined(I586_CPU)
 976         case CPUCLASS_586:
 977 #endif
 978 #if !defined(I686_CPU)
 979         case CPUCLASS_686:
 980 #endif
 981                 panic("CPU class not configured");
 982         default:
 983                 break;
 984         }
 985 }
 986
 987
 988 static  volatile u_int trap_by_rdmsr;
 989
 990 /*
 991  * Special exception 6 handler.
 992  * The rdmsr instruction generates invalid opcodes fault on 486-class
 993  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
 994  * function identblue() when this handler is called.  Stacked eip should
 995  * be advanced.
 996  */
 997 inthand_t       bluetrap6;
 998
 999 __asm
1000 ("                                                                      \n\
1001         .text                                                           \n\
1002         .p2align 2,0x90                                                 \n\
1003         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1004 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1005         ss                                                              \n\
1006         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1007         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1008         iret                                                            \n\
1009 ");
1010
1011 /*
1012  * Special exception 13 handler.
1013  * Accessing non-existent MSR generates general protection fault.
1014  */
1015 inthand_t       bluetrap13;
1016
1017 __asm
1018 ("                                                                      \n\
1019         .text                                                           \n\
1020         .p2align 2,0x90                                                 \n\
1021         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1022 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1023         ss                                                              \n\
1024         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1025         popl    %eax            /* discard error code */                \n\
1026         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1027         iret                                                            \n\
1028 ");
1029
1030 /*
1031  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1032  * support cpuid instruction.  This function should be called after
1033  * loading interrupt descriptor table register.
1034  *
1035  * I don't like this method that handles fault, but I couldn't get
1036  * information for any other methods.  Does blue giant know?
1037  */
1038 static int
1039 identblue(void)
1040 {
1041
1042         trap_by_rdmsr = 0;
1043
1044         /*
1045          * Cyrix 486-class CPU does not support rdmsr instruction.
1046          * The rdmsr instruction generates invalid opcode fault, and exception
1047          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1048          * bluetrap6() set the magic number to trap_by_rdmsr.
1049          */
1050         setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1051             GSEL(GCODE_SEL, SEL_KPL));
1052
1053         /*
1054          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1055          * In this case, rdmsr generates general protection fault, and
1056          * exception will be trapped by bluetrap13().
1057          */
1058         setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1059             GSEL(GCODE_SEL, SEL_KPL));
1060
1061         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1062
1063         if (trap_by_rdmsr == 0xa8c1d)
1064                 return IDENTBLUE_CYRIX486;
1065         else if (trap_by_rdmsr == 0xa89c4)
1066                 return IDENTBLUE_CYRIXM2;
1067         return IDENTBLUE_IBMCPU;
1068 }
1069
1070
1071 /*
1072  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1073  *
1074  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1075  * +-------+-------+---------------+
1076  * |  SID  |  RID  |   Device ID   |
1077  * |    (DIR 1)    |    (DIR 0)    |
1078  * +-------+-------+---------------+
1079  */
1080 static void
1081 identifycyrix(void)
1082 {
1083         int     ccr2_test = 0, dir_test = 0;
1084         u_char  ccr2, ccr3;
1085
1086         mpintr_lock();
1087
1088         ccr2 = read_cyrix_reg(CCR2);
1089         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1090         read_cyrix_reg(CCR2);
1091         if (read_cyrix_reg(CCR2) != ccr2)
1092                 ccr2_test = 1;
1093         write_cyrix_reg(CCR2, ccr2);
1094
1095         ccr3 = read_cyrix_reg(CCR3);
1096         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1097         read_cyrix_reg(CCR3);
1098         if (read_cyrix_reg(CCR3) != ccr3)
1099                 dir_test = 1;                                   /* CPU supports DIRs. */
1100         write_cyrix_reg(CCR3, ccr3);
1101
1102         if (dir_test) {
1103                 /* Device ID registers are available. */
1104                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1105                 cyrix_did += read_cyrix_reg(DIR0);
1106         } else if (ccr2_test)
1107                 cyrix_did = 0x0010;             /* 486S A-step */
1108         else
1109                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1110         mpintr_unlock();
1111 }
1112
1113 #if 0
1114 /* Update TSC freq with the value indicated by the caller. */
1115 static void
1116 tsc_frequency_changed(void *arg, const struct cf_level *level, int status)
1117 {
1118         /*
1119          * If there was an error during the transition or
1120          * TSC is P-state invariant, don't do anything.
1121          */
1122         if (status != 0 || tsc_is_invariant)
1123                 return;
1124
1125         /* Total setting for this level gives the new frequency in MHz. */
1126         hw_clockrate = level->total_set.freq;
1127 }
1128 #endif
1129
1130 /*
1131  * Final stage of CPU identification. -- Should I check TI?
1132  */
1133 void
1134 finishidentcpu(void)
1135 {
1136         int     isblue = 0;
1137         u_char  ccr3;
1138         u_int   regs[4];
1139
1140         cpu_vendor_id = find_cpu_vendor_id();
1141
1142         /*
1143          * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
1144          * function number again if it is set from BIOS.  It is necessary
1145          * for probing correct CPU topology later.
1146          * XXX This is only done on the BSP package.
1147          */
1148         if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
1149             ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1150             (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1151                 uint64_t msr;
1152                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1153                 if ((msr & 0x400000ULL) != 0) {
1154                         wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
1155                         do_cpuid(0, regs);
1156                         cpu_high = regs[0];
1157                 }
1158         }
1159
1160         /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
1161         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1162             cpu_vendor_id == CPU_VENDOR_AMD) {
1163                 init_exthigh();
1164                 if (cpu_exthigh >= 0x80000001) {
1165                         do_cpuid(0x80000001, regs);
1166                         amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1167                         amd_feature2 = regs[2];
1168                 }
1169 #if 0
1170                 if (cpu_exthigh >= 0x80000007) {
1171                         do_cpuid(0x80000007, regs);
1172                         amd_pminfo = regs[3];
1173                 }
1174 #endif
1175                 if (cpu_exthigh >= 0x80000008) {
1176                         do_cpuid(0x80000008, regs);
1177                         cpu_procinfo2 = regs[2];
1178                 }
1179         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1180                 if (cpu == CPU_486) {
1181                         /*
1182                          * These conditions are equivalent to:
1183                          *     - CPU does not support cpuid instruction.
1184                          *     - Cyrix/IBM CPU is detected.
1185                          */
1186                         isblue = identblue();
1187                         if (isblue == IDENTBLUE_IBMCPU) {
1188                                 strcpy(cpu_vendor, "IBM");
1189                                 cpu_vendor_id = CPU_VENDOR_IBM;
1190                                 cpu = CPU_BLUE;
1191                                 goto finish;
1192                         }
1193                 }
1194                 switch (cpu_id & 0xf00) {
1195                 case 0x600:
1196                         /*
1197                          * Cyrix's datasheet does not describe DIRs.
1198                          * Therefor, I assume it does not have them
1199                          * and use the result of the cpuid instruction.
1200                          * XXX they seem to have it for now at least. -Peter
1201                          */
1202                         identifycyrix();
1203                         cpu = CPU_M2;
1204                         break;
1205                 default:
1206                         identifycyrix();
1207                         /*
1208                          * This routine contains a trick.
1209                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1210                          */
1211                         switch (cyrix_did & 0x00f0) {
1212                         case 0x00:
1213                         case 0xf0:
1214                                 cpu = CPU_486DLC;
1215                                 break;
1216                         case 0x10:
1217                                 cpu = CPU_CY486DX;
1218                                 break;
1219                         case 0x20:
1220                                 if ((cyrix_did & 0x000f) < 8)
1221                                         cpu = CPU_M1;
1222                                 else
1223                                         cpu = CPU_M1SC;
1224                                 break;
1225                         case 0x30:
1226                                 cpu = CPU_M1;
1227                                 break;
1228                         case 0x40:
1229                                 /* MediaGX CPU */
1230                                 cpu = CPU_M1SC;
1231                                 break;
1232                         default:
1233                                 /* M2 and later CPUs are treated as M2. */
1234                                 cpu = CPU_M2;
1235
1236                                 /*
1237                                  * enable cpuid instruction.
1238                                  */
1239                                 ccr3 = read_cyrix_reg(CCR3);
1240                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1241                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1242                                 write_cyrix_reg(CCR3, ccr3);
1243
1244                                 do_cpuid(0, regs);
1245                                 cpu_high = regs[0];     /* eax */
1246                                 do_cpuid(1, regs);
1247                                 cpu_id = regs[0];       /* eax */
1248                                 cpu_feature = regs[3];  /* edx */
1249                                 break;
1250                         }
1251                 }
1252         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1253                 /*
1254                  * There are BlueLightning CPUs that do not change
1255                  * undefined flags by dividing 5 by 2.  In this case,
1256                  * the CPU identification routine in locore.s leaves
1257                  * cpu_vendor null string and puts CPU_486 into the
1258                  * cpu.
1259                  */
1260                 isblue = identblue();
1261                 if (isblue == IDENTBLUE_IBMCPU) {
1262                         strcpy(cpu_vendor, "IBM");
1263                         cpu_vendor_id = CPU_VENDOR_IBM;
1264                         cpu = CPU_BLUE;
1265                 }
1266         }
1267
1268         /*
1269          * Set MI flags for MI procedures implemented using machine-specific
1270          * features.
1271          */
1272 finish:
1273         if (cpu_feature & CPUID_SSE2)
1274                 cpu_mi_feature |= CPU_MI_BZERONT;
1275
1276         if (cpu_feature2 & CPUID2_MON)
1277                 cpu_mi_feature |= CPU_MI_MONITOR;
1278
1279 #ifdef CPU_HAS_SSE2
1280         if ((cpu_feature & CPUID_SSE2) == 0)
1281                 panic("CPU does not has SSE2, remove options CPU_HAS_SSE2");
1282 #endif
1283 }
1284
1285 static u_int
1286 find_cpu_vendor_id(void)
1287 {
1288         int     i;
1289
1290         for (i = 0; i < NELEM(cpu_vendors); i++)
1291                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1292                         return (cpu_vendors[i].vendor_id);
1293         return (0);
1294 }
1295
1296 static void
1297 print_AMD_assoc(int i)
1298 {
1299         if (i == 255)
1300                 kprintf(", fully associative\n");
1301         else
1302                 kprintf(", %d-way associative\n", i);
1303 }
1304
1305 /*
1306  * #31116 Rev 3.06 section 3.9
1307  * CPUID Fn8000_0006 L2/L3 Cache and L2 TLB Identifiers
1308  */
1309 static void
1310 print_AMD_L2L3_assoc(int i)
1311 {
1312         static const char *assoc_str[] = {
1313                 [0x0] = "disabled",
1314                 [0x1] = "direct mapped",
1315                 [0x2] = "2-way associative",
1316                 [0x4] = "4-way associative",
1317                 [0x6] = "8-way associative",
1318                 [0x8] = "16-way associative",
1319                 [0xa] = "32-way associative",
1320                 [0xb] = "48-way associative",
1321                 [0xc] = "64-way associative",
1322                 [0xd] = "96-way associative",
1323                 [0xe] = "128-way associative",
1324                 [0xf] = "fully associative"
1325         };
1326
1327         i &= 0xf;
1328         if (assoc_str[i] == NULL)
1329                 kprintf(", unknown associative\n");
1330         else
1331                 kprintf(", %s\n", assoc_str[i]);
1332 }
1333
1334 static void
1335 print_AMD_info(void)
1336 {
1337         quad_t amd_whcr;
1338
1339         if (cpu_exthigh >= 0x80000005) {
1340                 u_int regs[4];
1341
1342                 do_cpuid(0x80000005, regs);
1343                 kprintf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1344                 print_AMD_assoc(regs[1] >> 24);
1345                 kprintf("Instruction TLB: %d entries", regs[1] & 0xff);
1346                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1347                 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
1348                 kprintf(", %d bytes/line", regs[2] & 0xff);
1349                 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1350                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1351                 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1352                 kprintf(", %d bytes/line", regs[3] & 0xff);
1353                 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1354                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1355                 if (cpu_exthigh >= 0x80000006) {        /* K6-III or later */
1356                         do_cpuid(0x80000006, regs);
1357                         /*
1358                          * Report right L2 cache size on Duron rev. A0.
1359                          */
1360                         if ((cpu_id & 0xFF0) == 0x630)
1361                                 kprintf("L2 internal cache: 64 kbytes");
1362                         else
1363                                 kprintf("L2 internal cache: %d kbytes", regs[2] >> 16);
1364
1365                         kprintf(", %d bytes/line", regs[2] & 0xff);
1366                         kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1367                         print_AMD_L2L3_assoc((regs[2] >> 12) & 0x0f);
1368
1369                         /*
1370                          * #31116 Rev 3.06 section 2.16.2:
1371                          * ... If EDX[31:16] is not zero then the processor
1372                          * includes an L3. ...
1373                          */
1374                         if ((regs[3] & 0xffff0000) != 0) {
1375                                 kprintf("L3 shared cache: %d kbytes",
1376                                         (regs[3] >> 18) * 512);
1377                                 kprintf(", %d bytes/line", regs[3] & 0xff);
1378                                 kprintf(", %d lines/tag", (regs[3] >> 8) & 0x0f);
1379                                 print_AMD_L2L3_assoc((regs[3] >> 12) & 0x0f);
1380                         }
1381                 }
1382         }
1383         if (((cpu_id & 0xf00) == 0x500)
1384             && (((cpu_id & 0x0f0) > 0x80)
1385                 || (((cpu_id & 0x0f0) == 0x80)
1386                     && (cpu_id & 0x00f) > 0x07))) {
1387                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1388                 amd_whcr = rdmsr(0xc0000082);
1389                 if (!(amd_whcr & (0x3ff << 22))) {
1390                         kprintf("Write Allocate Disable\n");
1391                 } else {
1392                         kprintf("Write Allocate Enable Limit: %dM bytes\n",
1393                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1394                         kprintf("Write Allocate 15-16M bytes: %s\n",
1395                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1396                 }
1397         } else if (((cpu_id & 0xf00) == 0x500)
1398                    && ((cpu_id & 0x0f0) > 0x50)) {
1399                 /* K6, K6-2(old core) */
1400                 amd_whcr = rdmsr(0xc0000082);
1401                 if (!(amd_whcr & (0x7f << 1))) {
1402                         kprintf("Write Allocate Disable\n");
1403                 } else {
1404                         kprintf("Write Allocate Enable Limit: %dM bytes\n",
1405                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1406                         kprintf("Write Allocate 15-16M bytes: %s\n",
1407                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1408                         kprintf("Hardware Write Allocate Control: %s\n",
1409                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1410                 }
1411         }
1412
1413         /*
1414          * Opteron Rev E shows a bug as in very rare occasions a read memory
1415          * barrier is not performed as expected if it is followed by a
1416          * non-atomic read-modify-write instruction.
1417          * As long as that bug pops up very rarely (intensive machine usage
1418          * on other operating systems generally generates one unexplainable
1419          * crash any 2 months) and as long as a model specific fix would be
1420          * impratical at this stage, print out a warning string if the broken
1421          * model and family are identified.
1422          */
1423         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1424             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1425                 kprintf("WARNING: This architecture revision has known SMP "
1426                     "hardware bugs which may cause random instability\n");
1427 }
1428
1429 static void
1430 print_INTEL_info(void)
1431 {
1432         u_int regs[4];
1433         u_int rounds, regnum;
1434         u_int nwaycode, nway;
1435
1436         if (cpu_high >= 2) {
1437                 rounds = 0;
1438                 do {
1439                         do_cpuid(0x2, regs);
1440                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1441                                 break;  /* we have a buggy CPU */
1442
1443                         for (regnum = 0; regnum <= 3; ++regnum) {
1444                                 if (regs[regnum] & (1<<31))
1445                                         continue;
1446                                 if (regnum != 0)
1447                                         print_INTEL_TLB(regs[regnum] & 0xff);
1448                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1449                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1450                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1451                         }
1452                 } while (--rounds > 0);
1453         }
1454
1455         if (cpu_exthigh >= 0x80000006) {
1456                 do_cpuid(0x80000006, regs);
1457                 nwaycode = (regs[2] >> 12) & 0x0f;
1458                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1459                         nway = 1 << (nwaycode / 2);
1460                 else
1461                         nway = 0;
1462                 kprintf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
1463                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1464         }
1465
1466         kprintf("\n");
1467 }
1468
1469 static void
1470 print_INTEL_TLB(u_int data)
1471 {
1472         switch (data) {
1473         case 0x0:
1474         case 0x40:
1475         default:
1476                 break;
1477         case 0x1:
1478                 kprintf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
1479                 break;
1480         case 0x2:
1481                 kprintf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
1482                 break;
1483         case 0x3:
1484                 kprintf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
1485                 break;
1486         case 0x4:
1487                 kprintf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
1488                 break;
1489         case 0x6:
1490                 kprintf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
1491                 break;
1492         case 0x8:
1493                 kprintf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
1494                 break;
1495         case 0xa:
1496                 kprintf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
1497                 break;
1498         case 0xc:
1499                 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
1500                 break;
1501         case 0x22:
1502                 kprintf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
1503                 break;
1504         case 0x23:
1505                 kprintf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1506                 break;
1507         case 0x25:
1508                 kprintf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
1509                 break;
1510         case 0x29:
1511                 kprintf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
1512                 break;
1513         case 0x2c:
1514                 kprintf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
1515                 break;
1516         case 0x30:
1517                 kprintf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
1518                 break;
1519         case 0x39:
1520                 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
1521                 break;
1522         case 0x3b:
1523                 kprintf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
1524                 break;
1525         case 0x3c:
1526                 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
1527                 break;
1528         case 0x41:
1529                 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
1530                 break;
1531         case 0x42:
1532                 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
1533                 break;
1534         case 0x43:
1535                 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
1536                 break;
1537         case 0x44:
1538                 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
1539                 break;
1540         case 0x45:
1541                 kprintf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
1542                 break;
1543         case 0x46:
1544                 kprintf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
1545                 break;
1546         case 0x47:
1547                 kprintf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
1548                 break;
1549         case 0x50:
1550                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
1551                 break;
1552         case 0x51:
1553                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
1554                 break;
1555         case 0x52:
1556                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
1557                 break;
1558         case 0x5b:
1559                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
1560                 break;
1561         case 0x5c:
1562                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
1563                 break;
1564         case 0x5d:
1565                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
1566                 break;
1567         case 0x60:
1568                 kprintf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
1569                 break;
1570         case 0x66:
1571                 kprintf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
1572                 break;
1573         case 0x67:
1574                 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
1575                 break;
1576         case 0x68:
1577                 kprintf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
1578                 break;
1579         case 0x70:
1580                 kprintf("\nTrace cache: 12K-uops, 8-way set associative");
1581                 break;
1582         case 0x71:
1583                 kprintf("\nTrace cache: 16K-uops, 8-way set associative");
1584                 break;
1585         case 0x72:
1586                 kprintf("\nTrace cache: 32K-uops, 8-way set associative");
1587                 break;
1588         case 0x78:
1589                 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
1590                 break;
1591         case 0x79:
1592                 kprintf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
1593                 break;
1594         case 0x7a:
1595                 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
1596                 break;
1597         case 0x7b:
1598                 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
1599                 break;
1600         case 0x7c:
1601                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1602                 break;
1603         case 0x7d:
1604                 kprintf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
1605                 break;
1606         case 0x7f:
1607                 kprintf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
1608                 break;
1609         case 0x82:
1610                 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
1611                 break;
1612         case 0x83:
1613                 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
1614                 break;
1615         case 0x84:
1616                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
1617                 break;
1618         case 0x85:
1619                 kprintf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
1620                 break;
1621         case 0x86:
1622                 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
1623                 break;
1624         case 0x87:
1625                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
1626                 break;
1627         case 0xb0:
1628                 kprintf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
1629                 break;
1630         case 0xb3:
1631                 kprintf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
1632                 break;
1633         }
1634 }
1635
1636 static void
1637 print_transmeta_info(void)
1638 {
1639         u_int regs[4], nreg = 0;
1640
1641         do_cpuid(0x80860000, regs);
1642         nreg = regs[0];
1643         if (nreg >= 0x80860001) {
1644                 do_cpuid(0x80860001, regs);
1645                 kprintf("  Processor revision %u.%u.%u.%u\n",
1646                        (regs[1] >> 24) & 0xff,
1647                        (regs[1] >> 16) & 0xff,
1648                        (regs[1] >> 8) & 0xff,
1649                        regs[1] & 0xff);
1650         }
1651         if (nreg >= 0x80860002) {
1652                 do_cpuid(0x80860002, regs);
1653                 kprintf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
1654                        (regs[1] >> 24) & 0xff,
1655                        (regs[1] >> 16) & 0xff,
1656                        (regs[1] >> 8) & 0xff,
1657                        regs[1] & 0xff,
1658                        regs[2]);
1659         }
1660         if (nreg >= 0x80860006) {
1661                 char info[65];
1662                 do_cpuid(0x80860003, (u_int*) &info[0]);
1663                 do_cpuid(0x80860004, (u_int*) &info[16]);
1664                 do_cpuid(0x80860005, (u_int*) &info[32]);
1665                 do_cpuid(0x80860006, (u_int*) &info[48]);
1666                 info[64] = 0;
1667                 kprintf("  %s\n", info);
1668         }
1669 }
1670
1671 static void
1672 print_via_padlock_info(void)
1673 {
1674         u_int regs[4];
1675
1676         /* Check for supported models. */
1677         switch (cpu_id & 0xff0) {
1678         case 0x690:
1679                 if ((cpu_id & 0xf) < 3)
1680                         return;
1681         case 0x6a0:
1682         case 0x6d0:
1683         case 0x6f0:
1684                 break;
1685         default:
1686                 return;
1687         }
1688
1689         do_cpuid(0xc0000000, regs);
1690         if (regs[0] >= 0xc0000001)
1691                 do_cpuid(0xc0000001, regs);
1692         else
1693                 return;
1694
1695         kprintf("\n  VIA Padlock Features=0x%b", regs[3],
1696         "\020"
1697         "\003RNG"               /* RNG */
1698         "\007AES"               /* ACE */
1699         "\011AES-CTR"           /* ACE2 */
1700         "\013SHA1,SHA256"       /* PHE */
1701         "\015RSA"               /* PMM */
1702         );
1703 }
1704
1705 void
1706 additional_cpu_info(const char *line)
1707 {
1708         int i;
1709
1710         if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1711                 additional_cpu_info_ary[i] = line;
1712                 ++additional_cpu_info_count;
1713         }
1714 }