sys/platform/pc32/apic/ioapic_abi.c

   1 /*
   2  * Copyright (c) 2005 The DragonFly Project.  All rights reserved.
   3  * Copyright (c) 1996, by Steve Passe.  All rights reserved.
   4  * Copyright (c) 1991 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The DragonFly Project
   8  * by Matthew Dillon <dillon@backplane.com>
   9  *
  10  * This code is derived from software contributed to Berkeley by
  11  * William Jolitz.
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  * 3. Neither the name of The DragonFly Project nor the names of its
  24  *    contributors may be used to endorse or promote products derived
  25  *    from this software without specific, prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  31  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  35  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  * $DragonFly: src/sys/platform/pc32/apic/apic_abi.c,v 1.12 2007/04/30 16:45:55 dillon Exp $
  41  */
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/machintr.h>
  47 #include <sys/interrupt.h>
  48 #include <sys/bus.h>
  49 #include <sys/rman.h>
  50 #include <sys/thread2.h>
  51
  52 #include <machine/smp.h>
  53 #include <machine/segments.h>
  54 #include <machine/md_var.h>
  55 #include <machine/intr_machdep.h>
  56 #include <machine/globaldata.h>
  57 #include <machine/msi_var.h>
  58
  59 #include <machine_base/isa/isa_intr.h>
  60 #include <machine_base/icu/icu.h>
  61 #include <machine_base/icu/icu_var.h>
  62 #include <machine_base/apic/ioapic.h>
  63 #include <machine_base/apic/ioapic_abi.h>
  64 #include <machine_base/apic/ioapic_ipl.h>
  65 #include <machine_base/apic/apicreg.h>
  66
  67 #include <dev/acpica5/acpi_sci_var.h>
  68
  69 #define IOAPIC_HWI_VECTORS      IDT_HWI_VECTORS
  70
  71 extern inthand_t
  72         IDTVEC(ioapic_intr0),
  73         IDTVEC(ioapic_intr1),
  74         IDTVEC(ioapic_intr2),
  75         IDTVEC(ioapic_intr3),
  76         IDTVEC(ioapic_intr4),
  77         IDTVEC(ioapic_intr5),
  78         IDTVEC(ioapic_intr6),
  79         IDTVEC(ioapic_intr7),
  80         IDTVEC(ioapic_intr8),
  81         IDTVEC(ioapic_intr9),
  82         IDTVEC(ioapic_intr10),
  83         IDTVEC(ioapic_intr11),
  84         IDTVEC(ioapic_intr12),
  85         IDTVEC(ioapic_intr13),
  86         IDTVEC(ioapic_intr14),
  87         IDTVEC(ioapic_intr15),
  88         IDTVEC(ioapic_intr16),
  89         IDTVEC(ioapic_intr17),
  90         IDTVEC(ioapic_intr18),
  91         IDTVEC(ioapic_intr19),
  92         IDTVEC(ioapic_intr20),
  93         IDTVEC(ioapic_intr21),
  94         IDTVEC(ioapic_intr22),
  95         IDTVEC(ioapic_intr23),
  96         IDTVEC(ioapic_intr24),
  97         IDTVEC(ioapic_intr25),
  98         IDTVEC(ioapic_intr26),
  99         IDTVEC(ioapic_intr27),
 100         IDTVEC(ioapic_intr28),
 101         IDTVEC(ioapic_intr29),
 102         IDTVEC(ioapic_intr30),
 103         IDTVEC(ioapic_intr31),
 104         IDTVEC(ioapic_intr32),
 105         IDTVEC(ioapic_intr33),
 106         IDTVEC(ioapic_intr34),
 107         IDTVEC(ioapic_intr35),
 108         IDTVEC(ioapic_intr36),
 109         IDTVEC(ioapic_intr37),
 110         IDTVEC(ioapic_intr38),
 111         IDTVEC(ioapic_intr39),
 112         IDTVEC(ioapic_intr40),
 113         IDTVEC(ioapic_intr41),
 114         IDTVEC(ioapic_intr42),
 115         IDTVEC(ioapic_intr43),
 116         IDTVEC(ioapic_intr44),
 117         IDTVEC(ioapic_intr45),
 118         IDTVEC(ioapic_intr46),
 119         IDTVEC(ioapic_intr47),
 120         IDTVEC(ioapic_intr48),
 121         IDTVEC(ioapic_intr49),
 122         IDTVEC(ioapic_intr50),
 123         IDTVEC(ioapic_intr51),
 124         IDTVEC(ioapic_intr52),
 125         IDTVEC(ioapic_intr53),
 126         IDTVEC(ioapic_intr54),
 127         IDTVEC(ioapic_intr55),
 128         IDTVEC(ioapic_intr56),
 129         IDTVEC(ioapic_intr57),
 130         IDTVEC(ioapic_intr58),
 131         IDTVEC(ioapic_intr59),
 132         IDTVEC(ioapic_intr60),
 133         IDTVEC(ioapic_intr61),
 134         IDTVEC(ioapic_intr62),
 135         IDTVEC(ioapic_intr63),
 136         IDTVEC(ioapic_intr64),
 137         IDTVEC(ioapic_intr65),
 138         IDTVEC(ioapic_intr66),
 139         IDTVEC(ioapic_intr67),
 140         IDTVEC(ioapic_intr68),
 141         IDTVEC(ioapic_intr69),
 142         IDTVEC(ioapic_intr70),
 143         IDTVEC(ioapic_intr71),
 144         IDTVEC(ioapic_intr72),
 145         IDTVEC(ioapic_intr73),
 146         IDTVEC(ioapic_intr74),
 147         IDTVEC(ioapic_intr75),
 148         IDTVEC(ioapic_intr76),
 149         IDTVEC(ioapic_intr77),
 150         IDTVEC(ioapic_intr78),
 151         IDTVEC(ioapic_intr79),
 152         IDTVEC(ioapic_intr80),
 153         IDTVEC(ioapic_intr81),
 154         IDTVEC(ioapic_intr82),
 155         IDTVEC(ioapic_intr83),
 156         IDTVEC(ioapic_intr84),
 157         IDTVEC(ioapic_intr85),
 158         IDTVEC(ioapic_intr86),
 159         IDTVEC(ioapic_intr87),
 160         IDTVEC(ioapic_intr88),
 161         IDTVEC(ioapic_intr89),
 162         IDTVEC(ioapic_intr90),
 163         IDTVEC(ioapic_intr91),
 164         IDTVEC(ioapic_intr92),
 165         IDTVEC(ioapic_intr93),
 166         IDTVEC(ioapic_intr94),
 167         IDTVEC(ioapic_intr95),
 168         IDTVEC(ioapic_intr96),
 169         IDTVEC(ioapic_intr97),
 170         IDTVEC(ioapic_intr98),
 171         IDTVEC(ioapic_intr99),
 172         IDTVEC(ioapic_intr100),
 173         IDTVEC(ioapic_intr101),
 174         IDTVEC(ioapic_intr102),
 175         IDTVEC(ioapic_intr103),
 176         IDTVEC(ioapic_intr104),
 177         IDTVEC(ioapic_intr105),
 178         IDTVEC(ioapic_intr106),
 179         IDTVEC(ioapic_intr107),
 180         IDTVEC(ioapic_intr108),
 181         IDTVEC(ioapic_intr109),
 182         IDTVEC(ioapic_intr110),
 183         IDTVEC(ioapic_intr111),
 184         IDTVEC(ioapic_intr112),
 185         IDTVEC(ioapic_intr113),
 186         IDTVEC(ioapic_intr114),
 187         IDTVEC(ioapic_intr115),
 188         IDTVEC(ioapic_intr116),
 189         IDTVEC(ioapic_intr117),
 190         IDTVEC(ioapic_intr118),
 191         IDTVEC(ioapic_intr119),
 192         IDTVEC(ioapic_intr120),
 193         IDTVEC(ioapic_intr121),
 194         IDTVEC(ioapic_intr122),
 195         IDTVEC(ioapic_intr123),
 196         IDTVEC(ioapic_intr124),
 197         IDTVEC(ioapic_intr125),
 198         IDTVEC(ioapic_intr126),
 199         IDTVEC(ioapic_intr127),
 200         IDTVEC(ioapic_intr128),
 201         IDTVEC(ioapic_intr129),
 202         IDTVEC(ioapic_intr130),
 203         IDTVEC(ioapic_intr131),
 204         IDTVEC(ioapic_intr132),
 205         IDTVEC(ioapic_intr133),
 206         IDTVEC(ioapic_intr134),
 207         IDTVEC(ioapic_intr135),
 208         IDTVEC(ioapic_intr136),
 209         IDTVEC(ioapic_intr137),
 210         IDTVEC(ioapic_intr138),
 211         IDTVEC(ioapic_intr139),
 212         IDTVEC(ioapic_intr140),
 213         IDTVEC(ioapic_intr141),
 214         IDTVEC(ioapic_intr142),
 215         IDTVEC(ioapic_intr143),
 216         IDTVEC(ioapic_intr144),
 217         IDTVEC(ioapic_intr145),
 218         IDTVEC(ioapic_intr146),
 219         IDTVEC(ioapic_intr147),
 220         IDTVEC(ioapic_intr148),
 221         IDTVEC(ioapic_intr149),
 222         IDTVEC(ioapic_intr150),
 223         IDTVEC(ioapic_intr151),
 224         IDTVEC(ioapic_intr152),
 225         IDTVEC(ioapic_intr153),
 226         IDTVEC(ioapic_intr154),
 227         IDTVEC(ioapic_intr155),
 228         IDTVEC(ioapic_intr156),
 229         IDTVEC(ioapic_intr157),
 230         IDTVEC(ioapic_intr158),
 231         IDTVEC(ioapic_intr159),
 232         IDTVEC(ioapic_intr160),
 233         IDTVEC(ioapic_intr161),
 234         IDTVEC(ioapic_intr162),
 235         IDTVEC(ioapic_intr163),
 236         IDTVEC(ioapic_intr164),
 237         IDTVEC(ioapic_intr165),
 238         IDTVEC(ioapic_intr166),
 239         IDTVEC(ioapic_intr167),
 240         IDTVEC(ioapic_intr168),
 241         IDTVEC(ioapic_intr169),
 242         IDTVEC(ioapic_intr170),
 243         IDTVEC(ioapic_intr171),
 244         IDTVEC(ioapic_intr172),
 245         IDTVEC(ioapic_intr173),
 246         IDTVEC(ioapic_intr174),
 247         IDTVEC(ioapic_intr175),
 248         IDTVEC(ioapic_intr176),
 249         IDTVEC(ioapic_intr177),
 250         IDTVEC(ioapic_intr178),
 251         IDTVEC(ioapic_intr179),
 252         IDTVEC(ioapic_intr180),
 253         IDTVEC(ioapic_intr181),
 254         IDTVEC(ioapic_intr182),
 255         IDTVEC(ioapic_intr183),
 256         IDTVEC(ioapic_intr184),
 257         IDTVEC(ioapic_intr185),
 258         IDTVEC(ioapic_intr186),
 259         IDTVEC(ioapic_intr187),
 260         IDTVEC(ioapic_intr188),
 261         IDTVEC(ioapic_intr189),
 262         IDTVEC(ioapic_intr190),
 263         IDTVEC(ioapic_intr191);
 264
 265 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
 266         &IDTVEC(ioapic_intr0),
 267         &IDTVEC(ioapic_intr1),
 268         &IDTVEC(ioapic_intr2),
 269         &IDTVEC(ioapic_intr3),
 270         &IDTVEC(ioapic_intr4),
 271         &IDTVEC(ioapic_intr5),
 272         &IDTVEC(ioapic_intr6),
 273         &IDTVEC(ioapic_intr7),
 274         &IDTVEC(ioapic_intr8),
 275         &IDTVEC(ioapic_intr9),
 276         &IDTVEC(ioapic_intr10),
 277         &IDTVEC(ioapic_intr11),
 278         &IDTVEC(ioapic_intr12),
 279         &IDTVEC(ioapic_intr13),
 280         &IDTVEC(ioapic_intr14),
 281         &IDTVEC(ioapic_intr15),
 282         &IDTVEC(ioapic_intr16),
 283         &IDTVEC(ioapic_intr17),
 284         &IDTVEC(ioapic_intr18),
 285         &IDTVEC(ioapic_intr19),
 286         &IDTVEC(ioapic_intr20),
 287         &IDTVEC(ioapic_intr21),
 288         &IDTVEC(ioapic_intr22),
 289         &IDTVEC(ioapic_intr23),
 290         &IDTVEC(ioapic_intr24),
 291         &IDTVEC(ioapic_intr25),
 292         &IDTVEC(ioapic_intr26),
 293         &IDTVEC(ioapic_intr27),
 294         &IDTVEC(ioapic_intr28),
 295         &IDTVEC(ioapic_intr29),
 296         &IDTVEC(ioapic_intr30),
 297         &IDTVEC(ioapic_intr31),
 298         &IDTVEC(ioapic_intr32),
 299         &IDTVEC(ioapic_intr33),
 300         &IDTVEC(ioapic_intr34),
 301         &IDTVEC(ioapic_intr35),
 302         &IDTVEC(ioapic_intr36),
 303         &IDTVEC(ioapic_intr37),
 304         &IDTVEC(ioapic_intr38),
 305         &IDTVEC(ioapic_intr39),
 306         &IDTVEC(ioapic_intr40),
 307         &IDTVEC(ioapic_intr41),
 308         &IDTVEC(ioapic_intr42),
 309         &IDTVEC(ioapic_intr43),
 310         &IDTVEC(ioapic_intr44),
 311         &IDTVEC(ioapic_intr45),
 312         &IDTVEC(ioapic_intr46),
 313         &IDTVEC(ioapic_intr47),
 314         &IDTVEC(ioapic_intr48),
 315         &IDTVEC(ioapic_intr49),
 316         &IDTVEC(ioapic_intr50),
 317         &IDTVEC(ioapic_intr51),
 318         &IDTVEC(ioapic_intr52),
 319         &IDTVEC(ioapic_intr53),
 320         &IDTVEC(ioapic_intr54),
 321         &IDTVEC(ioapic_intr55),
 322         &IDTVEC(ioapic_intr56),
 323         &IDTVEC(ioapic_intr57),
 324         &IDTVEC(ioapic_intr58),
 325         &IDTVEC(ioapic_intr59),
 326         &IDTVEC(ioapic_intr60),
 327         &IDTVEC(ioapic_intr61),
 328         &IDTVEC(ioapic_intr62),
 329         &IDTVEC(ioapic_intr63),
 330         &IDTVEC(ioapic_intr64),
 331         &IDTVEC(ioapic_intr65),
 332         &IDTVEC(ioapic_intr66),
 333         &IDTVEC(ioapic_intr67),
 334         &IDTVEC(ioapic_intr68),
 335         &IDTVEC(ioapic_intr69),
 336         &IDTVEC(ioapic_intr70),
 337         &IDTVEC(ioapic_intr71),
 338         &IDTVEC(ioapic_intr72),
 339         &IDTVEC(ioapic_intr73),
 340         &IDTVEC(ioapic_intr74),
 341         &IDTVEC(ioapic_intr75),
 342         &IDTVEC(ioapic_intr76),
 343         &IDTVEC(ioapic_intr77),
 344         &IDTVEC(ioapic_intr78),
 345         &IDTVEC(ioapic_intr79),
 346         &IDTVEC(ioapic_intr80),
 347         &IDTVEC(ioapic_intr81),
 348         &IDTVEC(ioapic_intr82),
 349         &IDTVEC(ioapic_intr83),
 350         &IDTVEC(ioapic_intr84),
 351         &IDTVEC(ioapic_intr85),
 352         &IDTVEC(ioapic_intr86),
 353         &IDTVEC(ioapic_intr87),
 354         &IDTVEC(ioapic_intr88),
 355         &IDTVEC(ioapic_intr89),
 356         &IDTVEC(ioapic_intr90),
 357         &IDTVEC(ioapic_intr91),
 358         &IDTVEC(ioapic_intr92),
 359         &IDTVEC(ioapic_intr93),
 360         &IDTVEC(ioapic_intr94),
 361         &IDTVEC(ioapic_intr95),
 362         &IDTVEC(ioapic_intr96),
 363         &IDTVEC(ioapic_intr97),
 364         &IDTVEC(ioapic_intr98),
 365         &IDTVEC(ioapic_intr99),
 366         &IDTVEC(ioapic_intr100),
 367         &IDTVEC(ioapic_intr101),
 368         &IDTVEC(ioapic_intr102),
 369         &IDTVEC(ioapic_intr103),
 370         &IDTVEC(ioapic_intr104),
 371         &IDTVEC(ioapic_intr105),
 372         &IDTVEC(ioapic_intr106),
 373         &IDTVEC(ioapic_intr107),
 374         &IDTVEC(ioapic_intr108),
 375         &IDTVEC(ioapic_intr109),
 376         &IDTVEC(ioapic_intr110),
 377         &IDTVEC(ioapic_intr111),
 378         &IDTVEC(ioapic_intr112),
 379         &IDTVEC(ioapic_intr113),
 380         &IDTVEC(ioapic_intr114),
 381         &IDTVEC(ioapic_intr115),
 382         &IDTVEC(ioapic_intr116),
 383         &IDTVEC(ioapic_intr117),
 384         &IDTVEC(ioapic_intr118),
 385         &IDTVEC(ioapic_intr119),
 386         &IDTVEC(ioapic_intr120),
 387         &IDTVEC(ioapic_intr121),
 388         &IDTVEC(ioapic_intr122),
 389         &IDTVEC(ioapic_intr123),
 390         &IDTVEC(ioapic_intr124),
 391         &IDTVEC(ioapic_intr125),
 392         &IDTVEC(ioapic_intr126),
 393         &IDTVEC(ioapic_intr127),
 394         &IDTVEC(ioapic_intr128),
 395         &IDTVEC(ioapic_intr129),
 396         &IDTVEC(ioapic_intr130),
 397         &IDTVEC(ioapic_intr131),
 398         &IDTVEC(ioapic_intr132),
 399         &IDTVEC(ioapic_intr133),
 400         &IDTVEC(ioapic_intr134),
 401         &IDTVEC(ioapic_intr135),
 402         &IDTVEC(ioapic_intr136),
 403         &IDTVEC(ioapic_intr137),
 404         &IDTVEC(ioapic_intr138),
 405         &IDTVEC(ioapic_intr139),
 406         &IDTVEC(ioapic_intr140),
 407         &IDTVEC(ioapic_intr141),
 408         &IDTVEC(ioapic_intr142),
 409         &IDTVEC(ioapic_intr143),
 410         &IDTVEC(ioapic_intr144),
 411         &IDTVEC(ioapic_intr145),
 412         &IDTVEC(ioapic_intr146),
 413         &IDTVEC(ioapic_intr147),
 414         &IDTVEC(ioapic_intr148),
 415         &IDTVEC(ioapic_intr149),
 416         &IDTVEC(ioapic_intr150),
 417         &IDTVEC(ioapic_intr151),
 418         &IDTVEC(ioapic_intr152),
 419         &IDTVEC(ioapic_intr153),
 420         &IDTVEC(ioapic_intr154),
 421         &IDTVEC(ioapic_intr155),
 422         &IDTVEC(ioapic_intr156),
 423         &IDTVEC(ioapic_intr157),
 424         &IDTVEC(ioapic_intr158),
 425         &IDTVEC(ioapic_intr159),
 426         &IDTVEC(ioapic_intr160),
 427         &IDTVEC(ioapic_intr161),
 428         &IDTVEC(ioapic_intr162),
 429         &IDTVEC(ioapic_intr163),
 430         &IDTVEC(ioapic_intr164),
 431         &IDTVEC(ioapic_intr165),
 432         &IDTVEC(ioapic_intr166),
 433         &IDTVEC(ioapic_intr167),
 434         &IDTVEC(ioapic_intr168),
 435         &IDTVEC(ioapic_intr169),
 436         &IDTVEC(ioapic_intr170),
 437         &IDTVEC(ioapic_intr171),
 438         &IDTVEC(ioapic_intr172),
 439         &IDTVEC(ioapic_intr173),
 440         &IDTVEC(ioapic_intr174),
 441         &IDTVEC(ioapic_intr175),
 442         &IDTVEC(ioapic_intr176),
 443         &IDTVEC(ioapic_intr177),
 444         &IDTVEC(ioapic_intr178),
 445         &IDTVEC(ioapic_intr179),
 446         &IDTVEC(ioapic_intr180),
 447         &IDTVEC(ioapic_intr181),
 448         &IDTVEC(ioapic_intr182),
 449         &IDTVEC(ioapic_intr183),
 450         &IDTVEC(ioapic_intr184),
 451         &IDTVEC(ioapic_intr185),
 452         &IDTVEC(ioapic_intr186),
 453         &IDTVEC(ioapic_intr187),
 454         &IDTVEC(ioapic_intr188),
 455         &IDTVEC(ioapic_intr189),
 456         &IDTVEC(ioapic_intr190),
 457         &IDTVEC(ioapic_intr191)
 458 };
 459
 460 #define IOAPIC_HWI_SYSCALL      (IDT_OFFSET_SYSCALL - IDT_OFFSET)
 461
 462 static struct ioapic_irqmap {
 463         int                     im_type;        /* IOAPIC_IMT_ */
 464         enum intr_trigger       im_trig;
 465         enum intr_polarity      im_pola;
 466         int                     im_gsi;
 467         int                     im_msi_base;
 468         uint32_t                im_flags;       /* IOAPIC_IMF_ */
 469 } ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS];
 470
 471 static struct lwkt_token ioapic_irqmap_tok =
 472         LWKT_TOKEN_INITIALIZER(ioapic_irqmap_token);
 473
 474 #define IOAPIC_IMT_UNUSED       0
 475 #define IOAPIC_IMT_RESERVED     1
 476 #define IOAPIC_IMT_LEGACY       2
 477 #define IOAPIC_IMT_SYSCALL      3
 478 #define IOAPIC_IMT_SHADOW       4
 479 #define IOAPIC_IMT_MSI          5
 480
 481 #define IOAPIC_IMT_ISHWI(map)   ((map)->im_type != IOAPIC_IMT_RESERVED && \
 482                                  (map)->im_type != IOAPIC_IMT_SYSCALL && \
 483                                  (map)->im_type != IOAPIC_IMT_SHADOW)
 484
 485 #define IOAPIC_IMF_CONF         0x1
 486
 487 extern void     IOAPIC_INTREN(int);
 488 extern void     IOAPIC_INTRDIS(int);
 489
 490 extern int      imcr_present;
 491
 492 static void     ioapic_abi_intr_enable(int);
 493 static void     ioapic_abi_intr_disable(int);
 494 static void     ioapic_abi_intr_setup(int, int);
 495 static void     ioapic_abi_intr_teardown(int);
 496 static void     ioapic_abi_intr_config(int,
 497                     enum intr_trigger, enum intr_polarity);
 498 static int      ioapic_abi_intr_cpuid(int);
 499
 500 static int      ioapic_abi_msi_alloc(int [], int, int);
 501 static void     ioapic_abi_msi_release(const int [], int, int);
 502 static void     ioapic_abi_msi_map(int, uint64_t *, uint32_t *, int);
 503
 504 static void     ioapic_abi_finalize(void);
 505 static void     ioapic_abi_cleanup(void);
 506 static void     ioapic_abi_setdefault(void);
 507 static void     ioapic_abi_stabilize(void);
 508 static void     ioapic_abi_initmap(void);
 509 static void     ioapic_abi_rman_setup(struct rman *);
 510
 511 static int      ioapic_abi_gsi_cpuid(int, int);
 512
 513 struct machintr_abi MachIntrABI_IOAPIC = {
 514         MACHINTR_IOAPIC,
 515
 516         .intr_disable   = ioapic_abi_intr_disable,
 517         .intr_enable    = ioapic_abi_intr_enable,
 518         .intr_setup     = ioapic_abi_intr_setup,
 519         .intr_teardown  = ioapic_abi_intr_teardown,
 520         .intr_config    = ioapic_abi_intr_config,
 521         .intr_cpuid     = ioapic_abi_intr_cpuid,
 522
 523         .msi_alloc      = ioapic_abi_msi_alloc,
 524         .msi_release    = ioapic_abi_msi_release,
 525         .msi_map        = ioapic_abi_msi_map,
 526
 527         .finalize       = ioapic_abi_finalize,
 528         .cleanup        = ioapic_abi_cleanup,
 529         .setdefault     = ioapic_abi_setdefault,
 530         .stabilize      = ioapic_abi_stabilize,
 531         .initmap        = ioapic_abi_initmap,
 532         .rman_setup     = ioapic_abi_rman_setup
 533 };
 534
 535 static int      ioapic_abi_extint_irq = -1;
 536 static int      ioapic_abi_legacy_irq_max;
 537 static int      ioapic_abi_gsi_balance;
 538 static int      ioapic_abi_msi_start;   /* NOTE: for testing only */
 539
 540 struct ioapic_irqinfo   ioapic_irqs[IOAPIC_HWI_VECTORS];
 541
 542 static void
 543 ioapic_abi_intr_enable(int irq)
 544 {
 545         const struct ioapic_irqmap *map;
 546
 547         KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
 548             ("ioapic enable, invalid irq %d\n", irq));
 549
 550         map = &ioapic_irqmaps[mycpuid][irq];
 551         KASSERT(IOAPIC_IMT_ISHWI(map),
 552             ("ioapic enable, not hwi irq %d, type %d, cpu%d\n",
 553              irq, map->im_type, mycpuid));
 554         if (map->im_type != IOAPIC_IMT_LEGACY)
 555                 return;
 556
 557         IOAPIC_INTREN(irq);
 558 }
 559
 560 static void
 561 ioapic_abi_intr_disable(int irq)
 562 {
 563         const struct ioapic_irqmap *map;
 564
 565         KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
 566             ("ioapic disable, invalid irq %d\n", irq));
 567
 568         map = &ioapic_irqmaps[mycpuid][irq];
 569         KASSERT(IOAPIC_IMT_ISHWI(map),
 570             ("ioapic disable, not hwi irq %d, type %d, cpu%d\n",
 571              irq, map->im_type, mycpuid));
 572         if (map->im_type != IOAPIC_IMT_LEGACY)
 573                 return;
 574
 575         IOAPIC_INTRDIS(irq);
 576 }
 577
 578 static void
 579 ioapic_abi_finalize(void)
 580 {
 581         KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
 582         KKASSERT(ioapic_enable);
 583
 584         /*
 585          * If an IMCR is present, program bit 0 to disconnect the 8259
 586          * from the BSP.
 587          */
 588         if (imcr_present) {
 589                 outb(0x22, 0x70);       /* select IMCR */
 590                 outb(0x23, 0x01);       /* disconnect 8259 */
 591         }
 592 }
 593
 594 /*
 595  * This routine is called after physical interrupts are enabled but before
 596  * the critical section is released.  We need to clean out any interrupts
 597  * that had already been posted to the cpu.
 598  */
 599 static void
 600 ioapic_abi_cleanup(void)
 601 {
 602         bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
 603 }
 604
 605 /* Must never be called */
 606 static void
 607 ioapic_abi_stabilize(void)
 608 {
 609         panic("ioapic_stabilize() is called\n");
 610 }
 611
 612 static void
 613 ioapic_abi_intr_setup(int intr, int flags)
 614 {
 615         const struct ioapic_irqmap *map;
 616         int vector, select;
 617         uint32_t value;
 618         u_long ef;
 619
 620         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
 621             ("ioapic setup, invalid irq %d\n", intr));
 622
 623         map = &ioapic_irqmaps[mycpuid][intr];
 624         KASSERT(IOAPIC_IMT_ISHWI(map),
 625             ("ioapic setup, not hwi irq %d, type %d, cpu%d",
 626              intr, map->im_type, mycpuid));
 627         if (map->im_type != IOAPIC_IMT_LEGACY)
 628                 return;
 629
 630         KASSERT(ioapic_irqs[intr].io_addr != NULL,
 631             ("ioapic setup, no GSI information, irq %d\n", intr));
 632
 633         ef = read_eflags();
 634         cpu_disable_intr();
 635
 636         vector = IDT_OFFSET + intr;
 637
 638         /*
 639          * Now reprogram the vector in the IO APIC.  In order to avoid
 640          * losing an EOI for a level interrupt, which is vector based,
 641          * make sure that the IO APIC is programmed for edge-triggering
 642          * first, then reprogrammed with the new vector.  This should
 643          * clear the IRR bit.
 644          */
 645         imen_lock();
 646
 647         select = ioapic_irqs[intr].io_idx;
 648         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
 649         value |= IOART_INTMSET;
 650
 651         ioapic_write(ioapic_irqs[intr].io_addr, select,
 652             (value & ~APIC_TRIGMOD_MASK));
 653         ioapic_write(ioapic_irqs[intr].io_addr, select,
 654             (value & ~IOART_INTVEC) | vector);
 655
 656         imen_unlock();
 657
 658         IOAPIC_INTREN(intr);
 659
 660         write_eflags(ef);
 661 }
 662
 663 static void
 664 ioapic_abi_intr_teardown(int intr)
 665 {
 666         const struct ioapic_irqmap *map;
 667         int vector, select;
 668         uint32_t value;
 669         u_long ef;
 670
 671         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
 672             ("ioapic teardown, invalid irq %d\n", intr));
 673
 674         map = &ioapic_irqmaps[mycpuid][intr];
 675         KASSERT(IOAPIC_IMT_ISHWI(map),
 676             ("ioapic teardown, not hwi irq %d, type %d, cpu%d",
 677              intr, map->im_type, mycpuid));
 678         if (map->im_type != IOAPIC_IMT_LEGACY)
 679                 return;
 680
 681         KASSERT(ioapic_irqs[intr].io_addr != NULL,
 682             ("ioapic teardown, no GSI information, irq %d\n", intr));
 683
 684         ef = read_eflags();
 685         cpu_disable_intr();
 686
 687         /*
 688          * Teardown an interrupt vector.  The vector should already be
 689          * installed in the cpu's IDT, but make sure.
 690          */
 691         IOAPIC_INTRDIS(intr);
 692
 693         vector = IDT_OFFSET + intr;
 694
 695         /*
 696          * In order to avoid losing an EOI for a level interrupt, which
 697          * is vector based, make sure that the IO APIC is programmed for
 698          * edge-triggering first, then reprogrammed with the new vector.
 699          * This should clear the IRR bit.
 700          */
 701         imen_lock();
 702
 703         select = ioapic_irqs[intr].io_idx;
 704         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
 705
 706         ioapic_write(ioapic_irqs[intr].io_addr, select,
 707             (value & ~APIC_TRIGMOD_MASK));
 708         ioapic_write(ioapic_irqs[intr].io_addr, select,
 709             (value & ~IOART_INTVEC) | vector);
 710
 711         imen_unlock();
 712
 713         write_eflags(ef);
 714 }
 715
 716 static void
 717 ioapic_abi_setdefault(void)
 718 {
 719         int intr;
 720
 721         for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
 722                 if (intr == IOAPIC_HWI_SYSCALL)
 723                         continue;
 724                 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT,
 725                        SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 726         }
 727 }
 728
 729 static void
 730 ioapic_abi_initmap(void)
 731 {
 732         int cpu;
 733
 734         kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance);
 735
 736         kgetenv_int("hw.ioapic.msi_start", &ioapic_abi_msi_start);
 737         ioapic_abi_msi_start &= ~0x1f;  /* MUST be 32 aligned */
 738
 739         /*
 740          * NOTE: ncpus is not ready yet
 741          */
 742         for (cpu = 0; cpu < MAXCPU; ++cpu) {
 743                 int i;
 744
 745                 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
 746                         ioapic_irqmaps[cpu][i].im_gsi = -1;
 747                         ioapic_irqmaps[cpu][i].im_msi_base = -1;
 748                 }
 749                 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type =
 750                     IOAPIC_IMT_SYSCALL;
 751         }
 752 }
 753
 754 void
 755 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
 756     enum intr_polarity pola)
 757 {
 758         struct ioapic_irqinfo *info;
 759         struct ioapic_irqmap *map;
 760         void *ioaddr;
 761         int pin, cpuid;
 762
 763         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 764         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 765
 766         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
 767         if (irq > ioapic_abi_legacy_irq_max)
 768                 ioapic_abi_legacy_irq_max = irq;
 769
 770         cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
 771
 772         map = &ioapic_irqmaps[cpuid][irq];
 773
 774         KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
 775         map->im_type = IOAPIC_IMT_LEGACY;
 776
 777         map->im_gsi = gsi;
 778         map->im_trig = trig;
 779         map->im_pola = pola;
 780
 781         if (bootverbose) {
 782                 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
 783                         irq, map->im_gsi,
 784                         intr_str_trigger(map->im_trig),
 785                         intr_str_polarity(map->im_pola));
 786         }
 787
 788         pin = ioapic_gsi_pin(map->im_gsi);
 789         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 790
 791         info = &ioapic_irqs[irq];
 792
 793         imen_lock();
 794
 795         info->io_addr = ioaddr;
 796         info->io_idx = IOAPIC_REDTBL + (2 * pin);
 797         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
 798         if (map->im_trig == INTR_TRIGGER_LEVEL)
 799                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
 800
 801         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
 802             map->im_trig, map->im_pola, cpuid);
 803
 804         imen_unlock();
 805 }
 806
 807 void
 808 ioapic_abi_fixup_irqmap(void)
 809 {
 810         int cpu;
 811
 812         ioapic_abi_legacy_irq_max += 1;
 813         if (bootverbose) {
 814                 kprintf("IOAPIC: legacy irq max %d\n",
 815                     ioapic_abi_legacy_irq_max);
 816         }
 817
 818         for (cpu = 0; cpu < ncpus; ++cpu) {
 819                 int i;
 820
 821                 for (i = 0; i < ioapic_abi_legacy_irq_max; ++i) {
 822                         struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i];
 823
 824                         if (map->im_type == IOAPIC_IMT_UNUSED) {
 825                                 map->im_type = IOAPIC_IMT_RESERVED;
 826                                 if (bootverbose) {
 827                                         kprintf("IOAPIC: "
 828                                             "cpu%d irq %d reserved\n", cpu, i);
 829                                 }
 830                         }
 831                 }
 832         }
 833 }
 834
 835 int
 836 ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
 837 {
 838         int cpu;
 839
 840         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 841         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 842
 843         for (cpu = 0; cpu < ncpus; ++cpu) {
 844                 int irq;
 845
 846                 for (irq = 0; irq < ioapic_abi_legacy_irq_max; ++irq) {
 847                         const struct ioapic_irqmap *map =
 848                             &ioapic_irqmaps[cpu][irq];
 849
 850                         if (map->im_gsi == gsi) {
 851                                 KKASSERT(map->im_type == IOAPIC_IMT_LEGACY);
 852
 853                                 if (map->im_flags & IOAPIC_IMF_CONF) {
 854                                         if (map->im_trig != trig ||
 855                                             map->im_pola != pola)
 856                                                 return -1;
 857                                 }
 858                                 return irq;
 859                         }
 860                 }
 861         }
 862         return -1;
 863 }
 864
 865 int
 866 ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
 867 {
 868         int cpu;
 869
 870         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 871         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 872
 873         if (irq < 0 || irq >= ioapic_abi_legacy_irq_max)
 874                 return -1;
 875
 876         for (cpu = 0; cpu < ncpus; ++cpu) {
 877                 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq];
 878
 879                 if (map->im_type == IOAPIC_IMT_LEGACY) {
 880                         if (map->im_flags & IOAPIC_IMF_CONF) {
 881                                 if (map->im_trig != trig ||
 882                                     map->im_pola != pola)
 883                                         return -1;
 884                         }
 885                         return irq;
 886                 }
 887         }
 888         return -1;
 889 }
 890
 891 static void
 892 ioapic_abi_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
 893 {
 894         struct ioapic_irqinfo *info;
 895         struct ioapic_irqmap *map = NULL;
 896         void *ioaddr;
 897         int pin, cpuid;
 898
 899         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 900         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 901
 902         KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
 903         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
 904                 map = &ioapic_irqmaps[cpuid][irq];
 905                 if (map->im_type == IOAPIC_IMT_LEGACY)
 906                         break;
 907         }
 908         KKASSERT(cpuid < ncpus);
 909
 910 #ifdef notyet
 911         if (map->im_flags & IOAPIC_IMF_CONF) {
 912                 if (trig != map->im_trig) {
 913                         panic("ioapic_intr_config: trig %s -> %s\n",
 914                               intr_str_trigger(map->im_trig),
 915                               intr_str_trigger(trig));
 916                 }
 917                 if (pola != map->im_pola) {
 918                         panic("ioapic_intr_config: pola %s -> %s\n",
 919                               intr_str_polarity(map->im_pola),
 920                               intr_str_polarity(pola));
 921                 }
 922                 return;
 923         }
 924 #endif
 925         map->im_flags |= IOAPIC_IMF_CONF;
 926
 927         if (trig == map->im_trig && pola == map->im_pola)
 928                 return;
 929
 930         if (bootverbose) {
 931                 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
 932                         irq, map->im_gsi,
 933                         intr_str_trigger(map->im_trig),
 934                         intr_str_polarity(map->im_pola),
 935                         intr_str_trigger(trig),
 936                         intr_str_polarity(pola));
 937         }
 938         map->im_trig = trig;
 939         map->im_pola = pola;
 940
 941         pin = ioapic_gsi_pin(map->im_gsi);
 942         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 943
 944         info = &ioapic_irqs[irq];
 945
 946         imen_lock();
 947
 948         info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
 949         if (map->im_trig == INTR_TRIGGER_LEVEL)
 950                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
 951
 952         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
 953             map->im_trig, map->im_pola, cpuid);
 954
 955         imen_unlock();
 956 }
 957
 958 int
 959 ioapic_abi_extint_irqmap(int irq)
 960 {
 961         struct ioapic_irqinfo *info;
 962         struct ioapic_irqmap *map;
 963         void *ioaddr;
 964         int pin, error, vec;
 965
 966         /* XXX only irq0 is allowed */
 967         KKASSERT(irq == 0);
 968
 969         vec = IDT_OFFSET + irq;
 970
 971         if (ioapic_abi_extint_irq == irq)
 972                 return 0;
 973         else if (ioapic_abi_extint_irq >= 0)
 974                 return EEXIST;
 975
 976         error = icu_ioapic_extint(irq, vec);
 977         if (error)
 978                 return error;
 979
 980         /* ExtINT is always targeted to cpu0 */
 981         map = &ioapic_irqmaps[0][irq];
 982
 983         KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
 984                  map->im_type == IOAPIC_IMT_LEGACY);
 985         if (map->im_type == IOAPIC_IMT_LEGACY) {
 986                 if (map->im_flags & IOAPIC_IMF_CONF)
 987                         return EEXIST;
 988         }
 989         ioapic_abi_extint_irq = irq;
 990
 991         map->im_type = IOAPIC_IMT_LEGACY;
 992         map->im_trig = INTR_TRIGGER_EDGE;
 993         map->im_pola = INTR_POLARITY_HIGH;
 994         map->im_flags = IOAPIC_IMF_CONF;
 995
 996         map->im_gsi = ioapic_extpin_gsi();
 997         KKASSERT(map->im_gsi >= 0);
 998
 999         if (bootverbose) {
1000                 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
1001                         irq, map->im_gsi,
1002                         intr_str_trigger(map->im_trig),
1003                         intr_str_polarity(map->im_pola));
1004         }
1005
1006         pin = ioapic_gsi_pin(map->im_gsi);
1007         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
1008
1009         info = &ioapic_irqs[irq];
1010
1011         imen_lock();
1012
1013         info->io_addr = ioaddr;
1014         info->io_idx = IOAPIC_REDTBL + (2 * pin);
1015         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
1016
1017         ioapic_extpin_setup(ioaddr, pin, vec);
1018
1019         imen_unlock();
1020
1021         return 0;
1022 }
1023
1024 static int
1025 ioapic_abi_intr_cpuid(int irq)
1026 {
1027         const struct ioapic_irqmap *map = NULL;
1028         int cpuid;
1029
1030         KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
1031
1032         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1033                 map = &ioapic_irqmaps[cpuid][irq];
1034                 if (map->im_type == IOAPIC_IMT_LEGACY)
1035                         return cpuid;
1036         }
1037
1038         /* XXX some drivers tries to peek at reserved IRQs */
1039         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1040                 map = &ioapic_irqmaps[cpuid][irq];
1041                 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED);
1042         }
1043         return 0;
1044 }
1045
1046 static int
1047 ioapic_abi_gsi_cpuid(int irq, int gsi)
1048 {
1049         char envpath[32];
1050         int cpuid = -1;
1051
1052         KKASSERT(gsi >= 0);
1053
1054         if (irq == 0 || gsi == 0) {
1055                 if (bootverbose) {
1056                         kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
1057                             irq, gsi);
1058                 }
1059                 return 0;
1060         }
1061
1062         if (irq == acpi_sci_irqno()) {
1063                 if (bootverbose) {
1064                         kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
1065                             irq, gsi);
1066                 }
1067                 return 0;
1068         }
1069
1070         ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
1071         kgetenv_int(envpath, &cpuid);
1072
1073         if (cpuid < 0) {
1074                 if (!ioapic_abi_gsi_balance) {
1075                         if (bootverbose) {
1076                                 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 "
1077                                     "(fixed)\n", irq, gsi);
1078                         }
1079                         return 0;
1080                 }
1081
1082                 cpuid = gsi % ncpus;
1083                 if (bootverbose) {
1084                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
1085                             irq, gsi, cpuid);
1086                 }
1087         } else if (cpuid >= ncpus) {
1088                 cpuid = ncpus - 1;
1089                 if (bootverbose) {
1090                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
1091                             irq, gsi, cpuid);
1092                 }
1093         } else {
1094                 if (bootverbose) {
1095                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
1096                             irq, gsi, cpuid);
1097                 }
1098         }
1099         return cpuid;
1100 }
1101
1102 static void
1103 ioapic_abi_rman_setup(struct rman *rm)
1104 {
1105         int start, end, i;
1106
1107         KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
1108             ("invalid rman cpuid %d", rm->rm_cpuid));
1109
1110         start = end = -1;
1111         for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
1112                 const struct ioapic_irqmap *map =
1113                     &ioapic_irqmaps[rm->rm_cpuid][i];
1114
1115                 if (start < 0) {
1116                         if (IOAPIC_IMT_ISHWI(map))
1117                                 start = end = i;
1118                 } else {
1119                         if (IOAPIC_IMT_ISHWI(map)) {
1120                                 end = i;
1121                         } else {
1122                                 KKASSERT(end >= 0);
1123                                 if (bootverbose) {
1124                                         kprintf("IOAPIC: rman cpu%d %d - %d\n",
1125                                             rm->rm_cpuid, start, end);
1126                                 }
1127                                 if (rman_manage_region(rm, start, end)) {
1128                                         panic("rman_manage_region"
1129                                             "(cpu%d %d - %d)", rm->rm_cpuid,
1130                                             start, end);
1131                                 }
1132                                 start = end = -1;
1133                         }
1134                 }
1135         }
1136         if (start >= 0) {
1137                 KKASSERT(end >= 0);
1138                 if (bootverbose) {
1139                         kprintf("IOAPIC: rman cpu%d %d - %d\n",
1140                             rm->rm_cpuid, start, end);
1141                 }
1142                 if (rman_manage_region(rm, start, end)) {
1143                         panic("rman_manage_region(cpu%d %d - %d)",
1144                             rm->rm_cpuid, start, end);
1145                 }
1146         }
1147 }
1148
1149 static int
1150 ioapic_abi_msi_alloc(int intrs[], int count, int cpuid)
1151 {
1152         int i, error;
1153
1154         KASSERT(cpuid >= 0 && cpuid < ncpus,
1155             ("invalid cpuid %d", cpuid));
1156
1157         KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count));
1158         KASSERT((count & (count - 1)) == 0,
1159             ("count %d is not power of 2\n", count));
1160
1161         lwkt_gettoken(&ioapic_irqmap_tok);
1162
1163         /*
1164          * NOTE:
1165          * Since IDT_OFFSET is 32, which is the maximum valid 'count',
1166          * we do not need to find out the first properly aligned
1167          * interrupt vector.
1168          */
1169
1170         error = EMSGSIZE;
1171         for (i = ioapic_abi_msi_start; i < IOAPIC_HWI_VECTORS; i += count) {
1172                 int j;
1173
1174                 if (ioapic_irqmaps[cpuid][i].im_type != IOAPIC_IMT_UNUSED)
1175                         continue;
1176
1177                 for (j = 1; j < count; ++j) {
1178                         if (ioapic_irqmaps[cpuid][i + j].im_type !=
1179                             IOAPIC_IMT_UNUSED)
1180                                 break;
1181                 }
1182                 if (j != count)
1183                         continue;
1184
1185                 for (j = 0; j < count; ++j) {
1186                         int intr = i + j, cpu;
1187
1188                         for (cpu = 0; cpu < ncpus; ++cpu) {
1189                                 struct ioapic_irqmap *map;
1190
1191                                 map = &ioapic_irqmaps[cpu][intr];
1192                                 KASSERT(map->im_msi_base < 0,
1193                                     ("intr %d cpu%d, stale MSI-base %d\n",
1194                                      intr, cpu, map->im_msi_base));
1195                                 KASSERT(map->im_type == IOAPIC_IMT_UNUSED,
1196                                     ("intr %d cpu%d, already allocated\n",
1197                                      intr, cpu));
1198
1199                                 if (cpu == cpuid) {
1200                                         map->im_type = IOAPIC_IMT_MSI;
1201                                         map->im_msi_base = i;
1202                                 } else {
1203                                         map->im_type = IOAPIC_IMT_SHADOW;
1204                                 }
1205                         }
1206
1207                         intrs[j] = intr;
1208                         msi_setup(intr);
1209
1210                         if (bootverbose) {
1211                                 kprintf("alloc MSI intr %d on cpu%d\n",
1212                                     intr, cpuid);
1213                         }
1214                 }
1215                 error = 0;
1216                 break;
1217         }
1218
1219         lwkt_reltoken(&ioapic_irqmap_tok);
1220
1221         return error;
1222 }
1223
1224 static void
1225 ioapic_abi_msi_release(const int intrs[], int count, int cpuid)
1226 {
1227         int i, msi_base = -1, intr_next = -1, mask;
1228
1229         KASSERT(cpuid >= 0 && cpuid < ncpus,
1230             ("invalid cpuid %d", cpuid));
1231
1232         KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count));
1233
1234         mask = count - 1;
1235         KASSERT((count & mask) == 0, ("count %d is not power of 2\n", count));
1236
1237         lwkt_gettoken(&ioapic_irqmap_tok);
1238
1239         for (i = 0; i < count; ++i) {
1240                 int intr = intrs[i], cpu;
1241
1242                 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
1243                     ("invalid intr %d\n", intr));
1244
1245                 for (cpu = 0; cpu < ncpus; ++cpu) {
1246                         struct ioapic_irqmap *map;
1247
1248                         map = &ioapic_irqmaps[cpu][intr];
1249
1250                         if (cpu == cpuid) {
1251                                 KASSERT(map->im_type == IOAPIC_IMT_MSI,
1252                                     ("try release non-MSI intr %d cpu%d, "
1253                                      "type %d\n", intr, cpu, map->im_type));
1254                                 KASSERT(map->im_msi_base >= 0 &&
1255                                     map->im_msi_base <= intr,
1256                                     ("intr %d cpu%d, invalid MSI-base %d\n",
1257                                      intr, cpu, map->im_msi_base));
1258                                 KASSERT((map->im_msi_base & mask) == 0,
1259                                     ("intr %d cpu%d, MSI-base %d is "
1260                                      "not proper aligned %d\n",
1261                                      intr, cpu, map->im_msi_base, count));
1262
1263                                 if (msi_base < 0) {
1264                                         msi_base = map->im_msi_base;
1265                                 } else {
1266                                         KASSERT(map->im_msi_base == msi_base,
1267                                             ("intr %d cpu%d, "
1268                                              "inconsistent MSI-base, "
1269                                              "was %d, now %d\n",
1270                                              intr, cpu,
1271                                              msi_base, map->im_msi_base));
1272                                 }
1273                                 map->im_msi_base = -1;
1274                         } else {
1275                                 KASSERT(map->im_type == IOAPIC_IMT_SHADOW,
1276                                     ("try release non-MSIsh intr %d cpu%d, "
1277                                      "type %d\n", intr, cpu, map->im_type));
1278                                 KASSERT(map->im_msi_base < 0,
1279                                     ("intr %d cpu%d, invalid MSIsh-base %d\n",
1280                                      intr, cpu, map->im_msi_base));
1281                         }
1282                         map->im_type = IOAPIC_IMT_UNUSED;
1283                 }
1284
1285                 if (intr_next < intr)
1286                         intr_next = intr;
1287
1288                 if (bootverbose)
1289                         kprintf("release MSI intr %d on cpu%d\n", intr, cpuid);
1290         }
1291
1292         KKASSERT(intr_next > 0);
1293         KKASSERT(msi_base >= 0);
1294
1295         ++intr_next;
1296         if (intr_next < IOAPIC_HWI_VECTORS) {
1297                 int cpu;
1298
1299                 for (cpu = 0; cpu < ncpus; ++cpu) {
1300                         const struct ioapic_irqmap *map =
1301                             &ioapic_irqmaps[cpu][intr_next];
1302
1303                         if (map->im_type == IOAPIC_IMT_MSI) {
1304                                 KASSERT(map->im_msi_base != msi_base,
1305                                     ("more than %d MSI was allocated\n", count));
1306                         }
1307                 }
1308         }
1309
1310         lwkt_reltoken(&ioapic_irqmap_tok);
1311 }
1312
1313 static void
1314 ioapic_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid)
1315 {
1316         const struct ioapic_irqmap *map;
1317
1318         KASSERT(cpuid >= 0 && cpuid < ncpus,
1319             ("invalid cpuid %d", cpuid));
1320
1321         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
1322             ("invalid intr %d\n", intr));
1323
1324         lwkt_gettoken(&ioapic_irqmap_tok);
1325
1326         map = &ioapic_irqmaps[cpuid][intr];
1327         KASSERT(map->im_type == IOAPIC_IMT_MSI,
1328             ("try map non-MSI intr %d, type %d\n", intr, map->im_type));
1329         KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
1330             ("intr %d, invalid MSI-base %d\n", intr, map->im_msi_base));
1331
1332         msi_map(map->im_msi_base, addr, data, cpuid);
1333
1334         if (bootverbose)
1335                 kprintf("map MSI intr %d on cpu%d\n", intr, cpuid);
1336
1337         lwkt_reltoken(&ioapic_irqmap_tok);
1338 }