sys/dev/drm/radeon/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *
  30  * $FreeBSD: src/sys/dev/drm/radeon_cp.c,v 1.6.2.1 2003/04/26 07:05:29 anholt Exp $
  31  * $DragonFly: src/sys/dev/drm/radeon/Attic/radeon_cp.c,v 1.4 2003/08/07 21:16:55 dillon Exp $
  32  */
  33
  34 #include "radeon.h"
  35 #include "dev/drm/drmP.h"
  36 #include "dev/drm/drm.h"
  37 #include "radeon_drm.h"
  38 #include "radeon_drv.h"
  39
  40 #define RADEON_FIFO_DEBUG       0
  41
  42
  43 /* CP microcode (from ATI) */
  44 static u32 R200_cp_microcode[][2] = {
  45         { 0x21007000, 0000000000 },
  46         { 0x20007000, 0000000000 },
  47         { 0x000000ab, 0x00000004 },
  48         { 0x000000af, 0x00000004 },
  49         { 0x66544a49, 0000000000 },
  50         { 0x49494174, 0000000000 },
  51         { 0x54517d83, 0000000000 },
  52         { 0x498d8b64, 0000000000 },
  53         { 0x49494949, 0000000000 },
  54         { 0x49da493c, 0000000000 },
  55         { 0x49989898, 0000000000 },
  56         { 0xd34949d5, 0000000000 },
  57         { 0x9dc90e11, 0000000000 },
  58         { 0xce9b9b9b, 0000000000 },
  59         { 0x000f0000, 0x00000016 },
  60         { 0x352e232c, 0000000000 },
  61         { 0x00000013, 0x00000004 },
  62         { 0x000f0000, 0x00000016 },
  63         { 0x352e272c, 0000000000 },
  64         { 0x000f0001, 0x00000016 },
  65         { 0x3239362f, 0000000000 },
  66         { 0x000077ef, 0x00000002 },
  67         { 0x00061000, 0x00000002 },
  68         { 0x00000020, 0x0000001a },
  69         { 0x00004000, 0x0000001e },
  70         { 0x00061000, 0x00000002 },
  71         { 0x00000020, 0x0000001a },
  72         { 0x00004000, 0x0000001e },
  73         { 0x00061000, 0x00000002 },
  74         { 0x00000020, 0x0000001a },
  75         { 0x00004000, 0x0000001e },
  76         { 0x00000016, 0x00000004 },
  77         { 0x0003802a, 0x00000002 },
  78         { 0x040067e0, 0x00000002 },
  79         { 0x00000016, 0x00000004 },
  80         { 0x000077e0, 0x00000002 },
  81         { 0x00065000, 0x00000002 },
  82         { 0x000037e1, 0x00000002 },
  83         { 0x040067e1, 0x00000006 },
  84         { 0x000077e0, 0x00000002 },
  85         { 0x000077e1, 0x00000002 },
  86         { 0x000077e1, 0x00000006 },
  87         { 0xffffffff, 0000000000 },
  88         { 0x10000000, 0000000000 },
  89         { 0x0003802a, 0x00000002 },
  90         { 0x040067e0, 0x00000006 },
  91         { 0x00007675, 0x00000002 },
  92         { 0x00007676, 0x00000002 },
  93         { 0x00007677, 0x00000002 },
  94         { 0x00007678, 0x00000006 },
  95         { 0x0003802b, 0x00000002 },
  96         { 0x04002676, 0x00000002 },
  97         { 0x00007677, 0x00000002 },
  98         { 0x00007678, 0x00000006 },
  99         { 0x0000002e, 0x00000018 },
 100         { 0x0000002e, 0x00000018 },
 101         { 0000000000, 0x00000006 },
 102         { 0x0000002f, 0x00000018 },
 103         { 0x0000002f, 0x00000018 },
 104         { 0000000000, 0x00000006 },
 105         { 0x01605000, 0x00000002 },
 106         { 0x00065000, 0x00000002 },
 107         { 0x00098000, 0x00000002 },
 108         { 0x00061000, 0x00000002 },
 109         { 0x64c0603d, 0x00000004 },
 110         { 0x00080000, 0x00000016 },
 111         { 0000000000, 0000000000 },
 112         { 0x0400251d, 0x00000002 },
 113         { 0x00007580, 0x00000002 },
 114         { 0x00067581, 0x00000002 },
 115         { 0x04002580, 0x00000002 },
 116         { 0x00067581, 0x00000002 },
 117         { 0x00000046, 0x00000004 },
 118         { 0x00005000, 0000000000 },
 119         { 0x00061000, 0x00000002 },
 120         { 0x0000750e, 0x00000002 },
 121         { 0x00019000, 0x00000002 },
 122         { 0x00011055, 0x00000014 },
 123         { 0x00000055, 0x00000012 },
 124         { 0x0400250f, 0x00000002 },
 125         { 0x0000504a, 0x00000004 },
 126         { 0x00007565, 0x00000002 },
 127         { 0x00007566, 0x00000002 },
 128         { 0x00000051, 0x00000004 },
 129         { 0x01e655b4, 0x00000002 },
 130         { 0x4401b0dc, 0x00000002 },
 131         { 0x01c110dc, 0x00000002 },
 132         { 0x2666705d, 0x00000018 },
 133         { 0x040c2565, 0x00000002 },
 134         { 0x0000005d, 0x00000018 },
 135         { 0x04002564, 0x00000002 },
 136         { 0x00007566, 0x00000002 },
 137         { 0x00000054, 0x00000004 },
 138         { 0x00401060, 0x00000008 },
 139         { 0x00101000, 0x00000002 },
 140         { 0x000d80ff, 0x00000002 },
 141         { 0x00800063, 0x00000008 },
 142         { 0x000f9000, 0x00000002 },
 143         { 0x000e00ff, 0x00000002 },
 144         { 0000000000, 0x00000006 },
 145         { 0x00000080, 0x00000018 },
 146         { 0x00000054, 0x00000004 },
 147         { 0x00007576, 0x00000002 },
 148         { 0x00065000, 0x00000002 },
 149         { 0x00009000, 0x00000002 },
 150         { 0x00041000, 0x00000002 },
 151         { 0x0c00350e, 0x00000002 },
 152         { 0x00049000, 0x00000002 },
 153         { 0x00051000, 0x00000002 },
 154         { 0x01e785f8, 0x00000002 },
 155         { 0x00200000, 0x00000002 },
 156         { 0x00600073, 0x0000000c },
 157         { 0x00007563, 0x00000002 },
 158         { 0x006075f0, 0x00000021 },
 159         { 0x20007068, 0x00000004 },
 160         { 0x00005068, 0x00000004 },
 161         { 0x00007576, 0x00000002 },
 162         { 0x00007577, 0x00000002 },
 163         { 0x0000750e, 0x00000002 },
 164         { 0x0000750f, 0x00000002 },
 165         { 0x00a05000, 0x00000002 },
 166         { 0x00600076, 0x0000000c },
 167         { 0x006075f0, 0x00000021 },
 168         { 0x000075f8, 0x00000002 },
 169         { 0x00000076, 0x00000004 },
 170         { 0x000a750e, 0x00000002 },
 171         { 0x0020750f, 0x00000002 },
 172         { 0x00600079, 0x00000004 },
 173         { 0x00007570, 0x00000002 },
 174         { 0x00007571, 0x00000002 },
 175         { 0x00007572, 0x00000006 },
 176         { 0x00005000, 0x00000002 },
 177         { 0x00a05000, 0x00000002 },
 178         { 0x00007568, 0x00000002 },
 179         { 0x00061000, 0x00000002 },
 180         { 0x00000084, 0x0000000c },
 181         { 0x00058000, 0x00000002 },
 182         { 0x0c607562, 0x00000002 },
 183         { 0x00000086, 0x00000004 },
 184         { 0x00600085, 0x00000004 },
 185         { 0x400070dd, 0000000000 },
 186         { 0x000380dd, 0x00000002 },
 187         { 0x00000093, 0x0000001c },
 188         { 0x00065095, 0x00000018 },
 189         { 0x040025bb, 0x00000002 },
 190         { 0x00061096, 0x00000018 },
 191         { 0x040075bc, 0000000000 },
 192         { 0x000075bb, 0x00000002 },
 193         { 0x000075bc, 0000000000 },
 194         { 0x00090000, 0x00000006 },
 195         { 0x00090000, 0x00000002 },
 196         { 0x000d8002, 0x00000006 },
 197         { 0x00005000, 0x00000002 },
 198         { 0x00007821, 0x00000002 },
 199         { 0x00007800, 0000000000 },
 200         { 0x00007821, 0x00000002 },
 201         { 0x00007800, 0000000000 },
 202         { 0x01665000, 0x00000002 },
 203         { 0x000a0000, 0x00000002 },
 204         { 0x000671cc, 0x00000002 },
 205         { 0x0286f1cd, 0x00000002 },
 206         { 0x000000a3, 0x00000010 },
 207         { 0x21007000, 0000000000 },
 208         { 0x000000aa, 0x0000001c },
 209         { 0x00065000, 0x00000002 },
 210         { 0x000a0000, 0x00000002 },
 211         { 0x00061000, 0x00000002 },
 212         { 0x000b0000, 0x00000002 },
 213         { 0x38067000, 0x00000002 },
 214         { 0x000a00a6, 0x00000004 },
 215         { 0x20007000, 0000000000 },
 216         { 0x01200000, 0x00000002 },
 217         { 0x20077000, 0x00000002 },
 218         { 0x01200000, 0x00000002 },
 219         { 0x20007000, 0000000000 },
 220         { 0x00061000, 0x00000002 },
 221         { 0x0120751b, 0x00000002 },
 222         { 0x8040750a, 0x00000002 },
 223         { 0x8040750b, 0x00000002 },
 224         { 0x00110000, 0x00000002 },
 225         { 0x000380dd, 0x00000002 },
 226         { 0x000000bd, 0x0000001c },
 227         { 0x00061096, 0x00000018 },
 228         { 0x844075bd, 0x00000002 },
 229         { 0x00061095, 0x00000018 },
 230         { 0x840075bb, 0x00000002 },
 231         { 0x00061096, 0x00000018 },
 232         { 0x844075bc, 0x00000002 },
 233         { 0x000000c0, 0x00000004 },
 234         { 0x804075bd, 0x00000002 },
 235         { 0x800075bb, 0x00000002 },
 236         { 0x804075bc, 0x00000002 },
 237         { 0x00108000, 0x00000002 },
 238         { 0x01400000, 0x00000002 },
 239         { 0x006000c4, 0x0000000c },
 240         { 0x20c07000, 0x00000020 },
 241         { 0x000000c6, 0x00000012 },
 242         { 0x00800000, 0x00000006 },
 243         { 0x0080751d, 0x00000006 },
 244         { 0x000025bb, 0x00000002 },
 245         { 0x000040c0, 0x00000004 },
 246         { 0x0000775c, 0x00000002 },
 247         { 0x00a05000, 0x00000002 },
 248         { 0x00661000, 0x00000002 },
 249         { 0x0460275d, 0x00000020 },
 250         { 0x00004000, 0000000000 },
 251         { 0x00007999, 0x00000002 },
 252         { 0x00a05000, 0x00000002 },
 253         { 0x00661000, 0x00000002 },
 254         { 0x0460299b, 0x00000020 },
 255         { 0x00004000, 0000000000 },
 256         { 0x01e00830, 0x00000002 },
 257         { 0x21007000, 0000000000 },
 258         { 0x00005000, 0x00000002 },
 259         { 0x00038042, 0x00000002 },
 260         { 0x040025e0, 0x00000002 },
 261         { 0x000075e1, 0000000000 },
 262         { 0x00000001, 0000000000 },
 263         { 0x000380d9, 0x00000002 },
 264         { 0x04007394, 0000000000 },
 265         { 0000000000, 0000000000 },
 266         { 0000000000, 0000000000 },
 267         { 0000000000, 0000000000 },
 268         { 0000000000, 0000000000 },
 269         { 0000000000, 0000000000 },
 270         { 0000000000, 0000000000 },
 271         { 0000000000, 0000000000 },
 272         { 0000000000, 0000000000 },
 273         { 0000000000, 0000000000 },
 274         { 0000000000, 0000000000 },
 275         { 0000000000, 0000000000 },
 276         { 0000000000, 0000000000 },
 277         { 0000000000, 0000000000 },
 278         { 0000000000, 0000000000 },
 279         { 0000000000, 0000000000 },
 280         { 0000000000, 0000000000 },
 281         { 0000000000, 0000000000 },
 282         { 0000000000, 0000000000 },
 283         { 0000000000, 0000000000 },
 284         { 0000000000, 0000000000 },
 285         { 0000000000, 0000000000 },
 286         { 0000000000, 0000000000 },
 287         { 0000000000, 0000000000 },
 288         { 0000000000, 0000000000 },
 289         { 0000000000, 0000000000 },
 290         { 0000000000, 0000000000 },
 291         { 0000000000, 0000000000 },
 292         { 0000000000, 0000000000 },
 293         { 0000000000, 0000000000 },
 294         { 0000000000, 0000000000 },
 295         { 0000000000, 0000000000 },
 296         { 0000000000, 0000000000 },
 297         { 0000000000, 0000000000 },
 298         { 0000000000, 0000000000 },
 299         { 0000000000, 0000000000 },
 300         { 0000000000, 0000000000 },
 301 };
 302
 303
 304 static u32 radeon_cp_microcode[][2] = {
 305         { 0x21007000, 0000000000 },
 306         { 0x20007000, 0000000000 },
 307         { 0x000000b4, 0x00000004 },
 308         { 0x000000b8, 0x00000004 },
 309         { 0x6f5b4d4c, 0000000000 },
 310         { 0x4c4c427f, 0000000000 },
 311         { 0x5b568a92, 0000000000 },
 312         { 0x4ca09c6d, 0000000000 },
 313         { 0xad4c4c4c, 0000000000 },
 314         { 0x4ce1af3d, 0000000000 },
 315         { 0xd8afafaf, 0000000000 },
 316         { 0xd64c4cdc, 0000000000 },
 317         { 0x4cd10d10, 0000000000 },
 318         { 0x000f0000, 0x00000016 },
 319         { 0x362f242d, 0000000000 },
 320         { 0x00000012, 0x00000004 },
 321         { 0x000f0000, 0x00000016 },
 322         { 0x362f282d, 0000000000 },
 323         { 0x000380e7, 0x00000002 },
 324         { 0x04002c97, 0x00000002 },
 325         { 0x000f0001, 0x00000016 },
 326         { 0x333a3730, 0000000000 },
 327         { 0x000077ef, 0x00000002 },
 328         { 0x00061000, 0x00000002 },
 329         { 0x00000021, 0x0000001a },
 330         { 0x00004000, 0x0000001e },
 331         { 0x00061000, 0x00000002 },
 332         { 0x00000021, 0x0000001a },
 333         { 0x00004000, 0x0000001e },
 334         { 0x00061000, 0x00000002 },
 335         { 0x00000021, 0x0000001a },
 336         { 0x00004000, 0x0000001e },
 337         { 0x00000017, 0x00000004 },
 338         { 0x0003802b, 0x00000002 },
 339         { 0x040067e0, 0x00000002 },
 340         { 0x00000017, 0x00000004 },
 341         { 0x000077e0, 0x00000002 },
 342         { 0x00065000, 0x00000002 },
 343         { 0x000037e1, 0x00000002 },
 344         { 0x040067e1, 0x00000006 },
 345         { 0x000077e0, 0x00000002 },
 346         { 0x000077e1, 0x00000002 },
 347         { 0x000077e1, 0x00000006 },
 348         { 0xffffffff, 0000000000 },
 349         { 0x10000000, 0000000000 },
 350         { 0x0003802b, 0x00000002 },
 351         { 0x040067e0, 0x00000006 },
 352         { 0x00007675, 0x00000002 },
 353         { 0x00007676, 0x00000002 },
 354         { 0x00007677, 0x00000002 },
 355         { 0x00007678, 0x00000006 },
 356         { 0x0003802c, 0x00000002 },
 357         { 0x04002676, 0x00000002 },
 358         { 0x00007677, 0x00000002 },
 359         { 0x00007678, 0x00000006 },
 360         { 0x0000002f, 0x00000018 },
 361         { 0x0000002f, 0x00000018 },
 362         { 0000000000, 0x00000006 },
 363         { 0x00000030, 0x00000018 },
 364         { 0x00000030, 0x00000018 },
 365         { 0000000000, 0x00000006 },
 366         { 0x01605000, 0x00000002 },
 367         { 0x00065000, 0x00000002 },
 368         { 0x00098000, 0x00000002 },
 369         { 0x00061000, 0x00000002 },
 370         { 0x64c0603e, 0x00000004 },
 371         { 0x000380e6, 0x00000002 },
 372         { 0x040025c5, 0x00000002 },
 373         { 0x00080000, 0x00000016 },
 374         { 0000000000, 0000000000 },
 375         { 0x0400251d, 0x00000002 },
 376         { 0x00007580, 0x00000002 },
 377         { 0x00067581, 0x00000002 },
 378         { 0x04002580, 0x00000002 },
 379         { 0x00067581, 0x00000002 },
 380         { 0x00000049, 0x00000004 },
 381         { 0x00005000, 0000000000 },
 382         { 0x000380e6, 0x00000002 },
 383         { 0x040025c5, 0x00000002 },
 384         { 0x00061000, 0x00000002 },
 385         { 0x0000750e, 0x00000002 },
 386         { 0x00019000, 0x00000002 },
 387         { 0x00011055, 0x00000014 },
 388         { 0x00000055, 0x00000012 },
 389         { 0x0400250f, 0x00000002 },
 390         { 0x0000504f, 0x00000004 },
 391         { 0x000380e6, 0x00000002 },
 392         { 0x040025c5, 0x00000002 },
 393         { 0x00007565, 0x00000002 },
 394         { 0x00007566, 0x00000002 },
 395         { 0x00000058, 0x00000004 },
 396         { 0x000380e6, 0x00000002 },
 397         { 0x040025c5, 0x00000002 },
 398         { 0x01e655b4, 0x00000002 },
 399         { 0x4401b0e4, 0x00000002 },
 400         { 0x01c110e4, 0x00000002 },
 401         { 0x26667066, 0x00000018 },
 402         { 0x040c2565, 0x00000002 },
 403         { 0x00000066, 0x00000018 },
 404         { 0x04002564, 0x00000002 },
 405         { 0x00007566, 0x00000002 },
 406         { 0x0000005d, 0x00000004 },
 407         { 0x00401069, 0x00000008 },
 408         { 0x00101000, 0x00000002 },
 409         { 0x000d80ff, 0x00000002 },
 410         { 0x0080006c, 0x00000008 },
 411         { 0x000f9000, 0x00000002 },
 412         { 0x000e00ff, 0x00000002 },
 413         { 0000000000, 0x00000006 },
 414         { 0x0000008f, 0x00000018 },
 415         { 0x0000005b, 0x00000004 },
 416         { 0x000380e6, 0x00000002 },
 417         { 0x040025c5, 0x00000002 },
 418         { 0x00007576, 0x00000002 },
 419         { 0x00065000, 0x00000002 },
 420         { 0x00009000, 0x00000002 },
 421         { 0x00041000, 0x00000002 },
 422         { 0x0c00350e, 0x00000002 },
 423         { 0x00049000, 0x00000002 },
 424         { 0x00051000, 0x00000002 },
 425         { 0x01e785f8, 0x00000002 },
 426         { 0x00200000, 0x00000002 },
 427         { 0x0060007e, 0x0000000c },
 428         { 0x00007563, 0x00000002 },
 429         { 0x006075f0, 0x00000021 },
 430         { 0x20007073, 0x00000004 },
 431         { 0x00005073, 0x00000004 },
 432         { 0x000380e6, 0x00000002 },
 433         { 0x040025c5, 0x00000002 },
 434         { 0x00007576, 0x00000002 },
 435         { 0x00007577, 0x00000002 },
 436         { 0x0000750e, 0x00000002 },
 437         { 0x0000750f, 0x00000002 },
 438         { 0x00a05000, 0x00000002 },
 439         { 0x00600083, 0x0000000c },
 440         { 0x006075f0, 0x00000021 },
 441         { 0x000075f8, 0x00000002 },
 442         { 0x00000083, 0x00000004 },
 443         { 0x000a750e, 0x00000002 },
 444         { 0x000380e6, 0x00000002 },
 445         { 0x040025c5, 0x00000002 },
 446         { 0x0020750f, 0x00000002 },
 447         { 0x00600086, 0x00000004 },
 448         { 0x00007570, 0x00000002 },
 449         { 0x00007571, 0x00000002 },
 450         { 0x00007572, 0x00000006 },
 451         { 0x000380e6, 0x00000002 },
 452         { 0x040025c5, 0x00000002 },
 453         { 0x00005000, 0x00000002 },
 454         { 0x00a05000, 0x00000002 },
 455         { 0x00007568, 0x00000002 },
 456         { 0x00061000, 0x00000002 },
 457         { 0x00000095, 0x0000000c },
 458         { 0x00058000, 0x00000002 },
 459         { 0x0c607562, 0x00000002 },
 460         { 0x00000097, 0x00000004 },
 461         { 0x000380e6, 0x00000002 },
 462         { 0x040025c5, 0x00000002 },
 463         { 0x00600096, 0x00000004 },
 464         { 0x400070e5, 0000000000 },
 465         { 0x000380e6, 0x00000002 },
 466         { 0x040025c5, 0x00000002 },
 467         { 0x000380e5, 0x00000002 },
 468         { 0x000000a8, 0x0000001c },
 469         { 0x000650aa, 0x00000018 },
 470         { 0x040025bb, 0x00000002 },
 471         { 0x000610ab, 0x00000018 },
 472         { 0x040075bc, 0000000000 },
 473         { 0x000075bb, 0x00000002 },
 474         { 0x000075bc, 0000000000 },
 475         { 0x00090000, 0x00000006 },
 476         { 0x00090000, 0x00000002 },
 477         { 0x000d8002, 0x00000006 },
 478         { 0x00007832, 0x00000002 },
 479         { 0x00005000, 0x00000002 },
 480         { 0x000380e7, 0x00000002 },
 481         { 0x04002c97, 0x00000002 },
 482         { 0x00007820, 0x00000002 },
 483         { 0x00007821, 0x00000002 },
 484         { 0x00007800, 0000000000 },
 485         { 0x01200000, 0x00000002 },
 486         { 0x20077000, 0x00000002 },
 487         { 0x01200000, 0x00000002 },
 488         { 0x20007000, 0x00000002 },
 489         { 0x00061000, 0x00000002 },
 490         { 0x0120751b, 0x00000002 },
 491         { 0x8040750a, 0x00000002 },
 492         { 0x8040750b, 0x00000002 },
 493         { 0x00110000, 0x00000002 },
 494         { 0x000380e5, 0x00000002 },
 495         { 0x000000c6, 0x0000001c },
 496         { 0x000610ab, 0x00000018 },
 497         { 0x844075bd, 0x00000002 },
 498         { 0x000610aa, 0x00000018 },
 499         { 0x840075bb, 0x00000002 },
 500         { 0x000610ab, 0x00000018 },
 501         { 0x844075bc, 0x00000002 },
 502         { 0x000000c9, 0x00000004 },
 503         { 0x804075bd, 0x00000002 },
 504         { 0x800075bb, 0x00000002 },
 505         { 0x804075bc, 0x00000002 },
 506         { 0x00108000, 0x00000002 },
 507         { 0x01400000, 0x00000002 },
 508         { 0x006000cd, 0x0000000c },
 509         { 0x20c07000, 0x00000020 },
 510         { 0x000000cf, 0x00000012 },
 511         { 0x00800000, 0x00000006 },
 512         { 0x0080751d, 0x00000006 },
 513         { 0000000000, 0000000000 },
 514         { 0x0000775c, 0x00000002 },
 515         { 0x00a05000, 0x00000002 },
 516         { 0x00661000, 0x00000002 },
 517         { 0x0460275d, 0x00000020 },
 518         { 0x00004000, 0000000000 },
 519         { 0x01e00830, 0x00000002 },
 520         { 0x21007000, 0000000000 },
 521         { 0x6464614d, 0000000000 },
 522         { 0x69687420, 0000000000 },
 523         { 0x00000073, 0000000000 },
 524         { 0000000000, 0000000000 },
 525         { 0x00005000, 0x00000002 },
 526         { 0x000380d0, 0x00000002 },
 527         { 0x040025e0, 0x00000002 },
 528         { 0x000075e1, 0000000000 },
 529         { 0x00000001, 0000000000 },
 530         { 0x000380e0, 0x00000002 },
 531         { 0x04002394, 0x00000002 },
 532         { 0x00005000, 0000000000 },
 533         { 0000000000, 0000000000 },
 534         { 0000000000, 0000000000 },
 535         { 0x00000008, 0000000000 },
 536         { 0x00000004, 0000000000 },
 537         { 0000000000, 0000000000 },
 538         { 0000000000, 0000000000 },
 539         { 0000000000, 0000000000 },
 540         { 0000000000, 0000000000 },
 541         { 0000000000, 0000000000 },
 542         { 0000000000, 0000000000 },
 543         { 0000000000, 0000000000 },
 544         { 0000000000, 0000000000 },
 545         { 0000000000, 0000000000 },
 546         { 0000000000, 0000000000 },
 547         { 0000000000, 0000000000 },
 548         { 0000000000, 0000000000 },
 549         { 0000000000, 0000000000 },
 550         { 0000000000, 0000000000 },
 551         { 0000000000, 0000000000 },
 552         { 0000000000, 0000000000 },
 553         { 0000000000, 0000000000 },
 554         { 0000000000, 0000000000 },
 555         { 0000000000, 0000000000 },
 556         { 0000000000, 0000000000 },
 557         { 0000000000, 0000000000 },
 558         { 0000000000, 0000000000 },
 559         { 0000000000, 0000000000 },
 560         { 0000000000, 0000000000 },
 561 };
 562
 563
 564 int RADEON_READ_PLL(drm_device_t *dev, int addr)
 565 {
 566         drm_radeon_private_t *dev_priv = dev->dev_private;
 567
 568         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 569         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 570 }
 571
 572 #if RADEON_FIFO_DEBUG
 573 static void radeon_status( drm_radeon_private_t *dev_priv )
 574 {
 575         printk( "%s:\n", __FUNCTION__ );
 576         printk( "RBBM_STATUS = 0x%08x\n",
 577                 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
 578         printk( "CP_RB_RTPR = 0x%08x\n",
 579                 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
 580         printk( "CP_RB_WTPR = 0x%08x\n",
 581                 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
 582         printk( "AIC_CNTL = 0x%08x\n",
 583                 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
 584         printk( "AIC_STAT = 0x%08x\n",
 585                 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
 586         printk( "AIC_PT_BASE = 0x%08x\n",
 587                 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
 588         printk( "TLB_ADDR = 0x%08x\n",
 589                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
 590         printk( "TLB_DATA = 0x%08x\n",
 591                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
 592 }
 593 #endif
 594
 595
 596 /* ================================================================
 597  * Engine, FIFO control
 598  */
 599
 600 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
 601 {
 602         u32 tmp;
 603         int i;
 604
 605         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 606
 607         tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
 608         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 609         RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
 610
 611         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 612                 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
 613                        & RADEON_RB2D_DC_BUSY) ) {
 614                         return 0;
 615                 }
 616                 DRM_UDELAY( 1 );
 617         }
 618
 619 #if RADEON_FIFO_DEBUG
 620         DRM_ERROR( "failed!\n" );
 621         radeon_status( dev_priv );
 622 #endif
 623         return DRM_ERR(EBUSY);
 624 }
 625
 626 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
 627                                     int entries )
 628 {
 629         int i;
 630
 631         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 632
 633         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 634                 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
 635                               & RADEON_RBBM_FIFOCNT_MASK );
 636                 if ( slots >= entries ) return 0;
 637                 DRM_UDELAY( 1 );
 638         }
 639
 640 #if RADEON_FIFO_DEBUG
 641         DRM_ERROR( "failed!\n" );
 642         radeon_status( dev_priv );
 643 #endif
 644         return DRM_ERR(EBUSY);
 645 }
 646
 647 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
 648 {
 649         int i, ret;
 650
 651         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 652
 653         ret = radeon_do_wait_for_fifo( dev_priv, 64 );
 654         if ( ret ) return ret;
 655
 656         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 657                 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
 658                        & RADEON_RBBM_ACTIVE) ) {
 659                         radeon_do_pixcache_flush( dev_priv );
 660                         return 0;
 661                 }
 662                 DRM_UDELAY( 1 );
 663         }
 664
 665 #if RADEON_FIFO_DEBUG
 666         DRM_ERROR( "failed!\n" );
 667         radeon_status( dev_priv );
 668 #endif
 669         return DRM_ERR(EBUSY);
 670 }
 671
 672
 673 /* ================================================================
 674  * CP control, initialization
 675  */
 676
 677 /* Load the microcode for the CP */
 678 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
 679 {
 680         int i;
 681         DRM_DEBUG( "\n" );
 682
 683         radeon_do_wait_for_idle( dev_priv );
 684
 685         RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
 686
 687         if (dev_priv->is_r200)
 688         {
 689                 DRM_INFO("Loading R200 Microcode\n");
 690                 for ( i = 0 ; i < 256 ; i++ )
 691                 {
 692                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 693                                       R200_cp_microcode[i][1] );
 694                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 695                                       R200_cp_microcode[i][0] );
 696                 }
 697         }
 698         else
 699         {
 700                 for ( i = 0 ; i < 256 ; i++ ) {
 701                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 702                                       radeon_cp_microcode[i][1] );
 703                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 704                                       radeon_cp_microcode[i][0] );
 705                 }
 706         }
 707 }
 708
 709 /* Flush any pending commands to the CP.  This should only be used just
 710  * prior to a wait for idle, as it informs the engine that the command
 711  * stream is ending.
 712  */
 713 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
 714 {
 715         DRM_DEBUG( "\n" );
 716 #if 0
 717         u32 tmp;
 718
 719         tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
 720         RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
 721 #endif
 722 }
 723
 724 /* Wait for the CP to go idle.
 725  */
 726 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 727 {
 728         RING_LOCALS;
 729         DRM_DEBUG( "\n" );
 730
 731         BEGIN_RING( 6 );
 732
 733         RADEON_PURGE_CACHE();
 734         RADEON_PURGE_ZCACHE();
 735         RADEON_WAIT_UNTIL_IDLE();
 736
 737         ADVANCE_RING();
 738         COMMIT_RING();
 739
 740         return radeon_do_wait_for_idle( dev_priv );
 741 }
 742
 743 /* Start the Command Processor.
 744  */
 745 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
 746 {
 747         RING_LOCALS;
 748         DRM_DEBUG( "\n" );
 749
 750         radeon_do_wait_for_idle( dev_priv );
 751
 752         RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
 753
 754         dev_priv->cp_running = 1;
 755
 756         BEGIN_RING( 6 );
 757
 758         RADEON_PURGE_CACHE();
 759         RADEON_PURGE_ZCACHE();
 760         RADEON_WAIT_UNTIL_IDLE();
 761
 762         ADVANCE_RING();
 763         COMMIT_RING();
 764 }
 765
 766 /* Reset the Command Processor.  This will not flush any pending
 767  * commands, so you must wait for the CP command stream to complete
 768  * before calling this routine.
 769  */
 770 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
 771 {
 772         u32 cur_read_ptr;
 773         DRM_DEBUG( "\n" );
 774
 775         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 776         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 777         SET_RING_HEAD( dev_priv, cur_read_ptr );
 778         dev_priv->ring.tail = cur_read_ptr;
 779 }
 780
 781 /* Stop the Command Processor.  This will not flush any pending
 782  * commands, so you must flush the command stream and wait for the CP
 783  * to go idle before calling this routine.
 784  */
 785 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
 786 {
 787         DRM_DEBUG( "\n" );
 788
 789         RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
 790
 791         dev_priv->cp_running = 0;
 792 }
 793
 794 /* Reset the engine.  This will stop the CP if it is running.
 795  */
 796 static int radeon_do_engine_reset( drm_device_t *dev )
 797 {
 798         drm_radeon_private_t *dev_priv = dev->dev_private;
 799         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 800         DRM_DEBUG( "\n" );
 801
 802         radeon_do_pixcache_flush( dev_priv );
 803
 804         clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
 805         mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
 806
 807         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
 808                                               RADEON_FORCEON_MCLKA |
 809                                               RADEON_FORCEON_MCLKB |
 810                                               RADEON_FORCEON_YCLKA |
 811                                               RADEON_FORCEON_YCLKB |
 812                                               RADEON_FORCEON_MC |
 813                                               RADEON_FORCEON_AIC ) );
 814
 815         rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
 816
 817         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
 818                                                 RADEON_SOFT_RESET_CP |
 819                                                 RADEON_SOFT_RESET_HI |
 820                                                 RADEON_SOFT_RESET_SE |
 821                                                 RADEON_SOFT_RESET_RE |
 822                                                 RADEON_SOFT_RESET_PP |
 823                                                 RADEON_SOFT_RESET_E2 |
 824                                                 RADEON_SOFT_RESET_RB ) );
 825         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 826         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
 827                                                 ~( RADEON_SOFT_RESET_CP |
 828                                                    RADEON_SOFT_RESET_HI |
 829                                                    RADEON_SOFT_RESET_SE |
 830                                                    RADEON_SOFT_RESET_RE |
 831                                                    RADEON_SOFT_RESET_PP |
 832                                                    RADEON_SOFT_RESET_E2 |
 833                                                    RADEON_SOFT_RESET_RB ) ) );
 834         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 835
 836
 837         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
 838         RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
 839         RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
 840
 841         /* Reset the CP ring */
 842         radeon_do_cp_reset( dev_priv );
 843
 844         /* The CP is no longer running after an engine reset */
 845         dev_priv->cp_running = 0;
 846
 847         /* Reset any pending vertex, indirect buffers */
 848         radeon_freelist_reset( dev );
 849
 850         return 0;
 851 }
 852
 853 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
 854                                         drm_radeon_private_t *dev_priv )
 855 {
 856         u32 ring_start, cur_read_ptr;
 857         u32 tmp;
 858
 859         /* Initialize the memory controller */
 860         RADEON_WRITE( RADEON_MC_FB_LOCATION,
 861                       (dev_priv->agp_vm_start - 1) & 0xffff0000 );
 862
 863         if ( !dev_priv->is_pci ) {
 864                 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
 865                               (((dev_priv->agp_vm_start - 1 +
 866                                  dev_priv->agp_size) & 0xffff0000) |
 867                                (dev_priv->agp_vm_start >> 16)) );
 868         }
 869
 870 #if __REALLY_HAVE_AGP
 871         if ( !dev_priv->is_pci )
 872                 ring_start = (dev_priv->cp_ring->offset
 873                               - dev->agp->base
 874                               + dev_priv->agp_vm_start);
 875        else
 876 #endif
 877                 ring_start = (dev_priv->cp_ring->offset
 878                               - dev->sg->handle
 879                               + dev_priv->agp_vm_start);
 880
 881         RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
 882
 883         /* Set the write pointer delay */
 884         RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
 885
 886         /* Initialize the ring buffer's read and write pointers */
 887         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 888         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 889         SET_RING_HEAD( dev_priv, cur_read_ptr );
 890         dev_priv->ring.tail = cur_read_ptr;
 891
 892 #if __REALLY_HAVE_AGP
 893         if ( !dev_priv->is_pci ) {
 894                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 895                               dev_priv->ring_rptr->offset
 896                               - dev->agp->base
 897                               + dev_priv->agp_vm_start);
 898         } else
 899 #endif
 900         {
 901                 drm_sg_mem_t *entry = dev->sg;
 902                 unsigned long tmp_ofs, page_ofs;
 903
 904                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
 905                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 906
 907                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 908                              entry->busaddr[page_ofs]);
 909                 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
 910                            entry->busaddr[page_ofs],
 911                            entry->handle + tmp_ofs );
 912         }
 913
 914         /* Initialize the scratch register pointer.  This will cause
 915          * the scratch register values to be written out to memory
 916          * whenever they are updated.
 917          *
 918          * We simply put this behind the ring read pointer, this works
 919          * with PCI GART as well as (whatever kind of) AGP GART
 920          */
 921         RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
 922                                          + RADEON_SCRATCH_REG_OFFSET );
 923
 924         dev_priv->scratch = ((__volatile__ u32 *)
 925                              dev_priv->ring_rptr->handle +
 926                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 927
 928         RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
 929
 930         /* Writeback doesn't seem to work everywhere, test it first */
 931         DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
 932         RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
 933
 934         for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
 935                 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
 936                         break;
 937                 DRM_UDELAY( 1 );
 938         }
 939
 940         if ( tmp < dev_priv->usec_timeout ) {
 941                 dev_priv->writeback_works = 1;
 942                 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
 943         } else {
 944                 dev_priv->writeback_works = 0;
 945                 DRM_DEBUG( "writeback test failed\n" );
 946         }
 947
 948         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 949         RADEON_WRITE( RADEON_LAST_FRAME_REG,
 950                       dev_priv->sarea_priv->last_frame );
 951
 952         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 953         RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
 954                       dev_priv->sarea_priv->last_dispatch );
 955
 956         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 957         RADEON_WRITE( RADEON_LAST_CLEAR_REG,
 958                       dev_priv->sarea_priv->last_clear );
 959
 960         /* Set ring buffer size */
 961 #ifdef __BIG_ENDIAN
 962         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
 963 #else
 964         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
 965 #endif
 966
 967         radeon_do_wait_for_idle( dev_priv );
 968
 969         /* Turn on bus mastering */
 970         tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
 971         RADEON_WRITE( RADEON_BUS_CNTL, tmp );
 972
 973         /* Sync everything up */
 974         RADEON_WRITE( RADEON_ISYNC_CNTL,
 975                       (RADEON_ISYNC_ANY2D_IDLE3D |
 976                        RADEON_ISYNC_ANY3D_IDLE2D |
 977                        RADEON_ISYNC_WAIT_IDLEGUI |
 978                        RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
 979 }
 980
 981 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 982 {
 983         drm_radeon_private_t *dev_priv;
 984         u32 tmp;
 985         DRM_DEBUG( "\n" );
 986
 987         dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
 988         if ( dev_priv == NULL )
 989                 return DRM_ERR(ENOMEM);
 990
 991         memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
 992
 993         dev_priv->is_pci = init->is_pci;
 994
 995         if ( dev_priv->is_pci && !dev->sg ) {
 996                 DRM_ERROR( "PCI GART memory not allocated!\n" );
 997                 dev->dev_private = (void *)dev_priv;
 998                 radeon_do_cleanup_cp(dev);
 999                 return DRM_ERR(EINVAL);
1000         }
1001
1002         dev_priv->usec_timeout = init->usec_timeout;
1003         if ( dev_priv->usec_timeout < 1 ||
1004              dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1005                 DRM_DEBUG( "TIMEOUT problem!\n" );
1006                 dev->dev_private = (void *)dev_priv;
1007                 radeon_do_cleanup_cp(dev);
1008                 return DRM_ERR(EINVAL);
1009         }
1010
1011         dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1012         dev_priv->do_boxes = 0;
1013         dev_priv->cp_mode = init->cp_mode;
1014
1015         /* We don't support anything other than bus-mastering ring mode,
1016          * but the ring can be in either AGP or PCI space for the ring
1017          * read pointer.
1018          */
1019         if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1020              ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1021                 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1022                 dev->dev_private = (void *)dev_priv;
1023                 radeon_do_cleanup_cp(dev);
1024                 return DRM_ERR(EINVAL);
1025         }
1026
1027         switch ( init->fb_bpp ) {
1028         case 16:
1029                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1030                 break;
1031         case 32:
1032         default:
1033                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1034                 break;
1035         }
1036         dev_priv->front_offset  = init->front_offset;
1037         dev_priv->front_pitch   = init->front_pitch;
1038         dev_priv->back_offset   = init->back_offset;
1039         dev_priv->back_pitch    = init->back_pitch;
1040
1041         switch ( init->depth_bpp ) {
1042         case 16:
1043                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1044                 break;
1045         case 32:
1046         default:
1047                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1048                 break;
1049         }
1050         dev_priv->depth_offset  = init->depth_offset;
1051         dev_priv->depth_pitch   = init->depth_pitch;
1052
1053         dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1054                                         (dev_priv->front_offset >> 10));
1055         dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1056                                        (dev_priv->back_offset >> 10));
1057         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1058                                         (dev_priv->depth_offset >> 10));
1059
1060         /* Hardware state for depth clears.  Remove this if/when we no
1061          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1062          * all values to prevent unwanted 3D state from slipping through
1063          * and screwing with the clear operation.
1064          */
1065         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1066                                            (dev_priv->color_fmt << 10) |
1067                                            (1<<15));
1068
1069         dev_priv->depth_clear.rb3d_zstencilcntl =
1070                 (dev_priv->depth_fmt |
1071                  RADEON_Z_TEST_ALWAYS |
1072                  RADEON_STENCIL_TEST_ALWAYS |
1073                  RADEON_STENCIL_S_FAIL_REPLACE |
1074                  RADEON_STENCIL_ZPASS_REPLACE |
1075                  RADEON_STENCIL_ZFAIL_REPLACE |
1076                  RADEON_Z_WRITE_ENABLE);
1077
1078         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1079                                          RADEON_BFACE_SOLID |
1080                                          RADEON_FFACE_SOLID |
1081                                          RADEON_FLAT_SHADE_VTX_LAST |
1082                                          RADEON_DIFFUSE_SHADE_FLAT |
1083                                          RADEON_ALPHA_SHADE_FLAT |
1084                                          RADEON_SPECULAR_SHADE_FLAT |
1085                                          RADEON_FOG_SHADE_FLAT |
1086                                          RADEON_VTX_PIX_CENTER_OGL |
1087                                          RADEON_ROUND_MODE_TRUNC |
1088                                          RADEON_ROUND_PREC_8TH_PIX);
1089
1090         DRM_GETSAREA();
1091
1092         dev_priv->fb_offset = init->fb_offset;
1093         dev_priv->mmio_offset = init->mmio_offset;
1094         dev_priv->ring_offset = init->ring_offset;
1095         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1096         dev_priv->buffers_offset = init->buffers_offset;
1097         dev_priv->agp_textures_offset = init->agp_textures_offset;
1098
1099         if(!dev_priv->sarea) {
1100                 DRM_ERROR("could not find sarea!\n");
1101                 dev->dev_private = (void *)dev_priv;
1102                 radeon_do_cleanup_cp(dev);
1103                 return DRM_ERR(EINVAL);
1104         }
1105
1106         DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
1107         if(!dev_priv->fb) {
1108                 DRM_ERROR("could not find framebuffer!\n");
1109                 dev->dev_private = (void *)dev_priv;
1110                 radeon_do_cleanup_cp(dev);
1111                 return DRM_ERR(EINVAL);
1112         }
1113         DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
1114         if(!dev_priv->mmio) {
1115                 DRM_ERROR("could not find mmio region!\n");
1116                 dev->dev_private = (void *)dev_priv;
1117                 radeon_do_cleanup_cp(dev);
1118                 return DRM_ERR(EINVAL);
1119         }
1120         DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
1121         if(!dev_priv->cp_ring) {
1122                 DRM_ERROR("could not find cp ring region!\n");
1123                 dev->dev_private = (void *)dev_priv;
1124                 radeon_do_cleanup_cp(dev);
1125                 return DRM_ERR(EINVAL);
1126         }
1127         DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
1128         if(!dev_priv->ring_rptr) {
1129                 DRM_ERROR("could not find ring read pointer!\n");
1130                 dev->dev_private = (void *)dev_priv;
1131                 radeon_do_cleanup_cp(dev);
1132                 return DRM_ERR(EINVAL);
1133         }
1134         DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1135         if(!dev_priv->buffers) {
1136                 DRM_ERROR("could not find dma buffer region!\n");
1137                 dev->dev_private = (void *)dev_priv;
1138                 radeon_do_cleanup_cp(dev);
1139                 return DRM_ERR(EINVAL);
1140         }
1141
1142         if ( !dev_priv->is_pci ) {
1143                 DRM_FIND_MAP( dev_priv->agp_textures,
1144                               init->agp_textures_offset );
1145                 if(!dev_priv->agp_textures) {
1146                         DRM_ERROR("could not find agp texture region!\n");
1147                         dev->dev_private = (void *)dev_priv;
1148                         radeon_do_cleanup_cp(dev);
1149                         return DRM_ERR(EINVAL);
1150                 }
1151         }
1152
1153         dev_priv->sarea_priv =
1154                 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1155                                        init->sarea_priv_offset);
1156
1157         if ( !dev_priv->is_pci ) {
1158                 DRM_IOREMAP( dev_priv->cp_ring );
1159                 DRM_IOREMAP( dev_priv->ring_rptr );
1160                 DRM_IOREMAP( dev_priv->buffers );
1161                 if(!dev_priv->cp_ring->handle ||
1162                    !dev_priv->ring_rptr->handle ||
1163                    !dev_priv->buffers->handle) {
1164                         DRM_ERROR("could not find ioremap agp regions!\n");
1165                         dev->dev_private = (void *)dev_priv;
1166                         radeon_do_cleanup_cp(dev);
1167                         return DRM_ERR(EINVAL);
1168                 }
1169         } else {
1170                 dev_priv->cp_ring->handle =
1171                         (void *)dev_priv->cp_ring->offset;
1172                 dev_priv->ring_rptr->handle =
1173                         (void *)dev_priv->ring_rptr->offset;
1174                 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1175
1176                 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1177                            dev_priv->cp_ring->handle );
1178                 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1179                            dev_priv->ring_rptr->handle );
1180                 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1181                            dev_priv->buffers->handle );
1182         }
1183
1184
1185         dev_priv->agp_size = init->agp_size;
1186         dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1187 #if __REALLY_HAVE_AGP
1188         if ( !dev_priv->is_pci )
1189                 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1190                                                 - dev->agp->base
1191                                                 + dev_priv->agp_vm_start);
1192         else
1193 #endif
1194                 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1195                                                 - dev->sg->handle
1196                                                 + dev_priv->agp_vm_start);
1197
1198         DRM_DEBUG( "dev_priv->agp_size %d\n",
1199                    dev_priv->agp_size );
1200         DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
1201                    dev_priv->agp_vm_start );
1202         DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
1203                    dev_priv->agp_buffers_offset );
1204
1205         dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1206         dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1207                               + init->ring_size / sizeof(u32));
1208         dev_priv->ring.size = init->ring_size;
1209         dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1210
1211         dev_priv->ring.tail_mask =
1212                 (dev_priv->ring.size / sizeof(u32)) - 1;
1213
1214         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1215
1216 #if __REALLY_HAVE_SG
1217         if ( dev_priv->is_pci ) {
1218                 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1219                                             &dev_priv->bus_pci_gart)) {
1220                         DRM_ERROR( "failed to init PCI GART!\n" );
1221                         dev->dev_private = (void *)dev_priv;
1222                         radeon_do_cleanup_cp(dev);
1223                         return DRM_ERR(ENOMEM);
1224                 }
1225                 /* Turn on PCI GART
1226                  */
1227                 tmp = RADEON_READ( RADEON_AIC_CNTL )
1228                       | RADEON_PCIGART_TRANSLATE_EN;
1229                 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1230
1231                 /* set PCI GART page-table base address
1232                  */
1233                 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1234
1235                 /* set address range for PCI address translate
1236                  */
1237                 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
1238                 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
1239                                                   + dev_priv->agp_size - 1);
1240
1241                 /* Turn off AGP aperture -- is this required for PCIGART?
1242                  */
1243                 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1244                 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1245         } else {
1246 #endif /* __REALLY_HAVE_SG */
1247                 /* Turn off PCI GART
1248                  */
1249                 tmp = RADEON_READ( RADEON_AIC_CNTL )
1250                       & ~RADEON_PCIGART_TRANSLATE_EN;
1251                 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1252 #if __REALLY_HAVE_SG
1253         }
1254 #endif /* __REALLY_HAVE_SG */
1255
1256         radeon_cp_load_microcode( dev_priv );
1257         radeon_cp_init_ring_buffer( dev, dev_priv );
1258
1259         dev_priv->last_buf = 0;
1260
1261         dev->dev_private = (void *)dev_priv;
1262
1263         radeon_do_engine_reset( dev );
1264
1265         return 0;
1266 }
1267
1268 int radeon_do_cleanup_cp( drm_device_t *dev )
1269 {
1270         DRM_DEBUG( "\n" );
1271
1272         if ( dev->dev_private ) {
1273                 drm_radeon_private_t *dev_priv = dev->dev_private;
1274
1275                 if ( !dev_priv->is_pci ) {
1276                         if ( dev_priv->cp_ring != NULL )
1277                                 DRM_IOREMAPFREE( dev_priv->cp_ring );
1278                         if ( dev_priv->ring_rptr != NULL )
1279                                 DRM_IOREMAPFREE( dev_priv->ring_rptr );
1280                         if ( dev_priv->buffers != NULL )
1281                                 DRM_IOREMAPFREE( dev_priv->buffers );
1282                 } else {
1283 #if __REALLY_HAVE_SG
1284                         if (!DRM(ati_pcigart_cleanup)( dev,
1285                                                 dev_priv->phys_pci_gart,
1286                                                 dev_priv->bus_pci_gart ))
1287                                 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1288 #endif /* __REALLY_HAVE_SG */
1289                 }
1290
1291                 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1292                            DRM_MEM_DRIVER );
1293                 dev->dev_private = NULL;
1294         }
1295
1296         return 0;
1297 }
1298
1299 int radeon_cp_init( DRM_IOCTL_ARGS )
1300 {
1301         DRM_DEVICE;
1302         drm_radeon_init_t init;
1303
1304         DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1305
1306         switch ( init.func ) {
1307         case RADEON_INIT_CP:
1308         case RADEON_INIT_R200_CP:
1309                 return radeon_do_init_cp( dev, &init );
1310         case RADEON_CLEANUP_CP:
1311                 return radeon_do_cleanup_cp( dev );
1312         }
1313
1314         return DRM_ERR(EINVAL);
1315 }
1316
1317 int radeon_cp_start( DRM_IOCTL_ARGS )
1318 {
1319         DRM_DEVICE;
1320         drm_radeon_private_t *dev_priv = dev->dev_private;
1321         DRM_DEBUG( "\n" );
1322
1323         LOCK_TEST_WITH_RETURN( dev, filp );
1324
1325         if ( dev_priv->cp_running ) {
1326                 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1327                 return 0;
1328         }
1329         if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1330                 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1331                            __FUNCTION__, dev_priv->cp_mode );
1332                 return 0;
1333         }
1334
1335         radeon_do_cp_start( dev_priv );
1336
1337         return 0;
1338 }
1339
1340 /* Stop the CP.  The engine must have been idled before calling this
1341  * routine.
1342  */
1343 int radeon_cp_stop( DRM_IOCTL_ARGS )
1344 {
1345         DRM_DEVICE;
1346         drm_radeon_private_t *dev_priv = dev->dev_private;
1347         drm_radeon_cp_stop_t stop;
1348         int ret;
1349         DRM_DEBUG( "\n" );
1350
1351         LOCK_TEST_WITH_RETURN( dev, filp );
1352
1353         DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1354
1355         if (!dev_priv->cp_running)
1356                 return 0;
1357
1358         /* Flush any pending CP commands.  This ensures any outstanding
1359          * commands are exectuted by the engine before we turn it off.
1360          */
1361         if ( stop.flush ) {
1362                 radeon_do_cp_flush( dev_priv );
1363         }
1364
1365         /* If we fail to make the engine go idle, we return an error
1366          * code so that the DRM ioctl wrapper can try again.
1367          */
1368         if ( stop.idle ) {
1369                 ret = radeon_do_cp_idle( dev_priv );
1370                 if ( ret ) return ret;
1371         }
1372
1373         /* Finally, we can turn off the CP.  If the engine isn't idle,
1374          * we will get some dropped triangles as they won't be fully
1375          * rendered before the CP is shut down.
1376          */
1377         radeon_do_cp_stop( dev_priv );
1378
1379         /* Reset the engine */
1380         radeon_do_engine_reset( dev );
1381
1382         return 0;
1383 }
1384
1385
1386 void radeon_do_release( drm_device_t *dev )
1387 {
1388         drm_radeon_private_t *dev_priv = dev->dev_private;
1389         int ret;
1390
1391         if (dev_priv) {
1392                 if (dev_priv->cp_running) {
1393                         /* Stop the cp */
1394                         while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1395                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1396 #ifdef __linux__
1397                                 schedule();
1398 #else
1399                                 tsleep(&ret, 0, "rdnrel", 1);
1400 #endif
1401                         }
1402                         radeon_do_cp_stop( dev_priv );
1403                         radeon_do_engine_reset( dev );
1404                 }
1405
1406                 /* Disable *all* interrupts */
1407                 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1408
1409                 /* Free memory heap structures */
1410                 radeon_mem_takedown( &(dev_priv->agp_heap) );
1411                 radeon_mem_takedown( &(dev_priv->fb_heap) );
1412
1413                 /* deallocate kernel resources */
1414                 radeon_do_cleanup_cp( dev );
1415         }
1416 }
1417
1418 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1419  */
1420 int radeon_cp_reset( DRM_IOCTL_ARGS )
1421 {
1422         DRM_DEVICE;
1423         drm_radeon_private_t *dev_priv = dev->dev_private;
1424         DRM_DEBUG( "\n" );
1425
1426         LOCK_TEST_WITH_RETURN( dev, filp );
1427
1428         if ( !dev_priv ) {
1429                 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1430                 return DRM_ERR(EINVAL);
1431         }
1432
1433         radeon_do_cp_reset( dev_priv );
1434
1435         /* The CP is no longer running after an engine reset */
1436         dev_priv->cp_running = 0;
1437
1438         return 0;
1439 }
1440
1441 int radeon_cp_idle( DRM_IOCTL_ARGS )
1442 {
1443         DRM_DEVICE;
1444         drm_radeon_private_t *dev_priv = dev->dev_private;
1445         DRM_DEBUG( "\n" );
1446
1447         LOCK_TEST_WITH_RETURN( dev, filp );
1448
1449         return radeon_do_cp_idle( dev_priv );
1450 }
1451
1452 int radeon_engine_reset( DRM_IOCTL_ARGS )
1453 {
1454         DRM_DEVICE;
1455         DRM_DEBUG( "\n" );
1456
1457         LOCK_TEST_WITH_RETURN( dev, filp );
1458
1459         return radeon_do_engine_reset( dev );
1460 }
1461
1462
1463 /* ================================================================
1464  * Fullscreen mode
1465  */
1466
1467 /* KW: Deprecated to say the least:
1468  */
1469 int radeon_fullscreen( DRM_IOCTL_ARGS )
1470 {
1471         return 0;
1472 }
1473
1474
1475 /* ================================================================
1476  * Freelist management
1477  */
1478
1479 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1480  *   bufs until freelist code is used.  Note this hides a problem with
1481  *   the scratch register * (used to keep track of last buffer
1482  *   completed) being written to before * the last buffer has actually
1483  *   completed rendering.
1484  *
1485  * KW:  It's also a good way to find free buffers quickly.
1486  *
1487  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1488  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1489  * we essentially have to do this, else old clients will break.
1490  *
1491  * However, it does leave open a potential deadlock where all the
1492  * buffers are held by other clients, which can't release them because
1493  * they can't get the lock.
1494  */
1495
1496 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1497 {
1498         drm_device_dma_t *dma = dev->dma;
1499         drm_radeon_private_t *dev_priv = dev->dev_private;
1500         drm_radeon_buf_priv_t *buf_priv;
1501         drm_buf_t *buf;
1502         int i, t;
1503         int start;
1504
1505         if ( ++dev_priv->last_buf >= dma->buf_count )
1506                 dev_priv->last_buf = 0;
1507
1508         start = dev_priv->last_buf;
1509
1510         for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1511                 u32 done_age = GET_SCRATCH( 1 );
1512                 DRM_DEBUG("done_age = %d\n",done_age);
1513                 for ( i = start ; i < dma->buf_count ; i++ ) {
1514                         buf = dma->buflist[i];
1515                         buf_priv = buf->dev_private;
1516                         if ( buf->filp == 0 || (buf->pending &&
1517                                                buf_priv->age <= done_age) ) {
1518                                 dev_priv->stats.requested_bufs++;
1519                                 buf->pending = 0;
1520                                 return buf;
1521                         }
1522                         start = 0;
1523                 }
1524
1525                 if (t) {
1526                         DRM_UDELAY( 1 );
1527                         dev_priv->stats.freelist_loops++;
1528                 }
1529         }
1530
1531         DRM_DEBUG( "returning NULL!\n" );
1532         return NULL;
1533 }
1534 #if 0
1535 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1536 {
1537         drm_device_dma_t *dma = dev->dma;
1538         drm_radeon_private_t *dev_priv = dev->dev_private;
1539         drm_radeon_buf_priv_t *buf_priv;
1540         drm_buf_t *buf;
1541         int i, t;
1542         int start;
1543         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1544
1545         if ( ++dev_priv->last_buf >= dma->buf_count )
1546                 dev_priv->last_buf = 0;
1547
1548         start = dev_priv->last_buf;
1549         dev_priv->stats.freelist_loops++;
1550
1551         for ( t = 0 ; t < 2 ; t++ ) {
1552                 for ( i = start ; i < dma->buf_count ; i++ ) {
1553                         buf = dma->buflist[i];
1554                         buf_priv = buf->dev_private;
1555                         if ( buf->filp == 0 || (buf->pending &&
1556                                                buf_priv->age <= done_age) ) {
1557                                 dev_priv->stats.requested_bufs++;
1558                                 buf->pending = 0;
1559                                 return buf;
1560                         }
1561                 }
1562                 start = 0;
1563         }
1564
1565         return NULL;
1566 }
1567 #endif
1568
1569 void radeon_freelist_reset( drm_device_t *dev )
1570 {
1571         drm_device_dma_t *dma = dev->dma;
1572         drm_radeon_private_t *dev_priv = dev->dev_private;
1573         int i;
1574
1575         dev_priv->last_buf = 0;
1576         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1577                 drm_buf_t *buf = dma->buflist[i];
1578                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1579                 buf_priv->age = 0;
1580         }
1581 }
1582
1583
1584 /* ================================================================
1585  * CP command submission
1586  */
1587
1588 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1589 {
1590         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1591         int i;
1592         u32 last_head = GET_RING_HEAD( dev_priv );
1593
1594         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1595                 u32 head = GET_RING_HEAD( dev_priv );
1596
1597                 ring->space = (head - ring->tail) * sizeof(u32);
1598                 if ( ring->space <= 0 )
1599                         ring->space += ring->size;
1600                 if ( ring->space > n )
1601                         return 0;
1602
1603                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1604
1605                 if (head != last_head)
1606                         i = 0;
1607                 last_head = head;
1608
1609                 DRM_UDELAY( 1 );
1610         }
1611
1612         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1613 #if RADEON_FIFO_DEBUG
1614         radeon_status( dev_priv );
1615         DRM_ERROR( "failed!\n" );
1616 #endif
1617         return DRM_ERR(EBUSY);
1618 }
1619
1620 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1621 {
1622         int i;
1623         drm_buf_t *buf;
1624
1625         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1626                 buf = radeon_freelist_get( dev );
1627                 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1628
1629                 buf->filp = filp;
1630
1631                 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1632                                    sizeof(buf->idx) ) )
1633                         return DRM_ERR(EFAULT);
1634                 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1635                                    sizeof(buf->total) ) )
1636                         return DRM_ERR(EFAULT);
1637
1638                 d->granted_count++;
1639         }
1640         return 0;
1641 }
1642
1643 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1644 {
1645         DRM_DEVICE;
1646         drm_device_dma_t *dma = dev->dma;
1647         int ret = 0;
1648         drm_dma_t d;
1649
1650         LOCK_TEST_WITH_RETURN( dev, filp );
1651
1652         DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1653
1654         /* Please don't send us buffers.
1655          */
1656         if ( d.send_count != 0 ) {
1657                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1658                            DRM_CURRENTPID, d.send_count );
1659                 return DRM_ERR(EINVAL);
1660         }
1661
1662         /* We'll send you buffers.
1663          */
1664         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1665                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1666                            DRM_CURRENTPID, d.request_count, dma->buf_count );
1667                 return DRM_ERR(EINVAL);
1668         }
1669
1670         d.granted_count = 0;
1671
1672         if ( d.request_count ) {
1673                 ret = radeon_cp_get_buffers( filp, dev, &d );
1674         }
1675
1676         DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
1677
1678         return ret;
1679 }