sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  */
  32
  33 /*
  34  * The following controllers are supported by this driver:
  35  *   BCM5706C A2, A3
  36  *   BCM5706S A2, A3
  37  *   BCM5708C B1, B2
  38  *   BCM5708S B1, B2
  39  *   BCM5709C A1, C0
  40  *   BCM5716  C0
  41  *
  42  * The following controllers are not supported by this driver:
  43  *   BCM5706C A0, A1
  44  *   BCM5706S A0, A1
  45  *   BCM5708C A0, B0
  46  *   BCM5708S A0, B0
  47  *   BCM5709C A0, B0, B1
  48  *   BCM5709S A0, A1, B0, B1, B2, C0
  49  */
  50
  51 #include "opt_bce.h"
  52 #include "opt_polling.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/bus.h>
  56 #include <sys/endian.h>
  57 #include <sys/kernel.h>
  58 #include <sys/interrupt.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/queue.h>
  62 #ifdef BCE_DEBUG
  63 #include <sys/random.h>
  64 #endif
  65 #include <sys/rman.h>
  66 #include <sys/serialize.h>
  67 #include <sys/socket.h>
  68 #include <sys/sockio.h>
  69 #include <sys/sysctl.h>
  70
  71 #include <net/bpf.h>
  72 #include <net/ethernet.h>
  73 #include <net/if.h>
  74 #include <net/if_arp.h>
  75 #include <net/if_dl.h>
  76 #include <net/if_media.h>
  77 #include <net/if_types.h>
  78 #include <net/ifq_var.h>
  79 #include <net/vlan/if_vlan_var.h>
  80 #include <net/vlan/if_vlan_ether.h>
  81
  82 #include <dev/netif/mii_layer/mii.h>
  83 #include <dev/netif/mii_layer/miivar.h>
  84
  85 #include <bus/pci/pcireg.h>
  86 #include <bus/pci/pcivar.h>
  87
  88 #include "miibus_if.h"
  89
  90 #include <dev/netif/bce/if_bcereg.h>
  91 #include <dev/netif/bce/if_bcefw.h>
  92
  93 /****************************************************************************/
  94 /* BCE Debug Options                                                        */
  95 /****************************************************************************/
  96 #ifdef BCE_DEBUG
  97
  98 static uint32_t bce_debug = BCE_WARN;
  99
 100 /*
 101  *          0 = Never
 102  *          1 = 1 in 2,147,483,648
 103  *        256 = 1 in     8,388,608
 104  *       2048 = 1 in     1,048,576
 105  *      65536 = 1 in        32,768
 106  *    1048576 = 1 in         2,048
 107  *  268435456 = 1 in             8
 108  *  536870912 = 1 in             4
 109  * 1073741824 = 1 in             2
 110  *
 111  * bce_debug_l2fhdr_status_check:
 112  *     How often the l2_fhdr frame error check will fail.
 113  *
 114  * bce_debug_unexpected_attention:
 115  *     How often the unexpected attention check will fail.
 116  *
 117  * bce_debug_mbuf_allocation_failure:
 118  *     How often to simulate an mbuf allocation failure.
 119  *
 120  * bce_debug_dma_map_addr_failure:
 121  *     How often to simulate a DMA mapping failure.
 122  *
 123  * bce_debug_bootcode_running_failure:
 124  *     How often to simulate a bootcode failure.
 125  */
 126 static int      bce_debug_l2fhdr_status_check = 0;
 127 static int      bce_debug_unexpected_attention = 0;
 128 static int      bce_debug_mbuf_allocation_failure = 0;
 129 static int      bce_debug_dma_map_addr_failure = 0;
 130 static int      bce_debug_bootcode_running_failure = 0;
 131
 132 #endif  /* BCE_DEBUG */
 133
 134
 135 /****************************************************************************/
 136 /* PCI Device ID Table                                                      */
 137 /*                                                                          */
 138 /* Used by bce_probe() to identify the devices supported by this driver.    */
 139 /****************************************************************************/
 140 #define BCE_DEVDESC_MAX         64
 141
 142 static struct bce_type bce_devs[] = {
 143         /* BCM5706C Controllers and OEM boards. */
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 145                 "HP NC370T Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 147                 "HP NC370i Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 149                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 151                 "HP NC371i Multifunction Gigabit Server Adapter" },
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 153                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 154
 155         /* BCM5706S controllers and OEM boards. */
 156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 157                 "HP NC370F Multifunction Gigabit Server Adapter" },
 158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 159                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 160
 161         /* BCM5708C controllers and OEM boards. */
 162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 163                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 165                 "HP NC373i Multifunction Gigabit Server Adapter" },
 166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 167                 "HP NC374m PCIe Multifunction Adapter" },
 168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 169                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 170
 171         /* BCM5708S controllers and OEM boards. */
 172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 173                 "HP NC373m Multifunction Gigabit Server Adapter" },
 174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 175                 "HP NC373i Multifunction Gigabit Server Adapter" },
 176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 177                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 179                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 180
 181         /* BCM5709C controllers and OEM boards. */
 182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 183                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 185                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 187                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 188
 189         /* BCM5709S controllers and OEM boards. */
 190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 191                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 193                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 195                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 196
 197         /* BCM5716 controllers and OEM boards. */
 198         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
 199                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 200
 201         { 0, 0, 0, 0, NULL }
 202 };
 203
 204
 205 /****************************************************************************/
 206 /* Supported Flash NVRAM device data.                                       */
 207 /****************************************************************************/
 208 static const struct flash_spec flash_table[] =
 209 {
 210 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 211 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 212
 213         /* Slow EEPROM */
 214         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 215          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 216          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 217          "EEPROM - slow"},
 218         /* Expansion entry 0001 */
 219         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 220          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 221          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 222          "Entry 0001"},
 223         /* Saifun SA25F010 (non-buffered flash) */
 224         /* strap, cfg1, & write1 need updates */
 225         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 226          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 227          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 228          "Non-buffered flash (128kB)"},
 229         /* Saifun SA25F020 (non-buffered flash) */
 230         /* strap, cfg1, & write1 need updates */
 231         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 232          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 233          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 234          "Non-buffered flash (256kB)"},
 235         /* Expansion entry 0100 */
 236         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 237          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 238          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 239          "Entry 0100"},
 240         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 241         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 242          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 243          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 244          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 245         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 246         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 247          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 248          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 249          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 250         /* Saifun SA25F005 (non-buffered flash) */
 251         /* strap, cfg1, & write1 need updates */
 252         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 253          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 254          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 255          "Non-buffered flash (64kB)"},
 256         /* Fast EEPROM */
 257         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 258          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 259          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 260          "EEPROM - fast"},
 261         /* Expansion entry 1001 */
 262         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 263          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 264          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 265          "Entry 1001"},
 266         /* Expansion entry 1010 */
 267         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 268          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 269          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 270          "Entry 1010"},
 271         /* ATMEL AT45DB011B (buffered flash) */
 272         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 273          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 274          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 275          "Buffered flash (128kB)"},
 276         /* Expansion entry 1100 */
 277         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 278          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 279          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 280          "Entry 1100"},
 281         /* Expansion entry 1101 */
 282         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 283          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 284          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 285          "Entry 1101"},
 286         /* Ateml Expansion entry 1110 */
 287         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 288          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 289          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 290          "Entry 1110 (Atmel)"},
 291         /* ATMEL AT45DB021B (buffered flash) */
 292         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 293          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 294          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 295          "Buffered flash (256kB)"},
 296 };
 297
 298 /*
 299  * The BCM5709 controllers transparently handle the
 300  * differences between Atmel 264 byte pages and all
 301  * flash devices which use 256 byte pages, so no
 302  * logical-to-physical mapping is required in the
 303  * driver.
 304  */
 305 static struct flash_spec flash_5709 = {
 306         .flags          = BCE_NV_BUFFERED,
 307         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 308         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 309         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 310         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 311         .name           = "5709/5716 buffered flash (256kB)",
 312 };
 313
 314
 315 /****************************************************************************/
 316 /* DragonFly device entry points.                                           */
 317 /****************************************************************************/
 318 static int      bce_probe(device_t);
 319 static int      bce_attach(device_t);
 320 static int      bce_detach(device_t);
 321 static void     bce_shutdown(device_t);
 322
 323 /****************************************************************************/
 324 /* BCE Debug Data Structure Dump Routines                                   */
 325 /****************************************************************************/
 326 #ifdef BCE_DEBUG
 327 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 328 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 329 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 330 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 331 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 332 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 333                                 struct l2_fhdr *) __unused;
 334 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 335 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 336 static void     bce_dump_status_block(struct bce_softc *);
 337 static void     bce_dump_driver_state(struct bce_softc *);
 338 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 339 static void     bce_dump_hw_state(struct bce_softc *);
 340 static void     bce_dump_txp_state(struct bce_softc *);
 341 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 342 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 343 static void     bce_freeze_controller(struct bce_softc *) __unused;
 344 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 345 static void     bce_breakpoint(struct bce_softc *);
 346 #endif  /* BCE_DEBUG */
 347
 348
 349 /****************************************************************************/
 350 /* BCE Register/Memory Access Routines                                      */
 351 /****************************************************************************/
 352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 353 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 354 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 355 static int      bce_miibus_read_reg(device_t, int, int);
 356 static int      bce_miibus_write_reg(device_t, int, int, int);
 357 static void     bce_miibus_statchg(device_t);
 358
 359
 360 /****************************************************************************/
 361 /* BCE NVRAM Access Routines                                                */
 362 /****************************************************************************/
 363 static int      bce_acquire_nvram_lock(struct bce_softc *);
 364 static int      bce_release_nvram_lock(struct bce_softc *);
 365 static void     bce_enable_nvram_access(struct bce_softc *);
 366 static void     bce_disable_nvram_access(struct bce_softc *);
 367 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 368                                      uint32_t);
 369 static int      bce_init_nvram(struct bce_softc *);
 370 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 371 static int      bce_nvram_test(struct bce_softc *);
 372
 373 /****************************************************************************/
 374 /* BCE DMA Allocate/Free Routines                                           */
 375 /****************************************************************************/
 376 static int      bce_dma_alloc(struct bce_softc *);
 377 static void     bce_dma_free(struct bce_softc *);
 378 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 379
 380 /****************************************************************************/
 381 /* BCE Firmware Synchronization and Load                                    */
 382 /****************************************************************************/
 383 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 384 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 385                                  uint32_t, uint32_t);
 386 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 387                                 struct fw_info *);
 388 static void     bce_init_rxp_cpu(struct bce_softc *);
 389 static void     bce_init_txp_cpu(struct bce_softc *);
 390 static void     bce_init_tpat_cpu(struct bce_softc *);
 391 static void     bce_init_cp_cpu(struct bce_softc *);
 392 static void     bce_init_com_cpu(struct bce_softc *);
 393 static void     bce_init_cpus(struct bce_softc *);
 394
 395 static void     bce_stop(struct bce_softc *);
 396 static int      bce_reset(struct bce_softc *, uint32_t);
 397 static int      bce_chipinit(struct bce_softc *);
 398 static int      bce_blockinit(struct bce_softc *);
 399 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
 400                                uint32_t *, int);
 401 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
 402 static void     bce_probe_pci_caps(struct bce_softc *);
 403 static void     bce_print_adapter_info(struct bce_softc *);
 404 static void     bce_get_media(struct bce_softc *);
 405
 406 static void     bce_init_tx_context(struct bce_softc *);
 407 static int      bce_init_tx_chain(struct bce_softc *);
 408 static void     bce_init_rx_context(struct bce_softc *);
 409 static int      bce_init_rx_chain(struct bce_softc *);
 410 static void     bce_free_rx_chain(struct bce_softc *);
 411 static void     bce_free_tx_chain(struct bce_softc *);
 412
 413 static int      bce_encap(struct bce_softc *, struct mbuf **);
 414 static void     bce_start(struct ifnet *);
 415 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 416 static void     bce_watchdog(struct ifnet *);
 417 static int      bce_ifmedia_upd(struct ifnet *);
 418 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 419 static void     bce_init(void *);
 420 static void     bce_mgmt_init(struct bce_softc *);
 421
 422 static void     bce_init_ctx(struct bce_softc *);
 423 static void     bce_get_mac_addr(struct bce_softc *);
 424 static void     bce_set_mac_addr(struct bce_softc *);
 425 static void     bce_phy_intr(struct bce_softc *);
 426 static void     bce_rx_intr(struct bce_softc *, int);
 427 static void     bce_tx_intr(struct bce_softc *);
 428 static void     bce_disable_intr(struct bce_softc *);
 429 static void     bce_enable_intr(struct bce_softc *, int);
 430
 431 #ifdef DEVICE_POLLING
 432 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 433 #endif
 434 static void     bce_intr(void *);
 435 static void     bce_set_rx_mode(struct bce_softc *);
 436 static void     bce_stats_update(struct bce_softc *);
 437 static void     bce_tick(void *);
 438 static void     bce_tick_serialized(struct bce_softc *);
 439 static void     bce_pulse(void *);
 440 static void     bce_add_sysctls(struct bce_softc *);
 441
 442 static void     bce_coal_change(struct bce_softc *);
 443 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 444 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 445 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 446 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 447 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 448 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 449 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 450 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 451 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 452                                        uint32_t *, uint32_t);
 453
 454 /*
 455  * NOTE:
 456  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 457  * takes 1023 as the TX ticks limit.  However, using 1023 will
 458  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 459  * there is _no_ network activity on the NIC.
 460  */
 461 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 462 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 463 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 464 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 465 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 466 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
 467 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
 468 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
 469
 470 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 471 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 472 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 473 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 474 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 475 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 476 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 477 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 478
 479 /****************************************************************************/
 480 /* DragonFly device dispatch table.                                         */
 481 /****************************************************************************/
 482 static device_method_t bce_methods[] = {
 483         /* Device interface */
 484         DEVMETHOD(device_probe,         bce_probe),
 485         DEVMETHOD(device_attach,        bce_attach),
 486         DEVMETHOD(device_detach,        bce_detach),
 487         DEVMETHOD(device_shutdown,      bce_shutdown),
 488
 489         /* bus interface */
 490         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 491         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 492
 493         /* MII interface */
 494         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 495         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 496         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 497
 498         { 0, 0 }
 499 };
 500
 501 static driver_t bce_driver = {
 502         "bce",
 503         bce_methods,
 504         sizeof(struct bce_softc)
 505 };
 506
 507 static devclass_t bce_devclass;
 508
 509
 510 DECLARE_DUMMY_MODULE(if_bce);
 511 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 512 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
 513 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 514
 515
 516 /****************************************************************************/
 517 /* Device probe function.                                                   */
 518 /*                                                                          */
 519 /* Compares the device to the driver's list of supported devices and        */
 520 /* reports back to the OS whether this is the right driver for the device.  */
 521 /*                                                                          */
 522 /* Returns:                                                                 */
 523 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 524 /****************************************************************************/
 525 static int
 526 bce_probe(device_t dev)
 527 {
 528         struct bce_type *t;
 529         uint16_t vid, did, svid, sdid;
 530
 531         /* Get the data for the device to be probed. */
 532         vid  = pci_get_vendor(dev);
 533         did  = pci_get_device(dev);
 534         svid = pci_get_subvendor(dev);
 535         sdid = pci_get_subdevice(dev);
 536
 537         /* Look through the list of known devices for a match. */
 538         for (t = bce_devs; t->bce_name != NULL; ++t) {
 539                 if (vid == t->bce_vid && did == t->bce_did &&
 540                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 541                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 542                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 543                         char *descbuf;
 544
 545                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 546
 547                         /* Print out the device identity. */
 548                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 549                                   t->bce_name,
 550                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 551
 552                         device_set_desc_copy(dev, descbuf);
 553                         kfree(descbuf, M_TEMP);
 554                         return 0;
 555                 }
 556         }
 557         return ENXIO;
 558 }
 559
 560
 561 /****************************************************************************/
 562 /* PCI Capabilities Probe Function.                                         */
 563 /*                                                                          */
 564 /* Walks the PCI capabiites list for the device to find what features are   */
 565 /* supported.                                                               */
 566 /*                                                                          */
 567 /* Returns:                                                                 */
 568 /*   None.                                                                  */
 569 /****************************************************************************/
 570 static void
 571 bce_print_adapter_info(struct bce_softc *sc)
 572 {
 573         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
 574
 575         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 576                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 577
 578         /* Bus info. */
 579         if (sc->bce_flags & BCE_PCIE_FLAG) {
 580                 kprintf("Bus (PCIe x%d, ", sc->link_width);
 581                 switch (sc->link_speed) {
 582                 case 1:
 583                         kprintf("2.5Gbps); ");
 584                         break;
 585                 case 2:
 586                         kprintf("5Gbps); ");
 587                         break;
 588                 default:
 589                         kprintf("Unknown link speed); ");
 590                         break;
 591                 }
 592         } else {
 593                 kprintf("Bus (PCI%s, %s, %dMHz); ",
 594                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 595                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
 596                     sc->bus_speed_mhz);
 597         }
 598
 599         /* Firmware version and device features. */
 600         kprintf("B/C (0x%08X)", sc->bce_bc_ver);
 601
 602         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
 603             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 604                 kprintf("; Flags(");
 605                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
 606                         kprintf("MFW");
 607                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 608                         kprintf(" 2.5G");
 609                 kprintf(")");
 610         }
 611         kprintf("\n");
 612 }
 613
 614
 615 /****************************************************************************/
 616 /* PCI Capabilities Probe Function.                                         */
 617 /*                                                                          */
 618 /* Walks the PCI capabiites list for the device to find what features are   */
 619 /* supported.                                                               */
 620 /*                                                                          */
 621 /* Returns:                                                                 */
 622 /*   None.                                                                  */
 623 /****************************************************************************/
 624 static void
 625 bce_probe_pci_caps(struct bce_softc *sc)
 626 {
 627         device_t dev = sc->bce_dev;
 628         uint8_t ptr;
 629
 630         if (pci_is_pcix(dev))
 631                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 632
 633         ptr = pci_get_pciecap_ptr(dev);
 634         if (ptr) {
 635                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
 636
 637                 sc->link_speed = link_status & 0xf;
 638                 sc->link_width = (link_status >> 4) & 0x3f;
 639                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 640                 sc->bce_flags |= BCE_PCIE_FLAG;
 641         }
 642 }
 643
 644
 645 /****************************************************************************/
 646 /* Device attach function.                                                  */
 647 /*                                                                          */
 648 /* Allocates device resources, performs secondary chip identification,      */
 649 /* resets and initializes the hardware, and initializes driver instance     */
 650 /* variables.                                                               */
 651 /*                                                                          */
 652 /* Returns:                                                                 */
 653 /*   0 on success, positive value on failure.                               */
 654 /****************************************************************************/
 655 static int
 656 bce_attach(device_t dev)
 657 {
 658         struct bce_softc *sc = device_get_softc(dev);
 659         struct ifnet *ifp = &sc->arpcom.ac_if;
 660         uint32_t val;
 661         int rid, rc = 0;
 662 #ifdef notyet
 663         int count;
 664 #endif
 665
 666         sc->bce_dev = dev;
 667         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 668
 669         pci_enable_busmaster(dev);
 670
 671         bce_probe_pci_caps(sc);
 672
 673         /* Allocate PCI memory resources. */
 674         rid = PCIR_BAR(0);
 675         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 676                                                  RF_ACTIVE | PCI_RF_DENSE);
 677         if (sc->bce_res_mem == NULL) {
 678                 device_printf(dev, "PCI memory allocation failed\n");
 679                 return ENXIO;
 680         }
 681         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 682         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 683
 684         /* Allocate PCI IRQ resources. */
 685 #ifdef notyet
 686         count = pci_msi_count(dev);
 687         if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
 688                 rid = 1;
 689                 sc->bce_flags |= BCE_USING_MSI_FLAG;
 690         } else
 691 #endif
 692         rid = 0;
 693         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 694                                                  RF_SHAREABLE | RF_ACTIVE);
 695         if (sc->bce_res_irq == NULL) {
 696                 device_printf(dev, "PCI map interrupt failed\n");
 697                 rc = ENXIO;
 698                 goto fail;
 699         }
 700
 701         /*
 702          * Configure byte swap and enable indirect register access.
 703          * Rely on CPU to do target byte swapping on big endian systems.
 704          * Access to registers outside of PCI configurtion space are not
 705          * valid until this is done.
 706          */
 707         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 708                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 709                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 710
 711         /* Save ASIC revsion info. */
 712         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 713
 714         /* Weed out any non-production controller revisions. */
 715         switch(BCE_CHIP_ID(sc)) {
 716         case BCE_CHIP_ID_5706_A0:
 717         case BCE_CHIP_ID_5706_A1:
 718         case BCE_CHIP_ID_5708_A0:
 719         case BCE_CHIP_ID_5708_B0:
 720         case BCE_CHIP_ID_5709_A0:
 721         case BCE_CHIP_ID_5709_B0:
 722         case BCE_CHIP_ID_5709_B1:
 723 #ifdef foo
 724         /* 5709C B2 seems to work fine */
 725         case BCE_CHIP_ID_5709_B2:
 726 #endif
 727                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 728                               BCE_CHIP_ID(sc));
 729                 rc = ENODEV;
 730                 goto fail;
 731         }
 732
 733         /*
 734          * Find the base address for shared memory access.
 735          * Newer versions of bootcode use a signature and offset
 736          * while older versions use a fixed address.
 737          */
 738         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 739         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
 740             BCE_SHM_HDR_SIGNATURE_SIG) {
 741                 /* Multi-port devices use different offsets in shared memory. */
 742                 sc->bce_shmem_base = REG_RD_IND(sc,
 743                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
 744         } else {
 745                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 746         }
 747         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 748
 749         /* Fetch the bootcode revision. */
 750         sc->bce_bc_ver = REG_RD_IND(sc, sc->bce_shmem_base +
 751                 BCE_DEV_INFO_BC_REV);
 752
 753         /* Check if any management firmware is running. */
 754         val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
 755         if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED))
 756                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 757
 758         /* Get PCI bus information (speed and type). */
 759         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 760         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 761                 uint32_t clkreg;
 762
 763                 sc->bce_flags |= BCE_PCIX_FLAG;
 764
 765                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 766                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 767                 switch (clkreg) {
 768                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 769                         sc->bus_speed_mhz = 133;
 770                         break;
 771
 772                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 773                         sc->bus_speed_mhz = 100;
 774                         break;
 775
 776                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 777                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 778                         sc->bus_speed_mhz = 66;
 779                         break;
 780
 781                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 782                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 783                         sc->bus_speed_mhz = 50;
 784                         break;
 785
 786                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 787                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 788                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 789                         sc->bus_speed_mhz = 33;
 790                         break;
 791                 }
 792         } else {
 793                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 794                         sc->bus_speed_mhz = 66;
 795                 else
 796                         sc->bus_speed_mhz = 33;
 797         }
 798
 799         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 800                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 801
 802         /* Reset the controller. */
 803         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 804         if (rc != 0)
 805                 goto fail;
 806
 807         /* Initialize the controller. */
 808         rc = bce_chipinit(sc);
 809         if (rc != 0) {
 810                 device_printf(dev, "Controller initialization failed!\n");
 811                 goto fail;
 812         }
 813
 814         /* Perform NVRAM test. */
 815         rc = bce_nvram_test(sc);
 816         if (rc != 0) {
 817                 device_printf(dev, "NVRAM test failed!\n");
 818                 goto fail;
 819         }
 820
 821         /* Fetch the permanent Ethernet MAC address. */
 822         bce_get_mac_addr(sc);
 823
 824         /*
 825          * Trip points control how many BDs
 826          * should be ready before generating an
 827          * interrupt while ticks control how long
 828          * a BD can sit in the chain before
 829          * generating an interrupt.  Set the default
 830          * values for the RX and TX rings.
 831          */
 832
 833 #ifdef BCE_DRBUG
 834         /* Force more frequent interrupts. */
 835         sc->bce_tx_quick_cons_trip_int = 1;
 836         sc->bce_tx_quick_cons_trip     = 1;
 837         sc->bce_tx_ticks_int           = 0;
 838         sc->bce_tx_ticks               = 0;
 839
 840         sc->bce_rx_quick_cons_trip_int = 1;
 841         sc->bce_rx_quick_cons_trip     = 1;
 842         sc->bce_rx_ticks_int           = 0;
 843         sc->bce_rx_ticks               = 0;
 844 #else
 845         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 846         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 847         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 848         sc->bce_tx_ticks               = bce_tx_ticks;
 849
 850         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 851         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 852         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 853         sc->bce_rx_ticks               = bce_rx_ticks;
 854 #endif
 855
 856         /* Update statistics once every second. */
 857         sc->bce_stats_ticks = 1000000 & 0xffff00;
 858
 859         /* Find the media type for the adapter. */
 860         bce_get_media(sc);
 861
 862         /* Allocate DMA memory resources. */
 863         rc = bce_dma_alloc(sc);
 864         if (rc != 0) {
 865                 device_printf(dev, "DMA resource allocation failed!\n");
 866                 goto fail;
 867         }
 868
 869         /* Initialize the ifnet interface. */
 870         ifp->if_softc = sc;
 871         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 872         ifp->if_ioctl = bce_ioctl;
 873         ifp->if_start = bce_start;
 874         ifp->if_init = bce_init;
 875         ifp->if_watchdog = bce_watchdog;
 876 #ifdef DEVICE_POLLING
 877         ifp->if_poll = bce_poll;
 878 #endif
 879         ifp->if_mtu = ETHERMTU;
 880         ifp->if_hwassist = BCE_IF_HWASSIST;
 881         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 882         ifp->if_capenable = ifp->if_capabilities;
 883         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
 884         ifq_set_ready(&ifp->if_snd);
 885
 886         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 887                 ifp->if_baudrate = IF_Gbps(2.5);
 888         else
 889                 ifp->if_baudrate = IF_Gbps(1);
 890
 891         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 892         sc->mbuf_alloc_size  = MCLBYTES;
 893
 894         /* Look for our PHY. */
 895         rc = mii_phy_probe(dev, &sc->bce_miibus,
 896                            bce_ifmedia_upd, bce_ifmedia_sts);
 897         if (rc != 0) {
 898                 device_printf(dev, "PHY probe failed!\n");
 899                 goto fail;
 900         }
 901
 902         /* Attach to the Ethernet interface list. */
 903         ether_ifattach(ifp, sc->eaddr, NULL);
 904
 905         callout_init(&sc->bce_tick_callout);
 906         callout_init(&sc->bce_pulse_callout);
 907
 908         /* Hookup IRQ last. */
 909         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
 910                             &sc->bce_intrhand, ifp->if_serializer);
 911         if (rc != 0) {
 912                 device_printf(dev, "Failed to setup IRQ!\n");
 913                 ether_ifdetach(ifp);
 914                 goto fail;
 915         }
 916
 917         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
 918         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 919
 920         /* Print some important debugging info. */
 921         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 922
 923         /* Add the supported sysctls to the kernel. */
 924         bce_add_sysctls(sc);
 925
 926         /*
 927          * The chip reset earlier notified the bootcode that
 928          * a driver is present.  We now need to start our pulse
 929          * routine so that the bootcode is reminded that we're
 930          * still running.
 931          */
 932         bce_pulse(sc);
 933
 934         /* Get the firmware running so IPMI still works */
 935         bce_mgmt_init(sc);
 936
 937         bce_print_adapter_info(sc);
 938
 939         return 0;
 940 fail:
 941         bce_detach(dev);
 942         return(rc);
 943 }
 944
 945
 946 /****************************************************************************/
 947 /* Device detach function.                                                  */
 948 /*                                                                          */
 949 /* Stops the controller, resets the controller, and releases resources.     */
 950 /*                                                                          */
 951 /* Returns:                                                                 */
 952 /*   0 on success, positive value on failure.                               */
 953 /****************************************************************************/
 954 static int
 955 bce_detach(device_t dev)
 956 {
 957         struct bce_softc *sc = device_get_softc(dev);
 958
 959         if (device_is_attached(dev)) {
 960                 struct ifnet *ifp = &sc->arpcom.ac_if;
 961                 uint32_t msg;
 962
 963                 /* Stop and reset the controller. */
 964                 lwkt_serialize_enter(ifp->if_serializer);
 965                 callout_stop(&sc->bce_pulse_callout);
 966                 bce_stop(sc);
 967                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
 968                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
 969                 else
 970                         msg = BCE_DRV_MSG_CODE_UNLOAD;
 971                 bce_reset(sc, msg);
 972                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
 973                 lwkt_serialize_exit(ifp->if_serializer);
 974
 975                 ether_ifdetach(ifp);
 976         }
 977
 978         /* If we have a child device on the MII bus remove it too. */
 979         if (sc->bce_miibus)
 980                 device_delete_child(dev, sc->bce_miibus);
 981         bus_generic_detach(dev);
 982
 983         if (sc->bce_res_irq != NULL) {
 984                 bus_release_resource(dev, SYS_RES_IRQ,
 985                         sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
 986                         sc->bce_res_irq);
 987         }
 988
 989 #ifdef notyet
 990         if (sc->bce_flags & BCE_USING_MSI_FLAG)
 991                 pci_release_msi(dev);
 992 #endif
 993
 994         if (sc->bce_res_mem != NULL) {
 995                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
 996                                      sc->bce_res_mem);
 997         }
 998
 999         bce_dma_free(sc);
1000
1001         if (sc->bce_sysctl_tree != NULL)
1002                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1003
1004         return 0;
1005 }
1006
1007
1008 /****************************************************************************/
1009 /* Device shutdown function.                                                */
1010 /*                                                                          */
1011 /* Stops and resets the controller.                                         */
1012 /*                                                                          */
1013 /* Returns:                                                                 */
1014 /*   Nothing                                                                */
1015 /****************************************************************************/
1016 static void
1017 bce_shutdown(device_t dev)
1018 {
1019         struct bce_softc *sc = device_get_softc(dev);
1020         struct ifnet *ifp = &sc->arpcom.ac_if;
1021         uint32_t msg;
1022
1023         lwkt_serialize_enter(ifp->if_serializer);
1024         bce_stop(sc);
1025         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1026                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1027         else
1028                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1029         bce_reset(sc, msg);
1030         lwkt_serialize_exit(ifp->if_serializer);
1031 }
1032
1033
1034 /****************************************************************************/
1035 /* Indirect register read.                                                  */
1036 /*                                                                          */
1037 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1038 /* configuration space.  Using this mechanism avoids issues with posted     */
1039 /* reads but is much slower than memory-mapped I/O.                         */
1040 /*                                                                          */
1041 /* Returns:                                                                 */
1042 /*   The value of the register.                                             */
1043 /****************************************************************************/
1044 static uint32_t
1045 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1046 {
1047         device_t dev = sc->bce_dev;
1048
1049         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1050 #ifdef BCE_DEBUG
1051         {
1052                 uint32_t val;
1053                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1054                 DBPRINT(sc, BCE_EXCESSIVE,
1055                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1056                         __func__, offset, val);
1057                 return val;
1058         }
1059 #else
1060         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1061 #endif
1062 }
1063
1064
1065 /****************************************************************************/
1066 /* Indirect register write.                                                 */
1067 /*                                                                          */
1068 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1069 /* configuration space.  Using this mechanism avoids issues with posted     */
1070 /* writes but is muchh slower than memory-mapped I/O.                       */
1071 /*                                                                          */
1072 /* Returns:                                                                 */
1073 /*   Nothing.                                                               */
1074 /****************************************************************************/
1075 static void
1076 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1077 {
1078         device_t dev = sc->bce_dev;
1079
1080         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1081                 __func__, offset, val);
1082
1083         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1084         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1085 }
1086
1087
1088 /****************************************************************************/
1089 /* Context memory write.                                                    */
1090 /*                                                                          */
1091 /* The NetXtreme II controller uses context memory to track connection      */
1092 /* information for L2 and higher network protocols.                         */
1093 /*                                                                          */
1094 /* Returns:                                                                 */
1095 /*   Nothing.                                                               */
1096 /****************************************************************************/
1097 static void
1098 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1099     uint32_t ctx_val)
1100 {
1101         uint32_t idx, offset = ctx_offset + cid_addr;
1102         uint32_t val, retry_cnt = 5;
1103
1104         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1105             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1106                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1107                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1108
1109                 for (idx = 0; idx < retry_cnt; idx++) {
1110                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1111                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1112                                 break;
1113                         DELAY(5);
1114                 }
1115
1116                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1117                         device_printf(sc->bce_dev,
1118                             "Unable to write CTX memory: "
1119                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1120                             cid_addr, ctx_offset);
1121                 }
1122         } else {
1123                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1124                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1125         }
1126 }
1127
1128
1129 /****************************************************************************/
1130 /* PHY register read.                                                       */
1131 /*                                                                          */
1132 /* Implements register reads on the MII bus.                                */
1133 /*                                                                          */
1134 /* Returns:                                                                 */
1135 /*   The value of the register.                                             */
1136 /****************************************************************************/
1137 static int
1138 bce_miibus_read_reg(device_t dev, int phy, int reg)
1139 {
1140         struct bce_softc *sc = device_get_softc(dev);
1141         uint32_t val;
1142         int i;
1143
1144         /* Make sure we are accessing the correct PHY address. */
1145         if (phy != sc->bce_phy_addr) {
1146                 DBPRINT(sc, BCE_VERBOSE,
1147                         "Invalid PHY address %d for PHY read!\n", phy);
1148                 return 0;
1149         }
1150
1151         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1152                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1153                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1154
1155                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1156                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1157
1158                 DELAY(40);
1159         }
1160
1161         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1162               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1163               BCE_EMAC_MDIO_COMM_START_BUSY;
1164         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1165
1166         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1167                 DELAY(10);
1168
1169                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1170                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1171                         DELAY(5);
1172
1173                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1174                         val &= BCE_EMAC_MDIO_COMM_DATA;
1175                         break;
1176                 }
1177         }
1178
1179         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1180                 if_printf(&sc->arpcom.ac_if,
1181                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1182                           phy, reg);
1183                 val = 0x0;
1184         } else {
1185                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1186         }
1187
1188         DBPRINT(sc, BCE_EXCESSIVE,
1189                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1190                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1191
1192         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1193                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1194                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1195
1196                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1197                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1198
1199                 DELAY(40);
1200         }
1201         return (val & 0xffff);
1202 }
1203
1204
1205 /****************************************************************************/
1206 /* PHY register write.                                                      */
1207 /*                                                                          */
1208 /* Implements register writes on the MII bus.                               */
1209 /*                                                                          */
1210 /* Returns:                                                                 */
1211 /*   The value of the register.                                             */
1212 /****************************************************************************/
1213 static int
1214 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1215 {
1216         struct bce_softc *sc = device_get_softc(dev);
1217         uint32_t val1;
1218         int i;
1219
1220         /* Make sure we are accessing the correct PHY address. */
1221         if (phy != sc->bce_phy_addr) {
1222                 DBPRINT(sc, BCE_WARN,
1223                         "Invalid PHY address %d for PHY write!\n", phy);
1224                 return(0);
1225         }
1226
1227         DBPRINT(sc, BCE_EXCESSIVE,
1228                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1229                 __func__, phy, (uint16_t)(reg & 0xffff),
1230                 (uint16_t)(val & 0xffff));
1231
1232         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1233                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1234                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1235
1236                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1237                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1238
1239                 DELAY(40);
1240         }
1241
1242         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1243                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1244                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1245         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1246
1247         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1248                 DELAY(10);
1249
1250                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1251                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1252                         DELAY(5);
1253                         break;
1254                 }
1255         }
1256
1257         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1258                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1259
1260         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1261                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1262                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1263
1264                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1265                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1266
1267                 DELAY(40);
1268         }
1269         return 0;
1270 }
1271
1272
1273 /****************************************************************************/
1274 /* MII bus status change.                                                   */
1275 /*                                                                          */
1276 /* Called by the MII bus driver when the PHY establishes link to set the    */
1277 /* MAC interface registers.                                                 */
1278 /*                                                                          */
1279 /* Returns:                                                                 */
1280 /*   Nothing.                                                               */
1281 /****************************************************************************/
1282 static void
1283 bce_miibus_statchg(device_t dev)
1284 {
1285         struct bce_softc *sc = device_get_softc(dev);
1286         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1287
1288         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1289                 mii->mii_media_active);
1290
1291 #ifdef BCE_DEBUG
1292         /* Decode the interface media flags. */
1293         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1294         switch(IFM_TYPE(mii->mii_media_active)) {
1295         case IFM_ETHER:
1296                 kprintf("Ethernet )");
1297                 break;
1298         default:
1299                 kprintf("Unknown )");
1300                 break;
1301         }
1302
1303         kprintf(" Media Options: ( ");
1304         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1305         case IFM_AUTO:
1306                 kprintf("Autoselect )");
1307                 break;
1308         case IFM_MANUAL:
1309                 kprintf("Manual )");
1310                 break;
1311         case IFM_NONE:
1312                 kprintf("None )");
1313                 break;
1314         case IFM_10_T:
1315                 kprintf("10Base-T )");
1316                 break;
1317         case IFM_100_TX:
1318                 kprintf("100Base-TX )");
1319                 break;
1320         case IFM_1000_SX:
1321                 kprintf("1000Base-SX )");
1322                 break;
1323         case IFM_1000_T:
1324                 kprintf("1000Base-T )");
1325                 break;
1326         default:
1327                 kprintf("Other )");
1328                 break;
1329         }
1330
1331         kprintf(" Global Options: (");
1332         if (mii->mii_media_active & IFM_FDX)
1333                 kprintf(" FullDuplex");
1334         if (mii->mii_media_active & IFM_HDX)
1335                 kprintf(" HalfDuplex");
1336         if (mii->mii_media_active & IFM_LOOP)
1337                 kprintf(" Loopback");
1338         if (mii->mii_media_active & IFM_FLAG0)
1339                 kprintf(" Flag0");
1340         if (mii->mii_media_active & IFM_FLAG1)
1341                 kprintf(" Flag1");
1342         if (mii->mii_media_active & IFM_FLAG2)
1343                 kprintf(" Flag2");
1344         kprintf(" )\n");
1345 #endif
1346
1347         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1348
1349         /*
1350          * Set MII or GMII interface based on the speed negotiated
1351          * by the PHY.
1352          */
1353         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1354             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1355                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1356                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1357         } else {
1358                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1359                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1360         }
1361
1362         /*
1363          * Set half or full duplex based on the duplicity negotiated
1364          * by the PHY.
1365          */
1366         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1367                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1368                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1369         } else {
1370                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1371                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1372         }
1373 }
1374
1375
1376 /****************************************************************************/
1377 /* Acquire NVRAM lock.                                                      */
1378 /*                                                                          */
1379 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1380 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1381 /* for use by the driver.                                                   */
1382 /*                                                                          */
1383 /* Returns:                                                                 */
1384 /*   0 on success, positive value on failure.                               */
1385 /****************************************************************************/
1386 static int
1387 bce_acquire_nvram_lock(struct bce_softc *sc)
1388 {
1389         uint32_t val;
1390         int j;
1391
1392         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1393
1394         /* Request access to the flash interface. */
1395         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1396         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1397                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1398                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1399                         break;
1400
1401                 DELAY(5);
1402         }
1403
1404         if (j >= NVRAM_TIMEOUT_COUNT) {
1405                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1406                 return EBUSY;
1407         }
1408         return 0;
1409 }
1410
1411
1412 /****************************************************************************/
1413 /* Release NVRAM lock.                                                      */
1414 /*                                                                          */
1415 /* When the caller is finished accessing NVRAM the lock must be released.   */
1416 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1417 /* for use by the driver.                                                   */
1418 /*                                                                          */
1419 /* Returns:                                                                 */
1420 /*   0 on success, positive value on failure.                               */
1421 /****************************************************************************/
1422 static int
1423 bce_release_nvram_lock(struct bce_softc *sc)
1424 {
1425         int j;
1426         uint32_t val;
1427
1428         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1429
1430         /*
1431          * Relinquish nvram interface.
1432          */
1433         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1434
1435         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1436                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1437                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1438                         break;
1439
1440                 DELAY(5);
1441         }
1442
1443         if (j >= NVRAM_TIMEOUT_COUNT) {
1444                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1445                 return EBUSY;
1446         }
1447         return 0;
1448 }
1449
1450
1451 /****************************************************************************/
1452 /* Enable NVRAM access.                                                     */
1453 /*                                                                          */
1454 /* Before accessing NVRAM for read or write operations the caller must      */
1455 /* enabled NVRAM access.                                                    */
1456 /*                                                                          */
1457 /* Returns:                                                                 */
1458 /*   Nothing.                                                               */
1459 /****************************************************************************/
1460 static void
1461 bce_enable_nvram_access(struct bce_softc *sc)
1462 {
1463         uint32_t val;
1464
1465         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1466
1467         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1468         /* Enable both bits, even on read. */
1469         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1470                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1471 }
1472
1473
1474 /****************************************************************************/
1475 /* Disable NVRAM access.                                                    */
1476 /*                                                                          */
1477 /* When the caller is finished accessing NVRAM access must be disabled.     */
1478 /*                                                                          */
1479 /* Returns:                                                                 */
1480 /*   Nothing.                                                               */
1481 /****************************************************************************/
1482 static void
1483 bce_disable_nvram_access(struct bce_softc *sc)
1484 {
1485         uint32_t val;
1486
1487         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1488
1489         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1490
1491         /* Disable both bits, even after read. */
1492         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1493                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1494 }
1495
1496
1497 /****************************************************************************/
1498 /* Read a dword (32 bits) from NVRAM.                                       */
1499 /*                                                                          */
1500 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1501 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1502 /*                                                                          */
1503 /* Returns:                                                                 */
1504 /*   0 on success and the 32 bit value read, positive value on failure.     */
1505 /****************************************************************************/
1506 static int
1507 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1508                      uint32_t cmd_flags)
1509 {
1510         uint32_t cmd;
1511         int i, rc = 0;
1512
1513         /* Build the command word. */
1514         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1515
1516         /* Calculate the offset for buffered flash. */
1517         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1518                 offset = ((offset / sc->bce_flash_info->page_size) <<
1519                           sc->bce_flash_info->page_bits) +
1520                          (offset % sc->bce_flash_info->page_size);
1521         }
1522
1523         /*
1524          * Clear the DONE bit separately, set the address to read,
1525          * and issue the read.
1526          */
1527         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1528         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1529         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1530
1531         /* Wait for completion. */
1532         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1533                 uint32_t val;
1534
1535                 DELAY(5);
1536
1537                 val = REG_RD(sc, BCE_NVM_COMMAND);
1538                 if (val & BCE_NVM_COMMAND_DONE) {
1539                         val = REG_RD(sc, BCE_NVM_READ);
1540
1541                         val = be32toh(val);
1542                         memcpy(ret_val, &val, 4);
1543                         break;
1544                 }
1545         }
1546
1547         /* Check for errors. */
1548         if (i >= NVRAM_TIMEOUT_COUNT) {
1549                 if_printf(&sc->arpcom.ac_if,
1550                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1551                           offset);
1552                 rc = EBUSY;
1553         }
1554         return rc;
1555 }
1556
1557
1558 /****************************************************************************/
1559 /* Initialize NVRAM access.                                                 */
1560 /*                                                                          */
1561 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1562 /* access that device.                                                      */
1563 /*                                                                          */
1564 /* Returns:                                                                 */
1565 /*   0 on success, positive value on failure.                               */
1566 /****************************************************************************/
1567 static int
1568 bce_init_nvram(struct bce_softc *sc)
1569 {
1570         uint32_t val;
1571         int j, entry_count, rc = 0;
1572         const struct flash_spec *flash;
1573
1574         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1575
1576         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1577             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1578                 sc->bce_flash_info = &flash_5709;
1579                 goto bce_init_nvram_get_flash_size;
1580         }
1581
1582         /* Determine the selected interface. */
1583         val = REG_RD(sc, BCE_NVM_CFG1);
1584
1585         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1586
1587         /*
1588          * Flash reconfiguration is required to support additional
1589          * NVRAM devices not directly supported in hardware.
1590          * Check if the flash interface was reconfigured
1591          * by the bootcode.
1592          */
1593
1594         if (val & 0x40000000) {
1595                 /* Flash interface reconfigured by bootcode. */
1596
1597                 DBPRINT(sc, BCE_INFO_LOAD,
1598                         "%s(): Flash WAS reconfigured.\n", __func__);
1599
1600                 for (j = 0, flash = flash_table; j < entry_count;
1601                      j++, flash++) {
1602                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1603                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1604                                 sc->bce_flash_info = flash;
1605                                 break;
1606                         }
1607                 }
1608         } else {
1609                 /* Flash interface not yet reconfigured. */
1610                 uint32_t mask;
1611
1612                 DBPRINT(sc, BCE_INFO_LOAD,
1613                         "%s(): Flash was NOT reconfigured.\n", __func__);
1614
1615                 if (val & (1 << 23))
1616                         mask = FLASH_BACKUP_STRAP_MASK;
1617                 else
1618                         mask = FLASH_STRAP_MASK;
1619
1620                 /* Look for the matching NVRAM device configuration data. */
1621                 for (j = 0, flash = flash_table; j < entry_count;
1622                      j++, flash++) {
1623                         /* Check if the device matches any of the known devices. */
1624                         if ((val & mask) == (flash->strapping & mask)) {
1625                                 /* Found a device match. */
1626                                 sc->bce_flash_info = flash;
1627
1628                                 /* Request access to the flash interface. */
1629                                 rc = bce_acquire_nvram_lock(sc);
1630                                 if (rc != 0)
1631                                         return rc;
1632
1633                                 /* Reconfigure the flash interface. */
1634                                 bce_enable_nvram_access(sc);
1635                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1636                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1637                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1638                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1639                                 bce_disable_nvram_access(sc);
1640                                 bce_release_nvram_lock(sc);
1641                                 break;
1642                         }
1643                 }
1644         }
1645
1646         /* Check if a matching device was found. */
1647         if (j == entry_count) {
1648                 sc->bce_flash_info = NULL;
1649                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1650                 rc = ENODEV;
1651         }
1652
1653 bce_init_nvram_get_flash_size:
1654         /* Write the flash config data to the shared memory interface. */
1655         val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2) &
1656               BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1657         if (val)
1658                 sc->bce_flash_size = val;
1659         else
1660                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1661
1662         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1663                 __func__, sc->bce_flash_info->total_size);
1664
1665         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1666
1667         return rc;
1668 }
1669
1670
1671 /****************************************************************************/
1672 /* Read an arbitrary range of data from NVRAM.                              */
1673 /*                                                                          */
1674 /* Prepares the NVRAM interface for access and reads the requested data     */
1675 /* into the supplied buffer.                                                */
1676 /*                                                                          */
1677 /* Returns:                                                                 */
1678 /*   0 on success and the data read, positive value on failure.             */
1679 /****************************************************************************/
1680 static int
1681 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1682                int buf_size)
1683 {
1684         uint32_t cmd_flags, offset32, len32, extra;
1685         int rc = 0;
1686
1687         if (buf_size == 0)
1688                 return 0;
1689
1690         /* Request access to the flash interface. */
1691         rc = bce_acquire_nvram_lock(sc);
1692         if (rc != 0)
1693                 return rc;
1694
1695         /* Enable access to flash interface */
1696         bce_enable_nvram_access(sc);
1697
1698         len32 = buf_size;
1699         offset32 = offset;
1700         extra = 0;
1701
1702         cmd_flags = 0;
1703
1704         /* XXX should we release nvram lock if read_dword() fails? */
1705         if (offset32 & 3) {
1706                 uint8_t buf[4];
1707                 uint32_t pre_len;
1708
1709                 offset32 &= ~3;
1710                 pre_len = 4 - (offset & 3);
1711
1712                 if (pre_len >= len32) {
1713                         pre_len = len32;
1714                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1715                 } else {
1716                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1717                 }
1718
1719                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1720                 if (rc)
1721                         return rc;
1722
1723                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1724
1725                 offset32 += 4;
1726                 ret_buf += pre_len;
1727                 len32 -= pre_len;
1728         }
1729
1730         if (len32 & 3) {
1731                 extra = 4 - (len32 & 3);
1732                 len32 = (len32 + 4) & ~3;
1733         }
1734
1735         if (len32 == 4) {
1736                 uint8_t buf[4];
1737
1738                 if (cmd_flags)
1739                         cmd_flags = BCE_NVM_COMMAND_LAST;
1740                 else
1741                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1742                                     BCE_NVM_COMMAND_LAST;
1743
1744                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1745
1746                 memcpy(ret_buf, buf, 4 - extra);
1747         } else if (len32 > 0) {
1748                 uint8_t buf[4];
1749
1750                 /* Read the first word. */
1751                 if (cmd_flags)
1752                         cmd_flags = 0;
1753                 else
1754                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1755
1756                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1757
1758                 /* Advance to the next dword. */
1759                 offset32 += 4;
1760                 ret_buf += 4;
1761                 len32 -= 4;
1762
1763                 while (len32 > 4 && rc == 0) {
1764                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1765
1766                         /* Advance to the next dword. */
1767                         offset32 += 4;
1768                         ret_buf += 4;
1769                         len32 -= 4;
1770                 }
1771
1772                 if (rc)
1773                         goto bce_nvram_read_locked_exit;
1774
1775                 cmd_flags = BCE_NVM_COMMAND_LAST;
1776                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1777
1778                 memcpy(ret_buf, buf, 4 - extra);
1779         }
1780
1781 bce_nvram_read_locked_exit:
1782         /* Disable access to flash interface and release the lock. */
1783         bce_disable_nvram_access(sc);
1784         bce_release_nvram_lock(sc);
1785
1786         return rc;
1787 }
1788
1789
1790 /****************************************************************************/
1791 /* Verifies that NVRAM is accessible and contains valid data.               */
1792 /*                                                                          */
1793 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1794 /* correct.                                                                 */
1795 /*                                                                          */
1796 /* Returns:                                                                 */
1797 /*   0 on success, positive value on failure.                               */
1798 /****************************************************************************/
1799 static int
1800 bce_nvram_test(struct bce_softc *sc)
1801 {
1802         uint32_t buf[BCE_NVRAM_SIZE / 4];
1803         uint32_t magic, csum;
1804         uint8_t *data = (uint8_t *)buf;
1805         int rc = 0;
1806
1807         /*
1808          * Check that the device NVRAM is valid by reading
1809          * the magic value at offset 0.
1810          */
1811         rc = bce_nvram_read(sc, 0, data, 4);
1812         if (rc != 0)
1813                 return rc;
1814
1815         magic = be32toh(buf[0]);
1816         if (magic != BCE_NVRAM_MAGIC) {
1817                 if_printf(&sc->arpcom.ac_if,
1818                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1819                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1820                 return ENODEV;
1821         }
1822
1823         /*
1824          * Verify that the device NVRAM includes valid
1825          * configuration data.
1826          */
1827         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1828         if (rc != 0)
1829                 return rc;
1830
1831         csum = ether_crc32_le(data, 0x100);
1832         if (csum != BCE_CRC32_RESIDUAL) {
1833                 if_printf(&sc->arpcom.ac_if,
1834                           "Invalid Manufacturing Information NVRAM CRC! "
1835                           "Expected: 0x%08X, Found: 0x%08X\n",
1836                           BCE_CRC32_RESIDUAL, csum);
1837                 return ENODEV;
1838         }
1839
1840         csum = ether_crc32_le(data + 0x100, 0x100);
1841         if (csum != BCE_CRC32_RESIDUAL) {
1842                 if_printf(&sc->arpcom.ac_if,
1843                           "Invalid Feature Configuration Information "
1844                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1845                           BCE_CRC32_RESIDUAL, csum);
1846                 rc = ENODEV;
1847         }
1848         return rc;
1849 }
1850
1851
1852 /****************************************************************************/
1853 /* Identifies the current media type of the controller and sets the PHY     */
1854 /* address.                                                                 */
1855 /*                                                                          */
1856 /* Returns:                                                                 */
1857 /*   Nothing.                                                               */
1858 /****************************************************************************/
1859 static void
1860 bce_get_media(struct bce_softc *sc)
1861 {
1862         uint32_t val;
1863
1864         sc->bce_phy_addr = 1;
1865
1866         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1867             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1868                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1869                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1870                 uint32_t strap;
1871
1872                 /*
1873                  * The BCM5709S is software configurable
1874                  * for Copper or SerDes operation.
1875                  */
1876                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1877                         return;
1878                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1879                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1880                         return;
1881                 }
1882
1883                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1884                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1885                 } else {
1886                         strap =
1887                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1888                 }
1889
1890                 if (pci_get_function(sc->bce_dev) == 0) {
1891                         switch (strap) {
1892                         case 0x4:
1893                         case 0x5:
1894                         case 0x6:
1895                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1896                                 break;
1897                         }
1898                 } else {
1899                         switch (strap) {
1900                         case 0x1:
1901                         case 0x2:
1902                         case 0x4:
1903                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1904                                 break;
1905                         }
1906                 }
1907         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1908                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1909         }
1910
1911         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1912                 sc->bce_flags |= BCE_NO_WOL_FLAG;
1913                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1914                         sc->bce_phy_addr = 2;
1915                         val = REG_RD_IND(sc, sc->bce_shmem_base +
1916                             BCE_SHARED_HW_CFG_CONFIG);
1917                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1918                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1919                 }
1920         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1921             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1922                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1923         }
1924 }
1925
1926
1927 /****************************************************************************/
1928 /* Free any DMA memory owned by the driver.                                 */
1929 /*                                                                          */
1930 /* Scans through each data structre that requires DMA memory and frees      */
1931 /* the memory if allocated.                                                 */
1932 /*                                                                          */
1933 /* Returns:                                                                 */
1934 /*   Nothing.                                                               */
1935 /****************************************************************************/
1936 static void
1937 bce_dma_free(struct bce_softc *sc)
1938 {
1939         int i;
1940
1941         /* Destroy the status block. */
1942         if (sc->status_tag != NULL) {
1943                 if (sc->status_block != NULL) {
1944                         bus_dmamap_unload(sc->status_tag, sc->status_map);
1945                         bus_dmamem_free(sc->status_tag, sc->status_block,
1946                                         sc->status_map);
1947                 }
1948                 bus_dma_tag_destroy(sc->status_tag);
1949         }
1950
1951
1952         /* Destroy the statistics block. */
1953         if (sc->stats_tag != NULL) {
1954                 if (sc->stats_block != NULL) {
1955                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
1956                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
1957                                         sc->stats_map);
1958                 }
1959                 bus_dma_tag_destroy(sc->stats_tag);
1960         }
1961
1962         /* Destroy the CTX DMA stuffs. */
1963         if (sc->ctx_tag != NULL) {
1964                 for (i = 0; i < sc->ctx_pages; i++) {
1965                         if (sc->ctx_block[i] != NULL) {
1966                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
1967                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
1968                                                 sc->ctx_map[i]);
1969                         }
1970                 }
1971                 bus_dma_tag_destroy(sc->ctx_tag);
1972         }
1973
1974         /* Destroy the TX buffer descriptor DMA stuffs. */
1975         if (sc->tx_bd_chain_tag != NULL) {
1976                 for (i = 0; i < TX_PAGES; i++) {
1977                         if (sc->tx_bd_chain[i] != NULL) {
1978                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
1979                                                   sc->tx_bd_chain_map[i]);
1980                                 bus_dmamem_free(sc->tx_bd_chain_tag,
1981                                                 sc->tx_bd_chain[i],
1982                                                 sc->tx_bd_chain_map[i]);
1983                         }
1984                 }
1985                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
1986         }
1987
1988         /* Destroy the RX buffer descriptor DMA stuffs. */
1989         if (sc->rx_bd_chain_tag != NULL) {
1990                 for (i = 0; i < RX_PAGES; i++) {
1991                         if (sc->rx_bd_chain[i] != NULL) {
1992                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
1993                                                   sc->rx_bd_chain_map[i]);
1994                                 bus_dmamem_free(sc->rx_bd_chain_tag,
1995                                                 sc->rx_bd_chain[i],
1996                                                 sc->rx_bd_chain_map[i]);
1997                         }
1998                 }
1999                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2000         }
2001
2002         /* Destroy the TX mbuf DMA stuffs. */
2003         if (sc->tx_mbuf_tag != NULL) {
2004                 for (i = 0; i < TOTAL_TX_BD; i++) {
2005                         /* Must have been unloaded in bce_stop() */
2006                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2007                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2008                                            sc->tx_mbuf_map[i]);
2009                 }
2010                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2011         }
2012
2013         /* Destroy the RX mbuf DMA stuffs. */
2014         if (sc->rx_mbuf_tag != NULL) {
2015                 for (i = 0; i < TOTAL_RX_BD; i++) {
2016                         /* Must have been unloaded in bce_stop() */
2017                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2018                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2019                                            sc->rx_mbuf_map[i]);
2020                 }
2021                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2022                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2023         }
2024
2025         /* Destroy the parent tag */
2026         if (sc->parent_tag != NULL)
2027                 bus_dma_tag_destroy(sc->parent_tag);
2028 }
2029
2030
2031 /****************************************************************************/
2032 /* Get DMA memory from the OS.                                              */
2033 /*                                                                          */
2034 /* Validates that the OS has provided DMA buffers in response to a          */
2035 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2036 /* When the callback is used the OS will return 0 for the mapping function  */
2037 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2038 /* failures back to the caller.                                             */
2039 /*                                                                          */
2040 /* Returns:                                                                 */
2041 /*   Nothing.                                                               */
2042 /****************************************************************************/
2043 static void
2044 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2045 {
2046         bus_addr_t *busaddr = arg;
2047
2048         /*
2049          * Simulate a mapping failure.
2050          * XXX not correct.
2051          */
2052         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2053                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2054                         __FILE__, __LINE__);
2055                 error = ENOMEM);
2056
2057         /* Check for an error and signal the caller that an error occurred. */
2058         if (error)
2059                 return;
2060
2061         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2062         *busaddr = segs->ds_addr;
2063 }
2064
2065
2066 /****************************************************************************/
2067 /* Allocate any DMA memory needed by the driver.                            */
2068 /*                                                                          */
2069 /* Allocates DMA memory needed for the various global structures needed by  */
2070 /* hardware.                                                                */
2071 /*                                                                          */
2072 /* Memory alignment requirements:                                           */
2073 /* -----------------+----------+----------+----------+----------+           */
2074 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2075 /* -----------------+----------+----------+----------+----------+           */
2076 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2077 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2078 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2079 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2080 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2081 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2082 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2083 /* -----------------+----------+----------+----------+----------+           */
2084 /*                                                                          */
2085 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2086 /*                                                                          */
2087 /* Returns:                                                                 */
2088 /*   0 for success, positive value for failure.                             */
2089 /****************************************************************************/
2090 static int
2091 bce_dma_alloc(struct bce_softc *sc)
2092 {
2093         struct ifnet *ifp = &sc->arpcom.ac_if;
2094         int i, j, rc = 0;
2095         bus_addr_t busaddr, max_busaddr;
2096         bus_size_t status_align, stats_align;
2097
2098         /*
2099          * The embedded PCIe to PCI-X bridge (EPB)
2100          * in the 5708 cannot address memory above
2101          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2102          */
2103         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2104                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2105         else
2106                 max_busaddr = BUS_SPACE_MAXADDR;
2107
2108         /*
2109          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2110          */
2111         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2112             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2113                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2114                 if (sc->ctx_pages == 0)
2115                         sc->ctx_pages = 1;
2116                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2117                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2118                             sc->ctx_pages);
2119                         return ENOMEM;
2120                 }
2121                 status_align = 16;
2122                 stats_align = 16;
2123         } else {
2124                 status_align = 8;
2125                 stats_align = 8;
2126         }
2127
2128         /*
2129          * Allocate the parent bus DMA tag appropriate for PCI.
2130          */
2131         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2132                                 max_busaddr, BUS_SPACE_MAXADDR,
2133                                 NULL, NULL,
2134                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2135                                 BUS_SPACE_MAXSIZE_32BIT,
2136                                 0, &sc->parent_tag);
2137         if (rc != 0) {
2138                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2139                 return rc;
2140         }
2141
2142         /*
2143          * Allocate status block.
2144          */
2145         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2146                                 status_align, BCE_STATUS_BLK_SZ,
2147                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2148                                 &sc->status_tag, &sc->status_map,
2149                                 &sc->status_block_paddr);
2150         if (sc->status_block == NULL) {
2151                 if_printf(ifp, "Could not allocate status block!\n");
2152                 return ENOMEM;
2153         }
2154
2155         /*
2156          * Allocate statistics block.
2157          */
2158         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2159                                 stats_align, BCE_STATS_BLK_SZ,
2160                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2161                                 &sc->stats_tag, &sc->stats_map,
2162                                 &sc->stats_block_paddr);
2163         if (sc->stats_block == NULL) {
2164                 if_printf(ifp, "Could not allocate statistics block!\n");
2165                 return ENOMEM;
2166         }
2167
2168         /*
2169          * Allocate context block, if needed
2170          */
2171         if (sc->ctx_pages != 0) {
2172                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2173                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2174                                         NULL, NULL,
2175                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2176                                         0, &sc->ctx_tag);
2177                 if (rc != 0) {
2178                         if_printf(ifp, "Could not allocate "
2179                                   "context block DMA tag!\n");
2180                         return rc;
2181                 }
2182
2183                 for (i = 0; i < sc->ctx_pages; i++) {
2184                         rc = bus_dmamem_alloc(sc->ctx_tag,
2185                                               (void **)&sc->ctx_block[i],
2186                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2187                                               BUS_DMA_COHERENT,
2188                                               &sc->ctx_map[i]);
2189                         if (rc != 0) {
2190                                 if_printf(ifp, "Could not allocate %dth context "
2191                                           "DMA memory!\n", i);
2192                                 return rc;
2193                         }
2194
2195                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2196                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2197                                              bce_dma_map_addr, &busaddr,
2198                                              BUS_DMA_WAITOK);
2199                         if (rc != 0) {
2200                                 if (rc == EINPROGRESS) {
2201                                         panic("%s coherent memory loading "
2202                                               "is still in progress!", ifp->if_xname);
2203                                 }
2204                                 if_printf(ifp, "Could not map %dth context "
2205                                           "DMA memory!\n", i);
2206                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2207                                                 sc->ctx_map[i]);
2208                                 sc->ctx_block[i] = NULL;
2209                                 return rc;
2210                         }
2211                         sc->ctx_paddr[i] = busaddr;
2212                 }
2213         }
2214
2215         /*
2216          * Create a DMA tag for the TX buffer descriptor chain,
2217          * allocate and clear the  memory, and fetch the
2218          * physical address of the block.
2219          */
2220         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2221                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2222                                 NULL, NULL,
2223                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2224                                 0, &sc->tx_bd_chain_tag);
2225         if (rc != 0) {
2226                 if_printf(ifp, "Could not allocate "
2227                           "TX descriptor chain DMA tag!\n");
2228                 return rc;
2229         }
2230
2231         for (i = 0; i < TX_PAGES; i++) {
2232                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2233                                       (void **)&sc->tx_bd_chain[i],
2234                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2235                                       BUS_DMA_COHERENT,
2236                                       &sc->tx_bd_chain_map[i]);
2237                 if (rc != 0) {
2238                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2239                                   "chain DMA memory!\n", i);
2240                         return rc;
2241                 }
2242
2243                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2244                                      sc->tx_bd_chain_map[i],
2245                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2246                                      bce_dma_map_addr, &busaddr,
2247                                      BUS_DMA_WAITOK);
2248                 if (rc != 0) {
2249                         if (rc == EINPROGRESS) {
2250                                 panic("%s coherent memory loading "
2251                                       "is still in progress!", ifp->if_xname);
2252                         }
2253                         if_printf(ifp, "Could not map %dth TX descriptor "
2254                                   "chain DMA memory!\n", i);
2255                         bus_dmamem_free(sc->tx_bd_chain_tag,
2256                                         sc->tx_bd_chain[i],
2257                                         sc->tx_bd_chain_map[i]);
2258                         sc->tx_bd_chain[i] = NULL;
2259                         return rc;
2260                 }
2261
2262                 sc->tx_bd_chain_paddr[i] = busaddr;
2263                 /* DRC - Fix for 64 bit systems. */
2264                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2265                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2266         }
2267
2268         /* Create a DMA tag for TX mbufs. */
2269         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2270                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2271                                 NULL, NULL,
2272                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2273                                 BCE_MAX_SEGMENTS, MCLBYTES,
2274                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2275                                 BUS_DMA_ONEBPAGE,
2276                                 &sc->tx_mbuf_tag);
2277         if (rc != 0) {
2278                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2279                 return rc;
2280         }
2281
2282         /* Create DMA maps for the TX mbufs clusters. */
2283         for (i = 0; i < TOTAL_TX_BD; i++) {
2284                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2285                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2286                                        &sc->tx_mbuf_map[i]);
2287                 if (rc != 0) {
2288                         for (j = 0; j < i; ++j) {
2289                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2290                                                    sc->tx_mbuf_map[i]);
2291                         }
2292                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2293                         sc->tx_mbuf_tag = NULL;
2294
2295                         if_printf(ifp, "Unable to create "
2296                                   "%dth TX mbuf DMA map!\n", i);
2297                         return rc;
2298                 }
2299         }
2300
2301         /*
2302          * Create a DMA tag for the RX buffer descriptor chain,
2303          * allocate and clear the  memory, and fetch the physical
2304          * address of the blocks.
2305          */
2306         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2307                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2308                                 NULL, NULL,
2309                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2310                                 0, &sc->rx_bd_chain_tag);
2311         if (rc != 0) {
2312                 if_printf(ifp, "Could not allocate "
2313                           "RX descriptor chain DMA tag!\n");
2314                 return rc;
2315         }
2316
2317         for (i = 0; i < RX_PAGES; i++) {
2318                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2319                                       (void **)&sc->rx_bd_chain[i],
2320                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2321                                       BUS_DMA_COHERENT,
2322                                       &sc->rx_bd_chain_map[i]);
2323                 if (rc != 0) {
2324                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2325                                   "chain DMA memory!\n", i);
2326                         return rc;
2327                 }
2328
2329                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2330                                      sc->rx_bd_chain_map[i],
2331                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2332                                      bce_dma_map_addr, &busaddr,
2333                                      BUS_DMA_WAITOK);
2334                 if (rc != 0) {
2335                         if (rc == EINPROGRESS) {
2336                                 panic("%s coherent memory loading "
2337                                       "is still in progress!", ifp->if_xname);
2338                         }
2339                         if_printf(ifp, "Could not map %dth RX descriptor "
2340                                   "chain DMA memory!\n", i);
2341                         bus_dmamem_free(sc->rx_bd_chain_tag,
2342                                         sc->rx_bd_chain[i],
2343                                         sc->rx_bd_chain_map[i]);
2344                         sc->rx_bd_chain[i] = NULL;
2345                         return rc;
2346                 }
2347
2348                 sc->rx_bd_chain_paddr[i] = busaddr;
2349                 /* DRC - Fix for 64 bit systems. */
2350                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2351                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2352         }
2353
2354         /* Create a DMA tag for RX mbufs. */
2355         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2356                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2357                                 NULL, NULL,
2358                                 MCLBYTES, 1, MCLBYTES,
2359                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2360                                 BUS_DMA_WAITOK,
2361                                 &sc->rx_mbuf_tag);
2362         if (rc != 0) {
2363                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2364                 return rc;
2365         }
2366
2367         /* Create tmp DMA map for RX mbuf clusters. */
2368         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2369                                &sc->rx_mbuf_tmpmap);
2370         if (rc != 0) {
2371                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2372                 sc->rx_mbuf_tag = NULL;
2373
2374                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2375                 return rc;
2376         }
2377
2378         /* Create DMA maps for the RX mbuf clusters. */
2379         for (i = 0; i < TOTAL_RX_BD; i++) {
2380                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2381                                        &sc->rx_mbuf_map[i]);
2382                 if (rc != 0) {
2383                         for (j = 0; j < i; ++j) {
2384                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2385                                                    sc->rx_mbuf_map[j]);
2386                         }
2387                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2388                         sc->rx_mbuf_tag = NULL;
2389
2390                         if_printf(ifp, "Unable to create "
2391                                   "%dth RX mbuf DMA map!\n", i);
2392                         return rc;
2393                 }
2394         }
2395         return 0;
2396 }
2397
2398
2399 /****************************************************************************/
2400 /* Firmware synchronization.                                                */
2401 /*                                                                          */
2402 /* Before performing certain events such as a chip reset, synchronize with  */
2403 /* the firmware first.                                                      */
2404 /*                                                                          */
2405 /* Returns:                                                                 */
2406 /*   0 for success, positive value for failure.                             */
2407 /****************************************************************************/
2408 static int
2409 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2410 {
2411         int i, rc = 0;
2412         uint32_t val;
2413
2414         /* Don't waste any time if we've timed out before. */
2415         if (sc->bce_fw_timed_out)
2416                 return EBUSY;
2417
2418         /* Increment the message sequence number. */
2419         sc->bce_fw_wr_seq++;
2420         msg_data |= sc->bce_fw_wr_seq;
2421
2422         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2423
2424         /* Send the message to the bootcode driver mailbox. */
2425         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2426
2427         /* Wait for the bootcode to acknowledge the message. */
2428         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2429                 /* Check for a response in the bootcode firmware mailbox. */
2430                 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);
2431                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2432                         break;
2433                 DELAY(1000);
2434         }
2435
2436         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2437         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2438             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2439                 if_printf(&sc->arpcom.ac_if,
2440                           "Firmware synchronization timeout! "
2441                           "msg_data = 0x%08X\n", msg_data);
2442
2443                 msg_data &= ~BCE_DRV_MSG_CODE;
2444                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2445
2446                 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2447
2448                 sc->bce_fw_timed_out = 1;
2449                 rc = EBUSY;
2450         }
2451         return rc;
2452 }
2453
2454
2455 /****************************************************************************/
2456 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2457 /*                                                                          */
2458 /* Returns:                                                                 */
2459 /*   Nothing.                                                               */
2460 /****************************************************************************/
2461 static void
2462 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2463                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2464 {
2465         int i;
2466         uint32_t val;
2467
2468         for (i = 0; i < rv2p_code_len; i += 8) {
2469                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2470                 rv2p_code++;
2471                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2472                 rv2p_code++;
2473
2474                 if (rv2p_proc == RV2P_PROC1) {
2475                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2476                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2477                 } else {
2478                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2479                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2480                 }
2481         }
2482
2483         /* Reset the processor, un-stall is done later. */
2484         if (rv2p_proc == RV2P_PROC1)
2485                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2486         else
2487                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2488 }
2489
2490
2491 /****************************************************************************/
2492 /* Load RISC processor firmware.                                            */
2493 /*                                                                          */
2494 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2495 /* associated with a particular processor.                                  */
2496 /*                                                                          */
2497 /* Returns:                                                                 */
2498 /*   Nothing.                                                               */
2499 /****************************************************************************/
2500 static void
2501 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2502                 struct fw_info *fw)
2503 {
2504         uint32_t offset, val;
2505         int j;
2506
2507         /* Halt the CPU. */
2508         val = REG_RD_IND(sc, cpu_reg->mode);
2509         val |= cpu_reg->mode_value_halt;
2510         REG_WR_IND(sc, cpu_reg->mode, val);
2511         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2512
2513         /* Load the Text area. */
2514         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2515         if (fw->text) {
2516                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2517                         REG_WR_IND(sc, offset, fw->text[j]);
2518         }
2519
2520         /* Load the Data area. */
2521         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2522         if (fw->data) {
2523                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2524                         REG_WR_IND(sc, offset, fw->data[j]);
2525         }
2526
2527         /* Load the SBSS area. */
2528         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2529         if (fw->sbss) {
2530                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2531                         REG_WR_IND(sc, offset, fw->sbss[j]);
2532         }
2533
2534         /* Load the BSS area. */
2535         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2536         if (fw->bss) {
2537                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2538                         REG_WR_IND(sc, offset, fw->bss[j]);
2539         }
2540
2541         /* Load the Read-Only area. */
2542         offset = cpu_reg->spad_base +
2543                 (fw->rodata_addr - cpu_reg->mips_view_base);
2544         if (fw->rodata) {
2545                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2546                         REG_WR_IND(sc, offset, fw->rodata[j]);
2547         }
2548
2549         /* Clear the pre-fetch instruction. */
2550         REG_WR_IND(sc, cpu_reg->inst, 0);
2551         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2552
2553         /* Start the CPU. */
2554         val = REG_RD_IND(sc, cpu_reg->mode);
2555         val &= ~cpu_reg->mode_value_halt;
2556         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2557         REG_WR_IND(sc, cpu_reg->mode, val);
2558 }
2559
2560
2561 /****************************************************************************/
2562 /* Initialize the RX CPU.                                                   */
2563 /*                                                                          */
2564 /* Returns:                                                                 */
2565 /*   Nothing.                                                               */
2566 /****************************************************************************/
2567 static void
2568 bce_init_rxp_cpu(struct bce_softc *sc)
2569 {
2570         struct cpu_reg cpu_reg;
2571         struct fw_info fw;
2572
2573         cpu_reg.mode = BCE_RXP_CPU_MODE;
2574         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2575         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2576         cpu_reg.state = BCE_RXP_CPU_STATE;
2577         cpu_reg.state_value_clear = 0xffffff;
2578         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2579         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2580         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2581         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2582         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2583         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2584         cpu_reg.mips_view_base = 0x8000000;
2585
2586         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2587             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2588                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2589                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2590                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2591                 fw.start_addr = bce_RXP_b09FwStartAddr;
2592
2593                 fw.text_addr = bce_RXP_b09FwTextAddr;
2594                 fw.text_len = bce_RXP_b09FwTextLen;
2595                 fw.text_index = 0;
2596                 fw.text = bce_RXP_b09FwText;
2597
2598                 fw.data_addr = bce_RXP_b09FwDataAddr;
2599                 fw.data_len = bce_RXP_b09FwDataLen;
2600                 fw.data_index = 0;
2601                 fw.data = bce_RXP_b09FwData;
2602
2603                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2604                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2605                 fw.sbss_index = 0;
2606                 fw.sbss = bce_RXP_b09FwSbss;
2607
2608                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2609                 fw.bss_len = bce_RXP_b09FwBssLen;
2610                 fw.bss_index = 0;
2611                 fw.bss = bce_RXP_b09FwBss;
2612
2613                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2614                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2615                 fw.rodata_index = 0;
2616                 fw.rodata = bce_RXP_b09FwRodata;
2617         } else {
2618                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2619                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2620                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2621                 fw.start_addr = bce_RXP_b06FwStartAddr;
2622
2623                 fw.text_addr = bce_RXP_b06FwTextAddr;
2624                 fw.text_len = bce_RXP_b06FwTextLen;
2625                 fw.text_index = 0;
2626                 fw.text = bce_RXP_b06FwText;
2627
2628                 fw.data_addr = bce_RXP_b06FwDataAddr;
2629                 fw.data_len = bce_RXP_b06FwDataLen;
2630                 fw.data_index = 0;
2631                 fw.data = bce_RXP_b06FwData;
2632
2633                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2634                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2635                 fw.sbss_index = 0;
2636                 fw.sbss = bce_RXP_b06FwSbss;
2637
2638                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2639                 fw.bss_len = bce_RXP_b06FwBssLen;
2640                 fw.bss_index = 0;
2641                 fw.bss = bce_RXP_b06FwBss;
2642
2643                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2644                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2645                 fw.rodata_index = 0;
2646                 fw.rodata = bce_RXP_b06FwRodata;
2647         }
2648
2649         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2650         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2651 }
2652
2653
2654 /****************************************************************************/
2655 /* Initialize the TX CPU.                                                   */
2656 /*                                                                          */
2657 /* Returns:                                                                 */
2658 /*   Nothing.                                                               */
2659 /****************************************************************************/
2660 static void
2661 bce_init_txp_cpu(struct bce_softc *sc)
2662 {
2663         struct cpu_reg cpu_reg;
2664         struct fw_info fw;
2665
2666         cpu_reg.mode = BCE_TXP_CPU_MODE;
2667         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2668         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2669         cpu_reg.state = BCE_TXP_CPU_STATE;
2670         cpu_reg.state_value_clear = 0xffffff;
2671         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2672         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2673         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2674         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2675         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2676         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2677         cpu_reg.mips_view_base = 0x8000000;
2678
2679         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2680             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2681                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2682                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2683                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2684                 fw.start_addr = bce_TXP_b09FwStartAddr;
2685
2686                 fw.text_addr = bce_TXP_b09FwTextAddr;
2687                 fw.text_len = bce_TXP_b09FwTextLen;
2688                 fw.text_index = 0;
2689                 fw.text = bce_TXP_b09FwText;
2690
2691                 fw.data_addr = bce_TXP_b09FwDataAddr;
2692                 fw.data_len = bce_TXP_b09FwDataLen;
2693                 fw.data_index = 0;
2694                 fw.data = bce_TXP_b09FwData;
2695
2696                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2697                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2698                 fw.sbss_index = 0;
2699                 fw.sbss = bce_TXP_b09FwSbss;
2700
2701                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2702                 fw.bss_len = bce_TXP_b09FwBssLen;
2703                 fw.bss_index = 0;
2704                 fw.bss = bce_TXP_b09FwBss;
2705
2706                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2707                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2708                 fw.rodata_index = 0;
2709                 fw.rodata = bce_TXP_b09FwRodata;
2710         } else {
2711                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2712                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2713                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2714                 fw.start_addr = bce_TXP_b06FwStartAddr;
2715
2716                 fw.text_addr = bce_TXP_b06FwTextAddr;
2717                 fw.text_len = bce_TXP_b06FwTextLen;
2718                 fw.text_index = 0;
2719                 fw.text = bce_TXP_b06FwText;
2720
2721                 fw.data_addr = bce_TXP_b06FwDataAddr;
2722                 fw.data_len = bce_TXP_b06FwDataLen;
2723                 fw.data_index = 0;
2724                 fw.data = bce_TXP_b06FwData;
2725
2726                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2727                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2728                 fw.sbss_index = 0;
2729                 fw.sbss = bce_TXP_b06FwSbss;
2730
2731                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2732                 fw.bss_len = bce_TXP_b06FwBssLen;
2733                 fw.bss_index = 0;
2734                 fw.bss = bce_TXP_b06FwBss;
2735
2736                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2737                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2738                 fw.rodata_index = 0;
2739                 fw.rodata = bce_TXP_b06FwRodata;
2740         }
2741
2742         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2743         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2744 }
2745
2746
2747 /****************************************************************************/
2748 /* Initialize the TPAT CPU.                                                 */
2749 /*                                                                          */
2750 /* Returns:                                                                 */
2751 /*   Nothing.                                                               */
2752 /****************************************************************************/
2753 static void
2754 bce_init_tpat_cpu(struct bce_softc *sc)
2755 {
2756         struct cpu_reg cpu_reg;
2757         struct fw_info fw;
2758
2759         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2760         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2761         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2762         cpu_reg.state = BCE_TPAT_CPU_STATE;
2763         cpu_reg.state_value_clear = 0xffffff;
2764         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2765         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2766         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2767         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2768         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2769         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2770         cpu_reg.mips_view_base = 0x8000000;
2771
2772         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2773             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2774                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2775                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2776                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2777                 fw.start_addr = bce_TPAT_b09FwStartAddr;
2778
2779                 fw.text_addr = bce_TPAT_b09FwTextAddr;
2780                 fw.text_len = bce_TPAT_b09FwTextLen;
2781                 fw.text_index = 0;
2782                 fw.text = bce_TPAT_b09FwText;
2783
2784                 fw.data_addr = bce_TPAT_b09FwDataAddr;
2785                 fw.data_len = bce_TPAT_b09FwDataLen;
2786                 fw.data_index = 0;
2787                 fw.data = bce_TPAT_b09FwData;
2788
2789                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2790                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2791                 fw.sbss_index = 0;
2792                 fw.sbss = bce_TPAT_b09FwSbss;
2793
2794                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2795                 fw.bss_len = bce_TPAT_b09FwBssLen;
2796                 fw.bss_index = 0;
2797                 fw.bss = bce_TPAT_b09FwBss;
2798
2799                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2800                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2801                 fw.rodata_index = 0;
2802                 fw.rodata = bce_TPAT_b09FwRodata;
2803         } else {
2804                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2805                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2806                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2807                 fw.start_addr = bce_TPAT_b06FwStartAddr;
2808
2809                 fw.text_addr = bce_TPAT_b06FwTextAddr;
2810                 fw.text_len = bce_TPAT_b06FwTextLen;
2811                 fw.text_index = 0;
2812                 fw.text = bce_TPAT_b06FwText;
2813
2814                 fw.data_addr = bce_TPAT_b06FwDataAddr;
2815                 fw.data_len = bce_TPAT_b06FwDataLen;
2816                 fw.data_index = 0;
2817                 fw.data = bce_TPAT_b06FwData;
2818
2819                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2820                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2821                 fw.sbss_index = 0;
2822                 fw.sbss = bce_TPAT_b06FwSbss;
2823
2824                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2825                 fw.bss_len = bce_TPAT_b06FwBssLen;
2826                 fw.bss_index = 0;
2827                 fw.bss = bce_TPAT_b06FwBss;
2828
2829                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2830                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2831                 fw.rodata_index = 0;
2832                 fw.rodata = bce_TPAT_b06FwRodata;
2833         }
2834
2835         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2836         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2837 }
2838
2839
2840 /****************************************************************************/
2841 /* Initialize the CP CPU.                                                   */
2842 /*                                                                          */
2843 /* Returns:                                                                 */
2844 /*   Nothing.                                                               */
2845 /****************************************************************************/
2846 static void
2847 bce_init_cp_cpu(struct bce_softc *sc)
2848 {
2849         struct cpu_reg cpu_reg;
2850         struct fw_info fw;
2851
2852         cpu_reg.mode = BCE_CP_CPU_MODE;
2853         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2854         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2855         cpu_reg.state = BCE_CP_CPU_STATE;
2856         cpu_reg.state_value_clear = 0xffffff;
2857         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
2858         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
2859         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
2860         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
2861         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
2862         cpu_reg.spad_base = BCE_CP_SCRATCH;
2863         cpu_reg.mips_view_base = 0x8000000;
2864
2865         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2866             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2867                 fw.ver_major = bce_CP_b09FwReleaseMajor;
2868                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
2869                 fw.ver_fix = bce_CP_b09FwReleaseFix;
2870                 fw.start_addr = bce_CP_b09FwStartAddr;
2871
2872                 fw.text_addr = bce_CP_b09FwTextAddr;
2873                 fw.text_len = bce_CP_b09FwTextLen;
2874                 fw.text_index = 0;
2875                 fw.text = bce_CP_b09FwText;
2876
2877                 fw.data_addr = bce_CP_b09FwDataAddr;
2878                 fw.data_len = bce_CP_b09FwDataLen;
2879                 fw.data_index = 0;
2880                 fw.data = bce_CP_b09FwData;
2881
2882                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
2883                 fw.sbss_len = bce_CP_b09FwSbssLen;
2884                 fw.sbss_index = 0;
2885                 fw.sbss = bce_CP_b09FwSbss;
2886
2887                 fw.bss_addr = bce_CP_b09FwBssAddr;
2888                 fw.bss_len = bce_CP_b09FwBssLen;
2889                 fw.bss_index = 0;
2890                 fw.bss = bce_CP_b09FwBss;
2891
2892                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
2893                 fw.rodata_len = bce_CP_b09FwRodataLen;
2894                 fw.rodata_index = 0;
2895                 fw.rodata = bce_CP_b09FwRodata;
2896         } else {
2897                 fw.ver_major = bce_CP_b06FwReleaseMajor;
2898                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
2899                 fw.ver_fix = bce_CP_b06FwReleaseFix;
2900                 fw.start_addr = bce_CP_b06FwStartAddr;
2901
2902                 fw.text_addr = bce_CP_b06FwTextAddr;
2903                 fw.text_len = bce_CP_b06FwTextLen;
2904                 fw.text_index = 0;
2905                 fw.text = bce_CP_b06FwText;
2906
2907                 fw.data_addr = bce_CP_b06FwDataAddr;
2908                 fw.data_len = bce_CP_b06FwDataLen;
2909                 fw.data_index = 0;
2910                 fw.data = bce_CP_b06FwData;
2911
2912                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
2913                 fw.sbss_len = bce_CP_b06FwSbssLen;
2914                 fw.sbss_index = 0;
2915                 fw.sbss = bce_CP_b06FwSbss;
2916
2917                 fw.bss_addr = bce_CP_b06FwBssAddr;
2918                 fw.bss_len = bce_CP_b06FwBssLen;
2919                 fw.bss_index = 0;
2920                 fw.bss = bce_CP_b06FwBss;
2921
2922                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
2923                 fw.rodata_len = bce_CP_b06FwRodataLen;
2924                 fw.rodata_index = 0;
2925                 fw.rodata = bce_CP_b06FwRodata;
2926         }
2927
2928         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
2929         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2930 }
2931
2932
2933 /****************************************************************************/
2934 /* Initialize the COM CPU.                                                 */
2935 /*                                                                          */
2936 /* Returns:                                                                 */
2937 /*   Nothing.                                                               */
2938 /****************************************************************************/
2939 static void
2940 bce_init_com_cpu(struct bce_softc *sc)
2941 {
2942         struct cpu_reg cpu_reg;
2943         struct fw_info fw;
2944
2945         cpu_reg.mode = BCE_COM_CPU_MODE;
2946         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
2947         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
2948         cpu_reg.state = BCE_COM_CPU_STATE;
2949         cpu_reg.state_value_clear = 0xffffff;
2950         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
2951         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
2952         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
2953         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
2954         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
2955         cpu_reg.spad_base = BCE_COM_SCRATCH;
2956         cpu_reg.mips_view_base = 0x8000000;
2957
2958         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2959             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2960                 fw.ver_major = bce_COM_b09FwReleaseMajor;
2961                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
2962                 fw.ver_fix = bce_COM_b09FwReleaseFix;
2963                 fw.start_addr = bce_COM_b09FwStartAddr;
2964
2965                 fw.text_addr = bce_COM_b09FwTextAddr;
2966                 fw.text_len = bce_COM_b09FwTextLen;
2967                 fw.text_index = 0;
2968                 fw.text = bce_COM_b09FwText;
2969
2970                 fw.data_addr = bce_COM_b09FwDataAddr;
2971                 fw.data_len = bce_COM_b09FwDataLen;
2972                 fw.data_index = 0;
2973                 fw.data = bce_COM_b09FwData;
2974
2975                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
2976                 fw.sbss_len = bce_COM_b09FwSbssLen;
2977                 fw.sbss_index = 0;
2978                 fw.sbss = bce_COM_b09FwSbss;
2979
2980                 fw.bss_addr = bce_COM_b09FwBssAddr;
2981                 fw.bss_len = bce_COM_b09FwBssLen;
2982                 fw.bss_index = 0;
2983                 fw.bss = bce_COM_b09FwBss;
2984
2985                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
2986                 fw.rodata_len = bce_COM_b09FwRodataLen;
2987                 fw.rodata_index = 0;
2988                 fw.rodata = bce_COM_b09FwRodata;
2989         } else {
2990                 fw.ver_major = bce_COM_b06FwReleaseMajor;
2991                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
2992                 fw.ver_fix = bce_COM_b06FwReleaseFix;
2993                 fw.start_addr = bce_COM_b06FwStartAddr;
2994
2995                 fw.text_addr = bce_COM_b06FwTextAddr;
2996                 fw.text_len = bce_COM_b06FwTextLen;
2997                 fw.text_index = 0;
2998                 fw.text = bce_COM_b06FwText;
2999
3000                 fw.data_addr = bce_COM_b06FwDataAddr;
3001                 fw.data_len = bce_COM_b06FwDataLen;
3002                 fw.data_index = 0;
3003                 fw.data = bce_COM_b06FwData;
3004
3005                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3006                 fw.sbss_len = bce_COM_b06FwSbssLen;
3007                 fw.sbss_index = 0;
3008                 fw.sbss = bce_COM_b06FwSbss;
3009
3010                 fw.bss_addr = bce_COM_b06FwBssAddr;
3011                 fw.bss_len = bce_COM_b06FwBssLen;
3012                 fw.bss_index = 0;
3013                 fw.bss = bce_COM_b06FwBss;
3014
3015                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3016                 fw.rodata_len = bce_COM_b06FwRodataLen;
3017                 fw.rodata_index = 0;
3018                 fw.rodata = bce_COM_b06FwRodata;
3019         }
3020
3021         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3022         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3023 }
3024
3025
3026 /****************************************************************************/
3027 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3028 /*                                                                          */
3029 /* Loads the firmware for each CPU and starts the CPU.                      */
3030 /*                                                                          */
3031 /* Returns:                                                                 */
3032 /*   Nothing.                                                               */
3033 /****************************************************************************/
3034 static void
3035 bce_init_cpus(struct bce_softc *sc)
3036 {
3037         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3038             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3039                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3040                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3041                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3042                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3043                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3044                 } else {
3045                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3046                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3047                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3048                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3049                 }
3050         } else {
3051                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3052                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3053                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3054                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3055         }
3056
3057         bce_init_rxp_cpu(sc);
3058         bce_init_txp_cpu(sc);
3059         bce_init_tpat_cpu(sc);
3060         bce_init_com_cpu(sc);
3061         bce_init_cp_cpu(sc);
3062 }
3063
3064
3065 /****************************************************************************/
3066 /* Initialize context memory.                                               */
3067 /*                                                                          */
3068 /* Clears the memory associated with each Context ID (CID).                 */
3069 /*                                                                          */
3070 /* Returns:                                                                 */
3071 /*   Nothing.                                                               */
3072 /****************************************************************************/
3073 static void
3074 bce_init_ctx(struct bce_softc *sc)
3075 {
3076         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3077             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3078                 /* DRC: Replace this constant value with a #define. */
3079                 int i, retry_cnt = 10;
3080                 uint32_t val;
3081
3082                 /*
3083                  * BCM5709 context memory may be cached
3084                  * in host memory so prepare the host memory
3085                  * for access.
3086                  */
3087                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3088                     (1 << 12);
3089                 val |= (BCM_PAGE_BITS - 8) << 16;
3090                 REG_WR(sc, BCE_CTX_COMMAND, val);
3091
3092                 /* Wait for mem init command to complete. */
3093                 for (i = 0; i < retry_cnt; i++) {
3094                         val = REG_RD(sc, BCE_CTX_COMMAND);
3095                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3096                                 break;
3097                         DELAY(2);
3098                 }
3099
3100                 for (i = 0; i < sc->ctx_pages; i++) {
3101                         int j;
3102
3103                         /*
3104                          * Set the physical address of the context
3105                          * memory cache.
3106                          */
3107                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3108                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3109                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3110                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3111                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3112                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3113                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3114
3115                         /*
3116                          * Verify that the context memory write was successful.
3117                          */
3118                         for (j = 0; j < retry_cnt; j++) {
3119                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3120                                 if ((val &
3121                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3122                                         break;
3123                                 DELAY(5);
3124                         }
3125                 }
3126         } else {
3127                 uint32_t vcid_addr, offset;
3128
3129                 /*
3130                  * For the 5706/5708, context memory is local to
3131                  * the controller, so initialize the controller
3132                  * context memory.
3133                  */
3134
3135                 vcid_addr = GET_CID_ADDR(96);
3136                 while (vcid_addr) {
3137                         vcid_addr -= PHY_CTX_SIZE;
3138
3139                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3140                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3141
3142                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3143                                 CTX_WR(sc, 0x00, offset, 0);
3144
3145                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3146                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3147                 }
3148         }
3149 }
3150
3151
3152 /****************************************************************************/
3153 /* Fetch the permanent MAC address of the controller.                       */
3154 /*                                                                          */
3155 /* Returns:                                                                 */
3156 /*   Nothing.                                                               */
3157 /****************************************************************************/
3158 static void
3159 bce_get_mac_addr(struct bce_softc *sc)
3160 {
3161         uint32_t mac_lo = 0, mac_hi = 0;
3162
3163         /*
3164          * The NetXtreme II bootcode populates various NIC
3165          * power-on and runtime configuration items in a
3166          * shared memory area.  The factory configured MAC
3167          * address is available from both NVRAM and the
3168          * shared memory area so we'll read the value from
3169          * shared memory for speed.
3170          */
3171
3172         mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_UPPER);
3173         mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_LOWER);
3174
3175         if (mac_lo == 0 && mac_hi == 0) {
3176                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3177         } else {
3178                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3179                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3180                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3181                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3182                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3183                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3184         }
3185
3186         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3187 }
3188
3189
3190 /****************************************************************************/
3191 /* Program the MAC address.                                                 */
3192 /*                                                                          */
3193 /* Returns:                                                                 */
3194 /*   Nothing.                                                               */
3195 /****************************************************************************/
3196 static void
3197 bce_set_mac_addr(struct bce_softc *sc)
3198 {
3199         const uint8_t *mac_addr = sc->eaddr;
3200         uint32_t val;
3201
3202         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3203                 sc->eaddr, ":");
3204
3205         val = (mac_addr[0] << 8) | mac_addr[1];
3206         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3207
3208         val = (mac_addr[2] << 24) |
3209               (mac_addr[3] << 16) |
3210               (mac_addr[4] << 8) |
3211               mac_addr[5];
3212         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3213 }
3214
3215
3216 /****************************************************************************/
3217 /* Stop the controller.                                                     */
3218 /*                                                                          */
3219 /* Returns:                                                                 */
3220 /*   Nothing.                                                               */
3221 /****************************************************************************/
3222 static void
3223 bce_stop(struct bce_softc *sc)
3224 {
3225         struct ifnet *ifp = &sc->arpcom.ac_if;
3226         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3227         struct ifmedia_entry *ifm;
3228         int mtmp, itmp;
3229
3230         ASSERT_SERIALIZED(ifp->if_serializer);
3231
3232         callout_stop(&sc->bce_tick_callout);
3233
3234         /* Disable the transmit/receive blocks. */
3235         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3236         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3237         DELAY(20);
3238
3239         bce_disable_intr(sc);
3240
3241         /* Free the RX lists. */
3242         bce_free_rx_chain(sc);
3243
3244         /* Free TX buffers. */
3245         bce_free_tx_chain(sc);
3246
3247         /*
3248          * Isolate/power down the PHY, but leave the media selection
3249          * unchanged so that things will be put back to normal when
3250          * we bring the interface back up.
3251          *
3252          * 'mii' may be NULL if bce_stop() is called by bce_detach().
3253          */
3254         if (mii != NULL) {
3255                 itmp = ifp->if_flags;
3256                 ifp->if_flags |= IFF_UP;
3257                 ifm = mii->mii_media.ifm_cur;
3258                 mtmp = ifm->ifm_media;
3259                 ifm->ifm_media = IFM_ETHER | IFM_NONE;
3260                 mii_mediachg(mii);
3261                 ifm->ifm_media = mtmp;
3262                 ifp->if_flags = itmp;
3263         }
3264
3265         sc->bce_link = 0;
3266         sc->bce_coalchg_mask = 0;
3267
3268         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3269         ifp->if_timer = 0;
3270 }
3271
3272
3273 static int
3274 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3275 {
3276         uint32_t val;
3277         int i, rc = 0;
3278
3279         /* Wait for pending PCI transactions to complete. */
3280         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3281                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3282                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3283                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3284                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3285         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3286         DELAY(5);
3287
3288         /* Disable DMA */
3289         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3290             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3291                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3292                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3293                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3294         }
3295
3296         /* Assume bootcode is running. */
3297         sc->bce_fw_timed_out = 0;
3298
3299         /* Give the firmware a chance to prepare for the reset. */
3300         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3301         if (rc) {
3302                 if_printf(&sc->arpcom.ac_if,
3303                           "Firmware is not ready for reset\n");
3304                 return rc;
3305         }
3306
3307         /* Set a firmware reminder that this is a soft reset. */
3308         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
3309                    BCE_DRV_RESET_SIGNATURE_MAGIC);
3310
3311         /* Dummy read to force the chip to complete all current transactions. */
3312         val = REG_RD(sc, BCE_MISC_ID);
3313
3314         /* Chip reset. */
3315         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3316             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3317                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3318                 REG_RD(sc, BCE_MISC_COMMAND);
3319                 DELAY(5);
3320
3321                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3322                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3323
3324                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3325         } else {
3326                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3327                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3328                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3329                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3330
3331                 /* Allow up to 30us for reset to complete. */
3332                 for (i = 0; i < 10; i++) {
3333                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3334                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3335                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3336                                 break;
3337                         DELAY(10);
3338                 }
3339
3340                 /* Check that reset completed successfully. */
3341                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3342                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3343                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3344                         return EBUSY;
3345                 }
3346         }
3347
3348         /* Make sure byte swapping is properly configured. */
3349         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3350         if (val != 0x01020304) {
3351                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3352                 return ENODEV;
3353         }
3354
3355         /* Just completed a reset, assume that firmware is running again. */
3356         sc->bce_fw_timed_out = 0;
3357
3358         /* Wait for the firmware to finish its initialization. */
3359         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3360         if (rc) {
3361                 if_printf(&sc->arpcom.ac_if,
3362                           "Firmware did not complete initialization!\n");
3363         }
3364         return rc;
3365 }
3366
3367
3368 static int
3369 bce_chipinit(struct bce_softc *sc)
3370 {
3371         uint32_t val;
3372         int rc = 0;
3373
3374         /* Make sure the interrupt is not active. */
3375         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3376         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3377
3378         /*
3379          * Initialize DMA byte/word swapping, configure the number of DMA
3380          * channels and PCI clock compensation delay.
3381          */
3382         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3383               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3384 #if BYTE_ORDER == BIG_ENDIAN
3385               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3386 #endif
3387               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3388               DMA_READ_CHANS << 12 |
3389               DMA_WRITE_CHANS << 16;
3390
3391         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3392
3393         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3394                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3395
3396         /*
3397          * This setting resolves a problem observed on certain Intel PCI
3398          * chipsets that cannot handle multiple outstanding DMA operations.
3399          * See errata E9_5706A1_65.
3400          */
3401         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3402             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3403             !(sc->bce_flags & BCE_PCIX_FLAG))
3404                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3405
3406         REG_WR(sc, BCE_DMA_CONFIG, val);
3407
3408         /* Enable the RX_V2P and Context state machines before access. */
3409         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3410                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3411                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3412                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3413
3414         /* Initialize context mapping and zero out the quick contexts. */
3415         bce_init_ctx(sc);
3416
3417         /* Initialize the on-boards CPUs */
3418         bce_init_cpus(sc);
3419
3420         /* Prepare NVRAM for access. */
3421         rc = bce_init_nvram(sc);
3422         if (rc != 0)
3423                 return rc;
3424
3425         /* Set the kernel bypass block size */
3426         val = REG_RD(sc, BCE_MQ_CONFIG);
3427         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3428         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3429
3430         /* Enable bins used on the 5709/5716. */
3431         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3432             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3433                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3434                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3435                         val |= BCE_MQ_CONFIG_HALT_DIS;
3436         }
3437
3438         REG_WR(sc, BCE_MQ_CONFIG, val);
3439
3440         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3441         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3442         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3443
3444         /* Set the page size and clear the RV2P processor stall bits. */
3445         val = (BCM_PAGE_BITS - 8) << 24;
3446         REG_WR(sc, BCE_RV2P_CONFIG, val);
3447
3448         /* Configure page size. */
3449         val = REG_RD(sc, BCE_TBDR_CONFIG);
3450         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3451         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3452         REG_WR(sc, BCE_TBDR_CONFIG, val);
3453
3454         /* Set the perfect match control register to default. */
3455         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3456
3457         return 0;
3458 }
3459
3460
3461 /****************************************************************************/
3462 /* Initialize the controller in preparation to send/receive traffic.        */
3463 /*                                                                          */
3464 /* Returns:                                                                 */
3465 /*   0 for success, positive value for failure.                             */
3466 /****************************************************************************/
3467 static int
3468 bce_blockinit(struct bce_softc *sc)
3469 {
3470         uint32_t reg, val;
3471         int rc = 0;
3472
3473         /* Load the hardware default MAC address. */
3474         bce_set_mac_addr(sc);
3475
3476         /* Set the Ethernet backoff seed value */
3477         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3478               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3479         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3480
3481         sc->last_status_idx = 0;
3482         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3483
3484         /* Set up link change interrupt generation. */
3485         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3486
3487         /* Program the physical address of the status block. */
3488         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3489         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3490
3491         /* Program the physical address of the statistics block. */
3492         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3493                BCE_ADDR_LO(sc->stats_block_paddr));
3494         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3495                BCE_ADDR_HI(sc->stats_block_paddr));
3496
3497         /* Program various host coalescing parameters. */
3498         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3499                (sc->bce_tx_quick_cons_trip_int << 16) |
3500                sc->bce_tx_quick_cons_trip);
3501         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3502                (sc->bce_rx_quick_cons_trip_int << 16) |
3503                sc->bce_rx_quick_cons_trip);
3504         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3505                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3506         REG_WR(sc, BCE_HC_TX_TICKS,
3507                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3508         REG_WR(sc, BCE_HC_RX_TICKS,
3509                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3510         REG_WR(sc, BCE_HC_COM_TICKS,
3511                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3512         REG_WR(sc, BCE_HC_CMD_TICKS,
3513                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3514         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3515         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3516         REG_WR(sc, BCE_HC_CONFIG,
3517                BCE_HC_CONFIG_TX_TMR_MODE |
3518                BCE_HC_CONFIG_COLLECT_STATS);
3519
3520         /* Clear the internal statistics counters. */
3521         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3522
3523         /* Verify that bootcode is running. */
3524         reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
3525
3526         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3527                 if_printf(&sc->arpcom.ac_if,
3528                           "%s(%d): Simulating bootcode failure.\n",
3529                           __FILE__, __LINE__);
3530                 reg = 0);
3531
3532         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3533             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3534                 if_printf(&sc->arpcom.ac_if,
3535                           "Bootcode not running! Found: 0x%08X, "
3536                           "Expected: 08%08X\n",
3537                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3538                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3539                 return ENODEV;
3540         }
3541
3542         /* Enable DMA */
3543         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3544             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3545                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3546                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3547                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3548         }
3549
3550         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3551         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3552
3553         /* Enable link state change interrupt generation. */
3554         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3555
3556         /* Enable all remaining blocks in the MAC. */
3557         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3558             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3559                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3560                     BCE_MISC_ENABLE_DEFAULT_XI);
3561         } else {
3562                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3563         }
3564         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3565         DELAY(20);
3566
3567         /* Save the current host coalescing block settings. */
3568         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3569
3570         return 0;
3571 }
3572
3573
3574 /****************************************************************************/
3575 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3576 /*                                                                          */
3577 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3578 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3579 /* necessary.                                                               */
3580 /*                                                                          */
3581 /* Returns:                                                                 */
3582 /*   0 for success, positive value for failure.                             */
3583 /****************************************************************************/
3584 static int
3585 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3586                uint32_t *prod_bseq, int init)
3587 {
3588         bus_dmamap_t map;
3589         bus_dma_segment_t seg;
3590         struct mbuf *m_new;
3591         int error, nseg;
3592 #ifdef BCE_DEBUG
3593         uint16_t debug_chain_prod = *chain_prod;
3594 #endif
3595
3596         /* Make sure the inputs are valid. */
3597         DBRUNIF((*chain_prod > MAX_RX_BD),
3598                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3599                           "RX producer out of range: 0x%04X > 0x%04X\n",
3600                           __FILE__, __LINE__,
3601                           *chain_prod, (uint16_t)MAX_RX_BD));
3602
3603         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3604                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3605
3606         DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3607                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3608                           "Simulating mbuf allocation failure.\n",
3609                           __FILE__, __LINE__);
3610                 sc->mbuf_alloc_failed++;
3611                 return ENOBUFS);
3612
3613         /* This is a new mbuf allocation. */
3614         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3615         if (m_new == NULL)
3616                 return ENOBUFS;
3617         DBRUNIF(1, sc->rx_mbuf_alloc++);
3618
3619         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3620
3621         /* Map the mbuf cluster into device memory. */
3622         error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3623                         sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3624                         BUS_DMA_NOWAIT);
3625         if (error) {
3626                 m_freem(m_new);
3627                 if (init) {
3628                         if_printf(&sc->arpcom.ac_if,
3629                                   "Error mapping mbuf into RX chain!\n");
3630                 }
3631                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3632                 return error;
3633         }
3634
3635         if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3636                 bus_dmamap_unload(sc->rx_mbuf_tag,
3637                                   sc->rx_mbuf_map[*chain_prod]);
3638         }
3639
3640         map = sc->rx_mbuf_map[*chain_prod];
3641         sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3642         sc->rx_mbuf_tmpmap = map;
3643
3644         /* Watch for overflow. */
3645         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3646                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3647                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3648                           __FILE__, __LINE__, sc->free_rx_bd,
3649                           (uint16_t)USABLE_RX_BD));
3650
3651         /* Update some debug statistic counters */
3652         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3653                 sc->rx_low_watermark = sc->free_rx_bd);
3654         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3655
3656         /* Save the mbuf and update our counter. */
3657         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3658         sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3659         sc->free_rx_bd--;
3660
3661         bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3662
3663         DBRUN(BCE_VERBOSE_RECV,
3664               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3665
3666         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3667                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3668
3669         return 0;
3670 }
3671
3672
3673 static void
3674 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3675 {
3676         struct rx_bd *rxbd;
3677         bus_addr_t paddr;
3678         int len;
3679
3680         paddr = sc->rx_mbuf_paddr[chain_prod];
3681         len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3682
3683         /* Setup the rx_bd for the first segment. */
3684         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3685
3686         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3687         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3688         rxbd->rx_bd_len = htole32(len);
3689         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3690         *prod_bseq += len;
3691
3692         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3693 }
3694
3695
3696 /****************************************************************************/
3697 /* Initialize the TX context memory.                                        */
3698 /*                                                                          */
3699 /* Returns:                                                                 */
3700 /*   Nothing                                                                */
3701 /****************************************************************************/
3702 static void
3703 bce_init_tx_context(struct bce_softc *sc)
3704 {
3705         uint32_t val;
3706
3707         /* Initialize the context ID for an L2 TX chain. */
3708         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3709             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3710                 /* Set the CID type to support an L2 connection. */
3711                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3712                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3713                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3714                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3715
3716                 /* Point the hardware to the first page in the chain. */
3717                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3718                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3719                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3720                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3721                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3722                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3723         } else {
3724                 /* Set the CID type to support an L2 connection. */
3725                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3726                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3727                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3728                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3729
3730                 /* Point the hardware to the first page in the chain. */
3731                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3732                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3733                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3734                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3735                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3736                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3737         }
3738 }
3739
3740
3741 /****************************************************************************/
3742 /* Allocate memory and initialize the TX data structures.                   */
3743 /*                                                                          */
3744 /* Returns:                                                                 */
3745 /*   0 for success, positive value for failure.                             */
3746 /****************************************************************************/
3747 static int
3748 bce_init_tx_chain(struct bce_softc *sc)
3749 {
3750         struct tx_bd *txbd;
3751         int i, rc = 0;
3752
3753         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3754
3755         /* Set the initial TX producer/consumer indices. */
3756         sc->tx_prod = 0;
3757         sc->tx_cons = 0;
3758         sc->tx_prod_bseq   = 0;
3759         sc->used_tx_bd = 0;
3760         sc->max_tx_bd = USABLE_TX_BD;
3761         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3762         DBRUNIF(1, sc->tx_full_count = 0);
3763
3764         /*
3765          * The NetXtreme II supports a linked-list structre called
3766          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3767          * consists of a series of 1 or more chain pages, each of which
3768          * consists of a fixed number of BD entries.
3769          * The last BD entry on each page is a pointer to the next page
3770          * in the chain, and the last pointer in the BD chain
3771          * points back to the beginning of the chain.
3772          */
3773
3774         /* Set the TX next pointer chain entries. */
3775         for (i = 0; i < TX_PAGES; i++) {
3776                 int j;
3777
3778                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3779
3780                 /* Check if we've reached the last page. */
3781                 if (i == (TX_PAGES - 1))
3782                         j = 0;
3783                 else
3784                         j = i + 1;
3785
3786                 txbd->tx_bd_haddr_hi =
3787                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3788                 txbd->tx_bd_haddr_lo =
3789                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3790         }
3791         bce_init_tx_context(sc);
3792
3793         return(rc);
3794 }
3795
3796
3797 /****************************************************************************/
3798 /* Free memory and clear the TX data structures.                            */
3799 /*                                                                          */
3800 /* Returns:                                                                 */
3801 /*   Nothing.                                                               */
3802 /****************************************************************************/
3803 static void
3804 bce_free_tx_chain(struct bce_softc *sc)
3805 {
3806         int i;
3807
3808         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3809
3810         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3811         for (i = 0; i < TOTAL_TX_BD; i++) {
3812                 if (sc->tx_mbuf_ptr[i] != NULL) {
3813                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3814                         m_freem(sc->tx_mbuf_ptr[i]);
3815                         sc->tx_mbuf_ptr[i] = NULL;
3816                         DBRUNIF(1, sc->tx_mbuf_alloc--);
3817                 }
3818         }
3819
3820         /* Clear each TX chain page. */
3821         for (i = 0; i < TX_PAGES; i++)
3822                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3823         sc->used_tx_bd = 0;
3824
3825         /* Check if we lost any mbufs in the process. */
3826         DBRUNIF((sc->tx_mbuf_alloc),
3827                 if_printf(&sc->arpcom.ac_if,
3828                           "%s(%d): Memory leak! "
3829                           "Lost %d mbufs from tx chain!\n",
3830                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
3831
3832         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3833 }
3834
3835
3836 /****************************************************************************/
3837 /* Initialize the RX context memory.                                        */
3838 /*                                                                          */
3839 /* Returns:                                                                 */
3840 /*   Nothing                                                                */
3841 /****************************************************************************/
3842 static void
3843 bce_init_rx_context(struct bce_softc *sc)
3844 {
3845         uint32_t val;
3846
3847         /* Initialize the context ID for an L2 RX chain. */
3848         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3849             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3850
3851         /*
3852          * Set the level for generating pause frames
3853          * when the number of available rx_bd's gets
3854          * too low (the low watermark) and the level
3855          * when pause frames can be stopped (the high
3856          * watermark).
3857          */
3858         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3859             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3860                 uint32_t lo_water, hi_water;
3861
3862                 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
3863                 hi_water = USABLE_RX_BD / 4;
3864
3865                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
3866                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
3867
3868                 if (hi_water > 0xf)
3869                         hi_water = 0xf;
3870                 else if (hi_water == 0)
3871                         lo_water = 0;
3872                 val |= lo_water |
3873                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
3874         }
3875
3876         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
3877
3878         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
3879         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3880             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3881                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
3882                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
3883         }
3884
3885         /* Point the hardware to the first page in the chain. */
3886         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
3887         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
3888         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
3889         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
3890 }
3891
3892
3893 /****************************************************************************/
3894 /* Allocate memory and initialize the RX data structures.                   */
3895 /*                                                                          */
3896 /* Returns:                                                                 */
3897 /*   0 for success, positive value for failure.                             */
3898 /****************************************************************************/
3899 static int
3900 bce_init_rx_chain(struct bce_softc *sc)
3901 {
3902         struct rx_bd *rxbd;
3903         int i, rc = 0;
3904         uint16_t prod, chain_prod;
3905         uint32_t prod_bseq;
3906
3907         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3908
3909         /* Initialize the RX producer and consumer indices. */
3910         sc->rx_prod = 0;
3911         sc->rx_cons = 0;
3912         sc->rx_prod_bseq = 0;
3913         sc->free_rx_bd = USABLE_RX_BD;
3914         sc->max_rx_bd = USABLE_RX_BD;
3915         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3916         DBRUNIF(1, sc->rx_empty_count = 0);
3917
3918         /* Initialize the RX next pointer chain entries. */
3919         for (i = 0; i < RX_PAGES; i++) {
3920                 int j;
3921
3922                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3923
3924                 /* Check if we've reached the last page. */
3925                 if (i == (RX_PAGES - 1))
3926                         j = 0;
3927                 else
3928                         j = i + 1;
3929
3930                 /* Setup the chain page pointers. */
3931                 rxbd->rx_bd_haddr_hi =
3932                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
3933                 rxbd->rx_bd_haddr_lo =
3934                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
3935         }
3936
3937         /* Allocate mbuf clusters for the rx_bd chain. */
3938         prod = prod_bseq = 0;
3939         while (prod < TOTAL_RX_BD) {
3940                 chain_prod = RX_CHAIN_IDX(prod);
3941                 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
3942                         if_printf(&sc->arpcom.ac_if,
3943                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
3944                                   chain_prod);
3945                         rc = ENOBUFS;
3946                         break;
3947                 }
3948                 prod = NEXT_RX_BD(prod);
3949         }
3950
3951         /* Save the RX chain producer index. */
3952         sc->rx_prod = prod;
3953         sc->rx_prod_bseq = prod_bseq;
3954
3955         /* Tell the chip about the waiting rx_bd's. */
3956         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
3957             sc->rx_prod);
3958         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
3959             sc->rx_prod_bseq);
3960
3961         bce_init_rx_context(sc);
3962
3963         return(rc);
3964 }
3965
3966
3967 /****************************************************************************/
3968 /* Free memory and clear the RX data structures.                            */
3969 /*                                                                          */
3970 /* Returns:                                                                 */
3971 /*   Nothing.                                                               */
3972 /****************************************************************************/
3973 static void
3974 bce_free_rx_chain(struct bce_softc *sc)
3975 {
3976         int i;
3977
3978         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3979
3980         /* Free any mbufs still in the RX mbuf chain. */
3981         for (i = 0; i < TOTAL_RX_BD; i++) {
3982                 if (sc->rx_mbuf_ptr[i] != NULL) {
3983                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
3984                         m_freem(sc->rx_mbuf_ptr[i]);
3985                         sc->rx_mbuf_ptr[i] = NULL;
3986                         DBRUNIF(1, sc->rx_mbuf_alloc--);
3987                 }
3988         }
3989
3990         /* Clear each RX chain page. */
3991         for (i = 0; i < RX_PAGES; i++)
3992                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3993
3994         /* Check if we lost any mbufs in the process. */
3995         DBRUNIF((sc->rx_mbuf_alloc),
3996                 if_printf(&sc->arpcom.ac_if,
3997                           "%s(%d): Memory leak! "
3998                           "Lost %d mbufs from rx chain!\n",
3999                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
4000
4001         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4002 }
4003
4004
4005 /****************************************************************************/
4006 /* Set media options.                                                       */
4007 /*                                                                          */
4008 /* Returns:                                                                 */
4009 /*   0 for success, positive value for failure.                             */
4010 /****************************************************************************/
4011 static int
4012 bce_ifmedia_upd(struct ifnet *ifp)
4013 {
4014         struct bce_softc *sc = ifp->if_softc;
4015         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4016
4017         /*
4018          * 'mii' will be NULL, when this function is called on following
4019          * code path: bce_attach() -> bce_mgmt_init()
4020          */
4021         if (mii != NULL) {
4022                 /* Make sure the MII bus has been enumerated. */
4023                 sc->bce_link = 0;
4024                 if (mii->mii_instance) {
4025                         struct mii_softc *miisc;
4026
4027                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4028                                 mii_phy_reset(miisc);
4029                 }
4030                 mii_mediachg(mii);
4031         }
4032         return 0;
4033 }
4034
4035
4036 /****************************************************************************/
4037 /* Reports current media status.                                            */
4038 /*                                                                          */
4039 /* Returns:                                                                 */
4040 /*   Nothing.                                                               */
4041 /****************************************************************************/
4042 static void
4043 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4044 {
4045         struct bce_softc *sc = ifp->if_softc;
4046         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4047
4048         mii_pollstat(mii);
4049         ifmr->ifm_active = mii->mii_media_active;
4050         ifmr->ifm_status = mii->mii_media_status;
4051 }
4052
4053
4054 /****************************************************************************/
4055 /* Handles PHY generated interrupt events.                                  */
4056 /*                                                                          */
4057 /* Returns:                                                                 */
4058 /*   Nothing.                                                               */
4059 /****************************************************************************/
4060 static void
4061 bce_phy_intr(struct bce_softc *sc)
4062 {
4063         uint32_t new_link_state, old_link_state;
4064         struct ifnet *ifp = &sc->arpcom.ac_if;
4065
4066         ASSERT_SERIALIZED(ifp->if_serializer);
4067
4068         new_link_state = sc->status_block->status_attn_bits &
4069                          STATUS_ATTN_BITS_LINK_STATE;
4070         old_link_state = sc->status_block->status_attn_bits_ack &
4071                          STATUS_ATTN_BITS_LINK_STATE;
4072
4073         /* Handle any changes if the link state has changed. */
4074         if (new_link_state != old_link_state) { /* XXX redundant? */
4075                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4076
4077                 /* Update the status_attn_bits_ack field in the status block. */
4078                 if (new_link_state) {
4079                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4080                                STATUS_ATTN_BITS_LINK_STATE);
4081                         if (bootverbose)
4082                                 if_printf(ifp, "Link is now UP.\n");
4083                 } else {
4084                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4085                                STATUS_ATTN_BITS_LINK_STATE);
4086                         if (bootverbose)
4087                                 if_printf(ifp, "Link is now DOWN.\n");
4088                 }
4089
4090                 /*
4091                  * Assume link is down and allow tick routine to
4092                  * update the state based on the actual media state.
4093                  */
4094                 sc->bce_link = 0;
4095                 callout_stop(&sc->bce_tick_callout);
4096                 bce_tick_serialized(sc);
4097         }
4098
4099         /* Acknowledge the link change interrupt. */
4100         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4101 }
4102
4103
4104 /****************************************************************************/
4105 /* Reads the receive consumer value from the status block (skipping over    */
4106 /* chain page pointer if necessary).                                        */
4107 /*                                                                          */
4108 /* Returns:                                                                 */
4109 /*   hw_cons                                                                */
4110 /****************************************************************************/
4111 static __inline uint16_t
4112 bce_get_hw_rx_cons(struct bce_softc *sc)
4113 {
4114         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4115
4116         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4117                 hw_cons++;
4118         return hw_cons;
4119 }
4120
4121
4122 /****************************************************************************/
4123 /* Handles received frame interrupt events.                                 */
4124 /*                                                                          */
4125 /* Returns:                                                                 */
4126 /*   Nothing.                                                               */
4127 /****************************************************************************/
4128 static void
4129 bce_rx_intr(struct bce_softc *sc, int count)
4130 {
4131         struct ifnet *ifp = &sc->arpcom.ac_if;
4132         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4133         uint32_t sw_prod_bseq;
4134         struct mbuf_chain chain[MAXCPU];
4135
4136         ASSERT_SERIALIZED(ifp->if_serializer);
4137
4138         ether_input_chain_init(chain);
4139
4140         DBRUNIF(1, sc->rx_interrupts++);
4141
4142         /* Get the hardware's view of the RX consumer index. */
4143         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4144
4145         /* Get working copies of the driver's view of the RX indices. */
4146         sw_cons = sc->rx_cons;
4147         sw_prod = sc->rx_prod;
4148         sw_prod_bseq = sc->rx_prod_bseq;
4149
4150         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4151                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4152                 __func__, sw_prod, sw_cons, sw_prod_bseq);
4153
4154         /* Prevent speculative reads from getting ahead of the status block. */
4155         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4156                           BUS_SPACE_BARRIER_READ);
4157
4158         /* Update some debug statistics counters */
4159         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4160                 sc->rx_low_watermark = sc->free_rx_bd);
4161         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4162
4163         /* Scan through the receive chain as long as there is work to do. */
4164         while (sw_cons != hw_cons) {
4165                 struct mbuf *m = NULL;
4166                 struct l2_fhdr *l2fhdr = NULL;
4167                 struct rx_bd *rxbd;
4168                 unsigned int len;
4169                 uint32_t status = 0;
4170
4171 #ifdef DEVICE_POLLING
4172                 if (count >= 0 && count-- == 0) {
4173                         sc->hw_rx_cons = sw_cons;
4174                         break;
4175                 }
4176 #endif
4177
4178                 /*
4179                  * Convert the producer/consumer indices
4180                  * to an actual rx_bd index.
4181                  */
4182                 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
4183                 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
4184
4185                 /* Get the used rx_bd. */
4186                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4187                                        [RX_IDX(sw_chain_cons)];
4188                 sc->free_rx_bd++;
4189
4190                 DBRUN(BCE_VERBOSE_RECV,
4191                       if_printf(ifp, "%s(): ", __func__);
4192                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4193
4194                 /* The mbuf is stored with the last rx_bd entry of a packet. */
4195                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4196                         /* Validate that this is the last rx_bd. */
4197                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4198                                 if_printf(ifp, "%s(%d): "
4199                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4200                                 __FILE__, __LINE__, sw_chain_cons);
4201                                 bce_breakpoint(sc));
4202
4203                         if (sw_chain_cons != sw_chain_prod) {
4204                                 if_printf(ifp, "RX cons(%d) != prod(%d), "
4205                                           "drop!\n", sw_chain_cons,
4206                                           sw_chain_prod);
4207                                 ifp->if_ierrors++;
4208
4209                                 bce_setup_rxdesc_std(sc, sw_chain_cons,
4210                                                      &sw_prod_bseq);
4211                                 m = NULL;
4212                                 goto bce_rx_int_next_rx;
4213                         }
4214
4215                         /* Unmap the mbuf from DMA space. */
4216                         bus_dmamap_sync(sc->rx_mbuf_tag,
4217                                         sc->rx_mbuf_map[sw_chain_cons],
4218                                         BUS_DMASYNC_POSTREAD);
4219
4220                         /* Save the mbuf from the driver's chain. */
4221                         m = sc->rx_mbuf_ptr[sw_chain_cons];
4222
4223                         /*
4224                          * Frames received on the NetXteme II are prepended
4225                          * with an l2_fhdr structure which provides status
4226                          * information about the received frame (including
4227                          * VLAN tags and checksum info).  The frames are also
4228                          * automatically adjusted to align the IP header
4229                          * (i.e. two null bytes are inserted before the
4230                          * Ethernet header).  As a result the data DMA'd by
4231                          * the controller into the mbuf is as follows:
4232                          *
4233                          * +---------+-----+---------------------+-----+
4234                          * | l2_fhdr | pad | packet data         | FCS |
4235                          * +---------+-----+---------------------+-----+
4236                          *
4237                          * The l2_fhdr needs to be checked and skipped and the
4238                          * FCS needs to be stripped before sending the packet
4239                          * up the stack.
4240                          */
4241                         l2fhdr = mtod(m, struct l2_fhdr *);
4242
4243                         len = l2fhdr->l2_fhdr_pkt_len;
4244                         status = l2fhdr->l2_fhdr_status;
4245
4246                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4247                                 if_printf(ifp,
4248                                 "Simulating l2_fhdr status error.\n");
4249                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4250
4251                         /* Watch for unusual sized frames. */
4252                         DBRUNIF((len < BCE_MIN_MTU ||
4253                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4254                                 if_printf(ifp,
4255                                 "%s(%d): Unusual frame size found. "
4256                                 "Min(%d), Actual(%d), Max(%d)\n",
4257                                 __FILE__, __LINE__,
4258                                 (int)BCE_MIN_MTU, len,
4259                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4260                                 bce_dump_mbuf(sc, m);
4261                                 bce_breakpoint(sc));
4262
4263                         len -= ETHER_CRC_LEN;
4264
4265                         /* Check the received frame for errors. */
4266                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
4267                                       L2_FHDR_ERRORS_PHY_DECODE |
4268                                       L2_FHDR_ERRORS_ALIGNMENT |
4269                                       L2_FHDR_ERRORS_TOO_SHORT |
4270                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
4271                                 ifp->if_ierrors++;
4272                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
4273
4274                                 /* Reuse the mbuf for a new frame. */
4275                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4276                                                      &sw_prod_bseq);
4277                                 m = NULL;
4278                                 goto bce_rx_int_next_rx;
4279                         }
4280
4281                         /*
4282                          * Get a new mbuf for the rx_bd.   If no new
4283                          * mbufs are available then reuse the current mbuf,
4284                          * log an ierror on the interface, and generate
4285                          * an error in the system log.
4286                          */
4287                         if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4288                                            &sw_prod_bseq, 0)) {
4289                                 DBRUN(BCE_WARN,
4290                                       if_printf(ifp,
4291                                       "%s(%d): Failed to allocate new mbuf, "
4292                                       "incoming frame dropped!\n",
4293                                       __FILE__, __LINE__));
4294
4295                                 ifp->if_ierrors++;
4296
4297                                 /* Try and reuse the exisitng mbuf. */
4298                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4299                                                      &sw_prod_bseq);
4300                                 m = NULL;
4301                                 goto bce_rx_int_next_rx;
4302                         }
4303
4304                         /*
4305                          * Skip over the l2_fhdr when passing
4306                          * the data up the stack.
4307                          */
4308                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4309
4310                         m->m_pkthdr.len = m->m_len = len;
4311                         m->m_pkthdr.rcvif = ifp;
4312
4313                         DBRUN(BCE_VERBOSE_RECV,
4314                               struct ether_header *eh;
4315                               eh = mtod(m, struct ether_header *);
4316                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
4317                                         "type: 0x%04X\n", __func__,
4318                                         eh->ether_dhost, ":",
4319                                         eh->ether_shost, ":",
4320                                         htons(eh->ether_type)));
4321
4322                         /* Validate the checksum if offload enabled. */
4323                         if (ifp->if_capenable & IFCAP_RXCSUM) {
4324                                 /* Check for an IP datagram. */
4325                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4326                                         m->m_pkthdr.csum_flags |=
4327                                                 CSUM_IP_CHECKED;
4328
4329                                         /* Check if the IP checksum is valid. */
4330                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
4331                                              0xffff) == 0) {
4332                                                 m->m_pkthdr.csum_flags |=
4333                                                         CSUM_IP_VALID;
4334                                         } else {
4335                                                 DBPRINT(sc, BCE_WARN_RECV,
4336                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
4337                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
4338                                         }
4339                                 }
4340
4341                                 /* Check for a valid TCP/UDP frame. */
4342                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4343                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
4344
4345                                         /* Check for a good TCP/UDP checksum. */
4346                                         if ((status &
4347                                              (L2_FHDR_ERRORS_TCP_XSUM |
4348                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4349                                                 m->m_pkthdr.csum_data =
4350                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
4351                                                 m->m_pkthdr.csum_flags |=
4352                                                         CSUM_DATA_VALID |
4353                                                         CSUM_PSEUDO_HDR;
4354                                         } else {
4355                                                 DBPRINT(sc, BCE_WARN_RECV,
4356                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4357                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4358                                         }
4359                                 }
4360                         }
4361
4362                         ifp->if_ipackets++;
4363 bce_rx_int_next_rx:
4364                         sw_prod = NEXT_RX_BD(sw_prod);
4365                 }
4366
4367                 sw_cons = NEXT_RX_BD(sw_cons);
4368
4369                 /* If we have a packet, pass it up the stack */
4370                 if (m) {
4371                         DBPRINT(sc, BCE_VERBOSE_RECV,
4372                                 "%s(): Passing received frame up.\n", __func__);
4373
4374                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4375                                 m->m_flags |= M_VLANTAG;
4376                                 m->m_pkthdr.ether_vlantag =
4377                                         l2fhdr->l2_fhdr_vlan_tag;
4378                         }
4379                         ether_input_chain(ifp, m, NULL, chain);
4380
4381                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4382                 }
4383
4384                 /*
4385                  * If polling(4) is not enabled, refresh hw_cons to see
4386                  * whether there's new work.
4387                  *
4388                  * If polling(4) is enabled, i.e count >= 0, refreshing
4389                  * should not be performed, so that we would not spend
4390                  * too much time in RX processing.
4391                  */
4392                 if (count < 0 && sw_cons == hw_cons)
4393                         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4394
4395                 /*
4396                  * Prevent speculative reads from getting ahead
4397                  * of the status block.
4398                  */
4399                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4400                                   BUS_SPACE_BARRIER_READ);
4401         }
4402
4403         ether_input_dispatch(chain);
4404
4405         sc->rx_cons = sw_cons;
4406         sc->rx_prod = sw_prod;
4407         sc->rx_prod_bseq = sw_prod_bseq;
4408
4409         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4410             sc->rx_prod);
4411         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4412             sc->rx_prod_bseq);
4413
4414         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4415                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4416                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4417 }
4418
4419
4420 /****************************************************************************/
4421 /* Reads the transmit consumer value from the status block (skipping over   */
4422 /* chain page pointer if necessary).                                        */
4423 /*                                                                          */
4424 /* Returns:                                                                 */
4425 /*   hw_cons                                                                */
4426 /****************************************************************************/
4427 static __inline uint16_t
4428 bce_get_hw_tx_cons(struct bce_softc *sc)
4429 {
4430         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4431
4432         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4433                 hw_cons++;
4434         return hw_cons;
4435 }
4436
4437
4438 /****************************************************************************/
4439 /* Handles transmit completion interrupt events.                            */
4440 /*                                                                          */
4441 /* Returns:                                                                 */
4442 /*   Nothing.                                                               */
4443 /****************************************************************************/
4444 static void
4445 bce_tx_intr(struct bce_softc *sc)
4446 {
4447         struct ifnet *ifp = &sc->arpcom.ac_if;
4448         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4449
4450         ASSERT_SERIALIZED(ifp->if_serializer);
4451
4452         DBRUNIF(1, sc->tx_interrupts++);
4453
4454         /* Get the hardware's view of the TX consumer index. */
4455         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4456         sw_tx_cons = sc->tx_cons;
4457
4458         /* Prevent speculative reads from getting ahead of the status block. */
4459         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4460                           BUS_SPACE_BARRIER_READ);
4461
4462         /* Cycle through any completed TX chain page entries. */
4463         while (sw_tx_cons != hw_tx_cons) {
4464 #ifdef BCE_DEBUG
4465                 struct tx_bd *txbd = NULL;
4466 #endif
4467                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4468
4469                 DBPRINT(sc, BCE_INFO_SEND,
4470                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4471                         "sw_tx_chain_cons = 0x%04X\n",
4472                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4473
4474                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4475                         if_printf(ifp, "%s(%d): "
4476                                   "TX chain consumer out of range! "
4477                                   " 0x%04X > 0x%04X\n",
4478                                   __FILE__, __LINE__, sw_tx_chain_cons,
4479                                   (int)MAX_TX_BD);
4480                         bce_breakpoint(sc));
4481
4482                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4483                                 [TX_IDX(sw_tx_chain_cons)]);
4484
4485                 DBRUNIF((txbd == NULL),
4486                         if_printf(ifp, "%s(%d): "
4487                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4488                                   __FILE__, __LINE__, sw_tx_chain_cons);
4489                         bce_breakpoint(sc));
4490
4491                 DBRUN(BCE_INFO_SEND,
4492                       if_printf(ifp, "%s(): ", __func__);
4493                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4494
4495                 /*
4496                  * Free the associated mbuf. Remember
4497                  * that only the last tx_bd of a packet
4498                  * has an mbuf pointer and DMA map.
4499                  */
4500                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4501                         /* Validate that this is the last tx_bd. */
4502                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4503                                 if_printf(ifp, "%s(%d): "
4504                                 "tx_bd END flag not set but "
4505                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4506                                 bce_breakpoint(sc));
4507
4508                         DBRUN(BCE_INFO_SEND,
4509                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4510                                         "from tx_bd[0x%04X]\n", __func__,
4511                                         sw_tx_chain_cons));
4512
4513                         /* Unmap the mbuf. */
4514                         bus_dmamap_unload(sc->tx_mbuf_tag,
4515                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4516
4517                         /* Free the mbuf. */
4518                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4519                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4520                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4521
4522                         ifp->if_opackets++;
4523                 }
4524
4525                 sc->used_tx_bd--;
4526                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4527
4528                 if (sw_tx_cons == hw_tx_cons) {
4529                         /* Refresh hw_cons to see if there's new work. */
4530                         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4531                 }
4532
4533                 /*
4534                  * Prevent speculative reads from getting
4535                  * ahead of the status block.
4536                  */
4537                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4538                                   BUS_SPACE_BARRIER_READ);
4539         }
4540
4541         if (sc->used_tx_bd == 0) {
4542                 /* Clear the TX timeout timer. */
4543                 ifp->if_timer = 0;
4544         }
4545
4546         /* Clear the tx hardware queue full flag. */
4547         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4548                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4549                         DBPRINT(sc, BCE_WARN_SEND,
4550                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4551                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4552                 ifp->if_flags &= ~IFF_OACTIVE;
4553         }
4554         sc->tx_cons = sw_tx_cons;
4555 }
4556
4557
4558 /****************************************************************************/
4559 /* Disables interrupt generation.                                           */
4560 /*                                                                          */
4561 /* Returns:                                                                 */
4562 /*   Nothing.                                                               */
4563 /****************************************************************************/
4564 static void
4565 bce_disable_intr(struct bce_softc *sc)
4566 {
4567         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4568         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4569         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4570 }
4571
4572
4573 /****************************************************************************/
4574 /* Enables interrupt generation.                                            */
4575 /*                                                                          */
4576 /* Returns:                                                                 */
4577 /*   Nothing.                                                               */
4578 /****************************************************************************/
4579 static void
4580 bce_enable_intr(struct bce_softc *sc, int coal_now)
4581 {
4582         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4583
4584         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4585                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4586                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4587
4588         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4589                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4590
4591         if (coal_now) {
4592                 REG_WR(sc, BCE_HC_COMMAND,
4593                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4594         }
4595 }
4596
4597
4598 /****************************************************************************/
4599 /* Handles controller initialization.                                       */
4600 /*                                                                          */
4601 /* Returns:                                                                 */
4602 /*   Nothing.                                                               */
4603 /****************************************************************************/
4604 static void
4605 bce_init(void *xsc)
4606 {
4607         struct bce_softc *sc = xsc;
4608         struct ifnet *ifp = &sc->arpcom.ac_if;
4609         uint32_t ether_mtu;
4610         int error;
4611
4612         ASSERT_SERIALIZED(ifp->if_serializer);
4613
4614         /* Check if the driver is still running and bail out if it is. */
4615         if (ifp->if_flags & IFF_RUNNING)
4616                 return;
4617
4618         bce_stop(sc);
4619
4620         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4621         if (error) {
4622                 if_printf(ifp, "Controller reset failed!\n");
4623                 goto back;
4624         }
4625
4626         error = bce_chipinit(sc);
4627         if (error) {
4628                 if_printf(ifp, "Controller initialization failed!\n");
4629                 goto back;
4630         }
4631
4632         error = bce_blockinit(sc);
4633         if (error) {
4634                 if_printf(ifp, "Block initialization failed!\n");
4635                 goto back;
4636         }
4637
4638         /* Load our MAC address. */
4639         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4640         bce_set_mac_addr(sc);
4641
4642         /* Calculate and program the Ethernet MTU size. */
4643         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4644
4645         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4646
4647         /*
4648          * Program the mtu, enabling jumbo frame
4649          * support if necessary.  Also set the mbuf
4650          * allocation count for RX frames.
4651          */
4652         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4653 #ifdef notyet
4654                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4655                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4656                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4657                 sc->mbuf_alloc_size = MJUM9BYTES;
4658 #else
4659                 panic("jumbo buffer is not supported yet\n");
4660 #endif
4661         } else {
4662                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4663                 sc->mbuf_alloc_size = MCLBYTES;
4664         }
4665
4666         /* Calculate the RX Ethernet frame size for rx_bd's. */
4667         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4668
4669         DBPRINT(sc, BCE_INFO,
4670                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4671                 "max_frame_size = %d\n",
4672                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4673                 sc->max_frame_size);
4674
4675         /* Program appropriate promiscuous/multicast filtering. */
4676         bce_set_rx_mode(sc);
4677
4678         /* Init RX buffer descriptor chain. */
4679         bce_init_rx_chain(sc);  /* XXX return value */
4680
4681         /* Init TX buffer descriptor chain. */
4682         bce_init_tx_chain(sc);  /* XXX return value */
4683
4684 #ifdef DEVICE_POLLING
4685         /* Disable interrupts if we are polling. */
4686         if (ifp->if_flags & IFF_POLLING) {
4687                 bce_disable_intr(sc);
4688
4689                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4690                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4691                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4692                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4693         } else
4694 #endif
4695         /* Enable host interrupts. */
4696         bce_enable_intr(sc, 1);
4697
4698         bce_ifmedia_upd(ifp);
4699
4700         ifp->if_flags |= IFF_RUNNING;
4701         ifp->if_flags &= ~IFF_OACTIVE;
4702
4703         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4704 back:
4705         if (error)
4706                 bce_stop(sc);
4707 }
4708
4709
4710 /****************************************************************************/
4711 /* Initialize the controller just enough so that any management firmware    */
4712 /* running on the device will continue to operate corectly.                 */
4713 /*                                                                          */
4714 /* Returns:                                                                 */
4715 /*   Nothing.                                                               */
4716 /****************************************************************************/
4717 static void
4718 bce_mgmt_init(struct bce_softc *sc)
4719 {
4720         struct ifnet *ifp = &sc->arpcom.ac_if;
4721
4722         /* Bail out if management firmware is not running. */
4723         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4724                 return;
4725
4726         /* Enable all critical blocks in the MAC. */
4727         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4728             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4729                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4730                     BCE_MISC_ENABLE_DEFAULT_XI);
4731         } else {
4732                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4733         }
4734         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4735         DELAY(20);
4736
4737         bce_ifmedia_upd(ifp);
4738 }
4739
4740
4741 /****************************************************************************/
4742 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4743 /* memory visible to the controller.                                        */
4744 /*                                                                          */
4745 /* Returns:                                                                 */
4746 /*   0 for success, positive value for failure.                             */
4747 /****************************************************************************/
4748 static int
4749 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4750 {
4751         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4752         bus_dmamap_t map, tmp_map;
4753         struct mbuf *m0 = *m_head;
4754         struct tx_bd *txbd = NULL;
4755         uint16_t vlan_tag = 0, flags = 0;
4756         uint16_t chain_prod, chain_prod_start, prod;
4757         uint32_t prod_bseq;
4758         int i, error, maxsegs, nsegs;
4759 #ifdef BCE_DEBUG
4760         uint16_t debug_prod;
4761 #endif
4762
4763         /* Transfer any checksum offload flags to the bd. */
4764         if (m0->m_pkthdr.csum_flags) {
4765                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4766                         flags |= TX_BD_FLAGS_IP_CKSUM;
4767                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4768                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4769         }
4770
4771         /* Transfer any VLAN tags to the bd. */
4772         if (m0->m_flags & M_VLANTAG) {
4773                 flags |= TX_BD_FLAGS_VLAN_TAG;
4774                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4775         }
4776
4777         prod = sc->tx_prod;
4778         chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4779
4780         /* Map the mbuf into DMAable memory. */
4781         map = sc->tx_mbuf_map[chain_prod_start];
4782
4783         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4784         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4785                 ("not enough segements %d\n", maxsegs));
4786         if (maxsegs > BCE_MAX_SEGMENTS)
4787                 maxsegs = BCE_MAX_SEGMENTS;
4788
4789         /* Map the mbuf into our DMA address space. */
4790         error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4791                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4792         if (error)
4793                 goto back;
4794         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4795
4796         /* Reset m0 */
4797         m0 = *m_head;
4798
4799         /* prod points to an empty tx_bd at this point. */
4800         prod_bseq  = sc->tx_prod_bseq;
4801
4802 #ifdef BCE_DEBUG
4803         debug_prod = chain_prod;
4804 #endif
4805
4806         DBPRINT(sc, BCE_INFO_SEND,
4807                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4808                 "prod_bseq = 0x%08X\n",
4809                 __func__, prod, chain_prod, prod_bseq);
4810
4811         /*
4812          * Cycle through each mbuf segment that makes up
4813          * the outgoing frame, gathering the mapping info
4814          * for that segment and creating a tx_bd to for
4815          * the mbuf.
4816          */
4817         for (i = 0; i < nsegs; i++) {
4818                 chain_prod = TX_CHAIN_IDX(prod);
4819                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4820
4821                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4822                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4823                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4824                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4825                 txbd->tx_bd_flags = htole16(flags);
4826                 prod_bseq += segs[i].ds_len;
4827                 if (i == 0)
4828                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4829                 prod = NEXT_TX_BD(prod);
4830         }
4831
4832         /* Set the END flag on the last TX buffer descriptor. */
4833         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4834
4835         DBRUN(BCE_EXCESSIVE_SEND,
4836               bce_dump_tx_chain(sc, debug_prod, nsegs));
4837
4838         DBPRINT(sc, BCE_INFO_SEND,
4839                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4840                 "prod_bseq = 0x%08X\n",
4841                 __func__, prod, chain_prod, prod_bseq);
4842
4843         /*
4844          * Ensure that the mbuf pointer for this transmission
4845          * is placed at the array index of the last
4846          * descriptor in this chain.  This is done
4847          * because a single map is used for all
4848          * segments of the mbuf and we don't want to
4849          * unload the map before all of the segments
4850          * have been freed.
4851          */
4852         sc->tx_mbuf_ptr[chain_prod] = m0;
4853
4854         tmp_map = sc->tx_mbuf_map[chain_prod];
4855         sc->tx_mbuf_map[chain_prod] = map;
4856         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4857
4858         sc->used_tx_bd += nsegs;
4859
4860         /* Update some debug statistic counters */
4861         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4862                 sc->tx_hi_watermark = sc->used_tx_bd);
4863         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4864         DBRUNIF(1, sc->tx_mbuf_alloc++);
4865
4866         DBRUN(BCE_VERBOSE_SEND,
4867               bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
4868
4869         /* prod points to the next free tx_bd at this point. */
4870         sc->tx_prod = prod;
4871         sc->tx_prod_bseq = prod_bseq;
4872 back:
4873         if (error) {
4874                 m_freem(*m_head);
4875                 *m_head = NULL;
4876         }
4877         return error;
4878 }
4879
4880
4881 /****************************************************************************/
4882 /* Main transmit routine when called from another routine with a lock.      */
4883 /*                                                                          */
4884 /* Returns:                                                                 */
4885 /*   Nothing.                                                               */
4886 /****************************************************************************/
4887 static void
4888 bce_start(struct ifnet *ifp)
4889 {
4890         struct bce_softc *sc = ifp->if_softc;
4891         int count = 0;
4892
4893         ASSERT_SERIALIZED(ifp->if_serializer);
4894
4895         /* If there's no link or the transmit queue is empty then just exit. */
4896         if (!sc->bce_link) {
4897                 ifq_purge(&ifp->if_snd);
4898                 return;
4899         }
4900
4901         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4902                 return;
4903
4904         DBPRINT(sc, BCE_INFO_SEND,
4905                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
4906                 "tx_prod_bseq = 0x%08X\n",
4907                 __func__,
4908                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4909
4910         for (;;) {
4911                 struct mbuf *m_head;
4912
4913                 /*
4914                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4915                  * unlikely to fail.
4916                  */
4917                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4918                         ifp->if_flags |= IFF_OACTIVE;
4919                         break;
4920                 }
4921
4922                 /* Check for any frames to send. */
4923                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4924                 if (m_head == NULL)
4925                         break;
4926
4927                 /*
4928                  * Pack the data into the transmit ring. If we
4929                  * don't have room, place the mbuf back at the
4930                  * head of the queue and set the OACTIVE flag
4931                  * to wait for the NIC to drain the chain.
4932                  */
4933                 if (bce_encap(sc, &m_head)) {
4934                         ifp->if_oerrors++;
4935                         if (sc->used_tx_bd == 0) {
4936                                 continue;
4937                         } else {
4938                                 ifp->if_flags |= IFF_OACTIVE;
4939                                 break;
4940                         }
4941                 }
4942
4943                 count++;
4944
4945                 /* Send a copy of the frame to any BPF listeners. */
4946                 ETHER_BPF_MTAP(ifp, m_head);
4947         }
4948
4949         if (count == 0) {
4950                 /* no packets were dequeued */
4951                 DBPRINT(sc, BCE_VERBOSE_SEND,
4952                         "%s(): No packets were dequeued\n", __func__);
4953                 return;
4954         }
4955
4956         DBPRINT(sc, BCE_INFO_SEND,
4957                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
4958                 "tx_prod_bseq = 0x%08X\n",
4959                 __func__,
4960                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4961
4962         REG_WR(sc, BCE_MQ_COMMAND,
4963             REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
4964
4965         /* Start the transmit. */
4966         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
4967         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
4968
4969         /* Set the tx timeout. */
4970         ifp->if_timer = BCE_TX_TIMEOUT;
4971 }
4972
4973
4974 /****************************************************************************/
4975 /* Handles any IOCTL calls from the operating system.                       */
4976 /*                                                                          */
4977 /* Returns:                                                                 */
4978 /*   0 for success, positive value for failure.                             */
4979 /****************************************************************************/
4980 static int
4981 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4982 {
4983         struct bce_softc *sc = ifp->if_softc;
4984         struct ifreq *ifr = (struct ifreq *)data;
4985         struct mii_data *mii;
4986         int mask, error = 0;
4987
4988         ASSERT_SERIALIZED(ifp->if_serializer);
4989
4990         switch(command) {
4991         case SIOCSIFMTU:
4992                 /* Check that the MTU setting is supported. */
4993                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
4994 #ifdef notyet
4995                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
4996 #else
4997                     ifr->ifr_mtu > ETHERMTU
4998 #endif
4999                    ) {
5000                         error = EINVAL;
5001                         break;
5002                 }
5003
5004                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5005
5006                 ifp->if_mtu = ifr->ifr_mtu;
5007                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5008                 bce_init(sc);
5009                 break;
5010
5011         case SIOCSIFFLAGS:
5012                 if (ifp->if_flags & IFF_UP) {
5013                         if (ifp->if_flags & IFF_RUNNING) {
5014                                 mask = ifp->if_flags ^ sc->bce_if_flags;
5015
5016                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5017                                         bce_set_rx_mode(sc);
5018                         } else {
5019                                 bce_init(sc);
5020                         }
5021                 } else if (ifp->if_flags & IFF_RUNNING) {
5022                         bce_stop(sc);
5023
5024                         /* If MFW is running, restart the controller a bit. */
5025                         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5026                                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5027                                 bce_chipinit(sc);
5028                                 bce_mgmt_init(sc);
5029                         }
5030                 }
5031                 sc->bce_if_flags = ifp->if_flags;
5032                 break;
5033
5034         case SIOCADDMULTI:
5035         case SIOCDELMULTI:
5036                 if (ifp->if_flags & IFF_RUNNING)
5037                         bce_set_rx_mode(sc);
5038                 break;
5039
5040         case SIOCSIFMEDIA:
5041         case SIOCGIFMEDIA:
5042                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5043                         sc->bce_phy_flags);
5044                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5045
5046                 mii = device_get_softc(sc->bce_miibus);
5047                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5048                 break;
5049
5050         case SIOCSIFCAP:
5051                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5052                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5053                         (uint32_t) mask);
5054
5055                 if (mask & IFCAP_HWCSUM) {
5056                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5057                         if (IFCAP_HWCSUM & ifp->if_capenable)
5058                                 ifp->if_hwassist = BCE_IF_HWASSIST;
5059                         else
5060                                 ifp->if_hwassist = 0;
5061                 }
5062                 break;
5063
5064         default:
5065                 error = ether_ioctl(ifp, command, data);
5066                 break;
5067         }
5068         return error;
5069 }
5070
5071
5072 /****************************************************************************/
5073 /* Transmit timeout handler.                                                */
5074 /*                                                                          */
5075 /* Returns:                                                                 */
5076 /*   Nothing.                                                               */
5077 /****************************************************************************/
5078 static void
5079 bce_watchdog(struct ifnet *ifp)
5080 {
5081         struct bce_softc *sc = ifp->if_softc;
5082
5083         ASSERT_SERIALIZED(ifp->if_serializer);
5084
5085         DBRUN(BCE_VERBOSE_SEND,
5086               bce_dump_driver_state(sc);
5087               bce_dump_status_block(sc));
5088
5089         /*
5090          * If we are in this routine because of pause frames, then
5091          * don't reset the hardware.
5092          */
5093         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5094                 return;
5095
5096         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5097
5098         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5099
5100         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5101         bce_init(sc);
5102
5103         ifp->if_oerrors++;
5104
5105         if (!ifq_is_empty(&ifp->if_snd))
5106                 if_devstart(ifp);
5107 }
5108
5109
5110 #ifdef DEVICE_POLLING
5111
5112 static void
5113 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5114 {
5115         struct bce_softc *sc = ifp->if_softc;
5116         struct status_block *sblk = sc->status_block;
5117         uint16_t hw_tx_cons, hw_rx_cons;
5118
5119         ASSERT_SERIALIZED(ifp->if_serializer);
5120
5121         switch (cmd) {
5122         case POLL_REGISTER:
5123                 bce_disable_intr(sc);
5124
5125                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5126                        (1 << 16) | sc->bce_rx_quick_cons_trip);
5127                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5128                        (1 << 16) | sc->bce_tx_quick_cons_trip);
5129                 return;
5130         case POLL_DEREGISTER:
5131                 bce_enable_intr(sc, 1);
5132
5133                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5134                        (sc->bce_tx_quick_cons_trip_int << 16) |
5135                        sc->bce_tx_quick_cons_trip);
5136                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5137                        (sc->bce_rx_quick_cons_trip_int << 16) |
5138                        sc->bce_rx_quick_cons_trip);
5139                 return;
5140         default:
5141                 break;
5142         }
5143
5144         if (cmd == POLL_AND_CHECK_STATUS) {
5145                 uint32_t status_attn_bits;
5146
5147                 status_attn_bits = sblk->status_attn_bits;
5148
5149                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5150                         if_printf(ifp,
5151                         "Simulating unexpected status attention bit set.");
5152                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5153
5154                 /* Was it a link change interrupt? */
5155                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5156                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5157                         bce_phy_intr(sc);
5158
5159                 /* Clear any transient status updates during link state change. */
5160                 REG_WR(sc, BCE_HC_COMMAND,
5161                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5162                 REG_RD(sc, BCE_HC_COMMAND);
5163
5164                 /*
5165                  * If any other attention is asserted then
5166                  * the chip is toast.
5167                  */
5168                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5169                      (sblk->status_attn_bits_ack &
5170                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5171                         DBRUN(1, sc->unexpected_attentions++);
5172
5173                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5174                                   sblk->status_attn_bits);
5175
5176                         DBRUN(BCE_FATAL,
5177                         if (bce_debug_unexpected_attention == 0)
5178                                 bce_breakpoint(sc));
5179
5180                         bce_init(sc);
5181                         return;
5182                 }
5183         }
5184
5185         hw_rx_cons = bce_get_hw_rx_cons(sc);
5186         hw_tx_cons = bce_get_hw_tx_cons(sc);
5187
5188         /* Check for any completed RX frames. */
5189         if (hw_rx_cons != sc->hw_rx_cons)
5190                 bce_rx_intr(sc, count);
5191
5192         /* Check for any completed TX frames. */
5193         if (hw_tx_cons != sc->hw_tx_cons)
5194                 bce_tx_intr(sc);
5195
5196         /* Check for new frames to transmit. */
5197         if (!ifq_is_empty(&ifp->if_snd))
5198                 if_devstart(ifp);
5199 }
5200
5201 #endif  /* DEVICE_POLLING */
5202
5203
5204 /*
5205  * Interrupt handler.
5206  */
5207 /****************************************************************************/
5208 /* Main interrupt entry point.  Verifies that the controller generated the  */
5209 /* interrupt and then calls a separate routine for handle the various       */
5210 /* interrupt causes (PHY, TX, RX).                                          */
5211 /*                                                                          */
5212 /* Returns:                                                                 */
5213 /*   0 for success, positive value for failure.                             */
5214 /****************************************************************************/
5215 static void
5216 bce_intr(void *xsc)
5217 {
5218         struct bce_softc *sc = xsc;
5219         struct ifnet *ifp = &sc->arpcom.ac_if;
5220         struct status_block *sblk;
5221         uint16_t hw_rx_cons, hw_tx_cons;
5222
5223         ASSERT_SERIALIZED(ifp->if_serializer);
5224
5225         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5226         DBRUNIF(1, sc->interrupts_generated++);
5227
5228         sblk = sc->status_block;
5229
5230         /*
5231          * If the hardware status block index matches the last value
5232          * read by the driver and we haven't asserted our interrupt
5233          * then there's nothing to do.
5234          */
5235         if (sblk->status_idx == sc->last_status_idx &&
5236             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5237              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5238                 return;
5239
5240         /* Ack the interrupt and stop others from occuring. */
5241         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5242                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5243                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5244
5245         /* Check if the hardware has finished any work. */
5246         hw_rx_cons = bce_get_hw_rx_cons(sc);
5247         hw_tx_cons = bce_get_hw_tx_cons(sc);
5248
5249         /* Keep processing data as long as there is work to do. */
5250         for (;;) {
5251                 uint32_t status_attn_bits;
5252
5253                 status_attn_bits = sblk->status_attn_bits;
5254
5255                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5256                         if_printf(ifp,
5257                         "Simulating unexpected status attention bit set.");
5258                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5259
5260                 /* Was it a link change interrupt? */
5261                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5262                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5263                         bce_phy_intr(sc);
5264
5265                         /*
5266                          * Clear any transient status updates during link state
5267                          * change.
5268                          */
5269                         REG_WR(sc, BCE_HC_COMMAND,
5270                             sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5271                         REG_RD(sc, BCE_HC_COMMAND);
5272                 }
5273
5274                 /*
5275                  * If any other attention is asserted then
5276                  * the chip is toast.
5277                  */
5278                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5279                      (sblk->status_attn_bits_ack &
5280                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5281                         DBRUN(1, sc->unexpected_attentions++);
5282
5283                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5284                                   sblk->status_attn_bits);
5285
5286                         DBRUN(BCE_FATAL,
5287                         if (bce_debug_unexpected_attention == 0)
5288                                 bce_breakpoint(sc));
5289
5290                         bce_init(sc);
5291                         return;
5292                 }
5293
5294                 /* Check for any completed RX frames. */
5295                 if (hw_rx_cons != sc->hw_rx_cons)
5296                         bce_rx_intr(sc, -1);
5297
5298                 /* Check for any completed TX frames. */
5299                 if (hw_tx_cons != sc->hw_tx_cons)
5300                         bce_tx_intr(sc);
5301
5302                 /*
5303                  * Save the status block index value
5304                  * for use during the next interrupt.
5305                  */
5306                 sc->last_status_idx = sblk->status_idx;
5307
5308                 /*
5309                  * Prevent speculative reads from getting
5310                  * ahead of the status block.
5311                  */
5312                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5313                                   BUS_SPACE_BARRIER_READ);
5314
5315                 /*
5316                  * If there's no work left then exit the
5317                  * interrupt service routine.
5318                  */
5319                 hw_rx_cons = bce_get_hw_rx_cons(sc);
5320                 hw_tx_cons = bce_get_hw_tx_cons(sc);
5321                 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5322                         break;
5323         }
5324
5325         /* Re-enable interrupts. */
5326         bce_enable_intr(sc, 0);
5327
5328         if (sc->bce_coalchg_mask)
5329                 bce_coal_change(sc);
5330
5331         /* Handle any frames that arrived while handling the interrupt. */
5332         if (!ifq_is_empty(&ifp->if_snd))
5333                 if_devstart(ifp);
5334 }
5335
5336
5337 /****************************************************************************/
5338 /* Programs the various packet receive modes (broadcast and multicast).     */
5339 /*                                                                          */
5340 /* Returns:                                                                 */
5341 /*   Nothing.                                                               */
5342 /****************************************************************************/
5343 static void
5344 bce_set_rx_mode(struct bce_softc *sc)
5345 {
5346         struct ifnet *ifp = &sc->arpcom.ac_if;
5347         struct ifmultiaddr *ifma;
5348         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5349         uint32_t rx_mode, sort_mode;
5350         int h, i;
5351
5352         ASSERT_SERIALIZED(ifp->if_serializer);
5353
5354         /* Initialize receive mode default settings. */
5355         rx_mode = sc->rx_mode &
5356                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5357                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5358         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5359
5360         /*
5361          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5362          * be enbled.
5363          */
5364         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5365             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5366                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5367
5368         /*
5369          * Check for promiscuous, all multicast, or selected
5370          * multicast address filtering.
5371          */
5372         if (ifp->if_flags & IFF_PROMISC) {
5373                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5374
5375                 /* Enable promiscuous mode. */
5376                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5377                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5378         } else if (ifp->if_flags & IFF_ALLMULTI) {
5379                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5380
5381                 /* Enable all multicast addresses. */
5382                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5383                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5384                                0xffffffff);
5385                 }
5386                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5387         } else {
5388                 /* Accept one or more multicast(s). */
5389                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5390
5391                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5392                         if (ifma->ifma_addr->sa_family != AF_LINK)
5393                                 continue;
5394                         h = ether_crc32_le(
5395                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5396                             ETHER_ADDR_LEN) & 0xFF;
5397                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5398                 }
5399
5400                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5401                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5402                                hashes[i]);
5403                 }
5404                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5405         }
5406
5407         /* Only make changes if the recive mode has actually changed. */
5408         if (rx_mode != sc->rx_mode) {
5409                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5410                         rx_mode);
5411
5412                 sc->rx_mode = rx_mode;
5413                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5414         }
5415
5416         /* Disable and clear the exisitng sort before enabling a new sort. */
5417         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5418         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5419         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5420 }
5421
5422
5423 /****************************************************************************/
5424 /* Called periodically to updates statistics from the controllers           */
5425 /* statistics block.                                                        */
5426 /*                                                                          */
5427 /* Returns:                                                                 */
5428 /*   Nothing.                                                               */
5429 /****************************************************************************/
5430 static void
5431 bce_stats_update(struct bce_softc *sc)
5432 {
5433         struct ifnet *ifp = &sc->arpcom.ac_if;
5434         struct statistics_block *stats = sc->stats_block;
5435
5436         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5437
5438         ASSERT_SERIALIZED(ifp->if_serializer);
5439
5440         /*
5441          * Certain controllers don't report carrier sense errors correctly.
5442          * See errata E11_5708CA0_1165.
5443          */
5444         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5445             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5446                 ifp->if_oerrors +=
5447                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5448         }
5449
5450         /*
5451          * Update the sysctl statistics from the hardware statistics.
5452          */
5453         sc->stat_IfHCInOctets =
5454                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5455                  (uint64_t)stats->stat_IfHCInOctets_lo;
5456
5457         sc->stat_IfHCInBadOctets =
5458                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5459                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5460
5461         sc->stat_IfHCOutOctets =
5462                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5463                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5464
5465         sc->stat_IfHCOutBadOctets =
5466                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5467                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5468
5469         sc->stat_IfHCInUcastPkts =
5470                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5471                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5472
5473         sc->stat_IfHCInMulticastPkts =
5474                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5475                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5476
5477         sc->stat_IfHCInBroadcastPkts =
5478                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5479                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5480
5481         sc->stat_IfHCOutUcastPkts =
5482                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5483                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5484
5485         sc->stat_IfHCOutMulticastPkts =
5486                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5487                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5488
5489         sc->stat_IfHCOutBroadcastPkts =
5490                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5491                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5492
5493         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5494                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5495
5496         sc->stat_Dot3StatsCarrierSenseErrors =
5497                 stats->stat_Dot3StatsCarrierSenseErrors;
5498
5499         sc->stat_Dot3StatsFCSErrors =
5500                 stats->stat_Dot3StatsFCSErrors;
5501
5502         sc->stat_Dot3StatsAlignmentErrors =
5503                 stats->stat_Dot3StatsAlignmentErrors;
5504
5505         sc->stat_Dot3StatsSingleCollisionFrames =
5506                 stats->stat_Dot3StatsSingleCollisionFrames;
5507
5508         sc->stat_Dot3StatsMultipleCollisionFrames =
5509                 stats->stat_Dot3StatsMultipleCollisionFrames;
5510
5511         sc->stat_Dot3StatsDeferredTransmissions =
5512                 stats->stat_Dot3StatsDeferredTransmissions;
5513
5514         sc->stat_Dot3StatsExcessiveCollisions =
5515                 stats->stat_Dot3StatsExcessiveCollisions;
5516
5517         sc->stat_Dot3StatsLateCollisions =
5518                 stats->stat_Dot3StatsLateCollisions;
5519
5520         sc->stat_EtherStatsCollisions =
5521                 stats->stat_EtherStatsCollisions;
5522
5523         sc->stat_EtherStatsFragments =
5524                 stats->stat_EtherStatsFragments;
5525
5526         sc->stat_EtherStatsJabbers =
5527                 stats->stat_EtherStatsJabbers;
5528
5529         sc->stat_EtherStatsUndersizePkts =
5530                 stats->stat_EtherStatsUndersizePkts;
5531
5532         sc->stat_EtherStatsOverrsizePkts =
5533                 stats->stat_EtherStatsOverrsizePkts;
5534
5535         sc->stat_EtherStatsPktsRx64Octets =
5536                 stats->stat_EtherStatsPktsRx64Octets;
5537
5538         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5539                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5540
5541         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5542                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5543
5544         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5545                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5546
5547         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5548                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5549
5550         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5551                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5552
5553         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5554                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5555
5556         sc->stat_EtherStatsPktsTx64Octets =
5557                 stats->stat_EtherStatsPktsTx64Octets;
5558
5559         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5560                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5561
5562         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5563                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5564
5565         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5566                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5567
5568         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5569                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5570
5571         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5572                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5573
5574         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5575                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5576
5577         sc->stat_XonPauseFramesReceived =
5578                 stats->stat_XonPauseFramesReceived;
5579
5580         sc->stat_XoffPauseFramesReceived =
5581                 stats->stat_XoffPauseFramesReceived;
5582
5583         sc->stat_OutXonSent =
5584                 stats->stat_OutXonSent;
5585
5586         sc->stat_OutXoffSent =
5587                 stats->stat_OutXoffSent;
5588
5589         sc->stat_FlowControlDone =
5590                 stats->stat_FlowControlDone;
5591
5592         sc->stat_MacControlFramesReceived =
5593                 stats->stat_MacControlFramesReceived;
5594
5595         sc->stat_XoffStateEntered =
5596                 stats->stat_XoffStateEntered;
5597
5598         sc->stat_IfInFramesL2FilterDiscards =
5599                 stats->stat_IfInFramesL2FilterDiscards;
5600
5601         sc->stat_IfInRuleCheckerDiscards =
5602                 stats->stat_IfInRuleCheckerDiscards;
5603
5604         sc->stat_IfInFTQDiscards =
5605                 stats->stat_IfInFTQDiscards;
5606
5607         sc->stat_IfInMBUFDiscards =
5608                 stats->stat_IfInMBUFDiscards;
5609
5610         sc->stat_IfInRuleCheckerP4Hit =
5611                 stats->stat_IfInRuleCheckerP4Hit;
5612
5613         sc->stat_CatchupInRuleCheckerDiscards =
5614                 stats->stat_CatchupInRuleCheckerDiscards;
5615
5616         sc->stat_CatchupInFTQDiscards =
5617                 stats->stat_CatchupInFTQDiscards;
5618
5619         sc->stat_CatchupInMBUFDiscards =
5620                 stats->stat_CatchupInMBUFDiscards;
5621
5622         sc->stat_CatchupInRuleCheckerP4Hit =
5623                 stats->stat_CatchupInRuleCheckerP4Hit;
5624
5625         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5626
5627         /*
5628          * Update the interface statistics from the
5629          * hardware statistics.
5630          */
5631         ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5632
5633         ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5634             (u_long)sc->stat_EtherStatsOverrsizePkts +
5635             (u_long)sc->stat_IfInMBUFDiscards +
5636             (u_long)sc->stat_Dot3StatsAlignmentErrors +
5637             (u_long)sc->stat_Dot3StatsFCSErrors +
5638             (u_long)sc->stat_IfInRuleCheckerDiscards +
5639             (u_long)sc->stat_IfInFTQDiscards +
5640             (u_long)sc->com_no_buffers;
5641
5642         ifp->if_oerrors =
5643             (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5644             (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5645             (u_long)sc->stat_Dot3StatsLateCollisions;
5646
5647         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5648 }
5649
5650
5651 /****************************************************************************/
5652 /* Periodic function to notify the bootcode that the driver is still        */
5653 /* present.                                                                 */
5654 /*                                                                          */
5655 /* Returns:                                                                 */
5656 /*   Nothing.                                                               */
5657 /****************************************************************************/
5658 static void
5659 bce_pulse(void *xsc)
5660 {
5661         struct bce_softc *sc = xsc;
5662         struct ifnet *ifp = &sc->arpcom.ac_if;
5663         uint32_t msg;
5664
5665         lwkt_serialize_enter(ifp->if_serializer);
5666
5667         /* Tell the firmware that the driver is still running. */
5668         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5669         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
5670
5671         /* Schedule the next pulse. */
5672         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5673
5674         lwkt_serialize_exit(ifp->if_serializer);
5675 }
5676
5677
5678 /****************************************************************************/
5679 /* Periodic function to perform maintenance tasks.                          */
5680 /*                                                                          */
5681 /* Returns:                                                                 */
5682 /*   Nothing.                                                               */
5683 /****************************************************************************/
5684 static void
5685 bce_tick_serialized(struct bce_softc *sc)
5686 {
5687         struct ifnet *ifp = &sc->arpcom.ac_if;
5688         struct mii_data *mii;
5689
5690         ASSERT_SERIALIZED(ifp->if_serializer);
5691
5692         /* Update the statistics from the hardware statistics block. */
5693         bce_stats_update(sc);
5694
5695         /* Schedule the next tick. */
5696         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5697
5698         /* If link is up already up then we're done. */
5699         if (sc->bce_link)
5700                 return;
5701
5702         mii = device_get_softc(sc->bce_miibus);
5703         mii_tick(mii);
5704
5705         /* Check if the link has come up. */
5706         if ((mii->mii_media_status & IFM_ACTIVE) &&
5707             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5708                 sc->bce_link++;
5709                 /* Now that link is up, handle any outstanding TX traffic. */
5710                 if (!ifq_is_empty(&ifp->if_snd))
5711                         if_devstart(ifp);
5712         }
5713 }
5714
5715
5716 static void
5717 bce_tick(void *xsc)
5718 {
5719         struct bce_softc *sc = xsc;
5720         struct ifnet *ifp = &sc->arpcom.ac_if;
5721
5722         lwkt_serialize_enter(ifp->if_serializer);
5723         bce_tick_serialized(sc);
5724         lwkt_serialize_exit(ifp->if_serializer);
5725 }
5726
5727
5728 #ifdef BCE_DEBUG
5729 /****************************************************************************/
5730 /* Allows the driver state to be dumped through the sysctl interface.       */
5731 /*                                                                          */
5732 /* Returns:                                                                 */
5733 /*   0 for success, positive value for failure.                             */
5734 /****************************************************************************/
5735 static int
5736 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5737 {
5738         int error;
5739         int result;
5740         struct bce_softc *sc;
5741
5742         result = -1;
5743         error = sysctl_handle_int(oidp, &result, 0, req);
5744
5745         if (error || !req->newptr)
5746                 return (error);
5747
5748         if (result == 1) {
5749                 sc = (struct bce_softc *)arg1;
5750                 bce_dump_driver_state(sc);
5751         }
5752
5753         return error;
5754 }
5755
5756
5757 /****************************************************************************/
5758 /* Allows the hardware state to be dumped through the sysctl interface.     */
5759 /*                                                                          */
5760 /* Returns:                                                                 */
5761 /*   0 for success, positive value for failure.                             */
5762 /****************************************************************************/
5763 static int
5764 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5765 {
5766         int error;
5767         int result;
5768         struct bce_softc *sc;
5769
5770         result = -1;
5771         error = sysctl_handle_int(oidp, &result, 0, req);
5772
5773         if (error || !req->newptr)
5774                 return (error);
5775
5776         if (result == 1) {
5777                 sc = (struct bce_softc *)arg1;
5778                 bce_dump_hw_state(sc);
5779         }
5780
5781         return error;
5782 }
5783
5784
5785 /****************************************************************************/
5786 /* Provides a sysctl interface to allows dumping the RX chain.              */
5787 /*                                                                          */
5788 /* Returns:                                                                 */
5789 /*   0 for success, positive value for failure.                             */
5790 /****************************************************************************/
5791 static int
5792 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5793 {
5794         int error;
5795         int result;
5796         struct bce_softc *sc;
5797
5798         result = -1;
5799         error = sysctl_handle_int(oidp, &result, 0, req);
5800
5801         if (error || !req->newptr)
5802                 return (error);
5803
5804         if (result == 1) {
5805                 sc = (struct bce_softc *)arg1;
5806                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5807         }
5808
5809         return error;
5810 }
5811
5812
5813 /****************************************************************************/
5814 /* Provides a sysctl interface to allows dumping the TX chain.              */
5815 /*                                                                          */
5816 /* Returns:                                                                 */
5817 /*   0 for success, positive value for failure.                             */
5818 /****************************************************************************/
5819 static int
5820 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5821 {
5822         int error;
5823         int result;
5824         struct bce_softc *sc;
5825
5826         result = -1;
5827         error = sysctl_handle_int(oidp, &result, 0, req);
5828
5829         if (error || !req->newptr)
5830                 return (error);
5831
5832         if (result == 1) {
5833                 sc = (struct bce_softc *)arg1;
5834                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
5835         }
5836
5837         return error;
5838 }
5839
5840
5841 /****************************************************************************/
5842 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
5843 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
5844 /*                                                                          */
5845 /* Returns:                                                                 */
5846 /*   0 for success, positive value for failure.                             */
5847 /****************************************************************************/
5848 static int
5849 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5850 {
5851         struct bce_softc *sc;
5852         int error;
5853         uint32_t val, result;
5854
5855         result = -1;
5856         error = sysctl_handle_int(oidp, &result, 0, req);
5857         if (error || (req->newptr == NULL))
5858                 return (error);
5859
5860         /* Make sure the register is accessible. */
5861         if (result < 0x8000) {
5862                 sc = (struct bce_softc *)arg1;
5863                 val = REG_RD(sc, result);
5864                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5865                           result, val);
5866         } else if (result < 0x0280000) {
5867                 sc = (struct bce_softc *)arg1;
5868                 val = REG_RD_IND(sc, result);
5869                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5870                           result, val);
5871         }
5872         return (error);
5873 }
5874
5875
5876 /****************************************************************************/
5877 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
5878 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
5879 /*                                                                          */
5880 /* Returns:                                                                 */
5881 /*   0 for success, positive value for failure.                             */
5882 /****************************************************************************/
5883 static int
5884 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
5885 {
5886         struct bce_softc *sc;
5887         device_t dev;
5888         int error, result;
5889         uint16_t val;
5890
5891         result = -1;
5892         error = sysctl_handle_int(oidp, &result, 0, req);
5893         if (error || (req->newptr == NULL))
5894                 return (error);
5895
5896         /* Make sure the register is accessible. */
5897         if (result < 0x20) {
5898                 sc = (struct bce_softc *)arg1;
5899                 dev = sc->bce_dev;
5900                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
5901                 if_printf(&sc->arpcom.ac_if,
5902                           "phy 0x%02X = 0x%04X\n", result, val);
5903         }
5904         return (error);
5905 }
5906
5907
5908 /****************************************************************************/
5909 /* Provides a sysctl interface to forcing the driver to dump state and      */
5910 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
5911 /*                                                                          */
5912 /* Returns:                                                                 */
5913 /*   0 for success, positive value for failure.                             */
5914 /****************************************************************************/
5915 static int
5916 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
5917 {
5918         int error;
5919         int result;
5920         struct bce_softc *sc;
5921
5922         result = -1;
5923         error = sysctl_handle_int(oidp, &result, 0, req);
5924
5925         if (error || !req->newptr)
5926                 return (error);
5927
5928         if (result == 1) {
5929                 sc = (struct bce_softc *)arg1;
5930                 bce_breakpoint(sc);
5931         }
5932
5933         return error;
5934 }
5935 #endif
5936
5937
5938 /****************************************************************************/
5939 /* Adds any sysctl parameters for tuning or debugging purposes.             */
5940 /*                                                                          */
5941 /* Returns:                                                                 */
5942 /*   0 for success, positive value for failure.                             */
5943 /****************************************************************************/
5944 static void
5945 bce_add_sysctls(struct bce_softc *sc)
5946 {
5947         struct sysctl_ctx_list *ctx;
5948         struct sysctl_oid_list *children;
5949
5950         sysctl_ctx_init(&sc->bce_sysctl_ctx);
5951         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
5952                                               SYSCTL_STATIC_CHILDREN(_hw),
5953                                               OID_AUTO,
5954                                               device_get_nameunit(sc->bce_dev),
5955                                               CTLFLAG_RD, 0, "");
5956         if (sc->bce_sysctl_tree == NULL) {
5957                 device_printf(sc->bce_dev, "can't add sysctl node\n");
5958                 return;
5959         }
5960
5961         ctx = &sc->bce_sysctl_ctx;
5962         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
5963
5964         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
5965                         CTLTYPE_INT | CTLFLAG_RW,
5966                         sc, 0, bce_sysctl_tx_bds_int, "I",
5967                         "Send max coalesced BD count during interrupt");
5968         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
5969                         CTLTYPE_INT | CTLFLAG_RW,
5970                         sc, 0, bce_sysctl_tx_bds, "I",
5971                         "Send max coalesced BD count");
5972         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
5973                         CTLTYPE_INT | CTLFLAG_RW,
5974                         sc, 0, bce_sysctl_tx_ticks_int, "I",
5975                         "Send coalescing ticks during interrupt");
5976         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
5977                         CTLTYPE_INT | CTLFLAG_RW,
5978                         sc, 0, bce_sysctl_tx_ticks, "I",
5979                         "Send coalescing ticks");
5980
5981         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
5982                         CTLTYPE_INT | CTLFLAG_RW,
5983                         sc, 0, bce_sysctl_rx_bds_int, "I",
5984                         "Receive max coalesced BD count during interrupt");
5985         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
5986                         CTLTYPE_INT | CTLFLAG_RW,
5987                         sc, 0, bce_sysctl_rx_bds, "I",
5988                         "Receive max coalesced BD count");
5989         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
5990                         CTLTYPE_INT | CTLFLAG_RW,
5991                         sc, 0, bce_sysctl_rx_ticks_int, "I",
5992                         "Receive coalescing ticks during interrupt");
5993         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
5994                         CTLTYPE_INT | CTLFLAG_RW,
5995                         sc, 0, bce_sysctl_rx_ticks, "I",
5996                         "Receive coalescing ticks");
5997
5998 #ifdef BCE_DEBUG
5999         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6000                 "rx_low_watermark",
6001                 CTLFLAG_RD, &sc->rx_low_watermark,
6002                 0, "Lowest level of free rx_bd's");
6003
6004         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6005                 "rx_empty_count",
6006                 CTLFLAG_RD, &sc->rx_empty_count,
6007                 0, "Number of times the RX chain was empty");
6008
6009         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6010                 "tx_hi_watermark",
6011                 CTLFLAG_RD, &sc->tx_hi_watermark,
6012                 0, "Highest level of used tx_bd's");
6013
6014         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6015                 "tx_full_count",
6016                 CTLFLAG_RD, &sc->tx_full_count,
6017                 0, "Number of times the TX chain was full");
6018
6019         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6020                 "l2fhdr_status_errors",
6021                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6022                 0, "l2_fhdr status errors");
6023
6024         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6025                 "unexpected_attentions",
6026                 CTLFLAG_RD, &sc->unexpected_attentions,
6027                 0, "unexpected attentions");
6028
6029         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6030                 "lost_status_block_updates",
6031                 CTLFLAG_RD, &sc->lost_status_block_updates,
6032                 0, "lost status block updates");
6033
6034         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6035                 "mbuf_alloc_failed",
6036                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6037                 0, "mbuf cluster allocation failures");
6038 #endif
6039
6040         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6041                 "stat_IfHCInOctets",
6042                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6043                 "Bytes received");
6044
6045         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6046                 "stat_IfHCInBadOctets",
6047                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6048                 "Bad bytes received");
6049
6050         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6051                 "stat_IfHCOutOctets",
6052                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6053                 "Bytes sent");
6054
6055         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6056                 "stat_IfHCOutBadOctets",
6057                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6058                 "Bad bytes sent");
6059
6060         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6061                 "stat_IfHCInUcastPkts",
6062                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6063                 "Unicast packets received");
6064
6065         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6066                 "stat_IfHCInMulticastPkts",
6067                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6068                 "Multicast packets received");
6069
6070         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6071                 "stat_IfHCInBroadcastPkts",
6072                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6073                 "Broadcast packets received");
6074
6075         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6076                 "stat_IfHCOutUcastPkts",
6077                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6078                 "Unicast packets sent");
6079
6080         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6081                 "stat_IfHCOutMulticastPkts",
6082                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6083                 "Multicast packets sent");
6084
6085         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6086                 "stat_IfHCOutBroadcastPkts",
6087                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6088                 "Broadcast packets sent");
6089
6090         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6091                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6092                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6093                 0, "Internal MAC transmit errors");
6094
6095         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6096                 "stat_Dot3StatsCarrierSenseErrors",
6097                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6098                 0, "Carrier sense errors");
6099
6100         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6101                 "stat_Dot3StatsFCSErrors",
6102                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6103                 0, "Frame check sequence errors");
6104
6105         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6106                 "stat_Dot3StatsAlignmentErrors",
6107                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6108                 0, "Alignment errors");
6109
6110         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6111                 "stat_Dot3StatsSingleCollisionFrames",
6112                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6113                 0, "Single Collision Frames");
6114
6115         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6116                 "stat_Dot3StatsMultipleCollisionFrames",
6117                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6118                 0, "Multiple Collision Frames");
6119
6120         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6121                 "stat_Dot3StatsDeferredTransmissions",
6122                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6123                 0, "Deferred Transmissions");
6124
6125         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6126                 "stat_Dot3StatsExcessiveCollisions",
6127                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6128                 0, "Excessive Collisions");
6129
6130         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6131                 "stat_Dot3StatsLateCollisions",
6132                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6133                 0, "Late Collisions");
6134
6135         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6136                 "stat_EtherStatsCollisions",
6137                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6138                 0, "Collisions");
6139
6140         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6141                 "stat_EtherStatsFragments",
6142                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6143                 0, "Fragments");
6144
6145         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6146                 "stat_EtherStatsJabbers",
6147                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6148                 0, "Jabbers");
6149
6150         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6151                 "stat_EtherStatsUndersizePkts",
6152                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6153                 0, "Undersize packets");
6154
6155         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6156                 "stat_EtherStatsOverrsizePkts",
6157                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6158                 0, "stat_EtherStatsOverrsizePkts");
6159
6160         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6161                 "stat_EtherStatsPktsRx64Octets",
6162                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6163                 0, "Bytes received in 64 byte packets");
6164
6165         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6166                 "stat_EtherStatsPktsRx65Octetsto127Octets",
6167                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6168                 0, "Bytes received in 65 to 127 byte packets");
6169
6170         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6171                 "stat_EtherStatsPktsRx128Octetsto255Octets",
6172                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6173                 0, "Bytes received in 128 to 255 byte packets");
6174
6175         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6176                 "stat_EtherStatsPktsRx256Octetsto511Octets",
6177                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6178                 0, "Bytes received in 256 to 511 byte packets");
6179
6180         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6181                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6182                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6183                 0, "Bytes received in 512 to 1023 byte packets");
6184
6185         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6186                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6187                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6188                 0, "Bytes received in 1024 t0 1522 byte packets");
6189
6190         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6191                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6192                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6193                 0, "Bytes received in 1523 to 9022 byte packets");
6194
6195         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6196                 "stat_EtherStatsPktsTx64Octets",
6197                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6198                 0, "Bytes sent in 64 byte packets");
6199
6200         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6201                 "stat_EtherStatsPktsTx65Octetsto127Octets",
6202                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6203                 0, "Bytes sent in 65 to 127 byte packets");
6204
6205         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6206                 "stat_EtherStatsPktsTx128Octetsto255Octets",
6207                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6208                 0, "Bytes sent in 128 to 255 byte packets");
6209
6210         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6211                 "stat_EtherStatsPktsTx256Octetsto511Octets",
6212                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6213                 0, "Bytes sent in 256 to 511 byte packets");
6214
6215         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6216                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6217                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6218                 0, "Bytes sent in 512 to 1023 byte packets");
6219
6220         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6221                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6222                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6223                 0, "Bytes sent in 1024 to 1522 byte packets");
6224
6225         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6226                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6227                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6228                 0, "Bytes sent in 1523 to 9022 byte packets");
6229
6230         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6231                 "stat_XonPauseFramesReceived",
6232                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6233                 0, "XON pause frames receved");
6234
6235         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6236                 "stat_XoffPauseFramesReceived",
6237                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6238                 0, "XOFF pause frames received");
6239
6240         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6241                 "stat_OutXonSent",
6242                 CTLFLAG_RD, &sc->stat_OutXonSent,
6243                 0, "XON pause frames sent");
6244
6245         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6246                 "stat_OutXoffSent",
6247                 CTLFLAG_RD, &sc->stat_OutXoffSent,
6248                 0, "XOFF pause frames sent");
6249
6250         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6251                 "stat_FlowControlDone",
6252                 CTLFLAG_RD, &sc->stat_FlowControlDone,
6253                 0, "Flow control done");
6254
6255         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6256                 "stat_MacControlFramesReceived",
6257                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6258                 0, "MAC control frames received");
6259
6260         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6261                 "stat_XoffStateEntered",
6262                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6263                 0, "XOFF state entered");
6264
6265         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6266                 "stat_IfInFramesL2FilterDiscards",
6267                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6268                 0, "Received L2 packets discarded");
6269
6270         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6271                 "stat_IfInRuleCheckerDiscards",
6272                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6273                 0, "Received packets discarded by rule");
6274
6275         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6276                 "stat_IfInFTQDiscards",
6277                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6278                 0, "Received packet FTQ discards");
6279
6280         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6281                 "stat_IfInMBUFDiscards",
6282                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6283                 0, "Received packets discarded due to lack of controller buffer memory");
6284
6285         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6286                 "stat_IfInRuleCheckerP4Hit",
6287                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6288                 0, "Received packets rule checker hits");
6289
6290         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6291                 "stat_CatchupInRuleCheckerDiscards",
6292                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6293                 0, "Received packets discarded in Catchup path");
6294
6295         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6296                 "stat_CatchupInFTQDiscards",
6297                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6298                 0, "Received packets discarded in FTQ in Catchup path");
6299
6300         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6301                 "stat_CatchupInMBUFDiscards",
6302                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6303                 0, "Received packets discarded in controller buffer memory in Catchup path");
6304
6305         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6306                 "stat_CatchupInRuleCheckerP4Hit",
6307                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6308                 0, "Received packets rule checker hits in Catchup path");
6309
6310         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6311                 "com_no_buffers",
6312                 CTLFLAG_RD, &sc->com_no_buffers,
6313                 0, "Valid packets received but no RX buffers available");
6314
6315 #ifdef BCE_DEBUG
6316         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6317                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6318                 (void *)sc, 0,
6319                 bce_sysctl_driver_state, "I", "Drive state information");
6320
6321         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6322                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6323                 (void *)sc, 0,
6324                 bce_sysctl_hw_state, "I", "Hardware state information");
6325
6326         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6327                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6328                 (void *)sc, 0,
6329                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6330
6331         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6332                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6333                 (void *)sc, 0,
6334                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6335
6336         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6337                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6338                 (void *)sc, 0,
6339                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6340
6341         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6342                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6343                 (void *)sc, 0,
6344                 bce_sysctl_reg_read, "I", "Register read");
6345
6346         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6347                 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6348                 (void *)sc, 0,
6349                 bce_sysctl_phy_read, "I", "PHY register read");
6350
6351 #endif
6352
6353 }
6354
6355
6356 /****************************************************************************/
6357 /* BCE Debug Routines                                                       */
6358 /****************************************************************************/
6359 #ifdef BCE_DEBUG
6360
6361 /****************************************************************************/
6362 /* Freezes the controller to allow for a cohesive state dump.               */
6363 /*                                                                          */
6364 /* Returns:                                                                 */
6365 /*   Nothing.                                                               */
6366 /****************************************************************************/
6367 static void
6368 bce_freeze_controller(struct bce_softc *sc)
6369 {
6370         uint32_t val;
6371
6372         val = REG_RD(sc, BCE_MISC_COMMAND);
6373         val |= BCE_MISC_COMMAND_DISABLE_ALL;
6374         REG_WR(sc, BCE_MISC_COMMAND, val);
6375 }
6376
6377
6378 /****************************************************************************/
6379 /* Unfreezes the controller after a freeze operation.  This may not always  */
6380 /* work and the controller will require a reset!                            */
6381 /*                                                                          */
6382 /* Returns:                                                                 */
6383 /*   Nothing.                                                               */
6384 /****************************************************************************/
6385 static void
6386 bce_unfreeze_controller(struct bce_softc *sc)
6387 {
6388         uint32_t val;
6389
6390         val = REG_RD(sc, BCE_MISC_COMMAND);
6391         val |= BCE_MISC_COMMAND_ENABLE_ALL;
6392         REG_WR(sc, BCE_MISC_COMMAND, val);
6393 }
6394
6395
6396 /****************************************************************************/
6397 /* Prints out information about an mbuf.                                    */
6398 /*                                                                          */
6399 /* Returns:                                                                 */
6400 /*   Nothing.                                                               */
6401 /****************************************************************************/
6402 static void
6403 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6404 {
6405         struct ifnet *ifp = &sc->arpcom.ac_if;
6406         uint32_t val_hi, val_lo;
6407         struct mbuf *mp = m;
6408
6409         if (m == NULL) {
6410                 /* Index out of range. */
6411                 if_printf(ifp, "mbuf: null pointer\n");
6412                 return;
6413         }
6414
6415         while (mp) {
6416                 val_hi = BCE_ADDR_HI(mp);
6417                 val_lo = BCE_ADDR_LO(mp);
6418                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6419                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
6420
6421                 if (mp->m_flags & M_EXT)
6422                         kprintf("M_EXT ");
6423                 if (mp->m_flags & M_PKTHDR)
6424                         kprintf("M_PKTHDR ");
6425                 if (mp->m_flags & M_EOR)
6426                         kprintf("M_EOR ");
6427 #ifdef M_RDONLY
6428                 if (mp->m_flags & M_RDONLY)
6429                         kprintf("M_RDONLY ");
6430 #endif
6431
6432                 val_hi = BCE_ADDR_HI(mp->m_data);
6433                 val_lo = BCE_ADDR_LO(mp->m_data);
6434                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6435
6436                 if (mp->m_flags & M_PKTHDR) {
6437                         if_printf(ifp, "- m_pkthdr: flags = ( ");
6438                         if (mp->m_flags & M_BCAST)
6439                                 kprintf("M_BCAST ");
6440                         if (mp->m_flags & M_MCAST)
6441                                 kprintf("M_MCAST ");
6442                         if (mp->m_flags & M_FRAG)
6443                                 kprintf("M_FRAG ");
6444                         if (mp->m_flags & M_FIRSTFRAG)
6445                                 kprintf("M_FIRSTFRAG ");
6446                         if (mp->m_flags & M_LASTFRAG)
6447                                 kprintf("M_LASTFRAG ");
6448 #ifdef M_VLANTAG
6449                         if (mp->m_flags & M_VLANTAG)
6450                                 kprintf("M_VLANTAG ");
6451 #endif
6452 #ifdef M_PROMISC
6453                         if (mp->m_flags & M_PROMISC)
6454                                 kprintf("M_PROMISC ");
6455 #endif
6456                         kprintf(") csum_flags = ( ");
6457                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
6458                                 kprintf("CSUM_IP ");
6459                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6460                                 kprintf("CSUM_TCP ");
6461                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6462                                 kprintf("CSUM_UDP ");
6463                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6464                                 kprintf("CSUM_IP_FRAGS ");
6465                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6466                                 kprintf("CSUM_FRAGMENT ");
6467 #ifdef CSUM_TSO
6468                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6469                                 kprintf("CSUM_TSO ");
6470 #endif
6471                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6472                                 kprintf("CSUM_IP_CHECKED ");
6473                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6474                                 kprintf("CSUM_IP_VALID ");
6475                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6476                                 kprintf("CSUM_DATA_VALID ");
6477                         kprintf(")\n");
6478                 }
6479
6480                 if (mp->m_flags & M_EXT) {
6481                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6482                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6483                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6484                                   "ext_size = %d\n",
6485                                   val_hi, val_lo, mp->m_ext.ext_size);
6486                 }
6487                 mp = mp->m_next;
6488         }
6489 }
6490
6491
6492 /****************************************************************************/
6493 /* Prints out the mbufs in the TX mbuf chain.                               */
6494 /*                                                                          */
6495 /* Returns:                                                                 */
6496 /*   Nothing.                                                               */
6497 /****************************************************************************/
6498 static void
6499 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6500 {
6501         struct ifnet *ifp = &sc->arpcom.ac_if;
6502         int i;
6503
6504         if_printf(ifp,
6505         "----------------------------"
6506         "  tx mbuf data  "
6507         "----------------------------\n");
6508
6509         for (i = 0; i < count; i++) {
6510                 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6511                 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6512                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6513         }
6514
6515         if_printf(ifp,
6516         "----------------------------"
6517         "----------------"
6518         "----------------------------\n");
6519 }
6520
6521
6522 /****************************************************************************/
6523 /* Prints out the mbufs in the RX mbuf chain.                               */
6524 /*                                                                          */
6525 /* Returns:                                                                 */
6526 /*   Nothing.                                                               */
6527 /****************************************************************************/
6528 static void
6529 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6530 {
6531         struct ifnet *ifp = &sc->arpcom.ac_if;
6532         int i;
6533
6534         if_printf(ifp,
6535         "----------------------------"
6536         "  rx mbuf data  "
6537         "----------------------------\n");
6538
6539         for (i = 0; i < count; i++) {
6540                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6541                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6542                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6543         }
6544
6545         if_printf(ifp,
6546         "----------------------------"
6547         "----------------"
6548         "----------------------------\n");
6549 }
6550
6551
6552 /****************************************************************************/
6553 /* Prints out a tx_bd structure.                                            */
6554 /*                                                                          */
6555 /* Returns:                                                                 */
6556 /*   Nothing.                                                               */
6557 /****************************************************************************/
6558 static void
6559 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6560 {
6561         struct ifnet *ifp = &sc->arpcom.ac_if;
6562
6563         if (idx > MAX_TX_BD) {
6564                 /* Index out of range. */
6565                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6566         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6567                 /* TX Chain page pointer. */
6568                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6569                           "chain page pointer\n",
6570                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6571         } else {
6572                 /* Normal tx_bd entry. */
6573                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6574                           "nbytes = 0x%08X, "
6575                           "vlan tag= 0x%04X, flags = 0x%04X (",
6576                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6577                           txbd->tx_bd_mss_nbytes,
6578                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6579
6580                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6581                         kprintf(" CONN_FAULT");
6582
6583                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6584                         kprintf(" TCP_UDP_CKSUM");
6585
6586                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6587                         kprintf(" IP_CKSUM");
6588
6589                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6590                         kprintf("  VLAN");
6591
6592                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6593                         kprintf(" COAL_NOW");
6594
6595                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6596                         kprintf(" DONT_GEN_CRC");
6597
6598                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6599                         kprintf(" START");
6600
6601                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6602                         kprintf(" END");
6603
6604                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6605                         kprintf(" LSO");
6606
6607                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6608                         kprintf(" OPTION_WORD");
6609
6610                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6611                         kprintf(" FLAGS");
6612
6613                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6614                         kprintf(" SNAP");
6615
6616                 kprintf(" )\n");
6617         }
6618 }
6619
6620
6621 /****************************************************************************/
6622 /* Prints out a rx_bd structure.                                            */
6623 /*                                                                          */
6624 /* Returns:                                                                 */
6625 /*   Nothing.                                                               */
6626 /****************************************************************************/
6627 static void
6628 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6629 {
6630         struct ifnet *ifp = &sc->arpcom.ac_if;
6631
6632         if (idx > MAX_RX_BD) {
6633                 /* Index out of range. */
6634                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6635         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6636                 /* TX Chain page pointer. */
6637                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6638                           "chain page pointer\n",
6639                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6640         } else {
6641                 /* Normal tx_bd entry. */
6642                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6643                           "nbytes = 0x%08X, flags = 0x%08X\n",
6644                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6645                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6646         }
6647 }
6648
6649
6650 /****************************************************************************/
6651 /* Prints out a l2_fhdr structure.                                          */
6652 /*                                                                          */
6653 /* Returns:                                                                 */
6654 /*   Nothing.                                                               */
6655 /****************************************************************************/
6656 static void
6657 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6658 {
6659         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6660                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6661                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6662                   idx, l2fhdr->l2_fhdr_status,
6663                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6664                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6665 }
6666
6667
6668 /****************************************************************************/
6669 /* Prints out the tx chain.                                                 */
6670 /*                                                                          */
6671 /* Returns:                                                                 */
6672 /*   Nothing.                                                               */
6673 /****************************************************************************/
6674 static void
6675 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6676 {
6677         struct ifnet *ifp = &sc->arpcom.ac_if;
6678         int i;
6679
6680         /* First some info about the tx_bd chain structure. */
6681         if_printf(ifp,
6682         "----------------------------"
6683         "  tx_bd  chain  "
6684         "----------------------------\n");
6685
6686         if_printf(ifp, "page size      = 0x%08X, "
6687                   "tx chain pages        = 0x%08X\n",
6688                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6689
6690         if_printf(ifp, "tx_bd per page = 0x%08X, "
6691                   "usable tx_bd per page = 0x%08X\n",
6692                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6693                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6694
6695         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6696
6697         if_printf(ifp,
6698         "----------------------------"
6699         "  tx_bd data    "
6700         "----------------------------\n");
6701
6702         /* Now print out the tx_bd's themselves. */
6703         for (i = 0; i < count; i++) {
6704                 struct tx_bd *txbd;
6705
6706                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6707                 bce_dump_txbd(sc, tx_prod, txbd);
6708                 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6709         }
6710
6711         if_printf(ifp,
6712         "----------------------------"
6713         "----------------"
6714         "----------------------------\n");
6715 }
6716
6717
6718 /****************************************************************************/
6719 /* Prints out the rx chain.                                                 */
6720 /*                                                                          */
6721 /* Returns:                                                                 */
6722 /*   Nothing.                                                               */
6723 /****************************************************************************/
6724 static void
6725 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6726 {
6727         struct ifnet *ifp = &sc->arpcom.ac_if;
6728         int i;
6729
6730         /* First some info about the tx_bd chain structure. */
6731         if_printf(ifp,
6732         "----------------------------"
6733         "  rx_bd  chain  "
6734         "----------------------------\n");
6735
6736         if_printf(ifp, "page size      = 0x%08X, "
6737                   "rx chain pages        = 0x%08X\n",
6738                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6739
6740         if_printf(ifp, "rx_bd per page = 0x%08X, "
6741                   "usable rx_bd per page = 0x%08X\n",
6742                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6743                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6744
6745         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6746
6747         if_printf(ifp,
6748         "----------------------------"
6749         "   rx_bd data   "
6750         "----------------------------\n");
6751
6752         /* Now print out the rx_bd's themselves. */
6753         for (i = 0; i < count; i++) {
6754                 struct rx_bd *rxbd;
6755
6756                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6757                 bce_dump_rxbd(sc, rx_prod, rxbd);
6758                 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6759         }
6760
6761         if_printf(ifp,
6762         "----------------------------"
6763         "----------------"
6764         "----------------------------\n");
6765 }
6766
6767
6768 /****************************************************************************/
6769 /* Prints out the status block from host memory.                            */
6770 /*                                                                          */
6771 /* Returns:                                                                 */
6772 /*   Nothing.                                                               */
6773 /****************************************************************************/
6774 static void
6775 bce_dump_status_block(struct bce_softc *sc)
6776 {
6777         struct status_block *sblk = sc->status_block;
6778         struct ifnet *ifp = &sc->arpcom.ac_if;
6779
6780         if_printf(ifp,
6781         "----------------------------"
6782         "  Status Block  "
6783         "----------------------------\n");
6784
6785         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
6786
6787         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
6788                   sblk->status_attn_bits_ack);
6789
6790         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6791             sblk->status_rx_quick_consumer_index0,
6792             (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6793
6794         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6795             sblk->status_tx_quick_consumer_index0,
6796             (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6797
6798         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
6799
6800         /* Theses indices are not used for normal L2 drivers. */
6801         if (sblk->status_rx_quick_consumer_index1) {
6802                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6803                 sblk->status_rx_quick_consumer_index1,
6804                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6805         }
6806
6807         if (sblk->status_tx_quick_consumer_index1) {
6808                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6809                 sblk->status_tx_quick_consumer_index1,
6810                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6811         }
6812
6813         if (sblk->status_rx_quick_consumer_index2) {
6814                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6815                 sblk->status_rx_quick_consumer_index2,
6816                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6817         }
6818
6819         if (sblk->status_tx_quick_consumer_index2) {
6820                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6821                 sblk->status_tx_quick_consumer_index2,
6822                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6823         }
6824
6825         if (sblk->status_rx_quick_consumer_index3) {
6826                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6827                 sblk->status_rx_quick_consumer_index3,
6828                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
6829         }
6830
6831         if (sblk->status_tx_quick_consumer_index3) {
6832                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6833                 sblk->status_tx_quick_consumer_index3,
6834                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
6835         }
6836
6837         if (sblk->status_rx_quick_consumer_index4 ||
6838             sblk->status_rx_quick_consumer_index5) {
6839                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
6840                           sblk->status_rx_quick_consumer_index4,
6841                           sblk->status_rx_quick_consumer_index5);
6842         }
6843
6844         if (sblk->status_rx_quick_consumer_index6 ||
6845             sblk->status_rx_quick_consumer_index7) {
6846                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
6847                           sblk->status_rx_quick_consumer_index6,
6848                           sblk->status_rx_quick_consumer_index7);
6849         }
6850
6851         if (sblk->status_rx_quick_consumer_index8 ||
6852             sblk->status_rx_quick_consumer_index9) {
6853                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
6854                           sblk->status_rx_quick_consumer_index8,
6855                           sblk->status_rx_quick_consumer_index9);
6856         }
6857
6858         if (sblk->status_rx_quick_consumer_index10 ||
6859             sblk->status_rx_quick_consumer_index11) {
6860                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
6861                           sblk->status_rx_quick_consumer_index10,
6862                           sblk->status_rx_quick_consumer_index11);
6863         }
6864
6865         if (sblk->status_rx_quick_consumer_index12 ||
6866             sblk->status_rx_quick_consumer_index13) {
6867                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
6868                           sblk->status_rx_quick_consumer_index12,
6869                           sblk->status_rx_quick_consumer_index13);
6870         }
6871
6872         if (sblk->status_rx_quick_consumer_index14 ||
6873             sblk->status_rx_quick_consumer_index15) {
6874                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
6875                           sblk->status_rx_quick_consumer_index14,
6876                           sblk->status_rx_quick_consumer_index15);
6877         }
6878
6879         if (sblk->status_completion_producer_index ||
6880             sblk->status_cmd_consumer_index) {
6881                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
6882                           sblk->status_completion_producer_index,
6883                           sblk->status_cmd_consumer_index);
6884         }
6885
6886         if_printf(ifp,
6887         "----------------------------"
6888         "----------------"
6889         "----------------------------\n");
6890 }
6891
6892
6893 /****************************************************************************/
6894 /* Prints out the statistics block.                                         */
6895 /*                                                                          */
6896 /* Returns:                                                                 */
6897 /*   Nothing.                                                               */
6898 /****************************************************************************/
6899 static void
6900 bce_dump_stats_block(struct bce_softc *sc)
6901 {
6902         struct statistics_block *sblk = sc->stats_block;
6903         struct ifnet *ifp = &sc->arpcom.ac_if;
6904
6905         if_printf(ifp,
6906         "---------------"
6907         " Stats Block  (All Stats Not Shown Are 0) "
6908         "---------------\n");
6909
6910         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
6911                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
6912                           sblk->stat_IfHCInOctets_hi,
6913                           sblk->stat_IfHCInOctets_lo);
6914         }
6915
6916         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
6917                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
6918                           sblk->stat_IfHCInBadOctets_hi,
6919                           sblk->stat_IfHCInBadOctets_lo);
6920         }
6921
6922         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
6923                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
6924                           sblk->stat_IfHCOutOctets_hi,
6925                           sblk->stat_IfHCOutOctets_lo);
6926         }
6927
6928         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
6929                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
6930                           sblk->stat_IfHCOutBadOctets_hi,
6931                           sblk->stat_IfHCOutBadOctets_lo);
6932         }
6933
6934         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
6935                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
6936                           sblk->stat_IfHCInUcastPkts_hi,
6937                           sblk->stat_IfHCInUcastPkts_lo);
6938         }
6939
6940         if (sblk->stat_IfHCInBroadcastPkts_hi ||
6941             sblk->stat_IfHCInBroadcastPkts_lo) {
6942                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
6943                           sblk->stat_IfHCInBroadcastPkts_hi,
6944                           sblk->stat_IfHCInBroadcastPkts_lo);
6945         }
6946
6947         if (sblk->stat_IfHCInMulticastPkts_hi ||
6948             sblk->stat_IfHCInMulticastPkts_lo) {
6949                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
6950                           sblk->stat_IfHCInMulticastPkts_hi,
6951                           sblk->stat_IfHCInMulticastPkts_lo);
6952         }
6953
6954         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
6955                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
6956                           sblk->stat_IfHCOutUcastPkts_hi,
6957                           sblk->stat_IfHCOutUcastPkts_lo);
6958         }
6959
6960         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
6961             sblk->stat_IfHCOutBroadcastPkts_lo) {
6962                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
6963                           sblk->stat_IfHCOutBroadcastPkts_hi,
6964                           sblk->stat_IfHCOutBroadcastPkts_lo);
6965         }
6966
6967         if (sblk->stat_IfHCOutMulticastPkts_hi ||
6968             sblk->stat_IfHCOutMulticastPkts_lo) {
6969                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
6970                           sblk->stat_IfHCOutMulticastPkts_hi,
6971                           sblk->stat_IfHCOutMulticastPkts_lo);
6972         }
6973
6974         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
6975                 if_printf(ifp, "         0x%08X : "
6976                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
6977                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
6978         }
6979
6980         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
6981                 if_printf(ifp, "         0x%08X : "
6982                           "Dot3StatsCarrierSenseErrors\n",
6983                           sblk->stat_Dot3StatsCarrierSenseErrors);
6984         }
6985
6986         if (sblk->stat_Dot3StatsFCSErrors) {
6987                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
6988                           sblk->stat_Dot3StatsFCSErrors);
6989         }
6990
6991         if (sblk->stat_Dot3StatsAlignmentErrors) {
6992                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
6993                           sblk->stat_Dot3StatsAlignmentErrors);
6994         }
6995
6996         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
6997                 if_printf(ifp, "         0x%08X : "
6998                           "Dot3StatsSingleCollisionFrames\n",
6999                           sblk->stat_Dot3StatsSingleCollisionFrames);
7000         }
7001
7002         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7003                 if_printf(ifp, "         0x%08X : "
7004                           "Dot3StatsMultipleCollisionFrames\n",
7005                           sblk->stat_Dot3StatsMultipleCollisionFrames);
7006         }
7007
7008         if (sblk->stat_Dot3StatsDeferredTransmissions) {
7009                 if_printf(ifp, "         0x%08X : "
7010                           "Dot3StatsDeferredTransmissions\n",
7011                           sblk->stat_Dot3StatsDeferredTransmissions);
7012         }
7013
7014         if (sblk->stat_Dot3StatsExcessiveCollisions) {
7015                 if_printf(ifp, "         0x%08X : "
7016                           "Dot3StatsExcessiveCollisions\n",
7017                           sblk->stat_Dot3StatsExcessiveCollisions);
7018         }
7019
7020         if (sblk->stat_Dot3StatsLateCollisions) {
7021                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
7022                           sblk->stat_Dot3StatsLateCollisions);
7023         }
7024
7025         if (sblk->stat_EtherStatsCollisions) {
7026                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
7027                           sblk->stat_EtherStatsCollisions);
7028         }
7029
7030         if (sblk->stat_EtherStatsFragments)  {
7031                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
7032                           sblk->stat_EtherStatsFragments);
7033         }
7034
7035         if (sblk->stat_EtherStatsJabbers) {
7036                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
7037                           sblk->stat_EtherStatsJabbers);
7038         }
7039
7040         if (sblk->stat_EtherStatsUndersizePkts) {
7041                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
7042                           sblk->stat_EtherStatsUndersizePkts);
7043         }
7044
7045         if (sblk->stat_EtherStatsOverrsizePkts) {
7046                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
7047                           sblk->stat_EtherStatsOverrsizePkts);
7048         }
7049
7050         if (sblk->stat_EtherStatsPktsRx64Octets) {
7051                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
7052                           sblk->stat_EtherStatsPktsRx64Octets);
7053         }
7054
7055         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7056                 if_printf(ifp, "         0x%08X : "
7057                           "EtherStatsPktsRx65Octetsto127Octets\n",
7058                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7059         }
7060
7061         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7062                 if_printf(ifp, "         0x%08X : "
7063                           "EtherStatsPktsRx128Octetsto255Octets\n",
7064                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7065         }
7066
7067         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7068                 if_printf(ifp, "         0x%08X : "
7069                           "EtherStatsPktsRx256Octetsto511Octets\n",
7070                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7071         }
7072
7073         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7074                 if_printf(ifp, "         0x%08X : "
7075                           "EtherStatsPktsRx512Octetsto1023Octets\n",
7076                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7077         }
7078
7079         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7080                 if_printf(ifp, "         0x%08X : "
7081                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
7082                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7083         }
7084
7085         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7086                 if_printf(ifp, "         0x%08X : "
7087                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
7088                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7089         }
7090
7091         if (sblk->stat_EtherStatsPktsTx64Octets) {
7092                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
7093                           sblk->stat_EtherStatsPktsTx64Octets);
7094         }
7095
7096         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7097                 if_printf(ifp, "         0x%08X : "
7098                           "EtherStatsPktsTx65Octetsto127Octets\n",
7099                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7100         }
7101
7102         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7103                 if_printf(ifp, "         0x%08X : "
7104                           "EtherStatsPktsTx128Octetsto255Octets\n",
7105                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7106         }
7107
7108         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7109                 if_printf(ifp, "         0x%08X : "
7110                           "EtherStatsPktsTx256Octetsto511Octets\n",
7111                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7112         }
7113
7114         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7115                 if_printf(ifp, "         0x%08X : "
7116                           "EtherStatsPktsTx512Octetsto1023Octets\n",
7117                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7118         }
7119
7120         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7121                 if_printf(ifp, "         0x%08X : "
7122                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
7123                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7124         }
7125
7126         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7127                 if_printf(ifp, "         0x%08X : "
7128                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
7129                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7130         }
7131
7132         if (sblk->stat_XonPauseFramesReceived) {
7133                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
7134                           sblk->stat_XonPauseFramesReceived);
7135         }
7136
7137         if (sblk->stat_XoffPauseFramesReceived) {
7138                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
7139                           sblk->stat_XoffPauseFramesReceived);
7140         }
7141
7142         if (sblk->stat_OutXonSent) {
7143                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7144                           sblk->stat_OutXonSent);
7145         }
7146
7147         if (sblk->stat_OutXoffSent) {
7148                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7149                           sblk->stat_OutXoffSent);
7150         }
7151
7152         if (sblk->stat_FlowControlDone) {
7153                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
7154                           sblk->stat_FlowControlDone);
7155         }
7156
7157         if (sblk->stat_MacControlFramesReceived) {
7158                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
7159                           sblk->stat_MacControlFramesReceived);
7160         }
7161
7162         if (sblk->stat_XoffStateEntered) {
7163                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
7164                           sblk->stat_XoffStateEntered);
7165         }
7166
7167         if (sblk->stat_IfInFramesL2FilterDiscards) {
7168                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
7169         }
7170
7171         if (sblk->stat_IfInRuleCheckerDiscards) {
7172                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
7173                           sblk->stat_IfInRuleCheckerDiscards);
7174         }
7175
7176         if (sblk->stat_IfInFTQDiscards) {
7177                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
7178                           sblk->stat_IfInFTQDiscards);
7179         }
7180
7181         if (sblk->stat_IfInMBUFDiscards) {
7182                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
7183                           sblk->stat_IfInMBUFDiscards);
7184         }
7185
7186         if (sblk->stat_IfInRuleCheckerP4Hit) {
7187                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
7188                           sblk->stat_IfInRuleCheckerP4Hit);
7189         }
7190
7191         if (sblk->stat_CatchupInRuleCheckerDiscards) {
7192                 if_printf(ifp, "         0x%08X : "
7193                           "CatchupInRuleCheckerDiscards\n",
7194                           sblk->stat_CatchupInRuleCheckerDiscards);
7195         }
7196
7197         if (sblk->stat_CatchupInFTQDiscards) {
7198                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
7199                           sblk->stat_CatchupInFTQDiscards);
7200         }
7201
7202         if (sblk->stat_CatchupInMBUFDiscards) {
7203                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
7204                           sblk->stat_CatchupInMBUFDiscards);
7205         }
7206
7207         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7208                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
7209                           sblk->stat_CatchupInRuleCheckerP4Hit);
7210         }
7211
7212         if_printf(ifp,
7213         "----------------------------"
7214         "----------------"
7215         "----------------------------\n");
7216 }
7217
7218
7219 /****************************************************************************/
7220 /* Prints out a summary of the driver state.                                */
7221 /*                                                                          */
7222 /* Returns:                                                                 */
7223 /*   Nothing.                                                               */
7224 /****************************************************************************/
7225 static void
7226 bce_dump_driver_state(struct bce_softc *sc)
7227 {
7228         struct ifnet *ifp = &sc->arpcom.ac_if;
7229         uint32_t val_hi, val_lo;
7230
7231         if_printf(ifp,
7232         "-----------------------------"
7233         " Driver State "
7234         "-----------------------------\n");
7235
7236         val_hi = BCE_ADDR_HI(sc);
7237         val_lo = BCE_ADDR_LO(sc);
7238         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7239                   "virtual address\n", val_hi, val_lo);
7240
7241         val_hi = BCE_ADDR_HI(sc->status_block);
7242         val_lo = BCE_ADDR_LO(sc->status_block);
7243         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7244                   "virtual address\n", val_hi, val_lo);
7245
7246         val_hi = BCE_ADDR_HI(sc->stats_block);
7247         val_lo = BCE_ADDR_LO(sc->stats_block);
7248         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7249                   "virtual address\n", val_hi, val_lo);
7250
7251         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7252         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7253         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7254                   "virtual adddress\n", val_hi, val_lo);
7255
7256         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7257         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7258         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7259                   "virtual address\n", val_hi, val_lo);
7260
7261         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7262         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7263         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7264                   "virtual address\n", val_hi, val_lo);
7265
7266         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7267         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7268         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7269                   "virtual address\n", val_hi, val_lo);
7270
7271         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
7272                   "h/w intrs\n", sc->interrupts_generated);
7273
7274         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
7275                   "rx interrupts handled\n", sc->rx_interrupts);
7276
7277         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
7278                   "tx interrupts handled\n", sc->tx_interrupts);
7279
7280         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
7281                   "status block index\n", sc->last_status_idx);
7282
7283         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
7284                   "tx producer index\n",
7285                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
7286
7287         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
7288                   "tx consumer index\n",
7289                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
7290
7291         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
7292                   "tx producer bseq index\n", sc->tx_prod_bseq);
7293
7294         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
7295                   "rx producer index\n",
7296                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
7297
7298         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
7299                   "rx consumer index\n",
7300                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
7301
7302         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
7303                   "rx producer bseq index\n", sc->rx_prod_bseq);
7304
7305         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7306                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7307
7308         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
7309                   "free rx_bd's\n", sc->free_rx_bd);
7310
7311         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7312                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7313
7314         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
7315                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7316
7317         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7318                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7319
7320         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7321                   sc->used_tx_bd);
7322
7323         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7324                   sc->tx_hi_watermark, sc->max_tx_bd);
7325
7326         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
7327                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7328
7329         if_printf(ifp,
7330         "----------------------------"
7331         "----------------"
7332         "----------------------------\n");
7333 }
7334
7335
7336 /****************************************************************************/
7337 /* Prints out the hardware state through a summary of important registers,  */
7338 /* followed by a complete register dump.                                    */
7339 /*                                                                          */
7340 /* Returns:                                                                 */
7341 /*   Nothing.                                                               */
7342 /****************************************************************************/
7343 static void
7344 bce_dump_hw_state(struct bce_softc *sc)
7345 {
7346         struct ifnet *ifp = &sc->arpcom.ac_if;
7347         uint32_t val1;
7348         int i;
7349
7350         if_printf(ifp,
7351         "----------------------------"
7352         " Hardware State "
7353         "----------------------------\n");
7354
7355         if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_bc_ver);
7356
7357         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7358         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7359                   val1, BCE_MISC_ENABLE_STATUS_BITS);
7360
7361         val1 = REG_RD(sc, BCE_DMA_STATUS);
7362         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7363
7364         val1 = REG_RD(sc, BCE_CTX_STATUS);
7365         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7366
7367         val1 = REG_RD(sc, BCE_EMAC_STATUS);
7368         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7369                   val1, BCE_EMAC_STATUS);
7370
7371         val1 = REG_RD(sc, BCE_RPM_STATUS);
7372         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7373
7374         val1 = REG_RD(sc, BCE_TBDR_STATUS);
7375         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7376                   val1, BCE_TBDR_STATUS);
7377
7378         val1 = REG_RD(sc, BCE_TDMA_STATUS);
7379         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7380                   val1, BCE_TDMA_STATUS);
7381
7382         val1 = REG_RD(sc, BCE_HC_STATUS);
7383         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7384
7385         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7386         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7387                   val1, BCE_TXP_CPU_STATE);
7388
7389         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7390         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7391                   val1, BCE_TPAT_CPU_STATE);
7392
7393         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7394         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7395                   val1, BCE_RXP_CPU_STATE);
7396
7397         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7398         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7399                   val1, BCE_COM_CPU_STATE);
7400
7401         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7402         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7403                   val1, BCE_MCP_CPU_STATE);
7404
7405         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7406         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7407                   val1, BCE_CP_CPU_STATE);
7408
7409         if_printf(ifp,
7410         "----------------------------"
7411         "----------------"
7412         "----------------------------\n");
7413
7414         if_printf(ifp,
7415         "----------------------------"
7416         " Register  Dump "
7417         "----------------------------\n");
7418
7419         for (i = 0x400; i < 0x8000; i += 0x10) {
7420                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7421                           REG_RD(sc, i),
7422                           REG_RD(sc, i + 0x4),
7423                           REG_RD(sc, i + 0x8),
7424                           REG_RD(sc, i + 0xc));
7425         }
7426
7427         if_printf(ifp,
7428         "----------------------------"
7429         "----------------"
7430         "----------------------------\n");
7431 }
7432
7433
7434 /****************************************************************************/
7435 /* Prints out the TXP state.                                                */
7436 /*                                                                          */
7437 /* Returns:                                                                 */
7438 /*   Nothing.                                                               */
7439 /****************************************************************************/
7440 static void
7441 bce_dump_txp_state(struct bce_softc *sc)
7442 {
7443         struct ifnet *ifp = &sc->arpcom.ac_if;
7444         uint32_t val1;
7445         int i;
7446
7447         if_printf(ifp,
7448         "----------------------------"
7449         "   TXP  State   "
7450         "----------------------------\n");
7451
7452         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7453         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7454                   val1, BCE_TXP_CPU_MODE);
7455
7456         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7457         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7458                   val1, BCE_TXP_CPU_STATE);
7459
7460         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7461         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7462                   val1, BCE_TXP_CPU_EVENT_MASK);
7463
7464         if_printf(ifp,
7465         "----------------------------"
7466         " Register  Dump "
7467         "----------------------------\n");
7468
7469         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7470                 /* Skip the big blank spaces */
7471                 if (i < 0x454000 && i > 0x5ffff) {
7472                         if_printf(ifp, "0x%04X: "
7473                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7474                                   REG_RD_IND(sc, i),
7475                                   REG_RD_IND(sc, i + 0x4),
7476                                   REG_RD_IND(sc, i + 0x8),
7477                                   REG_RD_IND(sc, i + 0xc));
7478                 }
7479         }
7480
7481         if_printf(ifp,
7482         "----------------------------"
7483         "----------------"
7484         "----------------------------\n");
7485 }
7486
7487
7488 /****************************************************************************/
7489 /* Prints out the RXP state.                                                */
7490 /*                                                                          */
7491 /* Returns:                                                                 */
7492 /*   Nothing.                                                               */
7493 /****************************************************************************/
7494 static void
7495 bce_dump_rxp_state(struct bce_softc *sc)
7496 {
7497         struct ifnet *ifp = &sc->arpcom.ac_if;
7498         uint32_t val1;
7499         int i;
7500
7501         if_printf(ifp,
7502         "----------------------------"
7503         "   RXP  State   "
7504         "----------------------------\n");
7505
7506         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7507         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7508                   val1, BCE_RXP_CPU_MODE);
7509
7510         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7511         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7512                   val1, BCE_RXP_CPU_STATE);
7513
7514         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7515         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7516                   val1, BCE_RXP_CPU_EVENT_MASK);
7517
7518         if_printf(ifp,
7519         "----------------------------"
7520         " Register  Dump "
7521         "----------------------------\n");
7522
7523         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7524                 /* Skip the big blank sapces */
7525                 if (i < 0xc5400 && i > 0xdffff) {
7526                         if_printf(ifp, "0x%04X: "
7527                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7528                                   REG_RD_IND(sc, i),
7529                                   REG_RD_IND(sc, i + 0x4),
7530                                   REG_RD_IND(sc, i + 0x8),
7531                                   REG_RD_IND(sc, i + 0xc));
7532                 }
7533         }
7534
7535         if_printf(ifp,
7536         "----------------------------"
7537         "----------------"
7538         "----------------------------\n");
7539 }
7540
7541
7542 /****************************************************************************/
7543 /* Prints out the TPAT state.                                               */
7544 /*                                                                          */
7545 /* Returns:                                                                 */
7546 /*   Nothing.                                                               */
7547 /****************************************************************************/
7548 static void
7549 bce_dump_tpat_state(struct bce_softc *sc)
7550 {
7551         struct ifnet *ifp = &sc->arpcom.ac_if;
7552         uint32_t val1;
7553         int i;
7554
7555         if_printf(ifp,
7556         "----------------------------"
7557         "   TPAT State   "
7558         "----------------------------\n");
7559
7560         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7561         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7562                   val1, BCE_TPAT_CPU_MODE);
7563
7564         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7565         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7566                   val1, BCE_TPAT_CPU_STATE);
7567
7568         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7569         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7570                   val1, BCE_TPAT_CPU_EVENT_MASK);
7571
7572         if_printf(ifp,
7573         "----------------------------"
7574         " Register  Dump "
7575         "----------------------------\n");
7576
7577         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7578                 /* Skip the big blank spaces */
7579                 if (i < 0x854000 && i > 0x9ffff) {
7580                         if_printf(ifp, "0x%04X: "
7581                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7582                                   REG_RD_IND(sc, i),
7583                                   REG_RD_IND(sc, i + 0x4),
7584                                   REG_RD_IND(sc, i + 0x8),
7585                                   REG_RD_IND(sc, i + 0xc));
7586                 }
7587         }
7588
7589         if_printf(ifp,
7590         "----------------------------"
7591         "----------------"
7592         "----------------------------\n");
7593 }
7594
7595
7596 /****************************************************************************/
7597 /* Prints out the driver state and then enters the debugger.                */
7598 /*                                                                          */
7599 /* Returns:                                                                 */
7600 /*   Nothing.                                                               */
7601 /****************************************************************************/
7602 static void
7603 bce_breakpoint(struct bce_softc *sc)
7604 {
7605 #if 0
7606         bce_freeze_controller(sc);
7607 #endif
7608
7609         bce_dump_driver_state(sc);
7610         bce_dump_status_block(sc);
7611         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7612         bce_dump_hw_state(sc);
7613         bce_dump_txp_state(sc);
7614
7615 #if 0
7616         bce_unfreeze_controller(sc);
7617 #endif
7618
7619         /* Call the debugger. */
7620         breakpoint();
7621 }
7622
7623 #endif  /* BCE_DEBUG */
7624
7625 static int
7626 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7627 {
7628         struct bce_softc *sc = arg1;
7629
7630         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7631                         &sc->bce_tx_quick_cons_trip_int,
7632                         BCE_COALMASK_TX_BDS_INT);
7633 }
7634
7635 static int
7636 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7637 {
7638         struct bce_softc *sc = arg1;
7639
7640         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7641                         &sc->bce_tx_quick_cons_trip,
7642                         BCE_COALMASK_TX_BDS);
7643 }
7644
7645 static int
7646 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7647 {
7648         struct bce_softc *sc = arg1;
7649
7650         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7651                         &sc->bce_tx_ticks_int,
7652                         BCE_COALMASK_TX_TICKS_INT);
7653 }
7654
7655 static int
7656 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7657 {
7658         struct bce_softc *sc = arg1;
7659
7660         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7661                         &sc->bce_tx_ticks,
7662                         BCE_COALMASK_TX_TICKS);
7663 }
7664
7665 static int
7666 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7667 {
7668         struct bce_softc *sc = arg1;
7669
7670         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7671                         &sc->bce_rx_quick_cons_trip_int,
7672                         BCE_COALMASK_RX_BDS_INT);
7673 }
7674
7675 static int
7676 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7677 {
7678         struct bce_softc *sc = arg1;
7679
7680         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7681                         &sc->bce_rx_quick_cons_trip,
7682                         BCE_COALMASK_RX_BDS);
7683 }
7684
7685 static int
7686 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7687 {
7688         struct bce_softc *sc = arg1;
7689
7690         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7691                         &sc->bce_rx_ticks_int,
7692                         BCE_COALMASK_RX_TICKS_INT);
7693 }
7694
7695 static int
7696 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7697 {
7698         struct bce_softc *sc = arg1;
7699
7700         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7701                         &sc->bce_rx_ticks,
7702                         BCE_COALMASK_RX_TICKS);
7703 }
7704
7705 static int
7706 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7707                        uint32_t coalchg_mask)
7708 {
7709         struct bce_softc *sc = arg1;
7710         struct ifnet *ifp = &sc->arpcom.ac_if;
7711         int error = 0, v;
7712
7713         lwkt_serialize_enter(ifp->if_serializer);
7714
7715         v = *coal;
7716         error = sysctl_handle_int(oidp, &v, 0, req);
7717         if (!error && req->newptr != NULL) {
7718                 if (v < 0) {
7719                         error = EINVAL;
7720                 } else {
7721                         *coal = v;
7722                         sc->bce_coalchg_mask |= coalchg_mask;
7723                 }
7724         }
7725
7726         lwkt_serialize_exit(ifp->if_serializer);
7727         return error;
7728 }
7729
7730 static void
7731 bce_coal_change(struct bce_softc *sc)
7732 {
7733         struct ifnet *ifp = &sc->arpcom.ac_if;
7734
7735         ASSERT_SERIALIZED(ifp->if_serializer);
7736
7737         if ((ifp->if_flags & IFF_RUNNING) == 0) {
7738                 sc->bce_coalchg_mask = 0;
7739                 return;
7740         }
7741
7742         if (sc->bce_coalchg_mask &
7743             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7744                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7745                        (sc->bce_tx_quick_cons_trip_int << 16) |
7746                        sc->bce_tx_quick_cons_trip);
7747                 if (bootverbose) {
7748                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7749                                   sc->bce_tx_quick_cons_trip,
7750                                   sc->bce_tx_quick_cons_trip_int);
7751                 }
7752         }
7753
7754         if (sc->bce_coalchg_mask &
7755             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7756                 REG_WR(sc, BCE_HC_TX_TICKS,
7757                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7758                 if (bootverbose) {
7759                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7760                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7761                 }
7762         }
7763
7764         if (sc->bce_coalchg_mask &
7765             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7766                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7767                        (sc->bce_rx_quick_cons_trip_int << 16) |
7768                        sc->bce_rx_quick_cons_trip);
7769                 if (bootverbose) {
7770                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7771                                   sc->bce_rx_quick_cons_trip,
7772                                   sc->bce_rx_quick_cons_trip_int);
7773                 }
7774         }
7775
7776         if (sc->bce_coalchg_mask &
7777             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7778                 REG_WR(sc, BCE_HC_RX_TICKS,
7779                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7780                 if (bootverbose) {
7781                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7782                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7783                 }
7784         }
7785
7786         sc->bce_coalchg_mask = 0;
7787 }