2 * Copyright (c) 2007-2009
3 * Damien Bergamini <damien.bergamini@free.fr>
5 * Benjamin Close <benjsc@FreeBSD.org>
6 * Copyright (c) 2008 Sam Leffler, Errno Consulting
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network
28 #include <sys/param.h>
29 #include <sys/sockio.h>
30 #include <sys/sysctl.h>
32 #include <sys/kernel.h>
33 #include <sys/socket.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
38 #include <sys/endian.h>
39 #include <sys/firmware.h>
40 #include <sys/limits.h>
41 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/taskqueue.h>
44 #include <sys/libkern.h>
47 #include <sys/resource.h>
48 #include <machine/clock.h>
50 #include <bus/pci/pcireg.h>
51 #include <bus/pci/pcivar.h>
55 #include <net/if_arp.h>
56 #include <net/ifq_var.h>
57 #include <net/ethernet.h>
58 #include <net/if_dl.h>
59 #include <net/if_media.h>
60 #include <net/if_types.h>
62 #include <netinet/in.h>
63 #include <netinet/in_systm.h>
64 #include <netinet/in_var.h>
65 #include <netinet/if_ether.h>
66 #include <netinet/ip.h>
68 #include <netproto/802_11/ieee80211_var.h>
69 #include <netproto/802_11/ieee80211_radiotap.h>
70 #include <netproto/802_11/ieee80211_regdomain.h>
71 #include <netproto/802_11/ieee80211_ratectl.h>
73 #include "if_iwnreg.h"
74 #include "if_iwnvar.h"
76 static int iwn_probe(device_t);
77 static int iwn_attach(device_t);
78 static const struct iwn_hal *iwn_hal_attach(struct iwn_softc *);
79 static void iwn_radiotap_attach(struct iwn_softc *);
80 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *,
81 const char name[IFNAMSIZ], int unit, int opmode,
82 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
83 const uint8_t mac[IEEE80211_ADDR_LEN]);
84 static void iwn_vap_delete(struct ieee80211vap *);
85 static int iwn_cleanup(device_t);
86 static int iwn_detach(device_t);
87 static int iwn_nic_lock(struct iwn_softc *);
88 static int iwn_eeprom_lock(struct iwn_softc *);
89 static int iwn_init_otprom(struct iwn_softc *);
90 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);
91 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int);
92 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *,
93 void **, bus_size_t, bus_size_t, int);
94 static void iwn_dma_contig_free(struct iwn_dma_info *);
95 static int iwn_alloc_sched(struct iwn_softc *);
96 static void iwn_free_sched(struct iwn_softc *);
97 static int iwn_alloc_kw(struct iwn_softc *);
98 static void iwn_free_kw(struct iwn_softc *);
99 static int iwn_alloc_ict(struct iwn_softc *);
100 static void iwn_free_ict(struct iwn_softc *);
101 static int iwn_alloc_fwmem(struct iwn_softc *);
102 static void iwn_free_fwmem(struct iwn_softc *);
103 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
104 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
105 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
106 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *,
108 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
109 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
110 static void iwn5000_ict_reset(struct iwn_softc *);
111 static int iwn_read_eeprom(struct iwn_softc *,
112 uint8_t macaddr[IEEE80211_ADDR_LEN]);
113 static void iwn4965_read_eeprom(struct iwn_softc *);
114 static void iwn4965_print_power_group(struct iwn_softc *, int);
115 static void iwn5000_read_eeprom(struct iwn_softc *);
116 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *);
117 static void iwn_read_eeprom_band(struct iwn_softc *, int);
119 static void iwn_read_eeprom_ht40(struct iwn_softc *, int);
121 static void iwn_read_eeprom_channels(struct iwn_softc *, int,
123 static void iwn_read_eeprom_enhinfo(struct iwn_softc *);
124 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *,
125 const uint8_t mac[IEEE80211_ADDR_LEN]);
126 static void iwn_newassoc(struct ieee80211_node *, int);
127 static int iwn_media_change(struct ifnet *);
128 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
129 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *,
130 struct iwn_rx_data *);
131 static void iwn_timer_timeout(void *);
132 static void iwn_calib_reset(struct iwn_softc *);
133 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *,
134 struct iwn_rx_data *);
136 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *,
137 struct iwn_rx_data *);
139 static void iwn5000_rx_calib_results(struct iwn_softc *,
140 struct iwn_rx_desc *, struct iwn_rx_data *);
141 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *,
142 struct iwn_rx_data *);
143 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
144 struct iwn_rx_data *);
145 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
146 struct iwn_rx_data *);
147 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int,
149 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *);
150 static void iwn_notif_intr(struct iwn_softc *);
151 static void iwn_wakeup_intr(struct iwn_softc *);
152 static void iwn_rftoggle_intr(struct iwn_softc *);
153 static void iwn_fatal_intr(struct iwn_softc *);
154 static void iwn_intr(void *);
155 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t,
157 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t,
160 static void iwn5000_reset_sched(struct iwn_softc *, int, int);
162 static uint8_t iwn_plcp_signal(int);
163 static int iwn_tx_data(struct iwn_softc *, struct mbuf *,
164 struct ieee80211_node *, struct iwn_tx_ring *);
165 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
166 const struct ieee80211_bpf_params *);
167 static void iwn_start(struct ifnet *);
168 static void iwn_start_locked(struct ifnet *);
169 static void iwn_watchdog(struct iwn_softc *sc);
170 static int iwn_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
171 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int);
172 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *,
174 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *,
176 static int iwn_set_link_quality(struct iwn_softc *, uint8_t, int);
177 static int iwn_add_broadcast_node(struct iwn_softc *, int);
178 static int iwn_wme_update(struct ieee80211com *);
179 static void iwn_update_mcast(struct ifnet *);
180 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t);
181 static int iwn_set_critical_temp(struct iwn_softc *);
182 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *);
183 static void iwn4965_power_calibration(struct iwn_softc *, int);
184 static int iwn4965_set_txpower(struct iwn_softc *,
185 struct ieee80211_channel *, int);
186 static int iwn5000_set_txpower(struct iwn_softc *,
187 struct ieee80211_channel *, int);
188 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
189 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
190 static int iwn_get_noise(const struct iwn_rx_general_stats *);
191 static int iwn4965_get_temperature(struct iwn_softc *);
192 static int iwn5000_get_temperature(struct iwn_softc *);
193 static int iwn_init_sensitivity(struct iwn_softc *);
194 static void iwn_collect_noise(struct iwn_softc *,
195 const struct iwn_rx_general_stats *);
196 static int iwn4965_init_gains(struct iwn_softc *);
197 static int iwn5000_init_gains(struct iwn_softc *);
198 static int iwn4965_set_gains(struct iwn_softc *);
199 static int iwn5000_set_gains(struct iwn_softc *);
200 static void iwn_tune_sensitivity(struct iwn_softc *,
201 const struct iwn_rx_stats *);
202 static int iwn_send_sensitivity(struct iwn_softc *);
203 static int iwn_set_pslevel(struct iwn_softc *, int, int, int);
204 static int iwn_config(struct iwn_softc *);
205 static int iwn_scan(struct iwn_softc *);
206 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap);
207 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap);
209 static int iwn_ampdu_rx_start(struct ieee80211com *,
210 struct ieee80211_node *, uint8_t);
211 static void iwn_ampdu_rx_stop(struct ieee80211com *,
212 struct ieee80211_node *, uint8_t);
213 static int iwn_ampdu_tx_start(struct ieee80211com *,
214 struct ieee80211_node *, uint8_t);
215 static void iwn_ampdu_tx_stop(struct ieee80211com *,
216 struct ieee80211_node *, uint8_t);
217 static void iwn4965_ampdu_tx_start(struct iwn_softc *,
218 struct ieee80211_node *, uint8_t, uint16_t);
219 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t);
220 static void iwn5000_ampdu_tx_start(struct iwn_softc *,
221 struct ieee80211_node *, uint8_t, uint16_t);
222 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t);
224 static int iwn5000_query_calibration(struct iwn_softc *);
225 static int iwn5000_send_calibration(struct iwn_softc *);
226 static int iwn5000_send_wimax_coex(struct iwn_softc *);
227 static int iwn4965_post_alive(struct iwn_softc *);
228 static int iwn5000_post_alive(struct iwn_softc *);
229 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *,
231 static int iwn4965_load_firmware(struct iwn_softc *);
232 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,
233 const uint8_t *, int);
234 static int iwn5000_load_firmware(struct iwn_softc *);
235 static int iwn_read_firmware(struct iwn_softc *);
236 static int iwn_clock_wait(struct iwn_softc *);
237 static int iwn_apm_init(struct iwn_softc *);
238 static void iwn_apm_stop_master(struct iwn_softc *);
239 static void iwn_apm_stop(struct iwn_softc *);
240 static int iwn4965_nic_config(struct iwn_softc *);
241 static int iwn5000_nic_config(struct iwn_softc *);
242 static int iwn_hw_prepare(struct iwn_softc *);
243 static int iwn_hw_init(struct iwn_softc *);
244 static void iwn_hw_stop(struct iwn_softc *);
245 static void iwn_init_locked(struct iwn_softc *);
246 static void iwn_init(void *);
247 static void iwn_stop_locked(struct iwn_softc *);
248 static void iwn_stop(struct iwn_softc *);
249 static void iwn_scan_start(struct ieee80211com *);
250 static void iwn_scan_end(struct ieee80211com *);
251 static void iwn_set_channel(struct ieee80211com *);
252 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long);
253 static void iwn_scan_mindwell(struct ieee80211_scan_state *);
254 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *,
255 struct ieee80211_channel *);
256 static int iwn_setregdomain(struct ieee80211com *,
257 struct ieee80211_regdomain *, int,
258 struct ieee80211_channel []);
259 static void iwn_hw_reset(void *, int);
260 static void iwn_radio_on(void *, int);
261 static void iwn_radio_off(void *, int);
262 static void iwn_sysctlattach(struct iwn_softc *);
263 static int iwn_shutdown(device_t);
264 static int iwn_suspend(device_t);
265 static int iwn_resume(device_t);
270 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
271 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */
272 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */
273 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */
274 IWN_DEBUG_RESET = 0x00000010, /* reset processing */
275 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */
276 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */
277 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */
278 IWN_DEBUG_INTR = 0x00000100, /* ISR */
279 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */
280 IWN_DEBUG_NODE = 0x00000400, /* node management */
281 IWN_DEBUG_LED = 0x00000800, /* led management */
282 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */
283 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */
284 IWN_DEBUG_ANY = 0xffffffff
287 #define DPRINTF(sc, m, fmt, ...) do { \
288 if (sc->sc_debug & (m)) \
289 kprintf(fmt, __VA_ARGS__); \
292 static const char *iwn_intr_str(uint8_t);
294 #define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0)
303 static const struct iwn_ident iwn_ident_table [] = {
304 { 0x8086, 0x4229, "Intel(R) PRO/Wireless 4965BGN" },
305 { 0x8086, 0x422D, "Intel(R) PRO/Wireless 4965BGN" },
306 { 0x8086, 0x4230, "Intel(R) PRO/Wireless 4965BGN" },
307 { 0x8086, 0x4233, "Intel(R) PRO/Wireless 4965BGN" },
308 { 0x8086, 0x4232, "Intel(R) PRO/Wireless 5100" },
309 { 0x8086, 0x4237, "Intel(R) PRO/Wireless 5100" },
310 { 0x8086, 0x423C, "Intel(R) PRO/Wireless 5150" },
311 { 0x8086, 0x423D, "Intel(R) PRO/Wireless 5150" },
312 { 0x8086, 0x4235, "Intel(R) PRO/Wireless 5300" },
313 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5300" },
314 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5350" },
315 { 0x8086, 0x423A, "Intel(R) PRO/Wireless 5350" },
316 { 0x8086, 0x423B, "Intel(R) PRO/Wireless 5350" },
317 { 0x8086, 0x0083, "Intel(R) PRO/Wireless 1000" },
318 { 0x8086, 0x0084, "Intel(R) PRO/Wireless 1000" },
319 { 0x8086, 0x008D, "Intel(R) PRO/Wireless 6000" },
320 { 0x8086, 0x008E, "Intel(R) PRO/Wireless 6000" },
321 { 0x8086, 0x4238, "Intel(R) PRO/Wireless 6000" },
322 { 0x8086, 0x4239, "Intel(R) PRO/Wireless 6000" },
323 { 0x8086, 0x422B, "Intel(R) PRO/Wireless 6000" },
324 { 0x8086, 0x422C, "Intel(R) PRO/Wireless 6000" },
325 { 0x8086, 0x0086, "Intel(R) PRO/Wireless 6050" },
326 { 0x8086, 0x0087, "Intel(R) PRO/Wireless 6050" },
330 static const struct iwn_hal iwn4965_hal = {
331 iwn4965_load_firmware,
335 iwn4965_update_sched,
336 iwn4965_get_temperature,
344 iwn4965_ampdu_tx_start,
345 iwn4965_ampdu_tx_stop,
349 IWN4965_ID_BROADCAST,
352 IWN4965_FW_TEXT_MAXSZ,
353 IWN4965_FW_DATA_MAXSZ,
358 static const struct iwn_hal iwn5000_hal = {
359 iwn5000_load_firmware,
363 iwn5000_update_sched,
364 iwn5000_get_temperature,
372 iwn5000_ampdu_tx_start,
373 iwn5000_ampdu_tx_stop,
377 IWN5000_ID_BROADCAST,
380 IWN5000_FW_TEXT_MAXSZ,
381 IWN5000_FW_DATA_MAXSZ,
387 iwn_probe(device_t dev)
389 const struct iwn_ident *ident;
391 for (ident = iwn_ident_table; ident->name != NULL; ident++) {
392 if (pci_get_vendor(dev) == ident->vendor &&
393 pci_get_device(dev) == ident->device) {
394 device_set_desc(dev, ident->name);
402 iwn_attach(device_t dev)
404 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev);
405 struct ieee80211com *ic;
407 const struct iwn_hal *hal;
409 int i, error, result;
410 uint8_t macaddr[IEEE80211_ADDR_LEN];
415 if (bus_dma_tag_create(sc->sc_dmat,
417 BUS_SPACE_MAXADDR_32BIT,
425 device_printf(dev, "cannot allocate DMA tag\n");
432 /* prepare sysctl tree for use in sub modules */
433 sysctl_ctx_init(&sc->sc_sysctl_ctx);
434 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
435 SYSCTL_STATIC_CHILDREN(_hw),
437 device_get_nameunit(sc->sc_dev),
441 * Get the offset of the PCI Express Capability Structure in PCI
442 * Configuration Space.
444 error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
446 device_printf(dev, "PCIe capability structure not found!\n");
450 /* Clear device-specific "PCI retry timeout" register (41h). */
451 pci_write_config(dev, 0x41, 0, 1);
453 /* Hardware bug workaround. */
454 tmp = pci_read_config(dev, PCIR_COMMAND, 1);
455 if (tmp & PCIM_CMD_INTxDIS) {
456 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n",
458 tmp &= ~PCIM_CMD_INTxDIS;
459 pci_write_config(dev, PCIR_COMMAND, tmp, 1);
462 /* Enable bus-mastering. */
463 pci_enable_busmaster(dev);
465 sc->mem_rid = PCIR_BAR(0);
466 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
468 if (sc->mem == NULL ) {
469 device_printf(dev, "could not allocate memory resources\n");
474 sc->sc_st = rman_get_bustag(sc->mem);
475 sc->sc_sh = rman_get_bushandle(sc->mem);
477 if ((result = pci_msi_count(dev)) == 1 &&
478 pci_alloc_msi(dev, &result) == 0)
480 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
481 RF_ACTIVE | RF_SHAREABLE);
482 if (sc->irq == NULL) {
483 device_printf(dev, "could not allocate interrupt resource\n");
489 callout_init(&sc->sc_timer_to);
490 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc );
491 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc );
492 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc );
494 /* Attach Hardware Abstraction Layer. */
495 hal = iwn_hal_attach(sc);
497 error = ENXIO; /* XXX: Wrong error code? */
501 error = iwn_hw_prepare(sc);
503 device_printf(dev, "hardware not ready, error %d\n", error);
507 /* Allocate DMA memory for firmware transfers. */
508 error = iwn_alloc_fwmem(sc);
511 "could not allocate memory for firmware, error %d\n",
516 /* Allocate "Keep Warm" page. */
517 error = iwn_alloc_kw(sc);
520 "could not allocate \"Keep Warm\" page, error %d\n", error);
524 /* Allocate ICT table for 5000 Series. */
525 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
526 (error = iwn_alloc_ict(sc)) != 0) {
528 "%s: could not allocate ICT table, error %d\n",
533 /* Allocate TX scheduler "rings". */
534 error = iwn_alloc_sched(sc);
537 "could not allocate TX scheduler rings, error %d\n",
542 /* Allocate TX rings (16 on 4965AGN, 20 on 5000). */
543 for (i = 0; i < hal->ntxqs; i++) {
544 error = iwn_alloc_tx_ring(sc, &sc->txq[i], i);
547 "could not allocate Tx ring %d, error %d\n",
553 /* Allocate RX ring. */
554 error = iwn_alloc_rx_ring(sc, &sc->rxq);
557 "could not allocate Rx ring, error %d\n", error);
561 /* Clear pending interrupts. */
562 IWN_WRITE(sc, IWN_INT, 0xffffffff);
564 /* Count the number of available chains. */
566 ((sc->txchainmask >> 2) & 1) +
567 ((sc->txchainmask >> 1) & 1) +
568 ((sc->txchainmask >> 0) & 1);
570 ((sc->rxchainmask >> 2) & 1) +
571 ((sc->rxchainmask >> 1) & 1) +
572 ((sc->rxchainmask >> 0) & 1);
574 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
576 device_printf(dev, "can not allocate ifnet structure\n");
582 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
583 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
585 /* Set device capabilities. */
587 IEEE80211_C_STA /* station mode supported */
588 | IEEE80211_C_MONITOR /* monitor mode supported */
589 | IEEE80211_C_TXPMGT /* tx power management */
590 | IEEE80211_C_SHSLOT /* short slot time supported */
592 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
593 | IEEE80211_C_BGSCAN /* background scanning */
595 | IEEE80211_C_IBSS /* ibss/adhoc mode */
597 | IEEE80211_C_WME /* WME */
600 /* XXX disable until HT channel setup works */
602 IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */
603 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */
604 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */
605 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */
606 | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */
607 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */
608 /* s/w capabilities */
609 | IEEE80211_HTC_HT /* HT operation */
610 | IEEE80211_HTC_AMPDU /* tx A-MPDU */
611 | IEEE80211_HTC_AMSDU /* tx A-MSDU */
614 /* Set HT capabilities. */
616 #if IWN_RBUF_SIZE == 8192
617 IEEE80211_HTCAP_AMSDU7935 |
619 IEEE80211_HTCAP_CBW20_40 |
620 IEEE80211_HTCAP_SGI20 |
621 IEEE80211_HTCAP_SGI40;
622 if (sc->hw_type != IWN_HW_REV_TYPE_4965)
623 ic->ic_htcaps |= IEEE80211_HTCAP_GF;
624 if (sc->hw_type == IWN_HW_REV_TYPE_6050)
625 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN;
627 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS;
630 /* Read MAC address, channels, etc from EEPROM. */
631 error = iwn_read_eeprom(sc, macaddr);
633 device_printf(dev, "could not read EEPROM, error %d\n",
638 device_printf(sc->sc_dev, "MIMO %dT%dR, %.4s, address %6D\n",
639 sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
643 /* Set supported HT rates. */
644 ic->ic_sup_mcs[0] = 0xff;
645 if (sc->nrxchains > 1)
646 ic->ic_sup_mcs[1] = 0xff;
647 if (sc->nrxchains > 2)
648 ic->ic_sup_mcs[2] = 0xff;
651 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
653 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
654 ifp->if_init = iwn_init;
655 ifp->if_ioctl = iwn_ioctl;
656 ifp->if_start = iwn_start;
657 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
658 ifq_set_ready(&ifp->if_snd);
660 ieee80211_ifattach(ic, macaddr);
661 ic->ic_vap_create = iwn_vap_create;
662 ic->ic_vap_delete = iwn_vap_delete;
663 ic->ic_raw_xmit = iwn_raw_xmit;
664 ic->ic_node_alloc = iwn_node_alloc;
665 ic->ic_newassoc = iwn_newassoc;
666 ic->ic_wme.wme_update = iwn_wme_update;
667 ic->ic_update_mcast = iwn_update_mcast;
668 ic->ic_scan_start = iwn_scan_start;
669 ic->ic_scan_end = iwn_scan_end;
670 ic->ic_set_channel = iwn_set_channel;
671 ic->ic_scan_curchan = iwn_scan_curchan;
672 ic->ic_scan_mindwell = iwn_scan_mindwell;
673 ic->ic_setregdomain = iwn_setregdomain;
675 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
676 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
677 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start;
678 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop;
681 iwn_radiotap_attach(sc);
682 iwn_sysctlattach(sc);
685 * Hook our interrupt after all initialization is complete.
687 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
688 iwn_intr, sc, &sc->sc_ih, NULL);
690 device_printf(dev, "could not set up interrupt, error %d\n",
695 ieee80211_announce(ic);
702 static const struct iwn_hal *
703 iwn_hal_attach(struct iwn_softc *sc)
705 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf;
707 switch (sc->hw_type) {
708 case IWN_HW_REV_TYPE_4965:
709 sc->sc_hal = &iwn4965_hal;
710 sc->limits = &iwn4965_sensitivity_limits;
711 sc->fwname = "iwn4965fw";
712 sc->txchainmask = IWN_ANT_AB;
713 sc->rxchainmask = IWN_ANT_ABC;
715 case IWN_HW_REV_TYPE_5100:
716 sc->sc_hal = &iwn5000_hal;
717 sc->limits = &iwn5000_sensitivity_limits;
718 sc->fwname = "iwn5000fw";
719 sc->txchainmask = IWN_ANT_B;
720 sc->rxchainmask = IWN_ANT_AB;
722 case IWN_HW_REV_TYPE_5150:
723 sc->sc_hal = &iwn5000_hal;
724 sc->limits = &iwn5150_sensitivity_limits;
725 sc->fwname = "iwn5150fw";
726 sc->txchainmask = IWN_ANT_A;
727 sc->rxchainmask = IWN_ANT_AB;
729 case IWN_HW_REV_TYPE_5300:
730 case IWN_HW_REV_TYPE_5350:
731 sc->sc_hal = &iwn5000_hal;
732 sc->limits = &iwn5000_sensitivity_limits;
733 sc->fwname = "iwn5000fw";
734 sc->txchainmask = IWN_ANT_ABC;
735 sc->rxchainmask = IWN_ANT_ABC;
737 case IWN_HW_REV_TYPE_1000:
738 sc->sc_hal = &iwn5000_hal;
739 sc->limits = &iwn1000_sensitivity_limits;
740 sc->fwname = "iwn1000fw";
741 sc->txchainmask = IWN_ANT_A;
742 sc->rxchainmask = IWN_ANT_AB;
744 case IWN_HW_REV_TYPE_6000:
745 sc->sc_hal = &iwn5000_hal;
746 sc->limits = &iwn6000_sensitivity_limits;
747 sc->fwname = "iwn6000fw";
748 switch (pci_get_device(sc->sc_dev)) {
751 sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
752 sc->txchainmask = IWN_ANT_BC;
753 sc->rxchainmask = IWN_ANT_BC;
756 sc->txchainmask = IWN_ANT_ABC;
757 sc->rxchainmask = IWN_ANT_ABC;
761 case IWN_HW_REV_TYPE_6050:
762 sc->sc_hal = &iwn5000_hal;
763 sc->limits = &iwn6000_sensitivity_limits;
764 sc->fwname = "iwn6000fw";
765 sc->txchainmask = IWN_ANT_AB;
766 sc->rxchainmask = IWN_ANT_AB;
769 device_printf(sc->sc_dev, "adapter type %d not supported\n",
777 * Attach the interface to 802.11 radiotap.
780 iwn_radiotap_attach(struct iwn_softc *sc)
782 struct ifnet *ifp = sc->sc_ifp;
783 struct ieee80211com *ic = ifp->if_l2com;
785 ieee80211_radiotap_attach(ic,
786 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
787 IWN_TX_RADIOTAP_PRESENT,
788 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
789 IWN_RX_RADIOTAP_PRESENT);
792 static struct ieee80211vap *
793 iwn_vap_create(struct ieee80211com *ic,
794 const char name[IFNAMSIZ], int unit, int opmode, int flags,
795 const uint8_t bssid[IEEE80211_ADDR_LEN],
796 const uint8_t mac[IEEE80211_ADDR_LEN])
799 struct ieee80211vap *vap;
801 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
803 ivp = (struct iwn_vap *) kmalloc(sizeof(struct iwn_vap),
804 M_80211_VAP, M_INTWAIT | M_ZERO);
808 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
809 vap->iv_bmissthreshold = 10; /* override default */
810 /* Override with driver methods. */
811 ivp->iv_newstate = vap->iv_newstate;
812 vap->iv_newstate = iwn_newstate;
814 ieee80211_ratectl_init(vap);
815 /* Complete setup. */
816 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status);
817 ic->ic_opmode = opmode;
822 iwn_vap_delete(struct ieee80211vap *vap)
824 struct iwn_vap *ivp = IWN_VAP(vap);
826 ieee80211_ratectl_deinit(vap);
827 ieee80211_vap_detach(vap);
828 kfree(ivp, M_80211_VAP);
832 iwn_cleanup(device_t dev)
834 struct iwn_softc *sc = device_get_softc(dev);
835 struct ifnet *ifp = sc->sc_ifp;
836 struct ieee80211com *ic;
842 ieee80211_draintask(ic, &sc->sc_reinit_task);
843 ieee80211_draintask(ic, &sc->sc_radioon_task);
844 ieee80211_draintask(ic, &sc->sc_radiooff_task);
847 callout_stop(&sc->sc_timer_to);
848 ieee80211_ifdetach(ic);
851 /* Free DMA resources. */
852 iwn_free_rx_ring(sc, &sc->rxq);
853 if (sc->sc_hal != NULL)
854 for (i = 0; i < sc->sc_hal->ntxqs; i++)
855 iwn_free_tx_ring(sc, &sc->txq[i]);
862 if (sc->irq != NULL) {
863 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
864 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
865 if (sc->irq_rid == 1)
866 pci_release_msi(dev);
870 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
875 IWN_LOCK_DESTROY(sc);
880 iwn_detach(device_t dev)
882 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev);
885 bus_dma_tag_destroy(sc->sc_dmat);
890 iwn_nic_lock(struct iwn_softc *sc)
894 /* Request exclusive access to NIC. */
895 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
897 /* Spin until we actually get the lock. */
898 for (ntries = 0; ntries < 1000; ntries++) {
899 if ((IWN_READ(sc, IWN_GP_CNTRL) &
900 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) ==
901 IWN_GP_CNTRL_MAC_ACCESS_ENA)
909 iwn_nic_unlock(struct iwn_softc *sc)
911 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
914 static __inline uint32_t
915 iwn_prph_read(struct iwn_softc *sc, uint32_t addr)
917 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr);
918 IWN_BARRIER_READ_WRITE(sc);
919 return IWN_READ(sc, IWN_PRPH_RDATA);
923 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
925 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr);
926 IWN_BARRIER_WRITE(sc);
927 IWN_WRITE(sc, IWN_PRPH_WDATA, data);
931 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
933 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);
937 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
939 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);
943 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,
944 const uint32_t *data, int count)
946 for (; count > 0; count--, data++, addr += 4)
947 iwn_prph_write(sc, addr, *data);
950 static __inline uint32_t
951 iwn_mem_read(struct iwn_softc *sc, uint32_t addr)
953 IWN_WRITE(sc, IWN_MEM_RADDR, addr);
954 IWN_BARRIER_READ_WRITE(sc);
955 return IWN_READ(sc, IWN_MEM_RDATA);
959 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
961 IWN_WRITE(sc, IWN_MEM_WADDR, addr);
962 IWN_BARRIER_WRITE(sc);
963 IWN_WRITE(sc, IWN_MEM_WDATA, data);
967 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)
971 tmp = iwn_mem_read(sc, addr & ~3);
973 tmp = (tmp & 0x0000ffff) | data << 16;
975 tmp = (tmp & 0xffff0000) | data;
976 iwn_mem_write(sc, addr & ~3, tmp);
980 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,
983 for (; count > 0; count--, addr += 4)
984 *data++ = iwn_mem_read(sc, addr);
988 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
991 for (; count > 0; count--, addr += 4)
992 iwn_mem_write(sc, addr, val);
996 iwn_eeprom_lock(struct iwn_softc *sc)
1000 for (i = 0; i < 100; i++) {
1001 /* Request exclusive access to EEPROM. */
1002 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
1003 IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1005 /* Spin until we actually get the lock. */
1006 for (ntries = 0; ntries < 100; ntries++) {
1007 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
1008 IWN_HW_IF_CONFIG_EEPROM_LOCKED)
1016 static __inline void
1017 iwn_eeprom_unlock(struct iwn_softc *sc)
1019 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1023 * Initialize access by host to One Time Programmable ROM.
1024 * NB: This kind of ROM can be found on 1000 or 6000 Series only.
1027 iwn_init_otprom(struct iwn_softc *sc)
1029 uint16_t prev, base, next;
1032 /* Wait for clock stabilization before accessing prph. */
1033 error = iwn_clock_wait(sc);
1037 error = iwn_nic_lock(sc);
1040 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1042 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1045 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
1046 if (sc->hw_type != IWN_HW_REV_TYPE_1000) {
1047 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT,
1048 IWN_RESET_LINK_PWR_MGMT_DIS);
1050 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER);
1051 /* Clear ECC status. */
1052 IWN_SETBITS(sc, IWN_OTP_GP,
1053 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS);
1056 * Find the block before last block (contains the EEPROM image)
1057 * for HW without OTP shadow RAM.
1059 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
1060 /* Switch to absolute addressing mode. */
1061 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS);
1063 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) {
1064 error = iwn_read_prom_data(sc, base, &next, 2);
1067 if (next == 0) /* End of linked-list. */
1070 base = le16toh(next);
1072 if (count == 0 || count == IWN1000_OTP_NBLOCKS)
1074 /* Skip "next" word. */
1075 sc->prom_base = prev + 1;
1081 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)
1085 uint8_t *out = data;
1087 addr += sc->prom_base;
1088 for (; count > 0; count -= 2, addr++) {
1089 IWN_WRITE(sc, IWN_EEPROM, addr << 2);
1090 for (ntries = 0; ntries < 10; ntries++) {
1091 val = IWN_READ(sc, IWN_EEPROM);
1092 if (val & IWN_EEPROM_READ_VALID)
1097 device_printf(sc->sc_dev,
1098 "timeout reading ROM at 0x%x\n", addr);
1101 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1102 /* OTPROM, check for ECC errors. */
1103 tmp = IWN_READ(sc, IWN_OTP_GP);
1104 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
1105 device_printf(sc->sc_dev,
1106 "OTPROM ECC error at 0x%x\n", addr);
1109 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
1110 /* Correctable ECC error, clear bit. */
1111 IWN_SETBITS(sc, IWN_OTP_GP,
1112 IWN_OTP_GP_ECC_CORR_STTS);
1123 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1127 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs));
1128 *(bus_addr_t *)arg = segs[0].ds_addr;
1132 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
1133 void **kvap, bus_size_t size, bus_size_t alignment, int flags)
1140 error = bus_dma_tag_create(sc->sc_dmat, alignment,
1141 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size,
1142 1, size, flags, &dma->tag);
1144 device_printf(sc->sc_dev,
1145 "%s: bus_dma_tag_create failed, error %d\n",
1149 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr,
1150 flags | BUS_DMA_ZERO, &dma->map);
1152 device_printf(sc->sc_dev,
1153 "%s: bus_dmamem_alloc failed, error %d\n", __func__, error);
1156 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr,
1157 size, iwn_dma_map_addr, &dma->paddr, flags);
1159 device_printf(sc->sc_dev,
1160 "%s: bus_dmamap_load failed, error %d\n", __func__, error);
1168 iwn_dma_contig_free(dma);
1173 iwn_dma_contig_free(struct iwn_dma_info *dma)
1175 if (dma->tag != NULL) {
1176 if (dma->map != NULL) {
1177 if (dma->paddr == 0) {
1178 bus_dmamap_sync(dma->tag, dma->map,
1179 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1180 bus_dmamap_unload(dma->tag, dma->map);
1182 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map);
1184 bus_dma_tag_destroy(dma->tag);
1189 iwn_alloc_sched(struct iwn_softc *sc)
1191 /* TX scheduler rings must be aligned on a 1KB boundary. */
1192 return iwn_dma_contig_alloc(sc, &sc->sched_dma,
1193 (void **)&sc->sched, sc->sc_hal->schedsz, 1024, BUS_DMA_NOWAIT);
1197 iwn_free_sched(struct iwn_softc *sc)
1199 iwn_dma_contig_free(&sc->sched_dma);
1203 iwn_alloc_kw(struct iwn_softc *sc)
1205 /* "Keep Warm" page must be aligned on a 4KB boundary. */
1206 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096,
1211 iwn_free_kw(struct iwn_softc *sc)
1213 iwn_dma_contig_free(&sc->kw_dma);
1217 iwn_alloc_ict(struct iwn_softc *sc)
1219 /* ICT table must be aligned on a 4KB boundary. */
1220 return iwn_dma_contig_alloc(sc, &sc->ict_dma,
1221 (void **)&sc->ict, IWN_ICT_SIZE, 4096, BUS_DMA_NOWAIT);
1225 iwn_free_ict(struct iwn_softc *sc)
1227 iwn_dma_contig_free(&sc->ict_dma);
1231 iwn_alloc_fwmem(struct iwn_softc *sc)
1233 /* Must be aligned on a 16-byte boundary. */
1234 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL,
1235 sc->sc_hal->fwsz, 16, BUS_DMA_NOWAIT);
1239 iwn_free_fwmem(struct iwn_softc *sc)
1241 iwn_dma_contig_free(&sc->fw_dma);
1245 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1252 /* Allocate RX descriptors (256-byte aligned). */
1253 size = IWN_RX_RING_COUNT * sizeof (uint32_t);
1254 error = iwn_dma_contig_alloc(sc, &ring->desc_dma,
1255 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT);
1257 device_printf(sc->sc_dev,
1258 "%s: could not allocate Rx ring DMA memory, error %d\n",
1263 error = bus_dma_tag_create(sc->sc_dmat, 1, 0,
1264 BUS_SPACE_MAXADDR_32BIT,
1265 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1266 MCLBYTES, BUS_DMA_NOWAIT, &ring->data_dmat);
1268 device_printf(sc->sc_dev,
1269 "%s: bus_dma_tag_create_failed, error %d\n",
1274 /* Allocate RX status area (16-byte aligned). */
1275 error = iwn_dma_contig_alloc(sc, &ring->stat_dma,
1276 (void **)&ring->stat, sizeof (struct iwn_rx_status),
1277 16, BUS_DMA_NOWAIT);
1279 device_printf(sc->sc_dev,
1280 "%s: could not allocate Rx status DMA memory, error %d\n",
1286 * Allocate and map RX buffers.
1288 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1289 struct iwn_rx_data *data = &ring->data[i];
1292 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1294 device_printf(sc->sc_dev,
1295 "%s: bus_dmamap_create failed, error %d\n",
1300 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1301 if (data->m == NULL) {
1302 device_printf(sc->sc_dev,
1303 "%s: could not allocate rx mbuf\n", __func__);
1309 error = bus_dmamap_load(ring->data_dmat, data->map,
1310 mtod(data->m, caddr_t), MCLBYTES,
1311 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
1312 if (error != 0 && error != EFBIG) {
1313 device_printf(sc->sc_dev,
1314 "%s: bus_dmamap_load failed, error %d\n",
1317 error = ENOMEM; /* XXX unique code */
1320 bus_dmamap_sync(ring->data_dmat, data->map,
1321 BUS_DMASYNC_PREWRITE);
1323 /* Set physical address of RX buffer (256-byte aligned). */
1324 ring->desc[i] = htole32(paddr >> 8);
1326 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1327 BUS_DMASYNC_PREWRITE);
1330 iwn_free_rx_ring(sc, ring);
1335 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1339 if (iwn_nic_lock(sc) == 0) {
1340 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
1341 for (ntries = 0; ntries < 1000; ntries++) {
1342 if (IWN_READ(sc, IWN_FH_RX_STATUS) &
1343 IWN_FH_RX_STATUS_IDLE)
1350 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
1351 "timeout resetting Rx ring");
1355 sc->last_rx_valid = 0;
1359 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1363 iwn_dma_contig_free(&ring->desc_dma);
1364 iwn_dma_contig_free(&ring->stat_dma);
1366 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1367 struct iwn_rx_data *data = &ring->data[i];
1369 if (data->m != NULL) {
1370 bus_dmamap_sync(ring->data_dmat, data->map,
1371 BUS_DMASYNC_POSTREAD);
1372 bus_dmamap_unload(ring->data_dmat, data->map);
1375 if (data->map != NULL)
1376 bus_dmamap_destroy(ring->data_dmat, data->map);
1381 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
1391 /* Allocate TX descriptors (256-byte aligned.) */
1392 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_desc);
1393 error = iwn_dma_contig_alloc(sc, &ring->desc_dma,
1394 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT);
1396 device_printf(sc->sc_dev,
1397 "%s: could not allocate TX ring DMA memory, error %d\n",
1403 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need
1404 * to allocate commands space for other rings.
1409 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_cmd);
1410 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma,
1411 (void **)&ring->cmd, size, 4, BUS_DMA_NOWAIT);
1413 device_printf(sc->sc_dev,
1414 "%s: could not allocate TX cmd DMA memory, error %d\n",
1419 error = bus_dma_tag_create(sc->sc_dmat, 1, 0,
1420 BUS_SPACE_MAXADDR_32BIT,
1421 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IWN_MAX_SCATTER - 1,
1422 MCLBYTES, BUS_DMA_NOWAIT, &ring->data_dmat);
1424 device_printf(sc->sc_dev,
1425 "%s: bus_dma_tag_create_failed, error %d\n",
1430 paddr = ring->cmd_dma.paddr;
1431 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1432 struct iwn_tx_data *data = &ring->data[i];
1434 data->cmd_paddr = paddr;
1435 data->scratch_paddr = paddr + 12;
1436 paddr += sizeof (struct iwn_tx_cmd);
1438 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1440 device_printf(sc->sc_dev,
1441 "%s: bus_dmamap_create failed, error %d\n",
1445 bus_dmamap_sync(ring->data_dmat, data->map,
1446 BUS_DMASYNC_PREWRITE);
1450 iwn_free_tx_ring(sc, ring);
1455 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1459 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1460 struct iwn_tx_data *data = &ring->data[i];
1462 if (data->m != NULL) {
1463 bus_dmamap_unload(ring->data_dmat, data->map);
1468 /* Clear TX descriptors. */
1469 memset(ring->desc, 0, ring->desc_dma.size);
1470 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1471 BUS_DMASYNC_PREWRITE);
1472 sc->qfullmsk &= ~(1 << ring->qid);
1478 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1482 iwn_dma_contig_free(&ring->desc_dma);
1483 iwn_dma_contig_free(&ring->cmd_dma);
1485 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1486 struct iwn_tx_data *data = &ring->data[i];
1488 if (data->m != NULL) {
1489 bus_dmamap_sync(ring->data_dmat, data->map,
1490 BUS_DMASYNC_POSTWRITE);
1491 bus_dmamap_unload(ring->data_dmat, data->map);
1494 if (data->map != NULL)
1495 bus_dmamap_destroy(ring->data_dmat, data->map);
1500 iwn5000_ict_reset(struct iwn_softc *sc)
1502 /* Disable interrupts. */
1503 IWN_WRITE(sc, IWN_INT_MASK, 0);
1505 /* Reset ICT table. */
1506 memset(sc->ict, 0, IWN_ICT_SIZE);
1509 /* Set physical address of ICT table (4KB aligned.) */
1510 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__);
1511 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
1512 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
1514 /* Enable periodic RX interrupt. */
1515 sc->int_mask |= IWN_INT_RX_PERIODIC;
1516 /* Switch to ICT interrupt mode in driver. */
1517 sc->sc_flags |= IWN_FLAG_USE_ICT;
1519 /* Re-enable interrupts. */
1520 IWN_WRITE(sc, IWN_INT, 0xffffffff);
1521 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
1525 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
1527 const struct iwn_hal *hal = sc->sc_hal;
1531 /* Check whether adapter has an EEPROM or an OTPROM. */
1532 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
1533 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP))
1534 sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
1535 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n",
1536 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM");
1538 /* Adapter has to be powered on for EEPROM access to work. */
1539 error = iwn_apm_init(sc);
1541 device_printf(sc->sc_dev,
1542 "%s: could not power ON adapter, error %d\n",
1547 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) {
1548 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__);
1551 error = iwn_eeprom_lock(sc);
1553 device_printf(sc->sc_dev,
1554 "%s: could not lock ROM, error %d\n",
1559 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1560 error = iwn_init_otprom(sc);
1562 device_printf(sc->sc_dev,
1563 "%s: could not initialize OTPROM, error %d\n",
1569 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
1570 sc->rfcfg = le16toh(val);
1571 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg);
1573 /* Read MAC address. */
1574 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6);
1576 /* Read adapter-specific information from EEPROM. */
1577 hal->read_eeprom(sc);
1579 iwn_apm_stop(sc); /* Power OFF adapter. */
1581 iwn_eeprom_unlock(sc);
1586 iwn4965_read_eeprom(struct iwn_softc *sc)
1592 /* Read regulatory domain (4 ASCII characters.) */
1593 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
1595 /* Read the list of authorized channels (20MHz ones only.) */
1596 for (i = 0; i < 5; i++) {
1597 addr = iwn4965_regulatory_bands[i];
1598 iwn_read_eeprom_channels(sc, i, addr);
1601 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */
1602 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
1603 sc->maxpwr2GHz = val & 0xff;
1604 sc->maxpwr5GHz = val >> 8;
1605 /* Check that EEPROM values are within valid range. */
1606 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
1607 sc->maxpwr5GHz = 38;
1608 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
1609 sc->maxpwr2GHz = 38;
1610 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n",
1611 sc->maxpwr2GHz, sc->maxpwr5GHz);
1613 /* Read samples for each TX power group. */
1614 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
1617 /* Read voltage at which samples were taken. */
1618 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
1619 sc->eeprom_voltage = (int16_t)le16toh(val);
1620 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n",
1621 sc->eeprom_voltage);
1624 /* Print samples. */
1625 if (sc->sc_debug & IWN_DEBUG_ANY) {
1626 for (i = 0; i < IWN_NBANDS; i++)
1627 iwn4965_print_power_group(sc, i);
1634 iwn4965_print_power_group(struct iwn_softc *sc, int i)
1636 struct iwn4965_eeprom_band *band = &sc->bands[i];
1637 struct iwn4965_eeprom_chan_samples *chans = band->chans;
1640 kprintf("===band %d===\n", i);
1641 kprintf("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
1642 kprintf("chan1 num=%d\n", chans[0].num);
1643 for (c = 0; c < 2; c++) {
1644 for (j = 0; j < IWN_NSAMPLES; j++) {
1645 kprintf("chain %d, sample %d: temp=%d gain=%d "
1646 "power=%d pa_det=%d\n", c, j,
1647 chans[0].samples[c][j].temp,
1648 chans[0].samples[c][j].gain,
1649 chans[0].samples[c][j].power,
1650 chans[0].samples[c][j].pa_det);
1653 kprintf("chan2 num=%d\n", chans[1].num);
1654 for (c = 0; c < 2; c++) {
1655 for (j = 0; j < IWN_NSAMPLES; j++) {
1656 kprintf("chain %d, sample %d: temp=%d gain=%d "
1657 "power=%d pa_det=%d\n", c, j,
1658 chans[1].samples[c][j].temp,
1659 chans[1].samples[c][j].gain,
1660 chans[1].samples[c][j].power,
1661 chans[1].samples[c][j].pa_det);
1668 iwn5000_read_eeprom(struct iwn_softc *sc)
1670 struct iwn5000_eeprom_calib_hdr hdr;
1672 uint32_t addr, base;
1676 /* Read regulatory domain (4 ASCII characters.) */
1677 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1678 base = le16toh(val);
1679 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN,
1680 sc->eeprom_domain, 4);
1682 /* Read the list of authorized channels (20MHz ones only.) */
1683 for (i = 0; i < 5; i++) {
1684 addr = base + iwn5000_regulatory_bands[i];
1685 iwn_read_eeprom_channels(sc, i, addr);
1688 /* Read enhanced TX power information for 6000 Series. */
1689 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1690 iwn_read_eeprom_enhinfo(sc);
1692 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
1693 base = le16toh(val);
1694 iwn_read_prom_data(sc, base, &hdr, sizeof hdr);
1695 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
1696 "%s: calib version=%u pa type=%u voltage=%u\n",
1697 __func__, hdr.version, hdr.pa_type, le16toh(hdr.volt));
1698 sc->calib_ver = hdr.version;
1700 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
1701 /* Compute temperature offset. */
1702 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
1703 temp = le16toh(val);
1704 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
1705 volt = le16toh(val);
1706 sc->temp_off = temp - (volt / -5);
1707 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n",
1708 temp, volt, sc->temp_off);
1710 /* Read crystal calibration. */
1711 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL,
1712 &sc->eeprom_crystal, sizeof (uint32_t));
1713 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n",
1714 le32toh(sc->eeprom_crystal));
1719 * Translate EEPROM flags to net80211.
1722 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel)
1727 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0)
1728 nflags |= IEEE80211_CHAN_PASSIVE;
1729 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0)
1730 nflags |= IEEE80211_CHAN_NOADHOC;
1731 if (channel->flags & IWN_EEPROM_CHAN_RADAR) {
1732 nflags |= IEEE80211_CHAN_DFS;
1733 /* XXX apparently IBSS may still be marked */
1734 nflags |= IEEE80211_CHAN_NOADHOC;
1741 iwn_read_eeprom_band(struct iwn_softc *sc, int n)
1743 struct ifnet *ifp = sc->sc_ifp;
1744 struct ieee80211com *ic = ifp->if_l2com;
1745 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1746 const struct iwn_chan_band *band = &iwn_bands[n];
1747 struct ieee80211_channel *c;
1748 int i, chan, nflags;
1750 for (i = 0; i < band->nchan; i++) {
1751 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
1752 DPRINTF(sc, IWN_DEBUG_RESET,
1753 "skip chan %d flags 0x%x maxpwr %d\n",
1754 band->chan[i], channels[i].flags,
1755 channels[i].maxpwr);
1758 chan = band->chan[i];
1759 nflags = iwn_eeprom_channel_flags(&channels[i]);
1761 DPRINTF(sc, IWN_DEBUG_RESET,
1762 "add chan %d flags 0x%x maxpwr %d\n",
1763 chan, channels[i].flags, channels[i].maxpwr);
1765 c = &ic->ic_channels[ic->ic_nchans++];
1767 c->ic_maxregpower = channels[i].maxpwr;
1768 c->ic_maxpower = 2*c->ic_maxregpower;
1770 /* Save maximum allowed TX power for this channel. */
1771 sc->maxpwr[chan] = channels[i].maxpwr;
1773 if (n == 0) { /* 2GHz band */
1774 c->ic_freq = ieee80211_ieee2mhz(chan,
1777 /* G =>'s B is supported */
1778 c->ic_flags = IEEE80211_CHAN_B | nflags;
1780 c = &ic->ic_channels[ic->ic_nchans++];
1782 c->ic_flags = IEEE80211_CHAN_G | nflags;
1783 } else { /* 5GHz band */
1784 c->ic_freq = ieee80211_ieee2mhz(chan,
1786 c->ic_flags = IEEE80211_CHAN_A | nflags;
1787 sc->sc_flags |= IWN_FLAG_HAS_5GHZ;
1790 /* XXX no constraints on using HT20 */
1791 /* add HT20, HT40 added separately */
1792 c = &ic->ic_channels[ic->ic_nchans++];
1794 c->ic_flags |= IEEE80211_CHAN_HT20;
1795 /* XXX NARROW =>'s 1/2 and 1/4 width? */
1802 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n)
1804 struct ifnet *ifp = sc->sc_ifp;
1805 struct ieee80211com *ic = ifp->if_l2com;
1806 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1807 const struct iwn_chan_band *band = &iwn_bands[n];
1808 struct ieee80211_channel *c, *cent, *extc;
1811 for (i = 0; i < band->nchan; i++) {
1812 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID) ||
1813 !(channels[i].flags & IWN_EEPROM_CHAN_WIDE)) {
1814 DPRINTF(sc, IWN_DEBUG_RESET,
1815 "skip chan %d flags 0x%x maxpwr %d\n",
1816 band->chan[i], channels[i].flags,
1817 channels[i].maxpwr);
1821 * Each entry defines an HT40 channel pair; find the
1822 * center channel, then the extension channel above.
1824 cent = ieee80211_find_channel_byieee(ic, band->chan[i],
1825 band->flags & ~IEEE80211_CHAN_HT);
1826 if (cent == NULL) { /* XXX shouldn't happen */
1827 device_printf(sc->sc_dev,
1828 "%s: no entry for channel %d\n",
1829 __func__, band->chan[i]);
1832 extc = ieee80211_find_channel(ic, cent->ic_freq+20,
1833 band->flags & ~IEEE80211_CHAN_HT);
1835 DPRINTF(sc, IWN_DEBUG_RESET,
1836 "skip chan %d, extension channel not found\n",
1841 DPRINTF(sc, IWN_DEBUG_RESET,
1842 "add ht40 chan %d flags 0x%x maxpwr %d\n",
1843 band->chan[i], channels[i].flags, channels[i].maxpwr);
1845 c = &ic->ic_channels[ic->ic_nchans++];
1847 c->ic_extieee = extc->ic_ieee;
1848 c->ic_flags &= ~IEEE80211_CHAN_HT;
1849 c->ic_flags |= IEEE80211_CHAN_HT40U;
1850 c = &ic->ic_channels[ic->ic_nchans++];
1852 c->ic_extieee = cent->ic_ieee;
1853 c->ic_flags &= ~IEEE80211_CHAN_HT;
1854 c->ic_flags |= IEEE80211_CHAN_HT40D;
1860 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)
1862 struct ifnet *ifp = sc->sc_ifp;
1863 struct ieee80211com *ic = ifp->if_l2com;
1865 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n],
1866 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan));
1869 iwn_read_eeprom_band(sc, n);
1872 iwn_read_eeprom_ht40(sc, n);
1874 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans);
1877 #define nitems(_a) (sizeof((_a)) / sizeof((_a)[0]))
1880 iwn_read_eeprom_enhinfo(struct iwn_softc *sc)
1882 struct iwn_eeprom_enhinfo enhinfo[35];
1887 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1888 base = le16toh(val);
1889 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO,
1890 enhinfo, sizeof enhinfo);
1892 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr);
1893 for (i = 0; i < nitems(enhinfo); i++) {
1894 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0)
1895 continue; /* Skip invalid entries. */
1898 if (sc->txchainmask & IWN_ANT_A)
1899 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]);
1900 if (sc->txchainmask & IWN_ANT_B)
1901 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]);
1902 if (sc->txchainmask & IWN_ANT_C)
1903 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]);
1904 if (sc->ntxchains == 2)
1905 maxpwr = MAX(maxpwr, enhinfo[i].mimo2);
1906 else if (sc->ntxchains == 3)
1907 maxpwr = MAX(maxpwr, enhinfo[i].mimo3);
1908 maxpwr /= 2; /* Convert half-dBm to dBm. */
1910 DPRINTF(sc, IWN_DEBUG_RESET, "enhinfo %d, maxpwr=%d\n", i,
1912 sc->enh_maxpwr[i] = maxpwr;
1916 static struct ieee80211_node *
1917 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
1919 return kmalloc(sizeof (struct iwn_node), M_80211_NODE,M_INTWAIT | M_ZERO);
1923 iwn_newassoc(struct ieee80211_node *ni, int isnew)
1927 ieee80211_ratectl_node_deinit(ni);
1930 ieee80211_ratectl_node_init(ni);
1934 iwn_media_change(struct ifnet *ifp)
1936 int error = ieee80211_media_change(ifp);
1937 /* NB: only the fixed rate can change and that doesn't need a reset */
1938 return (error == ENETRESET ? 0 : error);
1942 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1944 struct iwn_vap *ivp = IWN_VAP(vap);
1945 struct ieee80211com *ic = vap->iv_ic;
1946 struct iwn_softc *sc = ic->ic_ifp->if_softc;
1949 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1950 ieee80211_state_name[vap->iv_state],
1951 ieee80211_state_name[nstate]);
1953 IEEE80211_UNLOCK(ic);
1955 callout_stop(&sc->sc_timer_to);
1957 if (nstate == IEEE80211_S_AUTH && vap->iv_state != IEEE80211_S_AUTH) {
1958 /* !AUTH -> AUTH requires adapter config */
1959 /* Reset state to handle reassociations correctly. */
1960 sc->rxon.associd = 0;
1961 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS);
1962 iwn_calib_reset(sc);
1963 error = iwn_auth(sc, vap);
1965 if (nstate == IEEE80211_S_RUN && vap->iv_state != IEEE80211_S_RUN) {
1967 * !RUN -> RUN requires setting the association id
1968 * which is done with a firmware cmd. We also defer
1969 * starting the timers until that work is done.
1971 error = iwn_run(sc, vap);
1973 if (nstate == IEEE80211_S_RUN) {
1975 * RUN -> RUN transition; just restart the timers.
1977 iwn_calib_reset(sc);
1981 return ivp->iv_newstate(vap, nstate, arg);
1985 * Process an RX_PHY firmware notification. This is usually immediately
1986 * followed by an MPDU_RX_DONE notification.
1989 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc,
1990 struct iwn_rx_data *data)
1992 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1);
1994 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__);
1995 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
1997 /* Save RX statistics, they will be used on MPDU_RX_DONE. */
1998 memcpy(&sc->last_rx_stat, stat, sizeof (*stat));
1999 sc->last_rx_valid = 1;
2003 iwn_timer_timeout(void *arg)
2005 struct iwn_softc *sc = arg;
2008 IWN_LOCK_ASSERT(sc);
2010 if (sc->calib_cnt && --sc->calib_cnt == 0) {
2011 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n",
2012 "send statistics request");
2013 (void) iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags,
2015 sc->calib_cnt = 60; /* do calibration every 60s */
2017 iwn_watchdog(sc); /* NB: piggyback tx watchdog */
2018 callout_reset(&sc->sc_timer_to, hz, iwn_timer_timeout, sc);
2022 iwn_calib_reset(struct iwn_softc *sc)
2024 callout_reset(&sc->sc_timer_to, hz, iwn_timer_timeout, sc);
2025 sc->calib_cnt = 60; /* do calibration every 60s */
2029 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification.
2030 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one.
2033 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2034 struct iwn_rx_data *data)
2036 const struct iwn_hal *hal = sc->sc_hal;
2037 struct ifnet *ifp = sc->sc_ifp;
2038 struct ieee80211com *ic = ifp->if_l2com;
2039 struct iwn_rx_ring *ring = &sc->rxq;
2040 struct ieee80211_frame *wh;
2041 struct ieee80211_node *ni;
2042 struct mbuf *m, *m1;
2043 struct iwn_rx_stat *stat;
2047 int error, len, rssi, nf;
2049 if (desc->type == IWN_MPDU_RX_DONE) {
2050 /* Check for prior RX_PHY notification. */
2051 if (!sc->last_rx_valid) {
2052 DPRINTF(sc, IWN_DEBUG_ANY,
2053 "%s: missing RX_PHY\n", __func__);
2057 sc->last_rx_valid = 0;
2058 stat = &sc->last_rx_stat;
2060 stat = (struct iwn_rx_stat *)(desc + 1);
2062 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2064 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) {
2065 device_printf(sc->sc_dev,
2066 "%s: invalid rx statistic header, len %d\n",
2067 __func__, stat->cfg_phy_len);
2071 if (desc->type == IWN_MPDU_RX_DONE) {
2072 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1);
2073 head = (caddr_t)(mpdu + 1);
2074 len = le16toh(mpdu->len);
2076 head = (caddr_t)(stat + 1) + stat->cfg_phy_len;
2077 len = le16toh(stat->len);
2080 flags = le32toh(*(uint32_t *)(head + len));
2082 /* Discard frames with a bad FCS early. */
2083 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) {
2084 DPRINTF(sc, IWN_DEBUG_RECV, "%s: rx flags error %x\n",
2089 /* Discard frames that are too short. */
2090 if (len < sizeof (*wh)) {
2091 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n",
2097 /* XXX don't need mbuf, just dma buffer */
2098 m1 = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2100 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n",
2105 bus_dmamap_unload(ring->data_dmat, data->map);
2107 error = bus_dmamap_load(ring->data_dmat, data->map,
2108 mtod(m1, caddr_t), MCLBYTES,
2109 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
2110 if (error != 0 && error != EFBIG) {
2111 device_printf(sc->sc_dev,
2112 "%s: bus_dmamap_load failed, error %d\n", __func__, error);
2120 /* Update RX descriptor. */
2121 ring->desc[ring->cur] = htole32(paddr >> 8);
2122 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
2123 BUS_DMASYNC_PREWRITE);
2125 /* Finalize mbuf. */
2126 m->m_pkthdr.rcvif = ifp;
2128 m->m_pkthdr.len = m->m_len = len;
2130 rssi = hal->get_rssi(sc, stat);
2132 /* Grab a reference to the source node. */
2133 wh = mtod(m, struct ieee80211_frame *);
2134 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
2135 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN &&
2136 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95;
2138 if (ieee80211_radiotap_active(ic)) {
2139 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap;
2141 tap->wr_tsft = htole64(stat->tstamp);
2143 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE))
2144 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2145 switch (stat->rate) {
2147 case 10: tap->wr_rate = 2; break;
2148 case 20: tap->wr_rate = 4; break;
2149 case 55: tap->wr_rate = 11; break;
2150 case 110: tap->wr_rate = 22; break;
2152 case 0xd: tap->wr_rate = 12; break;
2153 case 0xf: tap->wr_rate = 18; break;
2154 case 0x5: tap->wr_rate = 24; break;
2155 case 0x7: tap->wr_rate = 36; break;
2156 case 0x9: tap->wr_rate = 48; break;
2157 case 0xb: tap->wr_rate = 72; break;
2158 case 0x1: tap->wr_rate = 96; break;
2159 case 0x3: tap->wr_rate = 108; break;
2160 /* Unknown rate: should not happen. */
2161 default: tap->wr_rate = 0;
2163 tap->wr_dbm_antsignal = rssi;
2164 tap->wr_dbm_antnoise = nf;
2169 /* Send the frame to the 802.11 layer. */
2171 (void) ieee80211_input(ni, m, rssi - nf, nf);
2172 /* Node is no longer needed. */
2173 ieee80211_free_node(ni);
2175 (void) ieee80211_input_all(ic, m, rssi - nf, nf);
2181 /* Process an incoming Compressed BlockAck. */
2183 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2184 struct iwn_rx_data *data)
2186 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1);
2187 struct iwn_tx_ring *txq;
2189 txq = &sc->txq[letoh16(ba->qid)];
2195 * Process a CALIBRATION_RESULT notification sent by the initialization
2196 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.)
2199 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2200 struct iwn_rx_data *data)
2202 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1);
2205 /* Runtime firmware should not send such a notification. */
2206 if (sc->sc_flags & IWN_FLAG_CALIB_DONE)
2209 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2210 len = (le32toh(desc->len) & 0x3fff) - 4;
2212 switch (calib->code) {
2213 case IWN5000_PHY_CALIB_DC:
2214 if (sc->hw_type == IWN_HW_REV_TYPE_5150 ||
2215 sc->hw_type == IWN_HW_REV_TYPE_6050)
2218 case IWN5000_PHY_CALIB_LO:
2221 case IWN5000_PHY_CALIB_TX_IQ:
2224 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC:
2225 if (sc->hw_type < IWN_HW_REV_TYPE_6000 &&
2226 sc->hw_type != IWN_HW_REV_TYPE_5150)
2229 case IWN5000_PHY_CALIB_BASE_BAND:
2233 if (idx == -1) /* Ignore other results. */
2236 /* Save calibration result. */
2237 if (sc->calibcmd[idx].buf != NULL)
2238 kfree(sc->calibcmd[idx].buf, M_DEVBUF);
2239 sc->calibcmd[idx].buf = kmalloc(len, M_DEVBUF, M_INTWAIT);
2240 if (sc->calibcmd[idx].buf == NULL) {
2241 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2242 "not enough memory for calibration result %d\n",
2246 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2247 "saving calibration result code=%d len=%d\n", calib->code, len);
2248 sc->calibcmd[idx].len = len;
2249 memcpy(sc->calibcmd[idx].buf, calib, len);
2253 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification.
2254 * The latter is sent by the firmware after each received beacon.
2257 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2258 struct iwn_rx_data *data)
2260 const struct iwn_hal *hal = sc->sc_hal;
2261 struct ifnet *ifp = sc->sc_ifp;
2262 struct ieee80211com *ic = ifp->if_l2com;
2263 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2264 struct iwn_calib_state *calib = &sc->calib;
2265 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1);
2268 /* Beacon stats are meaningful only when associated and not scanning. */
2269 if (vap->iv_state != IEEE80211_S_RUN ||
2270 (ic->ic_flags & IEEE80211_F_SCAN))
2273 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2274 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: cmd %d\n", __func__, desc->type);
2275 iwn_calib_reset(sc); /* Reset TX power calibration timeout. */
2277 /* Test if temperature has changed. */
2278 if (stats->general.temp != sc->rawtemp) {
2279 /* Convert "raw" temperature to degC. */
2280 sc->rawtemp = stats->general.temp;
2281 temp = hal->get_temperature(sc);
2282 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n",
2285 /* Update TX power if need be (4965AGN only.) */
2286 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
2287 iwn4965_power_calibration(sc, temp);
2290 if (desc->type != IWN_BEACON_STATISTICS)
2291 return; /* Reply to a statistics request. */
2293 sc->noise = iwn_get_noise(&stats->rx.general);
2294 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise);
2296 /* Test that RSSI and noise are present in stats report. */
2297 if (le32toh(stats->rx.general.flags) != 1) {
2298 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
2299 "received statistics without RSSI");
2303 if (calib->state == IWN_CALIB_STATE_ASSOC)
2304 iwn_collect_noise(sc, &stats->rx.general);
2305 else if (calib->state == IWN_CALIB_STATE_RUN)
2306 iwn_tune_sensitivity(sc, &stats->rx);
2310 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN
2311 * and 5000 adapters have different incompatible TX status formats.
2314 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2315 struct iwn_rx_data *data)
2317 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1);
2318 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2320 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2321 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2322 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2323 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2324 le32toh(stat->status));
2326 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2327 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff);
2331 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2332 struct iwn_rx_data *data)
2334 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1);
2335 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2337 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2338 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2339 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2340 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2341 le32toh(stat->status));
2344 /* Reset TX scheduler slot. */
2345 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx);
2348 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2349 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff);
2353 * Adapter-independent backend for TX_DONE firmware notifications.
2356 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt,
2359 struct ifnet *ifp = sc->sc_ifp;
2360 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2361 struct iwn_tx_data *data = &ring->data[desc->idx];
2363 struct ieee80211_node *ni;
2364 struct ieee80211vap *vap;
2366 KASSERT(data->ni != NULL, ("no node"));
2368 /* Unmap and free mbuf. */
2369 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
2370 bus_dmamap_unload(ring->data_dmat, data->map);
2371 m = data->m, data->m = NULL;
2372 ni = data->ni, data->ni = NULL;
2375 if (m->m_flags & M_TXCB) {
2377 * Channels marked for "radar" require traffic to be received
2378 * to unlock before we can transmit. Until traffic is seen
2379 * any attempt to transmit is returned immediately with status
2380 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily
2381 * happen on first authenticate after scanning. To workaround
2382 * this we ignore a failure of this sort in AUTH state so the
2383 * 802.11 layer will fall back to using a timeout to wait for
2384 * the AUTH reply. This allows the firmware time to see
2385 * traffic so a subsequent retry of AUTH succeeds. It's
2386 * unclear why the firmware does not maintain state for
2387 * channels recently visited as this would allow immediate
2388 * use of the channel after a scan (where we see traffic).
2390 if (status == IWN_TX_FAIL_TX_LOCKED &&
2391 ni->ni_vap->iv_state == IEEE80211_S_AUTH)
2392 ieee80211_process_callback(ni, m, 0);
2394 ieee80211_process_callback(ni, m,
2395 (status & IWN_TX_FAIL) != 0);
2399 * Update rate control statistics for the node.
2401 if (status & 0x80) {
2403 ieee80211_ratectl_tx_complete(vap, ni,
2404 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
2406 ieee80211_ratectl_tx_complete(vap, ni,
2407 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
2410 ieee80211_free_node(ni);
2412 sc->sc_tx_timer = 0;
2413 if (--ring->queued < IWN_TX_RING_LOMARK) {
2414 sc->qfullmsk &= ~(1 << ring->qid);
2415 if (sc->qfullmsk == 0 &&
2416 (ifp->if_flags & IFF_OACTIVE)) {
2417 ifp->if_flags &= ~IFF_OACTIVE;
2418 iwn_start_locked(ifp);
2424 * Process a "command done" firmware notification. This is where we wakeup
2425 * processes waiting for a synchronous command completion.
2428 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc)
2430 struct iwn_tx_ring *ring = &sc->txq[4];
2431 struct iwn_tx_data *data;
2433 if ((desc->qid & 0xf) != 4)
2434 return; /* Not a command ack. */
2436 data = &ring->data[desc->idx];
2438 /* If the command was mapped in an mbuf, free it. */
2439 if (data->m != NULL) {
2440 bus_dmamap_unload(ring->data_dmat, data->map);
2444 wakeup(&ring->desc[desc->idx]);
2448 * Process an INT_FH_RX or INT_SW_RX interrupt.
2451 iwn_notif_intr(struct iwn_softc *sc)
2453 struct ifnet *ifp = sc->sc_ifp;
2454 struct ieee80211com *ic = ifp->if_l2com;
2455 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2458 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map,
2459 BUS_DMASYNC_POSTREAD);
2461 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff;
2462 while (sc->rxq.cur != hw) {
2463 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur];
2464 struct iwn_rx_desc *desc;
2466 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2467 BUS_DMASYNC_POSTREAD);
2468 desc = mtod(data->m, struct iwn_rx_desc *);
2470 DPRINTF(sc, IWN_DEBUG_RECV,
2471 "%s: qid %x idx %d flags %x type %d(%s) len %d\n",
2472 __func__, desc->qid & 0xf, desc->idx, desc->flags,
2473 desc->type, iwn_intr_str(desc->type),
2474 le16toh(desc->len));
2476 if (!(desc->qid & 0x80)) /* Reply to a command. */
2477 iwn_cmd_done(sc, desc);
2479 switch (desc->type) {
2481 iwn_rx_phy(sc, desc, data);
2484 case IWN_RX_DONE: /* 4965AGN only. */
2485 case IWN_MPDU_RX_DONE:
2486 /* An 802.11 frame has been received. */
2487 iwn_rx_done(sc, desc, data);
2491 case IWN_RX_COMPRESSED_BA:
2492 /* A Compressed BlockAck has been received. */
2493 iwn_rx_compressed_ba(sc, desc, data);
2498 /* An 802.11 frame has been transmitted. */
2499 sc->sc_hal->tx_done(sc, desc, data);
2502 case IWN_RX_STATISTICS:
2503 case IWN_BEACON_STATISTICS:
2504 iwn_rx_statistics(sc, desc, data);
2507 case IWN_BEACON_MISSED:
2509 struct iwn_beacon_missed *miss =
2510 (struct iwn_beacon_missed *)(desc + 1);
2513 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2514 BUS_DMASYNC_POSTREAD);
2515 misses = le32toh(miss->consecutive);
2517 /* XXX not sure why we're notified w/ zero */
2520 DPRINTF(sc, IWN_DEBUG_STATE,
2521 "%s: beacons missed %d/%d\n", __func__,
2522 misses, le32toh(miss->total));
2525 * If more than 5 consecutive beacons are missed,
2526 * reinitialize the sensitivity state machine.
2528 if (vap->iv_state == IEEE80211_S_RUN && misses > 5)
2529 (void) iwn_init_sensitivity(sc);
2530 if (misses >= vap->iv_bmissthreshold) {
2532 ieee80211_beacon_miss(ic);
2539 struct iwn_ucode_info *uc =
2540 (struct iwn_ucode_info *)(desc + 1);
2542 /* The microcontroller is ready. */
2543 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2544 BUS_DMASYNC_POSTREAD);
2545 DPRINTF(sc, IWN_DEBUG_RESET,
2546 "microcode alive notification version=%d.%d "
2547 "subtype=%x alive=%x\n", uc->major, uc->minor,
2548 uc->subtype, le32toh(uc->valid));
2550 if (le32toh(uc->valid) != 1) {
2551 device_printf(sc->sc_dev,
2552 "microcontroller initialization failed");
2555 if (uc->subtype == IWN_UCODE_INIT) {
2556 /* Save microcontroller report. */
2557 memcpy(&sc->ucode_info, uc, sizeof (*uc));
2559 /* Save the address of the error log in SRAM. */
2560 sc->errptr = le32toh(uc->errptr);
2563 case IWN_STATE_CHANGED:
2565 uint32_t *status = (uint32_t *)(desc + 1);
2568 * State change allows hardware switch change to be
2569 * noted. However, we handle this in iwn_intr as we
2570 * get both the enable/disble intr.
2572 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2573 BUS_DMASYNC_POSTREAD);
2574 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n",
2578 case IWN_START_SCAN:
2580 struct iwn_start_scan *scan =
2581 (struct iwn_start_scan *)(desc + 1);
2583 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2584 BUS_DMASYNC_POSTREAD);
2585 DPRINTF(sc, IWN_DEBUG_ANY,
2586 "%s: scanning channel %d status %x\n",
2587 __func__, scan->chan, le32toh(scan->status));
2592 struct iwn_stop_scan *scan =
2593 (struct iwn_stop_scan *)(desc + 1);
2595 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2596 BUS_DMASYNC_POSTREAD);
2597 DPRINTF(sc, IWN_DEBUG_STATE,
2598 "scan finished nchan=%d status=%d chan=%d\n",
2599 scan->nchan, scan->status, scan->chan);
2602 ieee80211_scan_next(vap);
2606 case IWN5000_CALIBRATION_RESULT:
2607 iwn5000_rx_calib_results(sc, desc, data);
2610 case IWN5000_CALIBRATION_DONE:
2611 sc->sc_flags |= IWN_FLAG_CALIB_DONE;
2616 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT;
2619 /* Tell the firmware what we have processed. */
2620 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1;
2621 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7);
2625 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up
2626 * from power-down sleep mode.
2629 iwn_wakeup_intr(struct iwn_softc *sc)
2633 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n",
2636 /* Wakeup RX and TX rings. */
2637 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7);
2638 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) {
2639 struct iwn_tx_ring *ring = &sc->txq[qid];
2640 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur);
2645 iwn_rftoggle_intr(struct iwn_softc *sc)
2647 struct ifnet *ifp = sc->sc_ifp;
2648 struct ieee80211com *ic = ifp->if_l2com;
2649 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL);
2651 IWN_LOCK_ASSERT(sc);
2653 device_printf(sc->sc_dev, "RF switch: radio %s\n",
2654 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled");
2655 if (tmp & IWN_GP_CNTRL_RFKILL)
2656 ieee80211_runtask(ic, &sc->sc_radioon_task);
2658 ieee80211_runtask(ic, &sc->sc_radiooff_task);
2662 * Dump the error log of the firmware when a firmware panic occurs. Although
2663 * we can't debug the firmware because it is neither open source nor free, it
2664 * can help us to identify certain classes of problems.
2667 iwn_fatal_intr(struct iwn_softc *sc)
2669 const struct iwn_hal *hal = sc->sc_hal;
2670 struct iwn_fw_dump dump;
2673 IWN_LOCK_ASSERT(sc);
2675 /* Force a complete recalibration on next init. */
2676 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE;
2678 /* Check that the error log address is valid. */
2679 if (sc->errptr < IWN_FW_DATA_BASE ||
2680 sc->errptr + sizeof (dump) >
2681 IWN_FW_DATA_BASE + hal->fw_data_maxsz) {
2682 kprintf("%s: bad firmware error log address 0x%08x\n",
2683 __func__, sc->errptr);
2686 if (iwn_nic_lock(sc) != 0) {
2687 kprintf("%s: could not read firmware error log\n",
2691 /* Read firmware error log from SRAM. */
2692 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,
2693 sizeof (dump) / sizeof (uint32_t));
2696 if (dump.valid == 0) {
2697 kprintf("%s: firmware error log is empty\n",
2701 kprintf("firmware error log:\n");
2702 kprintf(" error type = \"%s\" (0x%08X)\n",
2703 (dump.id < nitems(iwn_fw_errmsg)) ?
2704 iwn_fw_errmsg[dump.id] : "UNKNOWN",
2706 kprintf(" program counter = 0x%08X\n", dump.pc);
2707 kprintf(" source line = 0x%08X\n", dump.src_line);
2708 kprintf(" error data = 0x%08X%08X\n",
2709 dump.error_data[0], dump.error_data[1]);
2710 kprintf(" branch link = 0x%08X%08X\n",
2711 dump.branch_link[0], dump.branch_link[1]);
2712 kprintf(" interrupt link = 0x%08X%08X\n",
2713 dump.interrupt_link[0], dump.interrupt_link[1]);
2714 kprintf(" time = %u\n", dump.time[0]);
2716 /* Dump driver status (TX and RX rings) while we're here. */
2717 kprintf("driver status:\n");
2718 for (i = 0; i < hal->ntxqs; i++) {
2719 struct iwn_tx_ring *ring = &sc->txq[i];
2720 kprintf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n",
2721 i, ring->qid, ring->cur, ring->queued);
2723 kprintf(" rx ring: cur=%d\n", sc->rxq.cur);
2729 struct iwn_softc *sc = arg;
2730 struct ifnet *ifp = sc->sc_ifp;
2731 uint32_t r1, r2, tmp;
2735 /* Disable interrupts. */
2736 IWN_WRITE(sc, IWN_INT_MASK, 0);
2738 /* Read interrupts from ICT (fast) or from registers (slow). */
2739 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
2741 while (sc->ict[sc->ict_cur] != 0) {
2742 tmp |= sc->ict[sc->ict_cur];
2743 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */
2744 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
2747 if (tmp == 0xffffffff) /* Shouldn't happen. */
2749 else if (tmp & 0xc0000) /* Workaround a HW bug. */
2751 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
2752 r2 = 0; /* Unused. */
2754 r1 = IWN_READ(sc, IWN_INT);
2755 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0)
2756 return; /* Hardware gone! */
2757 r2 = IWN_READ(sc, IWN_FH_INT);
2760 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2);
2762 if (r1 == 0 && r2 == 0)
2763 goto done; /* Interrupt not for us. */
2765 /* Acknowledge interrupts. */
2766 IWN_WRITE(sc, IWN_INT, r1);
2767 if (!(sc->sc_flags & IWN_FLAG_USE_ICT))
2768 IWN_WRITE(sc, IWN_FH_INT, r2);
2770 if (r1 & IWN_INT_RF_TOGGLED) {
2771 iwn_rftoggle_intr(sc);
2774 if (r1 & IWN_INT_CT_REACHED) {
2775 device_printf(sc->sc_dev, "%s: critical temperature reached!\n",
2778 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) {
2780 ifp->if_flags &= ~IFF_UP;
2781 iwn_stop_locked(sc);
2784 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) ||
2785 (r2 & IWN_FH_INT_RX)) {
2786 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
2787 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX))
2788 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX);
2789 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
2790 IWN_INT_PERIODIC_DIS);
2792 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) {
2793 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
2794 IWN_INT_PERIODIC_ENA);
2800 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) {
2801 if (sc->sc_flags & IWN_FLAG_USE_ICT)
2802 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX);
2803 wakeup(sc); /* FH DMA transfer completed. */
2806 if (r1 & IWN_INT_ALIVE)
2807 wakeup(sc); /* Firmware is alive. */
2809 if (r1 & IWN_INT_WAKEUP)
2810 iwn_wakeup_intr(sc);
2813 /* Re-enable interrupts. */
2814 if (ifp->if_flags & IFF_UP)
2815 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
2822 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and
2823 * 5000 adapters use a slightly different format.)
2826 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
2829 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx];
2831 *w = htole16(len + 8);
2832 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2833 BUS_DMASYNC_PREWRITE);
2834 if (idx < IWN_SCHED_WINSZ) {
2835 *(w + IWN_TX_RING_COUNT) = *w;
2836 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2837 BUS_DMASYNC_PREWRITE);
2842 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
2845 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
2847 *w = htole16(id << 12 | (len + 8));
2849 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2850 BUS_DMASYNC_PREWRITE);
2851 if (idx < IWN_SCHED_WINSZ) {
2852 *(w + IWN_TX_RING_COUNT) = *w;
2853 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2854 BUS_DMASYNC_PREWRITE);
2860 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx)
2862 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
2864 *w = (*w & htole16(0xf000)) | htole16(1);
2865 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2866 BUS_DMASYNC_PREWRITE);
2867 if (idx < IWN_SCHED_WINSZ) {
2868 *(w + IWN_TX_RING_COUNT) = *w;
2869 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2870 BUS_DMASYNC_PREWRITE);
2876 iwn_plcp_signal(int rate) {
2879 for (i = 0; i < IWN_RIDX_MAX + 1; i++) {
2880 if (rate == iwn_rates[i].rate)
2888 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
2889 struct iwn_tx_ring *ring)
2891 const struct iwn_hal *hal = sc->sc_hal;
2892 const struct ieee80211_txparam *tp;
2893 const struct iwn_rate *rinfo;
2894 struct ieee80211vap *vap = ni->ni_vap;
2895 struct ieee80211com *ic = ni->ni_ic;
2896 struct iwn_node *wn = (void *)ni;
2897 struct iwn_tx_desc *desc;
2898 struct iwn_tx_data *data;
2899 struct iwn_tx_cmd *cmd;
2900 struct iwn_cmd_data *tx;
2901 struct ieee80211_frame *wh;
2902 struct ieee80211_key *k = NULL;
2904 bus_dma_segment_t segs[IWN_MAX_SCATTER];
2907 int totlen, error, pad, nsegs = 0, i, rate;
2908 uint8_t ridx, type, txant;
2910 IWN_LOCK_ASSERT(sc);
2912 wh = mtod(m, struct ieee80211_frame *);
2913 hdrlen = ieee80211_anyhdrsize(wh);
2914 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2916 desc = &ring->desc[ring->cur];
2917 data = &ring->data[ring->cur];
2919 /* Choose a TX rate index. */
2920 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
2921 if (type == IEEE80211_FC0_TYPE_MGT)
2922 rate = tp->mgmtrate;
2923 else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
2924 rate = tp->mcastrate;
2925 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
2926 rate = tp->ucastrate;
2928 /* XXX pass pktlen */
2929 ieee80211_ratectl_rate(ni, NULL, 0);
2931 rate = ni->ni_txrate;
2933 ridx = iwn_plcp_signal(rate);
2934 rinfo = &iwn_rates[ridx];
2936 /* Encrypt the frame if need be. */
2937 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
2938 k = ieee80211_crypto_encap(ni, m);
2943 /* Packet header may have moved, reset our local pointer. */
2944 wh = mtod(m, struct ieee80211_frame *);
2946 totlen = m->m_pkthdr.len;
2948 if (ieee80211_radiotap_active_vap(vap)) {
2949 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
2952 tap->wt_rate = rinfo->rate;
2954 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2956 ieee80211_radiotap_tx(vap, m);
2959 /* Prepare TX firmware command. */
2960 cmd = &ring->cmd[ring->cur];
2961 cmd->code = IWN_CMD_TX_DATA;
2963 cmd->qid = ring->qid;
2964 cmd->idx = ring->cur;
2966 tx = (struct iwn_cmd_data *)cmd->data;
2967 /* NB: No need to clear tx, all fields are reinitialized here. */
2968 tx->scratch = 0; /* clear "scratch" area */
2971 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
2972 flags |= IWN_TX_NEED_ACK;
2974 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
2975 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR))
2976 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */
2978 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
2979 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */
2981 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
2982 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2983 /* NB: Group frames are sent using CCK in 802.11b/g. */
2984 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) {
2985 flags |= IWN_TX_NEED_RTS;
2986 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
2987 ridx >= IWN_RIDX_OFDM6) {
2988 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2989 flags |= IWN_TX_NEED_CTS;
2990 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2991 flags |= IWN_TX_NEED_RTS;
2993 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) {
2994 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
2995 /* 5000 autoselects RTS/CTS or CTS-to-self. */
2996 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS);
2997 flags |= IWN_TX_NEED_PROTECTION;
2999 flags |= IWN_TX_FULL_TXOP;
3003 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
3004 type != IEEE80211_FC0_TYPE_DATA)
3005 tx->id = hal->broadcast_id;
3009 if (type == IEEE80211_FC0_TYPE_MGT) {
3010 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3012 /* Tell HW to set timestamp in probe responses. */
3013 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3014 flags |= IWN_TX_INSERT_TSTAMP;
3016 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3017 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3018 tx->timeout = htole16(3);
3020 tx->timeout = htole16(2);
3022 tx->timeout = htole16(0);
3025 /* First segment length must be a multiple of 4. */
3026 flags |= IWN_TX_NEED_PADDING;
3027 pad = 4 - (hdrlen & 3);
3031 tx->len = htole16(totlen);
3033 tx->rts_ntries = 60;
3034 tx->data_ntries = 15;
3035 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3036 tx->plcp = rinfo->plcp;
3037 tx->rflags = rinfo->flags;
3038 if (tx->id == hal->broadcast_id) {
3039 /* Group or management frame. */
3041 /* XXX Alternate between antenna A and B? */
3042 txant = IWN_LSB(sc->txchainmask);
3043 tx->rflags |= IWN_RFLAG_ANT(txant);
3046 flags |= IWN_TX_LINKQ; /* enable MRR */
3049 /* Set physical address of "scratch area". */
3050 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
3051 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
3053 /* Copy 802.11 header in TX command. */
3054 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3056 /* Trim 802.11 header. */
3059 tx->flags = htole32(flags);
3062 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map,
3063 m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
3064 if (error == EFBIG) {
3065 /* too many fragments, linearize */
3066 mnew = m_defrag(m, MB_DONTWAIT);
3068 device_printf(sc->sc_dev,
3069 "%s: could not defrag mbuf\n", __func__);
3074 error = bus_dmamap_load_mbuf_segment(ring->data_dmat,
3075 data->map, m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
3078 device_printf(sc->sc_dev,
3079 "%s: bus_dmamap_load_mbuf_segment failed, error %d\n",
3089 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3090 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3092 /* Fill TX descriptor. */
3093 desc->nsegs = 1 + nsegs;
3094 /* First DMA segment is used by the TX command. */
3095 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3096 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3097 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3098 /* Other DMA segments are for data payload. */
3099 for (i = 1; i <= nsegs; i++) {
3100 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr));
3101 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) |
3102 segs[i - 1].ds_len << 4);
3105 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3106 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3107 BUS_DMASYNC_PREWRITE);
3108 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3109 BUS_DMASYNC_PREWRITE);
3112 /* Update TX scheduler. */
3113 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3117 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3118 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3120 /* Mark TX ring as full if we reach a certain threshold. */
3121 if (++ring->queued > IWN_TX_RING_HIMARK)
3122 sc->qfullmsk |= 1 << ring->qid;
3128 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m,
3129 struct ieee80211_node *ni, struct iwn_tx_ring *ring,
3130 const struct ieee80211_bpf_params *params)
3132 const struct iwn_hal *hal = sc->sc_hal;
3133 const struct iwn_rate *rinfo;
3134 struct ifnet *ifp = sc->sc_ifp;
3135 struct ieee80211vap *vap = ni->ni_vap;
3136 struct ieee80211com *ic = ifp->if_l2com;
3137 struct iwn_tx_cmd *cmd;
3138 struct iwn_cmd_data *tx;
3139 struct ieee80211_frame *wh;
3140 struct iwn_tx_desc *desc;
3141 struct iwn_tx_data *data;
3144 bus_dma_segment_t segs[IWN_MAX_SCATTER];
3147 int totlen, error, pad, nsegs = 0, i, rate;
3148 uint8_t ridx, type, txant;
3150 IWN_LOCK_ASSERT(sc);
3152 wh = mtod(m, struct ieee80211_frame *);
3153 hdrlen = ieee80211_anyhdrsize(wh);
3154 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3156 desc = &ring->desc[ring->cur];
3157 data = &ring->data[ring->cur];
3159 /* Choose a TX rate index. */
3160 rate = params->ibp_rate0;
3161 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3162 /* XXX fall back to mcast/mgmt rate? */
3166 ridx = iwn_plcp_signal(rate);
3167 rinfo = &iwn_rates[ridx];
3169 totlen = m->m_pkthdr.len;
3171 /* Prepare TX firmware command. */
3172 cmd = &ring->cmd[ring->cur];
3173 cmd->code = IWN_CMD_TX_DATA;
3175 cmd->qid = ring->qid;
3176 cmd->idx = ring->cur;
3178 tx = (struct iwn_cmd_data *)cmd->data;
3179 /* NB: No need to clear tx, all fields are reinitialized here. */
3180 tx->scratch = 0; /* clear "scratch" area */
3183 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
3184 flags |= IWN_TX_NEED_ACK;
3185 if (params->ibp_flags & IEEE80211_BPF_RTS) {
3186 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3187 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3188 flags &= ~IWN_TX_NEED_RTS;
3189 flags |= IWN_TX_NEED_PROTECTION;
3191 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP;
3193 if (params->ibp_flags & IEEE80211_BPF_CTS) {
3194 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3195 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3196 flags &= ~IWN_TX_NEED_CTS;
3197 flags |= IWN_TX_NEED_PROTECTION;
3199 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP;
3201 if (type == IEEE80211_FC0_TYPE_MGT) {
3202 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3204 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3205 flags |= IWN_TX_INSERT_TSTAMP;
3207 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3208 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3209 tx->timeout = htole16(3);
3211 tx->timeout = htole16(2);
3213 tx->timeout = htole16(0);
3216 /* First segment length must be a multiple of 4. */
3217 flags |= IWN_TX_NEED_PADDING;
3218 pad = 4 - (hdrlen & 3);
3222 if (ieee80211_radiotap_active_vap(vap)) {
3223 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
3226 tap->wt_rate = rate;
3228 ieee80211_radiotap_tx(vap, m);
3231 tx->len = htole16(totlen);
3233 tx->id = hal->broadcast_id;
3234 tx->rts_ntries = params->ibp_try1;
3235 tx->data_ntries = params->ibp_try0;
3236 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3237 tx->plcp = rinfo->plcp;
3238 tx->rflags = rinfo->flags;
3239 /* Group or management frame. */
3241 txant = IWN_LSB(sc->txchainmask);
3242 tx->rflags |= IWN_RFLAG_ANT(txant);
3243 /* Set physical address of "scratch area". */
3244 paddr = ring->cmd_dma.paddr + ring->cur * sizeof (struct iwn_tx_cmd);
3245 tx->loaddr = htole32(IWN_LOADDR(paddr));
3246 tx->hiaddr = IWN_HIADDR(paddr);
3248 /* Copy 802.11 header in TX command. */
3249 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3251 /* Trim 802.11 header. */
3254 tx->flags = htole32(flags);
3257 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map,
3258 m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
3259 if (error == EFBIG) {
3260 /* Too many fragments, linearize. */
3261 mnew = m_defrag(m, MB_DONTWAIT);
3263 device_printf(sc->sc_dev,
3264 "%s: could not defrag mbuf\n", __func__);
3269 error = bus_dmamap_load_mbuf_segment(ring->data_dmat,
3270 data->map, m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
3273 device_printf(sc->sc_dev,
3274 "%s: bus_dmamap_load_mbuf_segment failed, error %d\n",
3284 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3285 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3287 /* Fill TX descriptor. */
3288 desc->nsegs = 1 + nsegs;
3289 /* First DMA segment is used by the TX command. */
3290 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3291 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3292 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3293 /* Other DMA segments are for data payload. */
3294 for (i = 1; i <= nsegs; i++) {
3295 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr));
3296 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) |
3297 segs[i - 1].ds_len << 4);
3300 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3301 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3302 BUS_DMASYNC_PREWRITE);
3303 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3304 BUS_DMASYNC_PREWRITE);
3307 /* Update TX scheduler. */
3308 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3312 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3313 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3315 /* Mark TX ring as full if we reach a certain threshold. */
3316 if (++ring->queued > IWN_TX_RING_HIMARK)
3317 sc->qfullmsk |= 1 << ring->qid;
3323 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
3324 const struct ieee80211_bpf_params *params)
3326 struct ieee80211com *ic = ni->ni_ic;
3327 struct ifnet *ifp = ic->ic_ifp;
3328 struct iwn_softc *sc = ifp->if_softc;
3329 struct iwn_tx_ring *txq;
3332 if ((ifp->if_flags & IFF_RUNNING) == 0) {
3333 ieee80211_free_node(ni);
3340 txq = &sc->txq[M_WME_GETAC(m)];
3342 txq = &sc->txq[params->ibp_pri & 3];
3344 if (params == NULL) {
3346 * Legacy path; interpret frame contents to decide
3347 * precisely how to send the frame.
3349 error = iwn_tx_data(sc, m, ni, txq);
3352 * Caller supplied explicit parameters to use in
3353 * sending the frame.
3355 error = iwn_tx_data_raw(sc, m, ni, txq, params);
3358 /* NB: m is reclaimed on tx failure */
3359 ieee80211_free_node(ni);
3367 iwn_start(struct ifnet *ifp)
3369 struct iwn_softc *sc = ifp->if_softc;
3372 iwn_start_locked(ifp);
3377 iwn_start_locked(struct ifnet *ifp)
3379 struct iwn_softc *sc = ifp->if_softc;
3380 struct ieee80211_node *ni;
3381 struct iwn_tx_ring *txq;
3385 IWN_LOCK_ASSERT(sc);
3388 if (sc->qfullmsk != 0) {
3389 ifp->if_flags |= IFF_OACTIVE;
3392 m = ifq_dequeue(&ifp->if_snd, NULL);
3395 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
3396 pri = M_WME_GETAC(m);
3397 txq = &sc->txq[pri];
3398 if (iwn_tx_data(sc, m, ni, txq) != 0) {
3400 ieee80211_free_node(ni);
3403 sc->sc_tx_timer = 5;
3408 iwn_watchdog(struct iwn_softc *sc)
3410 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
3411 struct ifnet *ifp = sc->sc_ifp;
3412 struct ieee80211com *ic = ifp->if_l2com;
3414 if_printf(ifp, "device timeout\n");
3415 ieee80211_runtask(ic, &sc->sc_reinit_task);
3420 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred)
3422 struct iwn_softc *sc = ifp->if_softc;
3423 struct ieee80211com *ic = ifp->if_l2com;
3424 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3425 struct ifreq *ifr = (struct ifreq *) data;
3426 int error = 0, startall = 0, stop = 0;
3431 if (ifp->if_flags & IFF_UP) {
3432 if (!(ifp->if_flags & IFF_RUNNING)) {
3433 iwn_init_locked(sc);
3434 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)
3440 if (ifp->if_flags & IFF_RUNNING)
3441 iwn_stop_locked(sc);
3445 ieee80211_start_all(ic);
3446 else if (vap != NULL && stop)
3447 ieee80211_stop(vap);
3450 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
3453 error = ether_ioctl(ifp, cmd, data);
3463 * Send a command to the firmware.
3466 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async)
3468 struct iwn_tx_ring *ring = &sc->txq[4];
3469 struct iwn_tx_desc *desc;
3470 struct iwn_tx_data *data;
3471 struct iwn_tx_cmd *cmd;
3476 IWN_LOCK_ASSERT(sc);
3478 desc = &ring->desc[ring->cur];
3479 data = &ring->data[ring->cur];
3482 if (size > sizeof cmd->data) {
3483 /* Command is too large to fit in a descriptor. */
3484 if (totlen > MCLBYTES)
3486 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
3489 cmd = mtod(m, struct iwn_tx_cmd *);
3490 error = bus_dmamap_load(ring->data_dmat, data->map, cmd,
3491 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
3498 cmd = &ring->cmd[ring->cur];
3499 paddr = data->cmd_paddr;
3504 cmd->qid = ring->qid;
3505 cmd->idx = ring->cur;
3506 memcpy(cmd->data, buf, size);
3509 desc->segs[0].addr = htole32(IWN_LOADDR(paddr));
3510 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4);
3512 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n",
3513 __func__, iwn_intr_str(cmd->code), cmd->code,
3514 cmd->flags, cmd->qid, cmd->idx);
3516 if (size > sizeof cmd->data) {
3517 bus_dmamap_sync(ring->data_dmat, data->map,
3518 BUS_DMASYNC_PREWRITE);
3520 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3521 BUS_DMASYNC_PREWRITE);
3523 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3524 BUS_DMASYNC_PREWRITE);
3527 /* Update TX scheduler. */
3528 sc->sc_hal->update_sched(sc, ring->qid, ring->cur, 0, 0);
3531 /* Kick command ring. */
3532 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3533 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3535 return async ? 0 : lksleep(desc, &sc->sc_lock, 0, "iwncmd", hz);
3539 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3541 struct iwn4965_node_info hnode;
3545 * We use the node structure for 5000 Series internally (it is
3546 * a superset of the one for 4965AGN). We thus copy the common
3547 * fields before sending the command.
3549 src = (caddr_t)node;
3550 dst = (caddr_t)&hnode;
3551 memcpy(dst, src, 48);
3552 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */
3553 memcpy(dst + 48, src + 72, 20);
3554 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async);
3558 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3560 /* Direct mapping. */
3561 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async);
3565 static const uint8_t iwn_ridx_to_plcp[] = {
3566 10, 20, 55, 110, /* CCK */
3567 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 0x3 /* OFDM R1-R4 */
3569 static const uint8_t iwn_siso_mcs_to_plcp[] = {
3570 0, 0, 0, 0, /* CCK */
3571 0, 0, 1, 2, 3, 4, 5, 6, 7 /* HT */
3573 static const uint8_t iwn_mimo_mcs_to_plcp[] = {
3574 0, 0, 0, 0, /* CCK */
3575 8, 8, 9, 10, 11, 12, 13, 14, 15 /* HT */
3578 static const uint8_t iwn_prev_ridx[] = {
3579 /* NB: allow fallback from CCK11 to OFDM9 and from OFDM6 to CCK5 */
3580 0, 0, 1, 5, /* CCK */
3581 2, 4, 3, 6, 7, 8, 9, 10, 10 /* OFDM */
3585 * Configure hardware link parameters for the specified
3586 * node operating on the specified channel.
3589 iwn_set_link_quality(struct iwn_softc *sc, uint8_t id, int async)
3591 struct ifnet *ifp = sc->sc_ifp;
3592 struct ieee80211com *ic = ifp->if_l2com;
3593 struct iwn_cmd_link_quality linkq;
3594 const struct iwn_rate *rinfo;
3596 uint8_t txant, ridx;
3598 /* Use the first valid TX antenna. */
3599 txant = IWN_LSB(sc->txchainmask);
3601 memset(&linkq, 0, sizeof linkq);
3603 linkq.antmsk_1stream = txant;
3604 linkq.antmsk_2stream = IWN_ANT_AB;
3605 linkq.ampdu_max = 31;
3606 linkq.ampdu_threshold = 3;
3607 linkq.ampdu_limit = htole16(4000); /* 4ms */
3610 if (IEEE80211_IS_CHAN_HT(c))
3614 if (id == IWN_ID_BSS)
3615 ridx = IWN_RIDX_OFDM54;
3616 else if (IEEE80211_IS_CHAN_A(ic->ic_curchan))
3617 ridx = IWN_RIDX_OFDM6;
3619 ridx = IWN_RIDX_CCK1;
3621 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) {
3622 rinfo = &iwn_rates[ridx];
3624 if (IEEE80211_IS_CHAN_HT40(c)) {
3625 linkq.retry[i].plcp = iwn_mimo_mcs_to_plcp[ridx]
3627 linkq.retry[i].rflags = IWN_RFLAG_HT
3630 } else if (IEEE80211_IS_CHAN_HT(c)) {
3631 linkq.retry[i].plcp = iwn_siso_mcs_to_plcp[ridx]
3633 linkq.retry[i].rflags = IWN_RFLAG_HT;
3638 linkq.retry[i].plcp = rinfo->plcp;
3639 linkq.retry[i].rflags = rinfo->flags;
3641 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant);
3642 ridx = iwn_prev_ridx[ridx];
3645 if (sc->sc_debug & IWN_DEBUG_STATE) {
3646 kprintf("%s: set link quality for node %d, mimo %d ssmask %d\n",
3647 __func__, id, linkq.mimo, linkq.antmsk_1stream);
3648 kprintf("%s:", __func__);
3649 for (i = 0; i < IWN_MAX_TX_RETRIES; i++)
3650 kprintf(" %d:%x", linkq.retry[i].plcp,
3651 linkq.retry[i].rflags);
3655 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async);
3659 * Broadcast node is used to send group-addressed and management frames.
3662 iwn_add_broadcast_node(struct iwn_softc *sc, int async)
3664 const struct iwn_hal *hal = sc->sc_hal;
3665 struct ifnet *ifp = sc->sc_ifp;
3666 struct iwn_node_info node;
3669 memset(&node, 0, sizeof node);
3670 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr);
3671 node.id = hal->broadcast_id;
3672 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__);
3673 error = hal->add_node(sc, &node, async);
3677 error = iwn_set_link_quality(sc, hal->broadcast_id, async);
3682 iwn_wme_update(struct ieee80211com *ic)
3684 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
3685 #define IWN_TXOP_TO_US(v) (v<<5)
3686 struct iwn_softc *sc = ic->ic_ifp->if_softc;
3687 struct iwn_edca_params cmd;
3690 memset(&cmd, 0, sizeof cmd);
3691 cmd.flags = htole32(IWN_EDCA_UPDATE);
3692 for (i = 0; i < WME_NUM_AC; i++) {
3693 const struct wmeParams *wmep =
3694 &ic->ic_wme.wme_chanParams.cap_wmeParams[i];
3695 cmd.ac[i].aifsn = wmep->wmep_aifsn;
3696 cmd.ac[i].cwmin = htole16(IWN_EXP2(wmep->wmep_logcwmin));
3697 cmd.ac[i].cwmax = htole16(IWN_EXP2(wmep->wmep_logcwmax));
3698 cmd.ac[i].txoplimit =
3699 htole16(IWN_TXOP_TO_US(wmep->wmep_txopLimit));
3701 IEEE80211_UNLOCK(ic);
3703 (void) iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1 /*async*/);
3707 #undef IWN_TXOP_TO_US
3712 iwn_update_mcast(struct ifnet *ifp)
3718 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on)
3720 struct iwn_cmd_led led;
3722 /* Clear microcode LED ownership. */
3723 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL);
3726 led.unit = htole32(10000); /* on/off in unit of 100ms */
3729 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1);
3733 * Set the critical temperature at which the firmware will stop the radio
3737 iwn_set_critical_temp(struct iwn_softc *sc)
3739 struct iwn_critical_temp crit;
3742 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF);
3744 if (sc->hw_type == IWN_HW_REV_TYPE_5150)
3745 temp = (IWN_CTOK(110) - sc->temp_off) * -5;
3746 else if (sc->hw_type == IWN_HW_REV_TYPE_4965)
3747 temp = IWN_CTOK(110);
3750 memset(&crit, 0, sizeof crit);
3751 crit.tempR = htole32(temp);
3752 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n",
3754 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0);
3758 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni)
3760 struct iwn_cmd_timing cmd;
3763 memset(&cmd, 0, sizeof cmd);
3764 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
3765 cmd.bintval = htole16(ni->ni_intval);
3766 cmd.lintval = htole16(10);
3768 /* Compute remaining time until next beacon. */
3769 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */
3770 mod = le64toh(cmd.tstamp) % val;
3771 cmd.binitval = htole32((uint32_t)(val - mod));
3773 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n",
3774 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod));
3776 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1);
3780 iwn4965_power_calibration(struct iwn_softc *sc, int temp)
3782 struct ifnet *ifp = sc->sc_ifp;
3783 struct ieee80211com *ic = ifp->if_l2com;
3785 /* Adjust TX power if need be (delta >= 3 degC.) */
3786 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
3787 __func__, sc->temp, temp);
3788 if (abs(temp - sc->temp) >= 3) {
3789 /* Record temperature of last calibration. */
3791 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1);
3796 * Set TX power for current channel (each rate has its own power settings).
3797 * This function takes into account the regulatory information from EEPROM,
3798 * the current temperature and the current voltage.
3801 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
3804 /* Fixed-point arithmetic division using a n-bit fractional part. */
3805 #define fdivround(a, b, n) \
3806 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n))
3807 /* Linear interpolation. */
3808 #define interpolate(x, x1, y1, x2, y2, n) \
3809 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n))
3811 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 };
3812 struct ifnet *ifp = sc->sc_ifp;
3813 struct ieee80211com *ic = ifp->if_l2com;
3814 struct iwn_ucode_info *uc = &sc->ucode_info;
3815 struct iwn4965_cmd_txpower cmd;
3816 struct iwn4965_eeprom_chan_samples *chans;
3817 int32_t vdiff, tdiff;
3818 int i, c, grp, maxpwr;
3819 const uint8_t *rf_gain, *dsp_gain;
3822 /* Retrieve channel number. */
3823 chan = ieee80211_chan2ieee(ic, ch);
3824 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n",
3827 memset(&cmd, 0, sizeof cmd);
3828 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1;
3831 if (IEEE80211_IS_CHAN_5GHZ(ch)) {
3832 maxpwr = sc->maxpwr5GHz;
3833 rf_gain = iwn4965_rf_gain_5ghz;
3834 dsp_gain = iwn4965_dsp_gain_5ghz;
3836 maxpwr = sc->maxpwr2GHz;
3837 rf_gain = iwn4965_rf_gain_2ghz;
3838 dsp_gain = iwn4965_dsp_gain_2ghz;
3841 /* Compute voltage compensation. */
3842 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7;
3847 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3848 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n",
3849 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage);
3851 /* Get channel attenuation group. */
3852 if (chan <= 20) /* 1-20 */
3854 else if (chan <= 43) /* 34-43 */
3856 else if (chan <= 70) /* 44-70 */
3858 else if (chan <= 124) /* 71-124 */
3862 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3863 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp);
3865 /* Get channel sub-band. */
3866 for (i = 0; i < IWN_NBANDS; i++)
3867 if (sc->bands[i].lo != 0 &&
3868 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi)
3870 if (i == IWN_NBANDS) /* Can't happen in real-life. */
3872 chans = sc->bands[i].chans;
3873 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3874 "%s: chan %d sub-band=%d\n", __func__, chan, i);
3876 for (c = 0; c < 2; c++) {
3877 uint8_t power, gain, temp;
3878 int maxchpwr, pwr, ridx, idx;
3880 power = interpolate(chan,
3881 chans[0].num, chans[0].samples[c][1].power,
3882 chans[1].num, chans[1].samples[c][1].power, 1);
3883 gain = interpolate(chan,
3884 chans[0].num, chans[0].samples[c][1].gain,
3885 chans[1].num, chans[1].samples[c][1].gain, 1);
3886 temp = interpolate(chan,
3887 chans[0].num, chans[0].samples[c][1].temp,
3888 chans[1].num, chans[1].samples[c][1].temp, 1);
3889 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3890 "%s: Tx chain %d: power=%d gain=%d temp=%d\n",
3891 __func__, c, power, gain, temp);
3893 /* Compute temperature compensation. */
3894 tdiff = ((sc->temp - temp) * 2) / tdiv[grp];
3895 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3896 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n",
3897 __func__, tdiff, sc->temp, temp);
3899 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) {
3900 /* Convert dBm to half-dBm. */
3901 maxchpwr = sc->maxpwr[chan] * 2;
3903 maxchpwr -= 6; /* MIMO 2T: -3dB */
3907 /* Adjust TX power based on rate. */
3908 if ((ridx % 8) == 5)
3909 pwr -= 15; /* OFDM48: -7.5dB */
3910 else if ((ridx % 8) == 6)
3911 pwr -= 17; /* OFDM54: -8.5dB */
3912 else if ((ridx % 8) == 7)
3913 pwr -= 20; /* OFDM60: -10dB */
3915 pwr -= 10; /* Others: -5dB */
3917 /* Do not exceed channel max TX power. */
3921 idx = gain - (pwr - power) - tdiff - vdiff;
3922 if ((ridx / 8) & 1) /* MIMO */
3923 idx += (int32_t)le32toh(uc->atten[grp][c]);
3926 idx += 9; /* 5GHz */
3927 if (ridx == IWN_RIDX_MAX)
3930 /* Make sure idx stays in a valid range. */
3933 else if (idx > IWN4965_MAX_PWR_INDEX)
3934 idx = IWN4965_MAX_PWR_INDEX;
3936 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3937 "%s: Tx chain %d, rate idx %d: power=%d\n",
3938 __func__, c, ridx, idx);
3939 cmd.power[ridx].rf_gain[c] = rf_gain[idx];
3940 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx];
3944 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3945 "%s: set tx power for chan %d\n", __func__, chan);
3946 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async);
3953 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
3956 struct iwn5000_cmd_txpower cmd;
3959 * TX power calibration is handled automatically by the firmware
3962 memset(&cmd, 0, sizeof cmd);
3963 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */
3964 cmd.flags = IWN5000_TXPOWER_NO_CLOSED;
3965 cmd.srv_limit = IWN5000_TXPOWER_AUTO;
3966 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__);
3967 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async);
3971 * Retrieve the maximum RSSI (in dBm) among receivers.
3974 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
3976 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;
3980 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;
3981 agc = (le16toh(phy->agc) >> 7) & 0x7f;
3985 if (mask & IWN_ANT_A) /* Ant A */
3986 rssi = max(rssi, phy->rssi[0]);
3987 if (mask & IWN_ATH_B) /* Ant B */
3988 rssi = max(rssi, phy->rssi[2]);
3989 if (mask & IWN_ANT_C) /* Ant C */
3990 rssi = max(rssi, phy->rssi[4]);
3992 rssi = max(rssi, phy->rssi[0]);
3993 rssi = max(rssi, phy->rssi[2]);
3994 rssi = max(rssi, phy->rssi[4]);
3997 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d mask 0x%x rssi %d %d %d "
3998 "result %d\n", __func__, agc, mask,
3999 phy->rssi[0], phy->rssi[2], phy->rssi[4],
4000 rssi - agc - IWN_RSSI_TO_DBM);
4001 return rssi - agc - IWN_RSSI_TO_DBM;
4005 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
4007 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;
4011 agc = (le32toh(phy->agc) >> 9) & 0x7f;
4013 rssi = MAX(le16toh(phy->rssi[0]) & 0xff,
4014 le16toh(phy->rssi[1]) & 0xff);
4015 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);
4017 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d rssi %d %d %d "
4018 "result %d\n", __func__, agc,
4019 phy->rssi[0], phy->rssi[1], phy->rssi[2],
4020 rssi - agc - IWN_RSSI_TO_DBM);
4021 return rssi - agc - IWN_RSSI_TO_DBM;
4025 * Retrieve the average noise (in dBm) among receivers.
4028 iwn_get_noise(const struct iwn_rx_general_stats *stats)
4030 int i, total, nbant, noise;
4033 for (i = 0; i < 3; i++) {
4034 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0)
4039 /* There should be at least one antenna but check anyway. */
4040 return (nbant == 0) ? -127 : (total / nbant) - 107;
4044 * Compute temperature (in degC) from last received statistics.
4047 iwn4965_get_temperature(struct iwn_softc *sc)
4049 struct iwn_ucode_info *uc = &sc->ucode_info;
4050 int32_t r1, r2, r3, r4, temp;
4052 r1 = le32toh(uc->temp[0].chan20MHz);
4053 r2 = le32toh(uc->temp[1].chan20MHz);
4054 r3 = le32toh(uc->temp[2].chan20MHz);
4055 r4 = le32toh(sc->rawtemp);
4057 if (r1 == r3) /* Prevents division by 0 (should not happen.) */
4060 /* Sign-extend 23-bit R4 value to 32-bit. */
4061 r4 = (r4 << 8) >> 8;
4062 /* Compute temperature in Kelvin. */
4063 temp = (259 * (r4 - r2)) / (r3 - r1);
4064 temp = (temp * 97) / 100 + 8;
4066 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp,
4068 return IWN_KTOC(temp);
4072 iwn5000_get_temperature(struct iwn_softc *sc)
4077 * Temperature is not used by the driver for 5000 Series because
4078 * TX power calibration is handled by firmware. We export it to
4079 * users through the sensor framework though.
4081 temp = le32toh(sc->rawtemp);
4082 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
4083 temp = (temp / -5) + sc->temp_off;
4084 temp = IWN_KTOC(temp);
4090 * Initialize sensitivity calibration state machine.
4093 iwn_init_sensitivity(struct iwn_softc *sc)
4095 const struct iwn_hal *hal = sc->sc_hal;
4096 struct iwn_calib_state *calib = &sc->calib;
4100 /* Reset calibration state machine. */
4101 memset(calib, 0, sizeof (*calib));
4102 calib->state = IWN_CALIB_STATE_INIT;
4103 calib->cck_state = IWN_CCK_STATE_HIFA;
4104 /* Set initial correlation values. */
4105 calib->ofdm_x1 = sc->limits->min_ofdm_x1;
4106 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1;
4107 calib->ofdm_x4 = sc->limits->min_ofdm_x4;
4108 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4;
4109 calib->cck_x4 = 125;
4110 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4;
4111 calib->energy_cck = sc->limits->energy_cck;
4113 /* Write initial sensitivity. */
4114 error = iwn_send_sensitivity(sc);
4118 /* Write initial gains. */
4119 error = hal->init_gains(sc);
4123 /* Request statistics at each beacon interval. */
4125 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: calibrate phy\n", __func__);
4126 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1);
4130 * Collect noise and RSSI statistics for the first 20 beacons received
4131 * after association and use them to determine connected antennas and
4132 * to set differential gains.
4135 iwn_collect_noise(struct iwn_softc *sc,
4136 const struct iwn_rx_general_stats *stats)
4138 const struct iwn_hal *hal = sc->sc_hal;
4139 struct iwn_calib_state *calib = &sc->calib;
4143 /* Accumulate RSSI and noise for all 3 antennas. */
4144 for (i = 0; i < 3; i++) {
4145 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff;
4146 calib->noise[i] += le32toh(stats->noise[i]) & 0xff;
4148 /* NB: We update differential gains only once after 20 beacons. */
4149 if (++calib->nbeacons < 20)
4152 /* Determine highest average RSSI. */
4153 val = MAX(calib->rssi[0], calib->rssi[1]);
4154 val = MAX(calib->rssi[2], val);
4156 /* Determine which antennas are connected. */
4158 for (i = 0; i < 3; i++)
4159 if (val - calib->rssi[i] <= 15 * 20)
4160 sc->chainmask |= 1 << i;
4161 /* If none of the TX antennas are connected, keep at least one. */
4162 if ((sc->chainmask & sc->txchainmask) == 0)
4163 sc->chainmask |= IWN_LSB(sc->txchainmask);
4165 (void)hal->set_gains(sc);
4166 calib->state = IWN_CALIB_STATE_RUN;
4169 /* XXX Disable RX chains with no antennas connected. */
4170 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask));
4171 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1);
4176 /* Enable power-saving mode if requested by user. */
4177 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON)
4178 (void)iwn_set_pslevel(sc, 0, 3, 1);
4183 iwn4965_init_gains(struct iwn_softc *sc)
4185 struct iwn_phy_calib_gain cmd;
4187 memset(&cmd, 0, sizeof cmd);
4188 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
4189 /* Differential gains initially set to 0 for all 3 antennas. */
4190 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4191 "%s: setting initial differential gains\n", __func__);
4192 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4196 iwn5000_init_gains(struct iwn_softc *sc)
4198 struct iwn_phy_calib cmd;
4200 memset(&cmd, 0, sizeof cmd);
4201 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN;
4204 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4205 "%s: setting initial differential gains\n", __func__);
4206 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4210 iwn4965_set_gains(struct iwn_softc *sc)
4212 struct iwn_calib_state *calib = &sc->calib;
4213 struct iwn_phy_calib_gain cmd;
4214 int i, delta, noise;
4216 /* Get minimal noise among connected antennas. */
4217 noise = INT_MAX; /* NB: There's at least one antenna. */
4218 for (i = 0; i < 3; i++)
4219 if (sc->chainmask & (1 << i))
4220 noise = MIN(calib->noise[i], noise);
4222 memset(&cmd, 0, sizeof cmd);
4223 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
4224 /* Set differential gains for connected antennas. */
4225 for (i = 0; i < 3; i++) {
4226 if (sc->chainmask & (1 << i)) {
4227 /* Compute attenuation (in unit of 1.5dB). */
4228 delta = (noise - (int32_t)calib->noise[i]) / 30;
4229 /* NB: delta <= 0 */
4230 /* Limit to [-4.5dB,0]. */
4231 cmd.gain[i] = MIN(abs(delta), 3);
4233 cmd.gain[i] |= 1 << 2; /* sign bit */
4236 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4237 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n",
4238 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask);
4239 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4243 iwn5000_set_gains(struct iwn_softc *sc)
4245 struct iwn_calib_state *calib = &sc->calib;
4246 struct iwn_phy_calib_gain cmd;
4247 int i, ant, delta, div;
4249 /* We collected 20 beacons and !=6050 need a 1.5 factor. */
4250 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
4252 memset(&cmd, 0, sizeof cmd);
4253 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN;
4256 /* Get first available RX antenna as referential. */
4257 ant = IWN_LSB(sc->rxchainmask);
4258 /* Set differential gains for other antennas. */
4259 for (i = ant + 1; i < 3; i++) {
4260 if (sc->chainmask & (1 << i)) {
4261 /* The delta is relative to antenna "ant". */
4262 delta = ((int32_t)calib->noise[ant] -
4263 (int32_t)calib->noise[i]) / div;
4264 /* Limit to [-4.5dB,+4.5dB]. */
4265 cmd.gain[i - 1] = MIN(abs(delta), 3);
4267 cmd.gain[i - 1] |= 1 << 2; /* sign bit */
4270 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4271 "setting differential gains Ant B/C: %x/%x (%x)\n",
4272 cmd.gain[0], cmd.gain[1], sc->chainmask);
4273 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4277 * Tune RF RX sensitivity based on the number of false alarms detected
4278 * during the last beacon period.
4281 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats)
4283 #define inc(val, inc, max) \
4284 if ((val) < (max)) { \
4285 if ((val) < (max) - (inc)) \
4291 #define dec(val, dec, min) \
4292 if ((val) > (min)) { \
4293 if ((val) > (min) + (dec)) \
4300 const struct iwn_sensitivity_limits *limits = sc->limits;
4301 struct iwn_calib_state *calib = &sc->calib;
4302 uint32_t val, rxena, fa;
4303 uint32_t energy[3], energy_min;
4304 uint8_t noise[3], noise_ref;
4305 int i, needs_update = 0;
4307 /* Check that we've been enabled long enough. */
4308 rxena = le32toh(stats->general.load);
4312 /* Compute number of false alarms since last call for OFDM. */
4313 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm;
4314 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm;
4315 fa *= 200 * 1024; /* 200TU */
4317 /* Save counters values for next call. */
4318 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp);
4319 calib->fa_ofdm = le32toh(stats->ofdm.fa);
4321 if (fa > 50 * rxena) {
4322 /* High false alarm count, decrease sensitivity. */
4323 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4324 "%s: OFDM high false alarm count: %u\n", __func__, fa);
4325 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1);
4326 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1);
4327 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4);
4328 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4);
4330 } else if (fa < 5 * rxena) {
4331 /* Low false alarm count, increase sensitivity. */
4332 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4333 "%s: OFDM low false alarm count: %u\n", __func__, fa);
4334 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1);
4335 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1);
4336 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4);
4337 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4);
4340 /* Compute maximum noise among 3 receivers. */
4341 for (i = 0; i < 3; i++)
4342 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff;
4343 val = MAX(noise[0], noise[1]);
4344 val = MAX(noise[2], val);
4345 /* Insert it into our samples table. */
4346 calib->noise_samples[calib->cur_noise_sample] = val;
4347 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20;
4349 /* Compute maximum noise among last 20 samples. */
4350 noise_ref = calib->noise_samples[0];
4351 for (i = 1; i < 20; i++)
4352 noise_ref = MAX(noise_ref, calib->noise_samples[i]);
4354 /* Compute maximum energy among 3 receivers. */
4355 for (i = 0; i < 3; i++)
4356 energy[i] = le32toh(stats->general.energy[i]);
4357 val = MIN(energy[0], energy[1]);
4358 val = MIN(energy[2], val);
4359 /* Insert it into our samples table. */
4360 calib->energy_samples[calib->cur_energy_sample] = val;
4361 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10;
4363 /* Compute minimum energy among last 10 samples. */
4364 energy_min = calib->energy_samples[0];
4365 for (i = 1; i < 10; i++)
4366 energy_min = MAX(energy_min, calib->energy_samples[i]);
4369 /* Compute number of false alarms since last call for CCK. */
4370 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck;
4371 fa += le32toh(stats->cck.fa) - calib->fa_cck;
4372 fa *= 200 * 1024; /* 200TU */
4374 /* Save counters values for next call. */
4375 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp);
4376 calib->fa_cck = le32toh(stats->cck.fa);
4378 if (fa > 50 * rxena) {
4379 /* High false alarm count, decrease sensitivity. */
4380 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4381 "%s: CCK high false alarm count: %u\n", __func__, fa);
4382 calib->cck_state = IWN_CCK_STATE_HIFA;
4385 if (calib->cck_x4 > 160) {
4386 calib->noise_ref = noise_ref;
4387 if (calib->energy_cck > 2)
4388 dec(calib->energy_cck, 2, energy_min);
4390 if (calib->cck_x4 < 160) {
4391 calib->cck_x4 = 161;
4394 inc(calib->cck_x4, 3, limits->max_cck_x4);
4396 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4);
4398 } else if (fa < 5 * rxena) {
4399 /* Low false alarm count, increase sensitivity. */
4400 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4401 "%s: CCK low false alarm count: %u\n", __func__, fa);
4402 calib->cck_state = IWN_CCK_STATE_LOFA;
4405 if (calib->cck_state != IWN_CCK_STATE_INIT &&
4406 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 ||
4407 calib->low_fa > 100)) {
4408 inc(calib->energy_cck, 2, limits->min_energy_cck);
4409 dec(calib->cck_x4, 3, limits->min_cck_x4);
4410 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4);
4413 /* Not worth to increase or decrease sensitivity. */
4414 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4415 "%s: CCK normal false alarm count: %u\n", __func__, fa);
4417 calib->noise_ref = noise_ref;
4419 if (calib->cck_state == IWN_CCK_STATE_HIFA) {
4420 /* Previous interval had many false alarms. */
4421 dec(calib->energy_cck, 8, energy_min);
4423 calib->cck_state = IWN_CCK_STATE_INIT;
4427 (void)iwn_send_sensitivity(sc);
4433 iwn_send_sensitivity(struct iwn_softc *sc)
4435 struct iwn_calib_state *calib = &sc->calib;
4436 struct iwn_sensitivity_cmd cmd;
4438 memset(&cmd, 0, sizeof cmd);
4439 cmd.which = IWN_SENSITIVITY_WORKTBL;
4440 /* OFDM modulation. */
4441 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1);
4442 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1);
4443 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4);
4444 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4);
4445 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm);
4446 cmd.energy_ofdm_th = htole16(62);
4447 /* CCK modulation. */
4448 cmd.corr_cck_x4 = htole16(calib->cck_x4);
4449 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4);
4450 cmd.energy_cck = htole16(calib->energy_cck);
4451 /* Barker modulation: use default values. */
4452 cmd.corr_barker = htole16(190);
4453 cmd.corr_barker_mrc = htole16(390);
4455 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4456 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__,
4457 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4,
4458 calib->ofdm_mrc_x4, calib->cck_x4,
4459 calib->cck_mrc_x4, calib->energy_cck);
4460 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1);
4464 * Set STA mode power saving level (between 0 and 5).
4465 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving.
4468 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async)
4470 const struct iwn_pmgt *pmgt;
4471 struct iwn_pmgt_cmd cmd;
4472 uint32_t max, skip_dtim;
4476 /* Select which PS parameters to use. */
4478 pmgt = &iwn_pmgt[0][level];
4479 else if (dtim <= 10)
4480 pmgt = &iwn_pmgt[1][level];
4482 pmgt = &iwn_pmgt[2][level];
4484 memset(&cmd, 0, sizeof cmd);
4485 if (level != 0) /* not CAM */
4486 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP);
4488 cmd.flags |= htole16(IWN_PS_FAST_PD);
4489 /* Retrieve PCIe Active State Power Management (ASPM). */
4490 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
4491 if (!(tmp & 0x1)) /* L0s Entry disabled. */
4492 cmd.flags |= htole16(IWN_PS_PCI_PMGT);
4493 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024);
4494 cmd.txtimeout = htole32(pmgt->txtimeout * 1024);
4500 skip_dtim = pmgt->skip_dtim;
4501 if (skip_dtim != 0) {
4502 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM);
4503 max = pmgt->intval[4];
4504 if (max == (uint32_t)-1)
4505 max = dtim * (skip_dtim + 1);
4506 else if (max > dtim)
4507 max = (max / dtim) * dtim;
4510 for (i = 0; i < 5; i++)
4511 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i]));
4513 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n",
4515 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async);
4519 iwn_config(struct iwn_softc *sc)
4521 const struct iwn_hal *hal = sc->sc_hal;
4522 struct ifnet *ifp = sc->sc_ifp;
4523 struct ieee80211com *ic = ifp->if_l2com;
4524 struct iwn_bluetooth bluetooth;
4529 /* Configure valid TX chains for 5000 Series. */
4530 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4531 txmask = htole32(sc->txchainmask);
4532 DPRINTF(sc, IWN_DEBUG_RESET,
4533 "%s: configuring valid TX chains 0x%x\n", __func__, txmask);
4534 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask,
4537 device_printf(sc->sc_dev,
4538 "%s: could not configure valid TX chains, "
4539 "error %d\n", __func__, error);
4544 /* Configure bluetooth coexistence. */
4545 memset(&bluetooth, 0, sizeof bluetooth);
4546 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO;
4547 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF;
4548 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF;
4549 DPRINTF(sc, IWN_DEBUG_RESET, "%s: config bluetooth coexistence\n",
4551 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0);
4553 device_printf(sc->sc_dev,
4554 "%s: could not configure bluetooth coexistence, error %d\n",
4559 /* Set mode, channel, RX filter and enable RX. */
4560 memset(&sc->rxon, 0, sizeof (struct iwn_rxon));
4561 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp));
4562 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp));
4563 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
4564 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
4565 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
4566 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
4567 switch (ic->ic_opmode) {
4568 case IEEE80211_M_STA:
4569 sc->rxon.mode = IWN_MODE_STA;
4570 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST);
4572 case IEEE80211_M_MONITOR:
4573 sc->rxon.mode = IWN_MODE_MONITOR;
4574 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST |
4575 IWN_FILTER_CTL | IWN_FILTER_PROMISC);
4578 /* Should not get there. */
4581 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */
4582 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */
4583 sc->rxon.ht_single_mask = 0xff;
4584 sc->rxon.ht_dual_mask = 0xff;
4585 sc->rxon.ht_triple_mask = 0xff;
4587 IWN_RXCHAIN_VALID(sc->rxchainmask) |
4588 IWN_RXCHAIN_MIMO_COUNT(2) |
4589 IWN_RXCHAIN_IDLE_COUNT(2);
4590 sc->rxon.rxchain = htole16(rxchain);
4591 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__);
4592 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 0);
4594 device_printf(sc->sc_dev,
4595 "%s: RXON command failed\n", __func__);
4599 error = iwn_add_broadcast_node(sc, 0);
4601 device_printf(sc->sc_dev,
4602 "%s: could not add broadcast node\n", __func__);
4606 /* Configuration has changed, set TX power accordingly. */
4607 error = hal->set_txpower(sc, ic->ic_curchan, 0);
4609 device_printf(sc->sc_dev,
4610 "%s: could not set TX power\n", __func__);
4614 error = iwn_set_critical_temp(sc);
4616 device_printf(sc->sc_dev,
4617 "%s: ccould not set critical temperature\n", __func__);
4621 /* Set power saving level to CAM during initialization. */
4622 error = iwn_set_pslevel(sc, 0, 0, 0);
4624 device_printf(sc->sc_dev,
4625 "%s: could not set power saving level\n", __func__);
4632 iwn_scan(struct iwn_softc *sc)
4634 struct ifnet *ifp = sc->sc_ifp;
4635 struct ieee80211com *ic = ifp->if_l2com;
4636 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/
4637 struct iwn_scan_hdr *hdr;
4638 struct iwn_cmd_data *tx;
4639 struct iwn_scan_essid *essid;
4640 struct iwn_scan_chan *chan;
4641 struct ieee80211_frame *wh;
4642 struct ieee80211_rateset *rs;
4643 struct ieee80211_channel *c;
4644 int buflen, error, nrates;
4646 uint8_t *buf, *frm, txant;
4648 buf = kmalloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_INTWAIT | M_ZERO);
4650 device_printf(sc->sc_dev,
4651 "%s: could not allocate buffer for scan command\n",
4655 hdr = (struct iwn_scan_hdr *)buf;
4658 * Move to the next channel if no frames are received within 10ms
4659 * after sending the probe request.
4661 hdr->quiet_time = htole16(10); /* timeout in milliseconds */
4662 hdr->quiet_threshold = htole16(1); /* min # of packets */
4664 /* Select antennas for scanning. */
4666 IWN_RXCHAIN_VALID(sc->rxchainmask) |
4667 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) |
4668 IWN_RXCHAIN_DRIVER_FORCE;
4669 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) &&
4670 sc->hw_type == IWN_HW_REV_TYPE_4965) {
4671 /* Ant A must be avoided in 5GHz because of an HW bug. */
4672 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC);
4673 } else /* Use all available RX antennas. */
4674 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask);
4675 hdr->rxchain = htole16(rxchain);
4676 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON);
4678 tx = (struct iwn_cmd_data *)(hdr + 1);
4679 tx->flags = htole32(IWN_TX_AUTO_SEQ);
4680 tx->id = sc->sc_hal->broadcast_id;
4681 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
4683 if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) {
4684 /* Send probe requests at 6Mbps. */
4685 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp;
4686 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A];
4688 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO);
4689 /* Send probe requests at 1Mbps. */
4690 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp;
4691 tx->rflags = IWN_RFLAG_CCK;
4692 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G];
4694 /* Use the first valid TX antenna. */
4695 txant = IWN_LSB(sc->txchainmask);
4696 tx->rflags |= IWN_RFLAG_ANT(txant);
4698 essid = (struct iwn_scan_essid *)(tx + 1);
4699 if (ss->ss_ssid[0].len != 0) {
4700 essid[0].id = IEEE80211_ELEMID_SSID;
4701 essid[0].len = ss->ss_ssid[0].len;
4702 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len);
4706 * Build a probe request frame. Most of the following code is a
4707 * copy & paste of what is done in net80211.
4709 wh = (struct ieee80211_frame *)(essid + 20);
4710 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
4711 IEEE80211_FC0_SUBTYPE_PROBE_REQ;
4712 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
4713 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr);
4714 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp));
4715 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr);
4716 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */
4717 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */
4719 frm = (uint8_t *)(wh + 1);
4722 *frm++ = IEEE80211_ELEMID_SSID;
4723 *frm++ = ss->ss_ssid[0].len;
4724 memcpy(frm, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len);
4725 frm += ss->ss_ssid[0].len;
4727 /* Add supported rates IE. */
4728 *frm++ = IEEE80211_ELEMID_RATES;
4729 nrates = rs->rs_nrates;
4730 if (nrates > IEEE80211_RATE_SIZE)
4731 nrates = IEEE80211_RATE_SIZE;
4733 memcpy(frm, rs->rs_rates, nrates);
4736 /* Add supported xrates IE. */
4737 if (rs->rs_nrates > IEEE80211_RATE_SIZE) {
4738 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE;
4739 *frm++ = IEEE80211_ELEMID_XRATES;
4740 *frm++ = (uint8_t)nrates;
4741 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates);
4745 /* Set length of probe request. */
4746 tx->len = htole16(frm - (uint8_t *)wh);
4749 chan = (struct iwn_scan_chan *)frm;
4750 chan->chan = htole16(ieee80211_chan2ieee(ic, c));
4752 if (ss->ss_nssid > 0)
4753 chan->flags |= htole32(IWN_CHAN_NPBREQS(1));
4754 chan->dsp_gain = 0x6e;
4755 if (IEEE80211_IS_CHAN_5GHZ(c) &&
4756 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) {
4757 chan->rf_gain = 0x3b;
4758 chan->active = htole16(24);
4759 chan->passive = htole16(110);
4760 chan->flags |= htole32(IWN_CHAN_ACTIVE);
4761 } else if (IEEE80211_IS_CHAN_5GHZ(c)) {
4762 chan->rf_gain = 0x3b;
4763 chan->active = htole16(24);
4764 if (sc->rxon.associd)
4765 chan->passive = htole16(78);
4767 chan->passive = htole16(110);
4768 hdr->crc_threshold = 0xffff;
4769 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) {
4770 chan->rf_gain = 0x28;
4771 chan->active = htole16(36);
4772 chan->passive = htole16(120);
4773 chan->flags |= htole32(IWN_CHAN_ACTIVE);
4775 chan->rf_gain = 0x28;
4776 chan->active = htole16(36);
4777 if (sc->rxon.associd)
4778 chan->passive = htole16(88);
4780 chan->passive = htole16(120);
4781 hdr->crc_threshold = 0xffff;
4784 DPRINTF(sc, IWN_DEBUG_STATE,
4785 "%s: chan %u flags 0x%x rf_gain 0x%x "
4786 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__,
4787 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain,
4788 chan->active, chan->passive);
4792 buflen = (uint8_t *)chan - buf;
4793 hdr->len = htole16(buflen);
4795 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n",
4797 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1);
4798 kfree(buf, M_DEVBUF);
4803 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap)
4805 const struct iwn_hal *hal = sc->sc_hal;
4806 struct ifnet *ifp = sc->sc_ifp;
4807 struct ieee80211com *ic = ifp->if_l2com;
4808 struct ieee80211_node *ni = vap->iv_bss;
4811 sc->calib.state = IWN_CALIB_STATE_INIT;
4813 /* Update adapter configuration. */
4814 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
4815 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan));
4816 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
4817 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
4818 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
4819 if (ic->ic_flags & IEEE80211_F_SHSLOT)
4820 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
4821 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4822 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
4823 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
4824 sc->rxon.cck_mask = 0;
4825 sc->rxon.ofdm_mask = 0x15;
4826 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
4827 sc->rxon.cck_mask = 0x03;
4828 sc->rxon.ofdm_mask = 0;
4830 /* XXX assume 802.11b/g */
4831 sc->rxon.cck_mask = 0x0f;
4832 sc->rxon.ofdm_mask = 0x15;
4834 DPRINTF(sc, IWN_DEBUG_STATE,
4835 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x "
4836 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x "
4837 "myaddr %6D wlap %6D bssid %6D associd %d filter 0x%x\n",
4839 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags),
4840 sc->rxon.cck_mask, sc->rxon.ofdm_mask,
4841 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask,
4842 le16toh(sc->rxon.rxchain),
4843 sc->rxon.myaddr, ":", sc->rxon.wlap, ":", sc->rxon.bssid, ":",
4844 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter));
4845 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1);
4847 device_printf(sc->sc_dev,
4848 "%s: RXON command failed, error %d\n", __func__, error);
4852 /* Configuration has changed, set TX power accordingly. */
4853 error = hal->set_txpower(sc, ni->ni_chan, 1);
4855 device_printf(sc->sc_dev,
4856 "%s: could not set Tx power, error %d\n", __func__, error);
4860 * Reconfiguring RXON clears the firmware nodes table so we must
4861 * add the broadcast node again.
4863 error = iwn_add_broadcast_node(sc, 1);
4865 device_printf(sc->sc_dev,
4866 "%s: could not add broadcast node, error %d\n",
4874 * Configure the adapter for associated state.
4877 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap)
4879 #define MS(v,x) (((v) & x) >> x##_S)
4880 const struct iwn_hal *hal = sc->sc_hal;
4881 struct ifnet *ifp = sc->sc_ifp;
4882 struct ieee80211com *ic = ifp->if_l2com;
4883 struct ieee80211_node *ni = vap->iv_bss;
4884 struct iwn_node_info node;
4887 sc->calib.state = IWN_CALIB_STATE_INIT;
4889 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4890 /* Link LED blinks while monitoring. */
4891 iwn_set_led(sc, IWN_LED_LINK, 5, 5);
4894 error = iwn_set_timing(sc, ni);
4896 device_printf(sc->sc_dev,
4897 "%s: could not set timing, error %d\n", __func__, error);
4901 /* Update adapter configuration. */
4902 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
4903 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan));
4904 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd));
4905 /* Short preamble and slot time are negotiated when associating. */
4906 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT);
4907 sc->rxon.flags |= htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
4908 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
4909 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
4911 sc->rxon.flags &= ~htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
4912 if (ic->ic_flags & IEEE80211_F_SHSLOT)
4913 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
4914 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4915 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
4916 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
4917 sc->rxon.cck_mask = 0;
4918 sc->rxon.ofdm_mask = 0x15;
4919 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
4920 sc->rxon.cck_mask = 0x03;
4921 sc->rxon.ofdm_mask = 0;
4923 /* XXX assume 802.11b/g */
4924 sc->rxon.cck_mask = 0x0f;
4925 sc->rxon.ofdm_mask = 0x15;
4928 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
4929 sc->rxon.flags &= ~htole32(IWN_RXON_HT);
4930 if (IEEE80211_IS_CHAN_HT40U(ni->ni_chan))
4931 sc->rxon.flags |= htole32(IWN_RXON_HT40U);
4932 else if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan))
4933 sc->rxon.flags |= htole32(IWN_RXON_HT40D);
4935 sc->rxon.flags |= htole32(IWN_RXON_HT20);
4936 sc->rxon.rxchain = htole16(
4937 IWN_RXCHAIN_VALID(3)
4938 | IWN_RXCHAIN_MIMO_COUNT(3)
4939 | IWN_RXCHAIN_IDLE_COUNT(1)
4940 | IWN_RXCHAIN_MIMO_FORCE);
4942 maxrxampdu = MS(ni->ni_htparam, IEEE80211_HTCAP_MAXRXAMPDU);
4943 ampdudensity = MS(ni->ni_htparam, IEEE80211_HTCAP_MPDUDENSITY);
4945 maxrxampdu = ampdudensity = 0;
4947 sc->rxon.filter |= htole32(IWN_FILTER_BSS);
4949 DPRINTF(sc, IWN_DEBUG_STATE,
4950 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x "
4951 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x "
4952 "myaddr %6D wlap %6D bssid %6D associd %d filter 0x%x\n",
4954 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags),
4955 sc->rxon.cck_mask, sc->rxon.ofdm_mask,
4956 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask,
4957 le16toh(sc->rxon.rxchain),
4958 sc->rxon.myaddr, ":", sc->rxon.wlap, ":", sc->rxon.bssid, ":",
4959 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter));
4960 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1);
4962 device_printf(sc->sc_dev,
4963 "%s: could not update configuration, error %d\n",
4968 /* Configuration has changed, set TX power accordingly. */
4969 error = hal->set_txpower(sc, ni->ni_chan, 1);
4971 device_printf(sc->sc_dev,
4972 "%s: could not set Tx power, error %d\n", __func__, error);
4977 memset(&node, 0, sizeof node);
4978 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr);
4979 node.id = IWN_ID_BSS;
4981 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) |
4982 IWN_AMDPU_DENSITY(5)); /* 2us */
4984 DPRINTF(sc, IWN_DEBUG_STATE, "%s: add BSS node, id %d htflags 0x%x\n",
4985 __func__, node.id, le32toh(node.htflags));
4986 error = hal->add_node(sc, &node, 1);
4988 device_printf(sc->sc_dev, "could not add BSS node\n");
4991 DPRINTF(sc, IWN_DEBUG_STATE, "setting link quality for node %d\n",
4993 error = iwn_set_link_quality(sc, node.id, 1);
4995 device_printf(sc->sc_dev,
4996 "%s: could not setup MRR for node %d, error %d\n",
4997 __func__, node.id, error);
5001 error = iwn_init_sensitivity(sc);
5003 device_printf(sc->sc_dev,
5004 "%s: could not set sensitivity, error %d\n",
5009 /* Start periodic calibration timer. */
5010 sc->calib.state = IWN_CALIB_STATE_ASSOC;
5011 iwn_calib_reset(sc);
5013 /* Link LED always on while associated. */
5014 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
5022 * This function is called by upper layer when an ADDBA request is received
5023 * from another STA and before the ADDBA response is sent.
5026 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
5029 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid];
5030 struct iwn_softc *sc = ic->ic_softc;
5031 struct iwn_node *wn = (void *)ni;
5032 struct iwn_node_info node;
5034 memset(&node, 0, sizeof node);
5036 node.control = IWN_NODE_UPDATE;
5037 node.flags = IWN_FLAG_SET_ADDBA;
5038 node.addba_tid = tid;
5039 node.addba_ssn = htole16(ba->ba_winstart);
5040 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n",
5041 wn->id, tid, ba->ba_winstart));
5042 return sc->sc_hal->add_node(sc, &node, 1);
5046 * This function is called by upper layer on teardown of an HT-immediate
5047 * Block Ack agreement (eg. uppon receipt of a DELBA frame.)
5050 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
5053 struct iwn_softc *sc = ic->ic_softc;
5054 struct iwn_node *wn = (void *)ni;
5055 struct iwn_node_info node;
5057 memset(&node, 0, sizeof node);
5059 node.control = IWN_NODE_UPDATE;
5060 node.flags = IWN_FLAG_SET_DELBA;
5061 node.delba_tid = tid;
5062 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid);
5063 (void)sc->sc_hal->add_node(sc, &node, 1);
5067 * This function is called by upper layer when an ADDBA response is received
5071 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
5074 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid];
5075 struct iwn_softc *sc = ic->ic_softc;
5076 const struct iwn_hal *hal = sc->sc_hal;
5077 struct iwn_node *wn = (void *)ni;
5078 struct iwn_node_info node;
5081 /* Enable TX for the specified RA/TID. */
5082 wn->disable_tid &= ~(1 << tid);
5083 memset(&node, 0, sizeof node);
5085 node.control = IWN_NODE_UPDATE;
5086 node.flags = IWN_FLAG_SET_DISABLE_TID;
5087 node.disable_tid = htole16(wn->disable_tid);
5088 error = hal->add_node(sc, &node, 1);
5092 if ((error = iwn_nic_lock(sc)) != 0)
5094 hal->ampdu_tx_start(sc, ni, tid, ba->ba_winstart);
5100 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
5103 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid];
5104 struct iwn_softc *sc = ic->ic_softc;
5107 error = iwn_nic_lock(sc);
5110 sc->sc_hal->ampdu_tx_stop(sc, tid, ba->ba_winstart);
5115 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5116 uint8_t tid, uint16_t ssn)
5118 struct iwn_node *wn = (void *)ni;
5121 /* Stop TX scheduler while we're changing its configuration. */
5122 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5123 IWN4965_TXQ_STATUS_CHGACT);
5125 /* Assign RA/TID translation to the queue. */
5126 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid),
5129 /* Enable chain-building mode for the queue. */
5130 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid);
5132 /* Set starting sequence number from the ADDBA request. */
5133 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5134 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5136 /* Set scheduler window size. */
5137 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid),
5139 /* Set scheduler frame limit. */
5140 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5141 IWN_SCHED_LIMIT << 16);
5143 /* Enable interrupts for the queue. */
5144 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5146 /* Mark the queue as active. */
5147 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5148 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA |
5149 iwn_tid2fifo[tid] << 1);
5153 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn)
5157 /* Stop TX scheduler while we're changing its configuration. */
5158 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5159 IWN4965_TXQ_STATUS_CHGACT);
5161 /* Set starting sequence number from the ADDBA request. */
5162 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5163 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5165 /* Disable interrupts for the queue. */
5166 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5168 /* Mark the queue as inactive. */
5169 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5170 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1);
5174 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5175 uint8_t tid, uint16_t ssn)
5177 struct iwn_node *wn = (void *)ni;
5180 /* Stop TX scheduler while we're changing its configuration. */
5181 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5182 IWN5000_TXQ_STATUS_CHGACT);
5184 /* Assign RA/TID translation to the queue. */
5185 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid),
5188 /* Enable chain-building mode for the queue. */
5189 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid);
5191 /* Enable aggregation for the queue. */
5192 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5194 /* Set starting sequence number from the ADDBA request. */
5195 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5196 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5198 /* Set scheduler window size and frame limit. */
5199 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5200 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5202 /* Enable interrupts for the queue. */
5203 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5205 /* Mark the queue as active. */
5206 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5207 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]);
5211 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn)
5215 /* Stop TX scheduler while we're changing its configuration. */
5216 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5217 IWN5000_TXQ_STATUS_CHGACT);
5219 /* Disable aggregation for the queue. */
5220 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5222 /* Set starting sequence number from the ADDBA request. */
5223 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5224 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5226 /* Disable interrupts for the queue. */
5227 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5229 /* Mark the queue as inactive. */
5230 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5231 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]);
5236 * Query calibration tables from the initialization firmware. We do this
5237 * only once at first boot. Called from a process context.
5240 iwn5000_query_calibration(struct iwn_softc *sc)
5242 struct iwn5000_calib_config cmd;
5245 memset(&cmd, 0, sizeof cmd);
5246 cmd.ucode.once.enable = 0xffffffff;
5247 cmd.ucode.once.start = 0xffffffff;
5248 cmd.ucode.once.send = 0xffffffff;
5249 cmd.ucode.flags = 0xffffffff;
5250 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n",
5252 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0);
5256 /* Wait at most two seconds for calibration to complete. */
5257 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE))
5258 error = lksleep(sc, &sc->sc_lock, 0, "iwninit", 2 * hz);
5263 * Send calibration results to the runtime firmware. These results were
5264 * obtained on first boot from the initialization firmware.
5267 iwn5000_send_calibration(struct iwn_softc *sc)
5271 for (idx = 0; idx < 5; idx++) {
5272 if (sc->calibcmd[idx].buf == NULL)
5273 continue; /* No results available. */
5274 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5275 "send calibration result idx=%d len=%d\n",
5276 idx, sc->calibcmd[idx].len);
5277 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf,
5278 sc->calibcmd[idx].len, 0);
5280 device_printf(sc->sc_dev,
5281 "%s: could not send calibration result, error %d\n",
5290 iwn5000_send_wimax_coex(struct iwn_softc *sc)
5292 struct iwn5000_wimax_coex wimax;
5295 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
5296 /* Enable WiMAX coexistence for combo adapters. */
5298 IWN_WIMAX_COEX_ASSOC_WA_UNMASK |
5299 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK |
5300 IWN_WIMAX_COEX_STA_TABLE_VALID |
5301 IWN_WIMAX_COEX_ENABLE;
5302 memcpy(wimax.events, iwn6050_wimax_events,
5303 sizeof iwn6050_wimax_events);
5307 /* Disable WiMAX coexistence. */
5309 memset(wimax.events, 0, sizeof wimax.events);
5311 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n",
5313 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0);
5317 * This function is called after the runtime firmware notifies us of its
5318 * readiness (called in a process context.)
5321 iwn4965_post_alive(struct iwn_softc *sc)
5325 if ((error = iwn_nic_lock(sc)) != 0)
5328 /* Clear TX scheduler state in SRAM. */
5329 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5330 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0,
5331 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t));
5333 /* Set physical address of TX scheduler rings (1KB aligned.) */
5334 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5336 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5338 /* Disable chain mode for all our 16 queues. */
5339 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0);
5341 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) {
5342 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0);
5343 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5345 /* Set scheduler window size. */
5346 iwn_mem_write(sc, sc->sched_base +
5347 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ);
5348 /* Set scheduler frame limit. */
5349 iwn_mem_write(sc, sc->sched_base +
5350 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5351 IWN_SCHED_LIMIT << 16);
5354 /* Enable interrupts for all our 16 queues. */
5355 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff);
5356 /* Identify TX FIFO rings (0-7). */
5357 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff);
5359 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
5360 for (qid = 0; qid < 7; qid++) {
5361 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
5362 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5363 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1);
5370 * This function is called after the initialization or runtime firmware
5371 * notifies us of its readiness (called in a process context.)
5374 iwn5000_post_alive(struct iwn_softc *sc)
5378 /* Switch to using ICT interrupt mode. */
5379 iwn5000_ict_reset(sc);
5381 error = iwn_nic_lock(sc);
5385 /* Clear TX scheduler state in SRAM. */
5386 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5387 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0,
5388 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t));
5390 /* Set physical address of TX scheduler rings (1KB aligned.) */
5391 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5393 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5395 /* Enable chain mode for all queues, except command queue. */
5396 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef);
5397 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0);
5399 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) {
5400 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0);
5401 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5403 iwn_mem_write(sc, sc->sched_base +
5404 IWN5000_SCHED_QUEUE_OFFSET(qid), 0);
5405 /* Set scheduler window size and frame limit. */
5406 iwn_mem_write(sc, sc->sched_base +
5407 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5408 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5411 /* Enable interrupts for all our 20 queues. */
5412 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff);
5413 /* Identify TX FIFO rings (0-7). */
5414 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff);
5416 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
5417 for (qid = 0; qid < 7; qid++) {
5418 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
5419 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5420 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]);
5424 /* Configure WiMAX coexistence for combo adapters. */
5425 error = iwn5000_send_wimax_coex(sc);
5427 device_printf(sc->sc_dev,
5428 "%s: could not configure WiMAX coexistence, error %d\n",
5432 if (sc->hw_type != IWN_HW_REV_TYPE_5150) {
5433 struct iwn5000_phy_calib_crystal cmd;
5435 /* Perform crystal calibration. */
5436 memset(&cmd, 0, sizeof cmd);
5437 cmd.code = IWN5000_PHY_CALIB_CRYSTAL;
5440 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff;
5441 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff;
5442 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5443 "sending crystal calibration %d, %d\n",
5444 cmd.cap_pin[0], cmd.cap_pin[1]);
5445 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5447 device_printf(sc->sc_dev,
5448 "%s: crystal calibration failed, error %d\n",
5453 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) {
5454 /* Query calibration from the initialization firmware. */
5455 error = iwn5000_query_calibration(sc);
5457 device_printf(sc->sc_dev,
5458 "%s: could not query calibration, error %d\n",
5463 * We have the calibration results now, reboot with the
5464 * runtime firmware (call ourselves recursively!)
5467 error = iwn_hw_init(sc);
5469 /* Send calibration results to runtime firmware. */
5470 error = iwn5000_send_calibration(sc);
5476 * The firmware boot code is small and is intended to be copied directly into
5477 * the NIC internal memory (no DMA transfer.)
5480 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size)
5484 size /= sizeof (uint32_t);
5486 error = iwn_nic_lock(sc);
5490 /* Copy microcode image into NIC memory. */
5491 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE,
5492 (const uint32_t *)ucode, size);
5494 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0);
5495 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE);
5496 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size);
5498 /* Start boot load now. */
5499 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START);
5501 /* Wait for transfer to complete. */
5502 for (ntries = 0; ntries < 1000; ntries++) {
5503 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) &
5504 IWN_BSM_WR_CTRL_START))
5508 if (ntries == 1000) {
5509 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
5515 /* Enable boot after power up. */
5516 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN);
5523 iwn4965_load_firmware(struct iwn_softc *sc)
5525 struct iwn_fw_info *fw = &sc->fw;
5526 struct iwn_dma_info *dma = &sc->fw_dma;
5529 /* Copy initialization sections into pre-allocated DMA-safe memory. */
5530 memcpy(dma->vaddr, fw->init.data, fw->init.datasz);
5531 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE);
5532 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
5533 fw->init.text, fw->init.textsz);
5534 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE);
5536 /* Tell adapter where to find initialization sections. */
5537 error = iwn_nic_lock(sc);
5540 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
5541 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz);
5542 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
5543 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
5544 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz);
5547 /* Load firmware boot code. */
5548 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz);
5550 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
5554 /* Now press "execute". */
5555 IWN_WRITE(sc, IWN_RESET, 0);
5557 /* Wait at most one second for first alive notification. */
5558 error = lksleep(sc, &sc->sc_lock, 0, "iwninit", hz);
5560 device_printf(sc->sc_dev,
5561 "%s: timeout waiting for adapter to initialize, error %d\n",
5566 /* Retrieve current temperature for initial TX power calibration. */
5567 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz;
5568 sc->temp = iwn4965_get_temperature(sc);
5570 /* Copy runtime sections into pre-allocated DMA-safe memory. */
5571 memcpy(dma->vaddr, fw->main.data, fw->main.datasz);
5572 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE);
5573 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
5574 fw->main.text, fw->main.textsz);
5575 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE);
5577 /* Tell adapter where to find runtime sections. */
5578 error = iwn_nic_lock(sc);
5582 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
5583 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz);
5584 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
5585 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
5586 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE,
5587 IWN_FW_UPDATED | fw->main.textsz);
5594 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst,
5595 const uint8_t *section, int size)
5597 struct iwn_dma_info *dma = &sc->fw_dma;
5600 /* Copy firmware section into pre-allocated DMA-safe memory. */
5601 memcpy(dma->vaddr, section, size);
5602 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE);
5604 error = iwn_nic_lock(sc);
5608 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
5609 IWN_FH_TX_CONFIG_DMA_PAUSE);
5611 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst);
5612 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL),
5613 IWN_LOADDR(dma->paddr));
5614 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL),
5615 IWN_HIADDR(dma->paddr) << 28 | size);
5616 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL),
5617 IWN_FH_TXBUF_STATUS_TBNUM(1) |
5618 IWN_FH_TXBUF_STATUS_TBIDX(1) |
5619 IWN_FH_TXBUF_STATUS_TFBD_VALID);
5621 /* Kick Flow Handler to start DMA transfer. */
5622 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
5623 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD);
5627 /* Wait at most five seconds for FH DMA transfer to complete. */
5628 return lksleep(sc, &sc->sc_lock, 0, "iwninit", hz);
5632 iwn5000_load_firmware(struct iwn_softc *sc)
5634 struct iwn_fw_part *fw;
5637 /* Load the initialization firmware on first boot only. */
5638 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ?
5639 &sc->fw.main : &sc->fw.init;
5641 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE,
5642 fw->text, fw->textsz);
5644 device_printf(sc->sc_dev,
5645 "%s: could not load firmware %s section, error %d\n",
5646 __func__, ".text", error);
5649 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE,
5650 fw->data, fw->datasz);
5652 device_printf(sc->sc_dev,
5653 "%s: could not load firmware %s section, error %d\n",
5654 __func__, ".data", error);
5658 /* Now press "execute". */
5659 IWN_WRITE(sc, IWN_RESET, 0);
5664 iwn_read_firmware(struct iwn_softc *sc)
5666 const struct iwn_hal *hal = sc->sc_hal;
5667 struct iwn_fw_info *fw = &sc->fw;
5668 const uint32_t *ptr;
5674 /* Read firmware image from filesystem. */
5675 sc->fw_fp = firmware_get(sc->fwname);
5676 if (sc->fw_fp == NULL) {
5677 device_printf(sc->sc_dev,
5678 "%s: could not load firmare image \"%s\"\n", __func__,
5685 size = sc->fw_fp->datasize;
5687 device_printf(sc->sc_dev,
5688 "%s: truncated firmware header: %zu bytes\n",
5693 /* Process firmware header. */
5694 ptr = (const uint32_t *)sc->fw_fp->data;
5695 rev = le32toh(*ptr++);
5696 /* Check firmware API version. */
5697 if (IWN_FW_API(rev) <= 1) {
5698 device_printf(sc->sc_dev,
5699 "%s: bad firmware, need API version >=2\n", __func__);
5702 if (IWN_FW_API(rev) >= 3) {
5703 /* Skip build number (version 2 header). */
5707 fw->main.textsz = le32toh(*ptr++);
5708 fw->main.datasz = le32toh(*ptr++);
5709 fw->init.textsz = le32toh(*ptr++);
5710 fw->init.datasz = le32toh(*ptr++);
5711 fw->boot.textsz = le32toh(*ptr++);
5714 /* Sanity-check firmware header. */
5715 if (fw->main.textsz > hal->fw_text_maxsz ||
5716 fw->main.datasz > hal->fw_data_maxsz ||
5717 fw->init.textsz > hal->fw_text_maxsz ||
5718 fw->init.datasz > hal->fw_data_maxsz ||
5719 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ ||
5720 (fw->boot.textsz & 3) != 0) {
5721 device_printf(sc->sc_dev, "%s: invalid firmware header\n",
5726 /* Check that all firmware sections fit. */
5727 if (fw->main.textsz + fw->main.datasz + fw->init.textsz +
5728 fw->init.datasz + fw->boot.textsz > size) {
5729 device_printf(sc->sc_dev,
5730 "%s: firmware file too short: %zu bytes\n",
5735 /* Get pointers to firmware sections. */
5736 fw->main.text = (const uint8_t *)ptr;
5737 fw->main.data = fw->main.text + fw->main.textsz;
5738 fw->init.text = fw->main.data + fw->main.datasz;
5739 fw->init.data = fw->init.text + fw->init.textsz;
5740 fw->boot.text = fw->init.data + fw->init.datasz;
5746 iwn_clock_wait(struct iwn_softc *sc)
5750 /* Set "initialization complete" bit. */
5751 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
5753 /* Wait for clock stabilization. */
5754 for (ntries = 0; ntries < 2500; ntries++) {
5755 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY)
5759 device_printf(sc->sc_dev,
5760 "%s: timeout waiting for clock stabilization\n", __func__);
5765 iwn_apm_init(struct iwn_softc *sc)
5770 /* Disable L0s exit timer (NMI bug workaround.) */
5771 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER);
5772 /* Don't wait for ICH L0s (ICH bug workaround.) */
5773 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX);
5775 /* Set FH wait threshold to max (HW bug under stress workaround.) */
5776 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000);
5778 /* Enable HAP INTA to move adapter from L1a to L0s. */
5779 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A);
5781 /* Retrieve PCIe Active State Power Management (ASPM). */
5782 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
5783 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
5784 if (tmp & 0x02) /* L1 Entry enabled. */
5785 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
5787 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
5789 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
5790 sc->hw_type != IWN_HW_REV_TYPE_6000 &&
5791 sc->hw_type != IWN_HW_REV_TYPE_6050)
5792 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT);
5794 /* Wait for clock stabilization before accessing prph. */
5795 error = iwn_clock_wait(sc);
5799 error = iwn_nic_lock(sc);
5803 if (sc->hw_type == IWN_HW_REV_TYPE_4965) {
5804 /* Enable DMA and BSM (Bootstrap State Machine.) */
5805 iwn_prph_write(sc, IWN_APMG_CLK_EN,
5806 IWN_APMG_CLK_CTRL_DMA_CLK_RQT |
5807 IWN_APMG_CLK_CTRL_BSM_CLK_RQT);
5810 iwn_prph_write(sc, IWN_APMG_CLK_EN,
5811 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
5815 /* Disable L1-Active. */
5816 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS);
5823 iwn_apm_stop_master(struct iwn_softc *sc)
5827 /* Stop busmaster DMA activity. */
5828 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER);
5829 for (ntries = 0; ntries < 100; ntries++) {
5830 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED)
5834 device_printf(sc->sc_dev, "%s: timeout waiting for master\n",
5839 iwn_apm_stop(struct iwn_softc *sc)
5841 iwn_apm_stop_master(sc);
5843 /* Reset the entire device. */
5844 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW);
5846 /* Clear "initialization complete" bit. */
5847 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
5851 iwn4965_nic_config(struct iwn_softc *sc)
5853 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) {
5855 * I don't believe this to be correct but this is what the
5856 * vendor driver is doing. Probably the bits should not be
5857 * shifted in IWN_RFCFG_*.
5859 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5860 IWN_RFCFG_TYPE(sc->rfcfg) |
5861 IWN_RFCFG_STEP(sc->rfcfg) |
5862 IWN_RFCFG_DASH(sc->rfcfg));
5864 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5865 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
5870 iwn5000_nic_config(struct iwn_softc *sc)
5875 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) {
5876 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5877 IWN_RFCFG_TYPE(sc->rfcfg) |
5878 IWN_RFCFG_STEP(sc->rfcfg) |
5879 IWN_RFCFG_DASH(sc->rfcfg));
5881 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5882 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
5884 error = iwn_nic_lock(sc);
5887 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS);
5889 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
5891 * Select first Switching Voltage Regulator (1.32V) to
5892 * solve a stability issue related to noisy DC2DC line
5893 * in the silicon of 1000 Series.
5895 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR);
5896 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK;
5897 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32;
5898 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp);
5902 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) {
5903 /* Use internal power amplifier only. */
5904 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA);
5906 if (sc->hw_type == IWN_HW_REV_TYPE_6050 && sc->calib_ver >= 6) {
5907 /* Indicate that ROM calibration version is >=6. */
5908 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6);
5914 * Take NIC ownership over Intel Active Management Technology (AMT).
5917 iwn_hw_prepare(struct iwn_softc *sc)
5921 /* Check if hardware is ready. */
5922 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
5923 for (ntries = 0; ntries < 5; ntries++) {
5924 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
5925 IWN_HW_IF_CONFIG_NIC_READY)
5930 /* Hardware not ready, force into ready state. */
5931 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE);
5932 for (ntries = 0; ntries < 15000; ntries++) {
5933 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) &
5934 IWN_HW_IF_CONFIG_PREPARE_DONE))
5938 if (ntries == 15000)
5941 /* Hardware should be ready now. */
5942 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
5943 for (ntries = 0; ntries < 5; ntries++) {
5944 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
5945 IWN_HW_IF_CONFIG_NIC_READY)
5953 iwn_hw_init(struct iwn_softc *sc)
5955 const struct iwn_hal *hal = sc->sc_hal;
5956 int error, chnl, qid;
5958 /* Clear pending interrupts. */
5959 IWN_WRITE(sc, IWN_INT, 0xffffffff);
5961 error = iwn_apm_init(sc);
5963 device_printf(sc->sc_dev,
5964 "%s: could not power ON adapter, error %d\n",
5969 /* Select VMAIN power source. */
5970 error = iwn_nic_lock(sc);
5973 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK);
5976 /* Perform adapter-specific initialization. */
5977 error = hal->nic_config(sc);
5981 /* Initialize RX ring. */
5982 error = iwn_nic_lock(sc);
5985 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
5986 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0);
5987 /* Set physical address of RX ring (256-byte aligned.) */
5988 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8);
5989 /* Set physical address of RX status (16-byte aligned.) */
5990 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4);
5992 IWN_WRITE(sc, IWN_FH_RX_CONFIG,
5993 IWN_FH_RX_CONFIG_ENA |
5994 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */
5995 IWN_FH_RX_CONFIG_IRQ_DST_HOST |
5996 IWN_FH_RX_CONFIG_SINGLE_FRAME |
5997 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) |
5998 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG));
6000 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7);
6002 error = iwn_nic_lock(sc);
6006 /* Initialize TX scheduler. */
6007 iwn_prph_write(sc, hal->sched_txfact_addr, 0);
6009 /* Set physical address of "keep warm" page (16-byte aligned.) */
6010 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4);
6012 /* Initialize TX rings. */
6013 for (qid = 0; qid < hal->ntxqs; qid++) {
6014 struct iwn_tx_ring *txq = &sc->txq[qid];
6016 /* Set physical address of TX ring (256-byte aligned.) */
6017 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid),
6018 txq->desc_dma.paddr >> 8);
6022 /* Enable DMA channels. */
6023 for (chnl = 0; chnl < hal->ndmachnls; chnl++) {
6024 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl),
6025 IWN_FH_TX_CONFIG_DMA_ENA |
6026 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA);
6029 /* Clear "radio off" and "commands blocked" bits. */
6030 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6031 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED);
6033 /* Clear pending interrupts. */
6034 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6035 /* Enable interrupt coalescing. */
6036 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8);
6037 /* Enable interrupts. */
6038 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6040 /* _Really_ make sure "radio off" bit is cleared! */
6041 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6042 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6044 error = hal->load_firmware(sc);
6046 device_printf(sc->sc_dev,
6047 "%s: could not load firmware, error %d\n",
6051 /* Wait at most one second for firmware alive notification. */
6052 error = lksleep(sc, &sc->sc_lock, 0, "iwninit", hz);
6054 device_printf(sc->sc_dev,
6055 "%s: timeout waiting for adapter to initialize, error %d\n",
6059 /* Do post-firmware initialization. */
6060 return hal->post_alive(sc);
6064 iwn_hw_stop(struct iwn_softc *sc)
6066 const struct iwn_hal *hal = sc->sc_hal;
6068 int chnl, qid, ntries;
6070 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO);
6072 /* Disable interrupts. */
6073 IWN_WRITE(sc, IWN_INT_MASK, 0);
6074 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6075 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff);
6076 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6078 /* Make sure we no longer hold the NIC lock. */
6081 /* Stop TX scheduler. */
6082 iwn_prph_write(sc, hal->sched_txfact_addr, 0);
6084 /* Stop all DMA channels. */
6085 if (iwn_nic_lock(sc) == 0) {
6086 for (chnl = 0; chnl < hal->ndmachnls; chnl++) {
6087 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0);
6088 for (ntries = 0; ntries < 200; ntries++) {
6089 tmp = IWN_READ(sc, IWN_FH_TX_STATUS);
6090 if ((tmp & IWN_FH_TX_STATUS_IDLE(chnl)) ==
6091 IWN_FH_TX_STATUS_IDLE(chnl))
6100 iwn_reset_rx_ring(sc, &sc->rxq);
6102 /* Reset all TX rings. */
6103 for (qid = 0; qid < hal->ntxqs; qid++)
6104 iwn_reset_tx_ring(sc, &sc->txq[qid]);
6106 if (iwn_nic_lock(sc) == 0) {
6107 iwn_prph_write(sc, IWN_APMG_CLK_DIS,
6108 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
6113 /* Power OFF adapter. */
6118 iwn_init_locked(struct iwn_softc *sc)
6120 struct ifnet *ifp = sc->sc_ifp;
6123 IWN_LOCK_ASSERT(sc);
6125 error = iwn_hw_prepare(sc);
6127 device_printf(sc->sc_dev, "%s: hardware not ready, eror %d\n",
6132 /* Initialize interrupt mask to default value. */
6133 sc->int_mask = IWN_INT_MASK_DEF;
6134 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6136 /* Check that the radio is not disabled by hardware switch. */
6137 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) {
6138 device_printf(sc->sc_dev,
6139 "radio is disabled by hardware switch\n");
6141 /* Enable interrupts to get RF toggle notifications. */
6142 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6143 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6147 /* Read firmware images from the filesystem. */
6148 error = iwn_read_firmware(sc);
6150 device_printf(sc->sc_dev,
6151 "%s: could not read firmware, error %d\n",
6156 /* Initialize hardware and upload firmware. */
6157 error = iwn_hw_init(sc);
6158 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6161 device_printf(sc->sc_dev,
6162 "%s: could not initialize hardware, error %d\n",
6167 /* Configure adapter now that it is ready. */
6168 error = iwn_config(sc);
6170 device_printf(sc->sc_dev,
6171 "%s: could not configure device, error %d\n",
6176 ifp->if_flags &= ~IFF_OACTIVE;
6177 ifp->if_flags |= IFF_RUNNING;
6182 iwn_stop_locked(sc);
6188 struct iwn_softc *sc = arg;
6189 struct ifnet *ifp = sc->sc_ifp;
6190 struct ieee80211com *ic = ifp->if_l2com;
6193 iwn_init_locked(sc);
6196 if (ifp->if_flags & IFF_RUNNING)
6197 ieee80211_start_all(ic);
6201 iwn_stop_locked(struct iwn_softc *sc)
6203 struct ifnet *ifp = sc->sc_ifp;
6205 IWN_LOCK_ASSERT(sc);
6207 sc->sc_tx_timer = 0;
6208 callout_stop(&sc->sc_timer_to);
6209 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
6211 /* Power OFF hardware. */
6216 iwn_stop(struct iwn_softc *sc)
6219 iwn_stop_locked(sc);
6224 * Callback from net80211 to start a scan.
6227 iwn_scan_start(struct ieee80211com *ic)
6229 struct ifnet *ifp = ic->ic_ifp;
6230 struct iwn_softc *sc = ifp->if_softc;
6233 /* make the link LED blink while we're scanning */
6234 iwn_set_led(sc, IWN_LED_LINK, 20, 2);
6239 * Callback from net80211 to terminate a scan.
6242 iwn_scan_end(struct ieee80211com *ic)
6244 struct ifnet *ifp = ic->ic_ifp;
6245 struct iwn_softc *sc = ifp->if_softc;
6246 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6249 if (vap->iv_state == IEEE80211_S_RUN) {
6250 /* Set link LED to ON status if we are associated */
6251 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
6257 * Callback from net80211 to force a channel change.
6260 iwn_set_channel(struct ieee80211com *ic)
6262 const struct ieee80211_channel *c = ic->ic_curchan;
6263 struct ifnet *ifp = ic->ic_ifp;
6264 struct iwn_softc *sc = ifp->if_softc;
6267 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq);
6268 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags);
6269 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq);
6270 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags);
6275 * Callback from net80211 to start scanning of the current channel.
6278 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell)
6280 struct ieee80211vap *vap = ss->ss_vap;
6281 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc;
6285 error = iwn_scan(sc);
6288 ieee80211_cancel_scan(vap);
6292 * Callback from net80211 to handle the minimum dwell time being met.
6293 * The intent is to terminate the scan but we just let the firmware
6294 * notify us when it's finished as we have no safe way to abort it.
6297 iwn_scan_mindwell(struct ieee80211_scan_state *ss)
6299 /* NB: don't try to abort scan; wait for firmware to finish */
6302 static struct iwn_eeprom_chan *
6303 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c)
6307 for (j = 0; j < 7; j++) {
6308 for (i = 0; i < iwn_bands[j].nchan; i++) {
6309 if (iwn_bands[j].chan[i] == c->ic_ieee)
6310 return &sc->eeprom_channels[j][i];
6318 * Enforce flags read from EEPROM.
6321 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd,
6322 int nchan, struct ieee80211_channel chans[])
6324 struct iwn_softc *sc = ic->ic_ifp->if_softc;
6327 for (i = 0; i < nchan; i++) {
6328 struct ieee80211_channel *c = &chans[i];
6329 struct iwn_eeprom_chan *channel;
6331 channel = iwn_find_eeprom_channel(sc, c);
6332 if (channel == NULL) {
6333 if_printf(ic->ic_ifp,
6334 "%s: invalid channel %u freq %u/0x%x\n",
6335 __func__, c->ic_ieee, c->ic_freq, c->ic_flags);
6338 c->ic_flags |= iwn_eeprom_channel_flags(channel);
6345 iwn_hw_reset(void *arg0, int pending)
6347 struct iwn_softc *sc = arg0;
6348 struct ifnet *ifp = sc->sc_ifp;
6349 struct ieee80211com *ic = ifp->if_l2com;
6353 ieee80211_notify_radio(ic, 1);
6357 iwn_radio_on(void *arg0, int pending)
6359 struct iwn_softc *sc = arg0;
6360 struct ifnet *ifp = sc->sc_ifp;
6361 struct ieee80211com *ic = ifp->if_l2com;
6362 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6366 ieee80211_init(vap);
6371 iwn_radio_off(void *arg0, int pending)
6373 struct iwn_softc *sc = arg0;
6374 struct ifnet *ifp = sc->sc_ifp;
6375 struct ieee80211com *ic = ifp->if_l2com;
6376 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6380 ieee80211_stop(vap);
6382 /* Enable interrupts to get RF toggle notification. */
6384 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6385 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6390 iwn_sysctlattach(struct iwn_softc *sc)
6392 struct sysctl_ctx_list *ctx;
6393 struct sysctl_oid *tree;
6395 ctx = &sc->sc_sysctl_ctx;
6396 tree = sc->sc_sysctl_tree;
6398 device_printf(sc->sc_dev, "can't add sysctl node\n");
6404 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6405 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs");
6410 iwn_shutdown(device_t dev)
6412 struct iwn_softc *sc = device_get_softc(dev);
6419 iwn_suspend(device_t dev)
6421 struct iwn_softc *sc = device_get_softc(dev);
6422 struct ifnet *ifp = sc->sc_ifp;
6423 struct ieee80211com *ic = ifp->if_l2com;
6424 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6428 ieee80211_stop(vap);
6433 iwn_resume(device_t dev)
6435 struct iwn_softc *sc = device_get_softc(dev);
6436 struct ifnet *ifp = sc->sc_ifp;
6437 struct ieee80211com *ic = ifp->if_l2com;
6438 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6440 /* Clear device-specific "PCI retry timeout" register (41h). */
6441 pci_write_config(dev, 0x41, 0, 1);
6443 if (ifp->if_flags & IFF_UP) {
6446 ieee80211_init(vap);
6447 if (ifp->if_flags & IFF_RUNNING)
6455 iwn_intr_str(uint8_t cmd)
6459 case IWN_UC_READY: return "UC_READY";
6460 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE";
6461 case IWN_TX_DONE: return "TX_DONE";
6462 case IWN_START_SCAN: return "START_SCAN";
6463 case IWN_STOP_SCAN: return "STOP_SCAN";
6464 case IWN_RX_STATISTICS: return "RX_STATS";
6465 case IWN_BEACON_STATISTICS: return "BEACON_STATS";
6466 case IWN_STATE_CHANGED: return "STATE_CHANGED";
6467 case IWN_BEACON_MISSED: return "BEACON_MISSED";
6468 case IWN_RX_PHY: return "RX_PHY";
6469 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE";
6470 case IWN_RX_DONE: return "RX_DONE";
6472 /* Command Notifications */
6473 case IWN_CMD_RXON: return "IWN_CMD_RXON";
6474 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC";
6475 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS";
6476 case IWN_CMD_TIMING: return "IWN_CMD_TIMING";
6477 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY";
6478 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED";
6479 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX";
6480 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG";
6481 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT";
6482 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE";
6483 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE";
6484 case IWN_CMD_SCAN: return "IWN_CMD_SCAN";
6485 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS";
6486 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER";
6487 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM";
6488 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG";
6489 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX";
6490 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP";
6491 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY";
6492 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB";
6494 return "UNKNOWN INTR NOTIF/CMD";
6496 #endif /* IWN_DEBUG */
6498 static device_method_t iwn_methods[] = {
6499 /* Device interface */
6500 DEVMETHOD(device_probe, iwn_probe),
6501 DEVMETHOD(device_attach, iwn_attach),
6502 DEVMETHOD(device_detach, iwn_detach),
6503 DEVMETHOD(device_shutdown, iwn_shutdown),
6504 DEVMETHOD(device_suspend, iwn_suspend),
6505 DEVMETHOD(device_resume, iwn_resume),
6509 static driver_t iwn_driver = {
6512 sizeof (struct iwn_softc)
6514 static devclass_t iwn_devclass;
6516 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0);
6517 MODULE_DEPEND(iwn, pci, 1, 1, 1);
6518 MODULE_DEPEND(iwn, firmware, 1, 1, 1);
6519 MODULE_DEPEND(iwn, wlan, 1, 1, 1);
6520 MODULE_DEPEND(iwn, wlan_amrr, 1, 1, 1);