2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/dev/an/if_anreg.h,v 1.1.2.8 2003/02/11 03:32:48 ambrisko Exp $
33 * $DragonFly: src/sys/dev/netif/an/if_anreg.h,v 1.7 2005/07/27 21:56:32 joerg Exp $
36 #define AN_TIMEOUT 65536
38 /* Default network name: <empty string> */
39 #define AN_DEFAULT_NETNAME ""
41 /* The nodename must be less than 16 bytes */
42 #define AN_DEFAULT_NODENAME "FreeBSD"
44 #define AN_DEFAULT_IBSS "FreeBSD IBSS"
47 * register space access macros
49 #define CSR_WRITE_2(sc, reg, val) \
50 bus_space_write_2(sc->an_btag, sc->an_bhandle, reg, val)
52 #define CSR_READ_2(sc, reg) \
53 bus_space_read_2(sc->an_btag, sc->an_bhandle, reg)
55 #define CSR_WRITE_1(sc, reg, val) \
56 bus_space_write_1(sc->an_btag, sc->an_bhandle, reg, val)
58 #define CSR_READ_1(sc, reg) \
59 bus_space_read_1(sc->an_btag, sc->an_bhandle, reg)
62 * memory space access macros
64 #define CSR_MEM_WRITE_2(sc, reg, val) \
65 bus_space_write_2(sc->an_mem_btag, sc->an_mem_bhandle, reg, val)
67 #define CSR_MEM_READ_2(sc, reg) \
68 bus_space_read_2(sc->an_mem_btag, sc->an_mem_bhandle, reg)
70 #define CSR_MEM_WRITE_1(sc, reg, val) \
71 bus_space_write_1(sc->an_mem_btag, sc->an_mem_bhandle, reg, val)
73 #define CSR_MEM_READ_1(sc, reg) \
74 bus_space_read_1(sc->an_mem_btag, sc->an_mem_bhandle, reg)
77 * aux. memory space access macros
79 #define CSR_MEM_AUX_WRITE_4(sc, reg, val) \
80 bus_space_write_4(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg, val)
82 #define CSR_MEM_AUX_READ_4(sc, reg) \
83 bus_space_read_4(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg)
85 #define CSR_MEM_AUX_WRITE_1(sc, reg, val) \
86 bus_space_write_1(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg, val)
88 #define CSR_MEM_AUX_READ_1(sc, reg) \
89 bus_space_read_1(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg)
92 * Size of Aironet I/O space.
97 * Size of aux. memory space ... probably not needed DJA
99 #define AN_AUXMEMSIZE (256 * 1024)
102 * Hermes register definitions and what little I know about them.
105 /* Hermes command/status registers. */
106 #define AN_COMMAND(x) (x ? 0x00 : 0x00)
107 #define AN_PARAM0(x) (x ? 0x04 : 0x02)
108 #define AN_PARAM1(x) (x ? 0x08 : 0x04)
109 #define AN_PARAM2(x) (x ? 0x0c : 0x06)
110 #define AN_STATUS(x) (x ? 0x10 : 0x08)
111 #define AN_RESP0(x) (x ? 0x14 : 0x0A)
112 #define AN_RESP1(x) (x ? 0x18 : 0x0C)
113 #define AN_RESP2(x) (x ? 0x1c : 0x0E)
114 #define AN_LINKSTAT(x) (x ? 0x20 : 0x10)
116 /* Command register */
117 #define AN_CMD_BUSY 0x8000 /* busy bit */
118 #define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */
119 #define AN_CMD_CODE_MASK 0x003F
120 #define AN_CMD_QUAL_MASK 0x7F00
123 #define AN_CMD_NOOP 0x0000 /* no-op */
124 #define AN_CMD_ENABLE 0x0001 /* enable */
125 #define AN_CMD_DISABLE 0x0002 /* disable */
126 #define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */
127 #define AN_CMD_FW_RESTART 0x0004 /* firmware resrart */
128 #define AN_CMD_HOST_SLEEP 0x0005
129 #define AN_CMD_MAGIC_PKT 0x0006
130 #define AN_CMD_READCFG 0x0008
131 #define AN_CMD_SET_MODE 0x0009
132 #define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
133 #define AN_CMD_TX 0x000B /* transmit */
134 #define AN_CMD_DEALLOC_MEM 0x000C
135 #define AN_CMD_NOOP2 0x0010
136 #define AN_CMD_ALLOC_DESC 0x0020
137 #define AN_CMD_ACCESS 0x0021
138 #define AN_CMD_ALLOC_BUF 0x0028
139 #define AN_CMD_PSP_NODES 0x0030
140 #define AN_CMD_SET_PHYREG 0x003E
141 #define AN_CMD_TX_TEST 0x003F
142 #define AN_CMD_SLEEP 0x0085
143 #define AN_CMD_SAVECFG 0x0108
146 * MPI 350 DMA descriptor information
148 #define AN_DESCRIPTOR_TX 0x01
149 #define AN_DESCRIPTOR_RX 0x02
150 #define AN_DESCRIPTOR_TXCMP 0x04
151 #define AN_DESCRIPTOR_HOSTWRITE 0x08
152 #define AN_DESCRIPTOR_HOSTREAD 0x10
153 #define AN_DESCRIPTOR_HOSTRW 0x20
155 #define AN_MAX_RX_DESC 1
156 #define AN_MAX_TX_DESC 1
157 #define AN_HOSTBUFSIZ 1840
159 struct an_card_rid_desc
167 struct an_card_rx_desc
176 struct an_card_tx_desc
178 unsigned an_offset:15;
185 #define AN_RID_BUFFER_SIZE 2048
186 #define AN_RX_BUFFER_SIZE 1840
187 #define AN_TX_BUFFER_SIZE 1840
188 #define AN_HOST_DESC_OFFSET 0x8
189 #define AN_RX_DESC_OFFSET (AN_HOST_DESC_OFFSET + \
190 sizeof(struct an_card_rid_desc))
191 #define AN_TX_DESC_OFFSET (AN_RX_DESC_OFFSET + \
192 (AN_MAX_RX_DESC * sizeof(struct an_card_rx_desc)))
209 * Reclaim qualifier bit, applicable to the
212 #define AN_RECLAIM 0x0100 /* reclaim NIC memory */
215 * ACCESS command qualifier bits.
217 #define AN_ACCESS_READ 0x0000
218 #define AN_ACCESS_WRITE 0x0100
221 * PROGRAM command qualifier bits.
223 #define AN_PROGRAM_DISABLE 0x0000
224 #define AN_PROGRAM_ENABLE_RAM 0x0100
225 #define AN_PROGRAM_ENABLE_NVRAM 0x0200
226 #define AN_PROGRAM_NVRAM 0x0300
228 /* Status register values */
229 #define AN_STAT_CMD_CODE 0x003F
230 #define AN_STAT_CMD_RESULT 0x7F00
232 /* Linkstat register */
233 #define AN_LINKSTAT_ASSOCIATED 0x0400
234 #define AN_LINKSTAT_AUTHFAIL 0x0300
235 #define AN_LINKSTAT_ASSOC_FAIL 0x8400
236 #define AN_LINKSTAT_DISASSOC 0x8200
237 #define AN_LINKSTAT_DEAUTH 0x8100
238 #define AN_LINKSTAT_SYNCLOST_TSF 0x8004
239 #define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003
240 #define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002
241 #define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001
242 #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000
244 /* memory handle management registers */
245 #define AN_RX_FID 0x20
246 #define AN_ALLOC_FID 0x22
247 #define AN_TX_CMP_FID 0x24
250 * Buffer Access Path (BAP) registers.
251 * These are I/O channels. I believe you can use each one for
252 * any desired purpose independently of the other. In general
253 * though, we use BAP1 for reading and writing LTV records and
254 * reading received data frames, and BAP0 for writing transmit
255 * frames. This is a convention though, not a rule.
261 #define AN_DATA0 0x36
262 #define AN_DATA1 0x38
263 #define AN_BAP0 AN_DATA0
264 #define AN_BAP1 AN_DATA1
266 #define AN_OFF_BUSY 0x8000
267 #define AN_OFF_ERR 0x4000
268 #define AN_OFF_DONE 0x2000
269 #define AN_OFF_DATAOFF 0x0FFF
271 /* Event registers */
272 #define AN_EVENT_STAT(x) (x ? 0x60 : 0x30) /* Event status */
273 #define AN_INT_EN(x) (x ? 0x64 : 0x32) /* Interrupt enable/
275 #define AN_EVENT_ACK(x) (x ? 0x68 : 0x34) /* Ack event */
278 #define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */
279 #define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */
280 #define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode*/
281 #define AN_EV_LINKSTAT 0x0080 /* link status available */
282 #define AN_EV_CMD 0x0010 /* command completed */
283 #define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
284 #define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */
285 #define AN_EV_TX 0x0002 /* async xmit completed succesfully */
286 #define AN_EV_RX 0x0001 /* async rx completed */
289 (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC|AN_EV_LINKSTAT)
291 /* Host software registers */
292 #define AN_SW0(x) (x ? 0x50 : 0x28)
293 #define AN_SW1(x) (x ? 0x54 : 0x2A)
294 #define AN_SW2(x) (x ? 0x58 : 0x2C)
295 #define AN_SW3(x) (x ? 0x5c : 0x2E)
299 #define AN_CNTL_AUX_ENA 0xC000
300 #define AN_CNTL_AUX_ENA_STAT 0xC000
301 #define AN_CNTL_AUX_DIS_STAT 0x0000
302 #define AN_CNTL_AUX_ENA_CNTL 0x8000
303 #define AN_CNTL_AUX_DIS_CNTL 0x4000
305 #define AN_AUX_PAGE 0x3A
306 #define AN_AUX_OFFSET 0x3C
307 #define AN_AUX_DATA 0x3E
310 * Length, Type, Value (LTV) record definitions and RID values.
318 #define AN_DEF_SSID_LEN 7
319 #define AN_DEF_SSID "tsunami"
321 #define AN_RXGAP_MAX 8
324 * Transmit frame structure.
327 u_int32_t an_tx_sw; /* 0x00 */
328 u_int16_t an_tx_status; /* 0x04 */
329 u_int16_t an_tx_payload_len; /* 0x06 */
330 u_int16_t an_tx_ctl; /* 0x08 */
331 u_int16_t an_tx_assoc_id; /* 0x0A */
332 u_int16_t an_tx_retry; /* 0x0C */
333 u_int8_t an_tx_assoc_cnt; /* 0x0E */
334 u_int8_t an_tx_rate; /* 0x0F */
335 u_int8_t an_tx_max_long_retries; /* 0x10 */
336 u_int8_t an_tx_max_short_retries; /*0x11 */
337 u_int8_t an_rsvd0[2]; /* 0x12 */
338 u_int16_t an_frame_ctl; /* 0x14 */
339 u_int16_t an_duration; /* 0x16 */
340 u_int8_t an_addr1[6]; /* 0x18 */
341 u_int8_t an_addr2[6]; /* 0x1E */
342 u_int8_t an_addr3[6]; /* 0x24 */
343 u_int16_t an_seq_ctl; /* 0x2A */
344 u_int8_t an_addr4[6]; /* 0x2C */
345 u_int8_t an_gaplen; /* 0x32 */
346 } __attribute__ ((packed));
348 struct an_rxframe_802_3 {
349 u_int16_t an_rx_802_3_status; /* 0x34 */
350 u_int16_t an_rx_802_3_payload_len;/* 0x36 */
351 u_int8_t an_rx_dst_addr[6]; /* 0x38 */
352 u_int8_t an_rx_src_addr[6]; /* 0x3E */
354 #define AN_RXGAP_MAX 8
357 struct an_txframe_802_3 {
359 * Transmit 802.3 header structure.
361 u_int16_t an_tx_802_3_status; /* 0x34 */
362 u_int16_t an_tx_802_3_payload_len;/* 0x36 */
363 u_int8_t an_tx_dst_addr[6]; /* 0x38 */
364 u_int8_t an_tx_src_addr[6]; /* 0x3E */
367 #define AN_TXSTAT_EXCESS_RETRY 0x0002
368 #define AN_TXSTAT_LIFE_EXCEEDED 0x0004
369 #define AN_TXSTAT_AID_FAIL 0x0008
370 #define AN_TXSTAT_MAC_DISABLED 0x0010
371 #define AN_TXSTAT_ASSOC_LOST 0x0020
373 #define AN_TXCTL_RSVD 0x0001
374 #define AN_TXCTL_TXOK_INTR 0x0002
375 #define AN_TXCTL_TXERR_INTR 0x0004
376 #define AN_TXCTL_HEADER_TYPE 0x0008
377 #define AN_TXCTL_PAYLOAD_TYPE 0x0010
378 #define AN_TXCTL_NORELEASE 0x0020
379 #define AN_TXCTL_NORETRIES 0x0040
380 #define AN_TXCTL_CLEAR_AID 0x0080
381 #define AN_TXCTL_STRICT_ORDER 0x0100
382 #define AN_TXCTL_USE_RTS 0x0200
384 #define AN_HEADERTYPE_8023 0x0000
385 #define AN_HEADERTYPE_80211 0x0008
387 #define AN_PAYLOADTYPE_ETHER 0x0000
388 #define AN_PAYLOADTYPE_LLC 0x0010
390 #define AN_TXCTL_80211 \
391 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_80211| \
392 AN_PAYLOADTYPE_LLC|AN_TXCTL_NORELEASE)
394 #define AN_TXCTL_8023 \
395 (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_8023| \
396 AN_PAYLOADTYPE_ETHER|AN_TXCTL_NORELEASE)
398 #define AN_TXGAP_80211 0
399 #define AN_TXGAP_8023 0
401 struct an_802_3_hdr {
402 u_int16_t an_8023_status;
403 u_int16_t an_8023_payload_len;
404 u_int8_t an_8023_dst_addr[6];
405 u_int8_t an_8023_src_addr[6];
406 u_int16_t an_8023_dat[3]; /* SNAP header */
407 u_int16_t an_8023_type;
411 u_int16_t an_snap_dat[3]; /* SNAP header */
412 u_int16_t an_snap_type;
415 struct an_dma_alloc {
416 u_int32_t an_dma_paddr;
417 caddr_t an_dma_vaddr;
418 bus_dmamap_t an_dma_map;
419 bus_dma_segment_t an_dma_seg;
420 bus_size_t an_dma_size;
424 #define AN_TX_RING_CNT 4
425 #define AN_INC(x, y) (x) = (x + 1) % y
427 struct an_tx_ring_data {
428 u_int16_t an_tx_fids[AN_TX_RING_CNT];
429 u_int16_t an_tx_ring[AN_TX_RING_CNT];
436 struct arpcom arpcom;
438 int port_rid; /* resource id for port range */
439 struct resource* port_res; /* resource for port range */
440 int mem_rid; /* resource id for memory range */
441 int mem_used; /* nonzero if memory used */
442 struct resource* mem_res; /* resource for memory range */
443 int mem_aux_rid; /* resource id for memory range */
444 int mem_aux_used; /* nonzero if memory used */
445 struct resource* mem_aux_res; /* resource for memory range */
446 int irq_rid; /* resource id for irq */
447 void* irq_handle; /* handle for irq handler */
448 struct resource* irq_res; /* resource for irq */
450 bus_space_handle_t an_bhandle_p;
451 bus_space_handle_t an_bhandle;
452 bus_space_tag_t an_btag;
453 bus_space_handle_t an_mem_bhandle;
454 bus_space_tag_t an_mem_btag;
455 bus_space_handle_t an_mem_aux_bhandle;
456 bus_space_tag_t an_mem_aux_btag;
457 bus_dma_tag_t an_dtag;
458 struct an_ltv_genconfig an_config;
459 struct an_ltv_caps an_caps;
460 struct an_ltv_ssidlist an_ssidlist;
461 struct an_ltv_aplist an_aplist;
462 struct an_ltv_key an_temp_keys[4];
466 u_int8_t an_txbuf[1536];
467 struct an_tx_ring_data an_rdata;
468 struct an_ltv_stats an_stats;
469 struct an_ltv_status an_status;
470 u_int8_t an_associated;
473 struct an_sigcache an_sigcache[MAXANCACHE];
476 struct an_ltv_rssi_map an_rssimap;
478 struct callout an_stat_timer;
479 struct ifmedia an_ifmedia;
482 u_char buf_802_11[MCLBYTES];
484 unsigned short* an_flash_buffer;
486 struct an_dma_alloc an_rid_buffer;
487 struct an_dma_alloc an_rx_buffer[AN_MAX_RX_DESC];
488 struct an_dma_alloc an_tx_buffer[AN_MAX_TX_DESC];
491 void an_release_resources (device_t);
492 int an_alloc_port (device_t, int, int);
493 int an_alloc_memory (device_t, int, int);
494 int an_alloc_aux_memory (device_t, int, int);
495 int an_alloc_irq (device_t, int, int);
496 int an_probe (device_t);
497 void an_shutdown (device_t);
498 void an_resume (device_t);
499 int an_attach (struct an_softc *, device_t, int);
500 int an_detach (device_t);
501 void an_stop (struct an_softc *);
503 driver_intr_t an_intr;
505 #define AN_802_3_OFFSET 0x2E
506 #define AN_802_11_OFFSET 0x44
507 #define AN_802_11_OFFSET_RAW 0x3C
509 #define AN_STAT_BADCRC 0x0001
510 #define AN_STAT_UNDECRYPTABLE 0x0002
511 #define AN_STAT_ERRSTAT 0x0003
512 #define AN_STAT_MAC_PORT 0x0700
513 #define AN_STAT_1042 0x2000 /* RFC1042 encoded */
514 #define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
515 #define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
516 #define AN_RXSTAT_MSG_TYPE 0xE000
518 #define AN_ENC_TX_802_3 0x00
519 #define AN_ENC_TX_802_11 0x11
520 #define AN_ENC_TX_E_II 0x0E
522 #define AN_ENC_TX_1042 0x00
523 #define AN_ENC_TX_TUNNEL 0xF8
525 #define AN_TXCNTL_MACPORT 0x00FF
526 #define AN_TXCNTL_STRUCTTYPE 0xFF00
529 * SNAP (sub-network access protocol) constants for transmission
530 * of IP datagrams over IEEE 802 networks, taken from RFC1042.
531 * We need these for the LLC/SNAP header fields in the TX/RX frame
534 #define AN_SNAP_K1 0xaa /* assigned global SAP for SNAP */
535 #define AN_SNAP_K2 0x00
536 #define AN_SNAP_CONTROL 0x03 /* unnumbered information format */
537 #define AN_SNAP_WORD0 (AN_SNAP_K1 | (AN_SNAP_K1 << 8))
538 #define AN_SNAP_WORD1 (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8))
539 #define AN_SNAPHDR_LEN 0x6