2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.8 2004/03/14 15:36:53 joerg Exp $
35 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
39 * VIA Rhine fast ethernet PCI NIC driver
41 * Supports various network adapters based on the VIA Rhine
42 * and Rhine II PCI controllers, including the D-Link DFE530TX.
43 * Datasheets are available at http://www.via.com.tw.
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The VIA Rhine controllers are similar in some respects to the
52 * the DEC tulip chips, except less complicated. The controller
53 * uses an MII bus and an external physical layer interface. The
54 * receiver has a one entry perfect filter and a 64-bit hash table
55 * multicast filter. Transmit and receive descriptors are similar
58 * The Rhine has a serious flaw in its transmit DMA mechanism:
59 * transmit buffers must be longword aligned. Unfortunately,
60 * FreeBSD doesn't guarantee that mbufs will be filled in starting
61 * at longword boundaries, so we have to do a buffer copy before
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/sockio.h>
69 #include <sys/malloc.h>
70 #include <sys/kernel.h>
71 #include <sys/socket.h>
74 #include <net/if_arp.h>
75 #include <net/ethernet.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
81 #include <vm/vm.h> /* for vtophys */
82 #include <vm/pmap.h> /* for vtophys */
83 #include <machine/clock.h> /* for DELAY */
84 #include <machine/bus_pio.h>
85 #include <machine/bus_memio.h>
86 #include <machine/bus.h>
87 #include <machine/resource.h>
91 #include "../mii_layer/mii.h"
92 #include "../mii_layer/miivar.h"
94 #include <bus/pci/pcireg.h>
95 #include <bus/pci/pcivar.h>
101 /* "controller miibus0" required. See GENERIC if you get errors here. */
102 #include "miibus_if.h"
107 * Various supported device vendors/types and their names.
109 static struct vr_type vr_devs[] = {
110 { VIA_VENDORID, VIA_DEVICEID_RHINE,
111 "VIA VT3043 Rhine I 10/100BaseTX" },
112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
113 "VIA VT86C100A Rhine II 10/100BaseTX" },
114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
115 "VIA VT6102 Rhine II 10/100BaseTX" },
116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
117 "VIA VT6105 Rhine III 10/100BaseTX" },
118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
119 "VIA VT6105M Rhine III 10/100BaseTX" },
120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
121 "Delta Electronics Rhine II 10/100BaseTX" },
122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
123 "Addtron Technology Rhine II 10/100BaseTX" },
127 static int vr_probe (device_t);
128 static int vr_attach (device_t);
129 static int vr_detach (device_t);
131 static int vr_newbuf (struct vr_softc *,
132 struct vr_chain_onefrag *,
134 static int vr_encap (struct vr_softc *, struct vr_chain *,
137 static void vr_rxeof (struct vr_softc *);
138 static void vr_rxeoc (struct vr_softc *);
139 static void vr_txeof (struct vr_softc *);
140 static void vr_txeoc (struct vr_softc *);
141 static void vr_tick (void *);
142 static void vr_intr (void *);
143 static void vr_start (struct ifnet *);
144 static int vr_ioctl (struct ifnet *, u_long, caddr_t);
145 static void vr_init (void *);
146 static void vr_stop (struct vr_softc *);
147 static void vr_watchdog (struct ifnet *);
148 static void vr_shutdown (device_t);
149 static int vr_ifmedia_upd (struct ifnet *);
150 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *);
153 static void vr_mii_sync (struct vr_softc *);
154 static void vr_mii_send (struct vr_softc *, u_int32_t, int);
156 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *);
157 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *);
158 static int vr_miibus_readreg (device_t, int, int);
159 static int vr_miibus_writereg (device_t, int, int, int);
160 static void vr_miibus_statchg (device_t);
162 static void vr_setcfg (struct vr_softc *, int);
163 static u_int8_t vr_calchash (u_int8_t *);
164 static void vr_setmulti (struct vr_softc *);
165 static void vr_reset (struct vr_softc *);
166 static int vr_list_rx_init (struct vr_softc *);
167 static int vr_list_tx_init (struct vr_softc *);
170 #define VR_RES SYS_RES_IOPORT
171 #define VR_RID VR_PCI_LOIO
173 #define VR_RES SYS_RES_MEMORY
174 #define VR_RID VR_PCI_LOMEM
177 static device_method_t vr_methods[] = {
178 /* Device interface */
179 DEVMETHOD(device_probe, vr_probe),
180 DEVMETHOD(device_attach, vr_attach),
181 DEVMETHOD(device_detach, vr_detach),
182 DEVMETHOD(device_shutdown, vr_shutdown),
185 DEVMETHOD(bus_print_child, bus_generic_print_child),
186 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
189 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
190 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
191 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
196 static driver_t vr_driver = {
199 sizeof(struct vr_softc)
202 static devclass_t vr_devclass;
204 DECLARE_DUMMY_MODULE(if_vr);
205 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0);
206 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
208 #define VR_SETBIT(sc, reg, x) \
209 CSR_WRITE_1(sc, reg, \
210 CSR_READ_1(sc, reg) | x)
212 #define VR_CLRBIT(sc, reg, x) \
213 CSR_WRITE_1(sc, reg, \
214 CSR_READ_1(sc, reg) & ~x)
216 #define VR_SETBIT16(sc, reg, x) \
217 CSR_WRITE_2(sc, reg, \
218 CSR_READ_2(sc, reg) | x)
220 #define VR_CLRBIT16(sc, reg, x) \
221 CSR_WRITE_2(sc, reg, \
222 CSR_READ_2(sc, reg) & ~x)
224 #define VR_SETBIT32(sc, reg, x) \
225 CSR_WRITE_4(sc, reg, \
226 CSR_READ_4(sc, reg) | x)
228 #define VR_CLRBIT32(sc, reg, x) \
229 CSR_WRITE_4(sc, reg, \
230 CSR_READ_4(sc, reg) & ~x)
233 CSR_WRITE_1(sc, VR_MIICMD, \
234 CSR_READ_1(sc, VR_MIICMD) | x)
237 CSR_WRITE_1(sc, VR_MIICMD, \
238 CSR_READ_1(sc, VR_MIICMD) & ~x)
242 * Sync the PHYs by setting data bit and strobing the clock 32 times.
244 static void vr_mii_sync(sc)
249 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
251 for (i = 0; i < 32; i++) {
252 SIO_SET(VR_MIICMD_CLK);
254 SIO_CLR(VR_MIICMD_CLK);
262 * Clock a series of bits through the MII.
264 static void vr_mii_send(sc, bits, cnt)
271 SIO_CLR(VR_MIICMD_CLK);
273 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
275 SIO_SET(VR_MIICMD_DATAIN);
277 SIO_CLR(VR_MIICMD_DATAIN);
280 SIO_CLR(VR_MIICMD_CLK);
282 SIO_SET(VR_MIICMD_CLK);
288 * Read an PHY register through the MII.
290 static int vr_mii_readreg(sc, frame)
292 struct vr_mii_frame *frame;
301 * Set up frame for RX.
303 frame->mii_stdelim = VR_MII_STARTDELIM;
304 frame->mii_opcode = VR_MII_READOP;
305 frame->mii_turnaround = 0;
308 CSR_WRITE_1(sc, VR_MIICMD, 0);
309 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
314 SIO_SET(VR_MIICMD_DIR);
319 * Send command/address info.
321 vr_mii_send(sc, frame->mii_stdelim, 2);
322 vr_mii_send(sc, frame->mii_opcode, 2);
323 vr_mii_send(sc, frame->mii_phyaddr, 5);
324 vr_mii_send(sc, frame->mii_regaddr, 5);
327 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
329 SIO_SET(VR_MIICMD_CLK);
333 SIO_CLR(VR_MIICMD_DIR);
336 SIO_CLR(VR_MIICMD_CLK);
338 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
339 SIO_SET(VR_MIICMD_CLK);
343 * Now try reading data bits. If the ack failed, we still
344 * need to clock through 16 cycles to keep the PHY(s) in sync.
347 for(i = 0; i < 16; i++) {
348 SIO_CLR(VR_MIICMD_CLK);
350 SIO_SET(VR_MIICMD_CLK);
356 for (i = 0x8000; i; i >>= 1) {
357 SIO_CLR(VR_MIICMD_CLK);
360 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
361 frame->mii_data |= i;
364 SIO_SET(VR_MIICMD_CLK);
370 SIO_CLR(VR_MIICMD_CLK);
372 SIO_SET(VR_MIICMD_CLK);
387 /* Set the PHY-adress */
388 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
391 /* Set the register-adress */
392 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
393 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
395 for (i = 0; i < 10000; i++) {
396 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
401 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
411 * Write to a PHY register through the MII.
413 static int vr_mii_writereg(sc, frame)
415 struct vr_mii_frame *frame;
423 CSR_WRITE_1(sc, VR_MIICMD, 0);
424 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
427 * Set up frame for TX.
430 frame->mii_stdelim = VR_MII_STARTDELIM;
431 frame->mii_opcode = VR_MII_WRITEOP;
432 frame->mii_turnaround = VR_MII_TURNAROUND;
435 * Turn on data output.
437 SIO_SET(VR_MIICMD_DIR);
441 vr_mii_send(sc, frame->mii_stdelim, 2);
442 vr_mii_send(sc, frame->mii_opcode, 2);
443 vr_mii_send(sc, frame->mii_phyaddr, 5);
444 vr_mii_send(sc, frame->mii_regaddr, 5);
445 vr_mii_send(sc, frame->mii_turnaround, 2);
446 vr_mii_send(sc, frame->mii_data, 16);
449 SIO_SET(VR_MIICMD_CLK);
451 SIO_CLR(VR_MIICMD_CLK);
457 SIO_CLR(VR_MIICMD_DIR);
469 /* Set the PHY-adress */
470 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
473 /* Set the register-adress and data to write */
474 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
475 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
477 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
479 for (i = 0; i < 10000; i++) {
480 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
491 static int vr_miibus_readreg(dev, phy, reg)
496 struct vr_mii_frame frame;
498 sc = device_get_softc(dev);
500 switch (sc->vr_revid) {
501 case REV_ID_VT6102_APOLLO:
508 bzero((char *)&frame, sizeof(frame));
510 frame.mii_phyaddr = phy;
511 frame.mii_regaddr = reg;
512 vr_mii_readreg(sc, &frame);
514 return(frame.mii_data);
517 static int vr_miibus_writereg(dev, phy, reg, data)
519 u_int16_t phy, reg, data;
522 struct vr_mii_frame frame;
524 sc = device_get_softc(dev);
526 switch (sc->vr_revid) {
527 case REV_ID_VT6102_APOLLO:
534 bzero((char *)&frame, sizeof(frame));
536 frame.mii_phyaddr = phy;
537 frame.mii_regaddr = reg;
538 frame.mii_data = data;
540 vr_mii_writereg(sc, &frame);
545 static void vr_miibus_statchg(dev)
549 struct mii_data *mii;
551 sc = device_get_softc(dev);
552 mii = device_get_softc(sc->vr_miibus);
553 vr_setcfg(sc, mii->mii_media_active);
559 * Calculate CRC of a multicast group address, return the lower 6 bits.
561 static u_int8_t vr_calchash(addr)
564 u_int32_t crc, carry;
568 /* Compute CRC for the address value. */
569 crc = 0xFFFFFFFF; /* initial value */
571 for (i = 0; i < 6; i++) {
573 for (j = 0; j < 8; j++) {
574 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
578 crc = (crc ^ 0x04c11db6) | carry;
582 /* return the filter bit position */
583 return((crc >> 26) & 0x0000003F);
587 * Program the 64-bit multicast hash filter.
589 static void vr_setmulti(sc)
594 u_int32_t hashes[2] = { 0, 0 };
595 struct ifmultiaddr *ifma;
599 ifp = &sc->arpcom.ac_if;
601 rxfilt = CSR_READ_1(sc, VR_RXCFG);
603 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
604 rxfilt |= VR_RXCFG_RX_MULTI;
605 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
606 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
607 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
611 /* first, zot all the existing hash bits */
612 CSR_WRITE_4(sc, VR_MAR0, 0);
613 CSR_WRITE_4(sc, VR_MAR1, 0);
615 /* now program new ones */
616 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
617 ifma = ifma->ifma_link.le_next) {
618 if (ifma->ifma_addr->sa_family != AF_LINK)
620 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
622 hashes[0] |= (1 << h);
624 hashes[1] |= (1 << (h - 32));
629 rxfilt |= VR_RXCFG_RX_MULTI;
631 rxfilt &= ~VR_RXCFG_RX_MULTI;
633 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
634 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
635 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
641 * In order to fiddle with the
642 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
643 * first have to put the transmit and/or receive logic in the idle state.
645 static void vr_setcfg(sc, media)
651 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
653 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
656 if ((media & IFM_GMASK) == IFM_FDX)
657 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
659 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
662 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
667 static void vr_reset(sc)
672 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
674 for (i = 0; i < VR_TIMEOUT; i++) {
676 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
679 if (i == VR_TIMEOUT) {
680 if (sc->vr_revid < REV_ID_VT3065_A)
681 printf("vr%d: reset never completed!\n", sc->vr_unit);
683 /* Use newer force reset command */
684 printf("vr%d: Using force reset command.\n", sc->vr_unit);
685 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
689 /* Wait a little while for the chip to get its brains in order. */
696 * Probe for a VIA Rhine chip. Check the PCI vendor and device
697 * IDs against our list and return a device name if we find a match.
699 static int vr_probe(dev)
706 while(t->vr_name != NULL) {
707 if ((pci_get_vendor(dev) == t->vr_vid) &&
708 (pci_get_device(dev) == t->vr_did)) {
709 device_set_desc(dev, t->vr_name);
719 * Attach the interface. Allocate softc structures, do ifmedia
720 * setup and ethernet/BPF attach.
722 static int vr_attach(dev)
726 u_char eaddr[ETHER_ADDR_LEN];
730 int unit, error = 0, rid;
734 sc = device_get_softc(dev);
735 unit = device_get_unit(dev);
736 bzero(sc, sizeof(struct vr_softc *));
739 * Handle power management nonsense.
742 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF;
743 if (command == 0x01) {
745 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4);
746 if (command & VR_PSTATE_MASK) {
747 u_int32_t iobase, membase, irq;
749 /* Save important PCI config data. */
750 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
751 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
752 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
754 /* Reset the power state. */
755 printf("vr%d: chip is in D%d power mode "
756 "-- setting to D0\n", unit, command & VR_PSTATE_MASK);
757 command &= 0xFFFFFFFC;
758 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4);
760 /* Restore PCI config data. */
761 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
762 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
763 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
768 * Map control/status registers.
770 command = pci_read_config(dev, PCIR_COMMAND, 4);
771 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
772 pci_write_config(dev, PCIR_COMMAND, command, 4);
773 command = pci_read_config(dev, PCIR_COMMAND, 4);
774 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF;
777 if (!(command & PCIM_CMD_PORTEN)) {
778 printf("vr%d: failed to enable I/O ports!\n", unit);
783 if (!(command & PCIM_CMD_MEMEN)) {
784 printf("vr%d: failed to enable memory mapping!\n", unit);
790 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid,
791 0, ~0, 1, RF_ACTIVE);
793 if (sc->vr_res == NULL) {
794 printf("vr%d: couldn't map ports/memory\n", unit);
799 sc->vr_btag = rman_get_bustag(sc->vr_res);
800 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
802 /* Allocate interrupt */
804 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
805 RF_SHAREABLE | RF_ACTIVE);
807 if (sc->vr_irq == NULL) {
808 printf("vr%d: couldn't map interrupt\n", unit);
809 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
814 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET,
815 vr_intr, sc, &sc->vr_intrhand);
818 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
819 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
820 printf("vr%d: couldn't set up irq\n", unit);
825 * Windows may put the chip in suspend mode when it
826 * shuts down. Be sure to kick it in the head to wake it
829 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
831 /* Reset the adapter. */
835 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
836 * initialization and disable AUTOPOLL.
838 pci_write_config(dev, VR_PCI_MODE,
839 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4);
840 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
843 * Get station address. The way the Rhine chips work,
844 * you're not allowed to directly access the EEPROM once
845 * they've been programmed a special way. Consequently,
846 * we need to read the node address from the PAR0 and PAR1
849 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
851 for (i = 0; i < ETHER_ADDR_LEN; i++)
852 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
855 * A Rhine chip was detected. Inform the world.
857 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":");
861 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
862 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
864 if (sc->vr_ldata == NULL) {
865 printf("vr%d: no memory for list buffers!\n", unit);
866 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
867 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
868 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
873 bzero(sc->vr_ldata, sizeof(struct vr_list_data));
875 ifp = &sc->arpcom.ac_if;
877 if_initname(ifp, "vr", unit);
878 ifp->if_mtu = ETHERMTU;
879 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
880 ifp->if_ioctl = vr_ioctl;
881 ifp->if_output = ether_output;
882 ifp->if_start = vr_start;
883 ifp->if_watchdog = vr_watchdog;
884 ifp->if_init = vr_init;
885 ifp->if_baudrate = 10000000;
886 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1;
891 if (mii_phy_probe(dev, &sc->vr_miibus,
892 vr_ifmedia_upd, vr_ifmedia_sts)) {
893 printf("vr%d: MII without any phy!\n", sc->vr_unit);
894 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
895 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
896 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
897 contigfree(sc->vr_ldata,
898 sizeof(struct vr_list_data), M_DEVBUF);
903 callout_handle_init(&sc->vr_stat_ch);
906 * Call MI attach routine.
908 ether_ifattach(ifp, eaddr);
915 static int vr_detach(dev)
924 sc = device_get_softc(dev);
925 ifp = &sc->arpcom.ac_if;
930 bus_generic_detach(dev);
931 device_delete_child(dev, sc->vr_miibus);
933 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
934 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
935 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
937 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
945 * Initialize the transmit descriptors.
947 static int vr_list_tx_init(sc)
950 struct vr_chain_data *cd;
951 struct vr_list_data *ld;
956 for (i = 0; i < VR_TX_LIST_CNT; i++) {
957 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
958 if (i == (VR_TX_LIST_CNT - 1))
959 cd->vr_tx_chain[i].vr_nextdesc =
962 cd->vr_tx_chain[i].vr_nextdesc =
963 &cd->vr_tx_chain[i + 1];
966 cd->vr_tx_free = &cd->vr_tx_chain[0];
967 cd->vr_tx_tail = cd->vr_tx_head = NULL;
974 * Initialize the RX descriptors and allocate mbufs for them. Note that
975 * we arrange the descriptors in a closed ring, so that the last descriptor
976 * points back to the first.
978 static int vr_list_rx_init(sc)
981 struct vr_chain_data *cd;
982 struct vr_list_data *ld;
988 for (i = 0; i < VR_RX_LIST_CNT; i++) {
989 cd->vr_rx_chain[i].vr_ptr =
990 (struct vr_desc *)&ld->vr_rx_list[i];
991 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
993 if (i == (VR_RX_LIST_CNT - 1)) {
994 cd->vr_rx_chain[i].vr_nextdesc =
996 ld->vr_rx_list[i].vr_next =
997 vtophys(&ld->vr_rx_list[0]);
999 cd->vr_rx_chain[i].vr_nextdesc =
1000 &cd->vr_rx_chain[i + 1];
1001 ld->vr_rx_list[i].vr_next =
1002 vtophys(&ld->vr_rx_list[i + 1]);
1006 cd->vr_rx_head = &cd->vr_rx_chain[0];
1012 * Initialize an RX descriptor and attach an MBUF cluster.
1013 * Note: the length fields are only 11 bits wide, which means the
1014 * largest size we can specify is 2047. This is important because
1015 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
1016 * overflow the field and make a mess.
1018 static int vr_newbuf(sc, c, m)
1019 struct vr_softc *sc;
1020 struct vr_chain_onefrag *c;
1023 struct mbuf *m_new = NULL;
1026 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1030 MCLGET(m_new, M_DONTWAIT);
1031 if (!(m_new->m_flags & M_EXT)) {
1035 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1038 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1039 m_new->m_data = m_new->m_ext.ext_buf;
1042 m_adj(m_new, sizeof(u_int64_t));
1045 c->vr_ptr->vr_status = VR_RXSTAT;
1046 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
1047 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
1053 * A frame has been uploaded: pass the resulting mbuf chain up to
1054 * the higher level protocols.
1056 static void vr_rxeof(sc)
1057 struct vr_softc *sc;
1059 struct ether_header *eh;
1062 struct vr_chain_onefrag *cur_rx;
1066 ifp = &sc->arpcom.ac_if;
1068 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
1070 struct mbuf *m0 = NULL;
1072 cur_rx = sc->vr_cdata.vr_rx_head;
1073 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
1074 m = cur_rx->vr_mbuf;
1077 * If an error occurs, update stats, clear the
1078 * status word and leave the mbuf cluster in place:
1079 * it should simply get re-used next time this descriptor
1080 * comes up in the ring.
1082 if (rxstat & VR_RXSTAT_RXERR) {
1084 printf("vr%d: rx error (%02x):",
1085 sc->vr_unit, rxstat & 0x000000ff);
1086 if (rxstat & VR_RXSTAT_CRCERR)
1087 printf(" crc error");
1088 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1089 printf(" frame alignment error\n");
1090 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1091 printf(" FIFO overflow");
1092 if (rxstat & VR_RXSTAT_GIANT)
1093 printf(" received giant packet");
1094 if (rxstat & VR_RXSTAT_RUNT)
1095 printf(" received runt packet");
1096 if (rxstat & VR_RXSTAT_BUSERR)
1097 printf(" system bus error");
1098 if (rxstat & VR_RXSTAT_BUFFERR)
1099 printf("rx buffer error");
1101 vr_newbuf(sc, cur_rx, m);
1105 /* No errors; receive the packet. */
1106 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
1109 * XXX The VIA Rhine chip includes the CRC with every
1110 * received frame, and there's no way to turn this
1111 * behavior off (at least, I can't find anything in
1112 * the manual that explains how to do it) so we have
1113 * to trim off the CRC manually.
1115 total_len -= ETHER_CRC_LEN;
1117 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1118 total_len + ETHER_ALIGN, 0, ifp, NULL);
1119 vr_newbuf(sc, cur_rx, m);
1124 m_adj(m0, ETHER_ALIGN);
1128 eh = mtod(m, struct ether_header *);
1130 /* Remove header from mbuf and pass it on. */
1131 m_adj(m, sizeof(struct ether_header));
1132 ether_input(ifp, eh, m);
1139 struct vr_softc *sc;
1144 ifp = &sc->arpcom.ac_if;
1148 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1152 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1154 ; /* Wait for receiver to stop */
1157 printf("vr%d: rx shutdown error!\n", sc->vr_unit);
1158 sc->vr_flags |= VR_F_RESTART;
1164 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1165 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1166 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1172 * A frame was downloaded to the chip. It's safe for us to clean up
1176 static void vr_txeof(sc)
1177 struct vr_softc *sc;
1179 struct vr_chain *cur_tx;
1182 ifp = &sc->arpcom.ac_if;
1184 /* Reset the timeout timer; if_txeoc will clear it. */
1188 if (sc->vr_cdata.vr_tx_head == NULL)
1192 * Go through our tx list and free mbufs for those
1193 * frames that have been transmitted.
1195 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) {
1199 cur_tx = sc->vr_cdata.vr_tx_head;
1200 txstat = cur_tx->vr_ptr->vr_status;
1202 if ((txstat & VR_TXSTAT_ABRT) ||
1203 (txstat & VR_TXSTAT_UDF)) {
1205 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1207 ; /* Wait for chip to shutdown */
1209 printf("vr%d: tx shutdown timeout\n", sc->vr_unit);
1210 sc->vr_flags |= VR_F_RESTART;
1213 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1214 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr));
1218 if (txstat & VR_TXSTAT_OWN)
1221 if (txstat & VR_TXSTAT_ERRSUM) {
1223 if (txstat & VR_TXSTAT_DEFER)
1224 ifp->if_collisions++;
1225 if (txstat & VR_TXSTAT_LATECOLL)
1226 ifp->if_collisions++;
1229 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3;
1232 if (cur_tx->vr_mbuf != NULL) {
1233 m_freem(cur_tx->vr_mbuf);
1234 cur_tx->vr_mbuf = NULL;
1237 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) {
1238 sc->vr_cdata.vr_tx_head = NULL;
1239 sc->vr_cdata.vr_tx_tail = NULL;
1243 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc;
1250 * TX 'end of channel' interrupt handler.
1252 static void vr_txeoc(sc)
1253 struct vr_softc *sc;
1257 ifp = &sc->arpcom.ac_if;
1259 if (sc->vr_cdata.vr_tx_head == NULL) {
1260 ifp->if_flags &= ~IFF_OACTIVE;
1261 sc->vr_cdata.vr_tx_tail = NULL;
1268 static void vr_tick(xsc)
1271 struct vr_softc *sc;
1272 struct mii_data *mii;
1278 if (sc->vr_flags & VR_F_RESTART) {
1279 printf("vr%d: restarting\n", sc->vr_unit);
1283 sc->vr_flags &= ~VR_F_RESTART;
1286 mii = device_get_softc(sc->vr_miibus);
1289 sc->vr_stat_ch = timeout(vr_tick, sc, hz);
1296 static void vr_intr(arg)
1299 struct vr_softc *sc;
1304 ifp = &sc->arpcom.ac_if;
1306 /* Supress unwanted interrupts. */
1307 if (!(ifp->if_flags & IFF_UP)) {
1312 /* Disable interrupts. */
1313 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1317 status = CSR_READ_2(sc, VR_ISR);
1319 CSR_WRITE_2(sc, VR_ISR, status);
1321 if ((status & VR_INTRS) == 0)
1324 if (status & VR_ISR_RX_OK)
1327 if (status & VR_ISR_RX_DROPPED) {
1328 printf("vr%d: rx packet lost\n", sc->vr_unit);
1332 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1333 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
1334 printf("vr%d: receive error (%04x)",
1335 sc->vr_unit, status);
1336 if (status & VR_ISR_RX_NOBUF)
1337 printf(" no buffers");
1338 if (status & VR_ISR_RX_OFLOW)
1339 printf(" overflow");
1340 if (status & VR_ISR_RX_DROPPED)
1341 printf(" packet lost");
1346 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1352 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1353 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1355 if ((status & VR_ISR_UDFI) ||
1356 (status & VR_ISR_TX_ABRT2) ||
1357 (status & VR_ISR_TX_ABRT)) {
1359 if (sc->vr_cdata.vr_tx_head != NULL) {
1360 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
1361 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
1369 /* Re-enable interrupts. */
1370 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1372 if (ifp->if_snd.ifq_head != NULL) {
1380 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1381 * pointers to the fragment pointers.
1383 static int vr_encap(sc, c, m_head)
1384 struct vr_softc *sc;
1386 struct mbuf *m_head;
1389 struct vr_desc *f = NULL;
1397 * The VIA Rhine wants packet buffers to be longword
1398 * aligned, but very often our mbufs aren't. Rather than
1399 * waste time trying to decide when to copy and when not
1400 * to copy, just do it all the time.
1403 struct mbuf *m_new = NULL;
1405 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1406 if (m_new == NULL) {
1407 printf("vr%d: no memory for tx list\n", sc->vr_unit);
1410 if (m_head->m_pkthdr.len > MHLEN) {
1411 MCLGET(m_new, M_DONTWAIT);
1412 if (!(m_new->m_flags & M_EXT)) {
1414 printf("vr%d: no memory for tx list\n",
1419 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1420 mtod(m_new, caddr_t));
1421 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1425 * The Rhine chip doesn't auto-pad, so we have to make
1426 * sure to pad short frames out to the minimum frame length
1429 if (m_head->m_len < VR_MIN_FRAMELEN) {
1430 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len;
1431 m_new->m_len = m_new->m_pkthdr.len;
1434 f->vr_data = vtophys(mtod(m_new, caddr_t));
1435 f->vr_ctl = total_len = m_new->m_len;
1436 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG;
1441 c->vr_mbuf = m_head;
1442 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT;
1443 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr);
1449 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1450 * to the mbuf data regions directly in the transmit lists. We also save a
1451 * copy of the pointers since the transmit list fragment pointers are
1452 * physical addresses.
1455 static void vr_start(ifp)
1458 struct vr_softc *sc;
1459 struct mbuf *m_head = NULL;
1460 struct vr_chain *cur_tx = NULL, *start_tx;
1464 if (ifp->if_flags & IFF_OACTIVE)
1468 * Check for an available queue slot. If there are none,
1471 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) {
1472 ifp->if_flags |= IFF_OACTIVE;
1476 start_tx = sc->vr_cdata.vr_tx_free;
1478 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) {
1479 IF_DEQUEUE(&ifp->if_snd, m_head);
1483 /* Pick a descriptor off the free list. */
1484 cur_tx = sc->vr_cdata.vr_tx_free;
1485 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc;
1487 /* Pack the data into the descriptor. */
1488 if (vr_encap(sc, cur_tx, m_head)) {
1489 IF_PREPEND(&ifp->if_snd, m_head);
1490 ifp->if_flags |= IFF_OACTIVE;
1495 if (cur_tx != start_tx)
1496 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1499 * If there's a BPF listener, bounce a copy of this frame
1503 bpf_mtap(ifp, cur_tx->vr_mbuf);
1505 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1506 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1510 * If there are no frames queued, bail.
1515 sc->vr_cdata.vr_tx_tail = cur_tx;
1517 if (sc->vr_cdata.vr_tx_head == NULL)
1518 sc->vr_cdata.vr_tx_head = start_tx;
1521 * Set a timeout in case the chip goes out to lunch.
1528 static void vr_init(xsc)
1531 struct vr_softc *sc = xsc;
1532 struct ifnet *ifp = &sc->arpcom.ac_if;
1533 struct mii_data *mii;
1538 mii = device_get_softc(sc->vr_miibus);
1541 * Cancel pending I/O and free all RX/TX buffers.
1547 * Set our station address.
1549 for (i = 0; i < ETHER_ADDR_LEN; i++)
1550 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1553 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1554 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1557 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1558 * so we must set both.
1560 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1561 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1563 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1564 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1566 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1567 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1569 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1570 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1572 /* Init circular RX list. */
1573 if (vr_list_rx_init(sc) == ENOBUFS) {
1574 printf("vr%d: initialization failed: no "
1575 "memory for rx buffers\n", sc->vr_unit);
1582 * Init tx descriptors.
1584 vr_list_tx_init(sc);
1586 /* If we want promiscuous mode, set the allframes bit. */
1587 if (ifp->if_flags & IFF_PROMISC)
1588 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1590 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1592 /* Set capture broadcast bit to capture broadcast frames. */
1593 if (ifp->if_flags & IFF_BROADCAST)
1594 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1596 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1599 * Program the multicast filter, if necessary.
1604 * Load the address of the RX list.
1606 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1608 /* Enable receiver and transmitter. */
1609 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1610 VR_CMD_TX_ON|VR_CMD_RX_ON|
1613 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1616 * Enable interrupts.
1618 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1619 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1623 ifp->if_flags |= IFF_RUNNING;
1624 ifp->if_flags &= ~IFF_OACTIVE;
1628 sc->vr_stat_ch = timeout(vr_tick, sc, hz);
1634 * Set media options.
1636 static int vr_ifmedia_upd(ifp)
1639 struct vr_softc *sc;
1643 if (ifp->if_flags & IFF_UP)
1650 * Report current media status.
1652 static void vr_ifmedia_sts(ifp, ifmr)
1654 struct ifmediareq *ifmr;
1656 struct vr_softc *sc;
1657 struct mii_data *mii;
1660 mii = device_get_softc(sc->vr_miibus);
1662 ifmr->ifm_active = mii->mii_media_active;
1663 ifmr->ifm_status = mii->mii_media_status;
1668 static int vr_ioctl(ifp, command, data)
1673 struct vr_softc *sc = ifp->if_softc;
1674 struct ifreq *ifr = (struct ifreq *) data;
1675 struct mii_data *mii;
1684 error = ether_ioctl(ifp, command, data);
1687 if (ifp->if_flags & IFF_UP) {
1690 if (ifp->if_flags & IFF_RUNNING)
1702 mii = device_get_softc(sc->vr_miibus);
1703 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1715 static void vr_watchdog(ifp)
1718 struct vr_softc *sc;
1723 printf("vr%d: watchdog timeout\n", sc->vr_unit);
1729 if (ifp->if_snd.ifq_head != NULL)
1736 * Stop the adapter and free any mbufs allocated to the
1739 static void vr_stop(sc)
1740 struct vr_softc *sc;
1745 ifp = &sc->arpcom.ac_if;
1748 untimeout(vr_tick, sc, sc->vr_stat_ch);
1750 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1751 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1752 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1753 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1754 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1757 * Free data in the RX lists.
1759 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1760 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1761 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1762 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1765 bzero((char *)&sc->vr_ldata->vr_rx_list,
1766 sizeof(sc->vr_ldata->vr_rx_list));
1769 * Free the TX list buffers.
1771 for (i = 0; i < VR_TX_LIST_CNT; i++) {
1772 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) {
1773 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf);
1774 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL;
1778 bzero((char *)&sc->vr_ldata->vr_tx_list,
1779 sizeof(sc->vr_ldata->vr_tx_list));
1781 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1787 * Stop all chip I/O so that the kernel's probe routines don't
1788 * get confused by errant DMAs when rebooting.
1790 static void vr_shutdown(dev)
1793 struct vr_softc *sc;
1795 sc = device_get_softc(dev);