2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
116 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
118 if (sc->rss_debug >= lvl) \
119 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
121 #else /* !EMX_RSS_DEBUG */
122 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
123 #endif /* EMX_RSS_DEBUG */
125 #define EMX_NAME "Intel(R) PRO/1000 "
127 #define EMX_DEVICE(id) \
128 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
129 #define EMX_DEVICE_NULL { 0, 0, NULL }
131 static const struct emx_device {
136 EMX_DEVICE(82571EB_COPPER),
137 EMX_DEVICE(82571EB_FIBER),
138 EMX_DEVICE(82571EB_SERDES),
139 EMX_DEVICE(82571EB_SERDES_DUAL),
140 EMX_DEVICE(82571EB_SERDES_QUAD),
141 EMX_DEVICE(82571EB_QUAD_COPPER),
142 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
143 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
144 EMX_DEVICE(82571EB_QUAD_FIBER),
145 EMX_DEVICE(82571PT_QUAD_COPPER),
147 EMX_DEVICE(82572EI_COPPER),
148 EMX_DEVICE(82572EI_FIBER),
149 EMX_DEVICE(82572EI_SERDES),
153 EMX_DEVICE(82573E_IAMT),
156 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
157 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
158 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
164 EMX_DEVICE(PCH_LPT_I217_LM),
165 EMX_DEVICE(PCH_LPT_I217_V),
166 EMX_DEVICE(PCH_LPTLP_I218_LM),
167 EMX_DEVICE(PCH_LPTLP_I218_V),
168 EMX_DEVICE(PCH_I218_LM2),
169 EMX_DEVICE(PCH_I218_V2),
170 EMX_DEVICE(PCH_I218_LM3),
171 EMX_DEVICE(PCH_I218_V3),
173 /* required last entry */
177 static int emx_probe(device_t);
178 static int emx_attach(device_t);
179 static int emx_detach(device_t);
180 static int emx_shutdown(device_t);
181 static int emx_suspend(device_t);
182 static int emx_resume(device_t);
184 static void emx_init(void *);
185 static void emx_stop(struct emx_softc *);
186 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
187 static void emx_start(struct ifnet *, struct ifaltq_subque *);
189 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
190 static void emx_npoll_status(struct ifnet *);
191 static void emx_npoll_tx(struct ifnet *, void *, int);
192 static void emx_npoll_rx(struct ifnet *, void *, int);
194 static void emx_watchdog(struct ifaltq_subque *);
195 static void emx_media_status(struct ifnet *, struct ifmediareq *);
196 static int emx_media_change(struct ifnet *);
197 static void emx_timer(void *);
198 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
199 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
200 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
202 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
206 static void emx_intr(void *);
207 static void emx_intr_mask(void *);
208 static void emx_intr_body(struct emx_softc *, boolean_t);
209 static void emx_rxeof(struct emx_rxdata *, int);
210 static void emx_txeof(struct emx_txdata *);
211 static void emx_tx_collect(struct emx_txdata *);
212 static void emx_tx_purge(struct emx_softc *);
213 static void emx_enable_intr(struct emx_softc *);
214 static void emx_disable_intr(struct emx_softc *);
216 static int emx_dma_alloc(struct emx_softc *);
217 static void emx_dma_free(struct emx_softc *);
218 static void emx_init_tx_ring(struct emx_txdata *);
219 static int emx_init_rx_ring(struct emx_rxdata *);
220 static void emx_free_tx_ring(struct emx_txdata *);
221 static void emx_free_rx_ring(struct emx_rxdata *);
222 static int emx_create_tx_ring(struct emx_txdata *);
223 static int emx_create_rx_ring(struct emx_rxdata *);
224 static void emx_destroy_tx_ring(struct emx_txdata *, int);
225 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
226 static int emx_newbuf(struct emx_rxdata *, int, int);
227 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
228 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
229 uint32_t *, uint32_t *);
230 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
231 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
232 uint32_t *, uint32_t *);
233 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
235 static int emx_is_valid_eaddr(const uint8_t *);
236 static int emx_reset(struct emx_softc *);
237 static void emx_setup_ifp(struct emx_softc *);
238 static void emx_init_tx_unit(struct emx_softc *);
239 static void emx_init_rx_unit(struct emx_softc *);
240 static void emx_update_stats(struct emx_softc *);
241 static void emx_set_promisc(struct emx_softc *);
242 static void emx_disable_promisc(struct emx_softc *);
243 static void emx_set_multi(struct emx_softc *);
244 static void emx_update_link_status(struct emx_softc *);
245 static void emx_smartspeed(struct emx_softc *);
246 static void emx_set_itr(struct emx_softc *, uint32_t);
247 static void emx_disable_aspm(struct emx_softc *);
249 static void emx_print_debug_info(struct emx_softc *);
250 static void emx_print_nvm_info(struct emx_softc *);
251 static void emx_print_hw_stats(struct emx_softc *);
253 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
254 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
255 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
256 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
257 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
259 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
260 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
262 static void emx_add_sysctl(struct emx_softc *);
264 static void emx_serialize_skipmain(struct emx_softc *);
265 static void emx_deserialize_skipmain(struct emx_softc *);
267 /* Management and WOL Support */
268 static void emx_get_mgmt(struct emx_softc *);
269 static void emx_rel_mgmt(struct emx_softc *);
270 static void emx_get_hw_control(struct emx_softc *);
271 static void emx_rel_hw_control(struct emx_softc *);
272 static void emx_enable_wol(device_t);
274 static device_method_t emx_methods[] = {
275 /* Device interface */
276 DEVMETHOD(device_probe, emx_probe),
277 DEVMETHOD(device_attach, emx_attach),
278 DEVMETHOD(device_detach, emx_detach),
279 DEVMETHOD(device_shutdown, emx_shutdown),
280 DEVMETHOD(device_suspend, emx_suspend),
281 DEVMETHOD(device_resume, emx_resume),
285 static driver_t emx_driver = {
288 sizeof(struct emx_softc),
291 static devclass_t emx_devclass;
293 DECLARE_DUMMY_MODULE(if_emx);
294 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
295 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
300 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
301 static int emx_rxd = EMX_DEFAULT_RXD;
302 static int emx_txd = EMX_DEFAULT_TXD;
303 static int emx_smart_pwr_down = 0;
304 static int emx_rxr = 0;
305 static int emx_txr = 1;
307 /* Controls whether promiscuous also shows bad packets */
308 static int emx_debug_sbp = 0;
310 static int emx_82573_workaround = 1;
311 static int emx_msi_enable = 1;
313 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
314 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
315 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
316 TUNABLE_INT("hw.emx.txd", &emx_txd);
317 TUNABLE_INT("hw.emx.txr", &emx_txr);
318 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
319 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
320 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
321 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
323 /* Global used in WOL setup with multiport cards */
324 static int emx_global_quad_port_a = 0;
326 /* Set this to one to display debug statistics */
327 static int emx_display_debug_stats = 0;
329 #if !defined(KTR_IF_EMX)
330 #define KTR_IF_EMX KTR_ALL
332 KTR_INFO_MASTER(if_emx);
333 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
334 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
335 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
336 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
337 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
338 #define logif(name) KTR_LOG(if_emx_ ## name)
341 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
343 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
344 /* DD bit must be cleared */
345 rxd->rxd_staterr = 0;
349 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
351 /* Ignore Checksum bit is set */
352 if (staterr & E1000_RXD_STAT_IXSM)
355 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
357 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
359 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
360 E1000_RXD_STAT_TCPCS) {
361 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
363 CSUM_FRAG_NOT_CHECKED;
364 mp->m_pkthdr.csum_data = htons(0xffff);
368 static __inline struct pktinfo *
369 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
370 uint32_t mrq, uint32_t hash, uint32_t staterr)
372 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
373 case EMX_RXDMRQ_IPV4_TCP:
374 pi->pi_netisr = NETISR_IP;
376 pi->pi_l3proto = IPPROTO_TCP;
379 case EMX_RXDMRQ_IPV6_TCP:
380 pi->pi_netisr = NETISR_IPV6;
382 pi->pi_l3proto = IPPROTO_TCP;
385 case EMX_RXDMRQ_IPV4:
386 if (staterr & E1000_RXD_STAT_IXSM)
390 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
391 E1000_RXD_STAT_TCPCS) {
392 pi->pi_netisr = NETISR_IP;
394 pi->pi_l3proto = IPPROTO_UDP;
402 m->m_flags |= M_HASH;
403 m->m_pkthdr.hash = toeplitz_hash(hash);
408 emx_probe(device_t dev)
410 const struct emx_device *d;
413 vid = pci_get_vendor(dev);
414 did = pci_get_device(dev);
416 for (d = emx_devices; d->desc != NULL; ++d) {
417 if (vid == d->vid && did == d->did) {
418 device_set_desc(dev, d->desc);
419 device_set_async_attach(dev, TRUE);
427 emx_attach(device_t dev)
429 struct emx_softc *sc = device_get_softc(dev);
430 int error = 0, i, throttle, msi_enable, tx_ring_max;
432 uint16_t eeprom_data, device_id, apme_mask;
433 driver_intr_t *intr_func;
435 int offset, offset_def;
441 for (i = 0; i < EMX_NRX_RING; ++i) {
442 sc->rx_data[i].sc = sc;
443 sc->rx_data[i].idx = i;
449 for (i = 0; i < EMX_NTX_RING; ++i) {
450 sc->tx_data[i].sc = sc;
451 sc->tx_data[i].idx = i;
455 * Initialize serializers
457 lwkt_serialize_init(&sc->main_serialize);
458 for (i = 0; i < EMX_NTX_RING; ++i)
459 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
460 for (i = 0; i < EMX_NRX_RING; ++i)
461 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
464 * Initialize serializer array
468 KKASSERT(i < EMX_NSERIALIZE);
469 sc->serializes[i++] = &sc->main_serialize;
471 KKASSERT(i < EMX_NSERIALIZE);
472 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
473 KKASSERT(i < EMX_NSERIALIZE);
474 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
476 KKASSERT(i < EMX_NSERIALIZE);
477 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
478 KKASSERT(i < EMX_NSERIALIZE);
479 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
481 KKASSERT(i == EMX_NSERIALIZE);
483 ifmedia_init(&sc->media, IFM_IMASK, emx_media_change, emx_media_status);
484 callout_init_mp(&sc->timer);
486 sc->dev = sc->osdep.dev = dev;
489 * Determine hardware and mac type
491 sc->hw.vendor_id = pci_get_vendor(dev);
492 sc->hw.device_id = pci_get_device(dev);
493 sc->hw.revision_id = pci_get_revid(dev);
494 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
495 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
497 if (e1000_set_mac_type(&sc->hw))
500 /* Enable bus mastering */
501 pci_enable_busmaster(dev);
506 sc->memory_rid = EMX_BAR_MEM;
507 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
508 &sc->memory_rid, RF_ACTIVE);
509 if (sc->memory == NULL) {
510 device_printf(dev, "Unable to allocate bus resource: memory\n");
514 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
515 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
517 /* XXX This is quite goofy, it is not actually used */
518 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
521 * Don't enable MSI-X on 82574, see:
522 * 82574 specification update errata #15
524 * Don't enable MSI on 82571/82572, see:
525 * 82571/82572 specification update errata #63
527 msi_enable = emx_msi_enable;
529 (sc->hw.mac.type == e1000_82571 ||
530 sc->hw.mac.type == e1000_82572))
536 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
537 &sc->intr_rid, &intr_flags);
539 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
542 unshared = device_getenv_int(dev, "irq.unshared", 0);
544 sc->flags |= EMX_FLAG_SHARED_INTR;
546 device_printf(dev, "IRQ shared\n");
548 intr_flags &= ~RF_SHAREABLE;
550 device_printf(dev, "IRQ unshared\n");
554 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
556 if (sc->intr_res == NULL) {
557 device_printf(dev, "Unable to allocate bus resource: "
563 /* Save PCI command register for Shared Code */
564 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
565 sc->hw.back = &sc->osdep;
568 * For I217/I218, we need to map the flash memory and this
569 * must happen after the MAC is identified.
571 if (sc->hw.mac.type == e1000_pch_lpt) {
572 sc->flash_rid = EMX_BAR_FLASH;
574 sc->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
575 &sc->flash_rid, RF_ACTIVE);
576 if (sc->flash == NULL) {
577 device_printf(dev, "Mapping of Flash failed\n");
581 sc->osdep.flash_bus_space_tag = rman_get_bustag(sc->flash);
582 sc->osdep.flash_bus_space_handle =
583 rman_get_bushandle(sc->flash);
586 * This is used in the shared code
587 * XXX this goof is actually not used.
589 sc->hw.flash_address = (uint8_t *)sc->flash;
592 /* Do Shared Code initialization */
593 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
594 device_printf(dev, "Setup of Shared code failed\n");
598 e1000_get_bus_info(&sc->hw);
600 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
601 sc->hw.phy.autoneg_wait_to_complete = FALSE;
602 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
605 * Interrupt throttle rate
607 throttle = device_getenv_int(dev, "int_throttle_ceil",
608 emx_int_throttle_ceil);
610 sc->int_throttle_ceil = 0;
613 throttle = EMX_DEFAULT_ITR;
615 /* Recalculate the tunable value to get the exact frequency. */
616 throttle = 1000000000 / 256 / throttle;
618 /* Upper 16bits of ITR is reserved and should be zero */
619 if (throttle & 0xffff0000)
620 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
622 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
625 e1000_init_script_state_82541(&sc->hw, TRUE);
626 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
629 if (sc->hw.phy.media_type == e1000_media_type_copper) {
630 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
631 sc->hw.phy.disable_polarity_correction = FALSE;
632 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
635 /* Set the frame limits assuming standard ethernet sized frames. */
636 sc->hw.mac.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
638 /* This controls when hardware reports transmit completion status. */
639 sc->hw.mac.report_tx_early = 1;
641 /* Calculate # of RX rings */
642 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
643 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
646 * Calculate # of TX rings
649 * I217/I218 claims to have 2 TX queues
652 * Don't enable multiple TX queues on 82574; it always gives
653 * watchdog timeout on TX queue0, when multiple TCP streams are
654 * received. It was originally suspected that the hardware TX
655 * checksum offloading caused this watchdog timeout, since only
656 * TCP ACKs are sent during TCP receiving tests. However, even
657 * if the hardware TX checksum offloading is disable, TX queue0
658 * still will give watchdog.
661 if (sc->hw.mac.type == e1000_82571 ||
662 sc->hw.mac.type == e1000_82572 ||
663 sc->hw.mac.type == e1000_80003es2lan ||
664 sc->hw.mac.type == e1000_pch_lpt ||
665 sc->hw.mac.type == e1000_82574)
666 tx_ring_max = EMX_NTX_RING;
667 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr);
668 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max);
670 /* Allocate RX/TX rings' busdma(9) stuffs */
671 error = emx_dma_alloc(sc);
675 /* Allocate multicast array memory. */
676 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
679 /* Indicate SOL/IDER usage */
680 if (e1000_check_reset_block(&sc->hw)) {
682 "PHY reset is blocked due to SOL/IDER session.\n");
685 /* Disable EEE on I217/I218 */
686 sc->hw.dev_spec.ich8lan.eee_disable = 1;
689 * Start from a known state, this is important in reading the
690 * nvm and mac from that.
692 e1000_reset_hw(&sc->hw);
694 /* Make sure we have a good EEPROM before we read from it */
695 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
697 * Some PCI-E parts fail the first check due to
698 * the link being in sleep state, call it again,
699 * if it fails a second time its a real issue.
701 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
703 "The EEPROM Checksum Is Not Valid\n");
709 /* Copy the permanent MAC address out of the EEPROM */
710 if (e1000_read_mac_addr(&sc->hw) < 0) {
711 device_printf(dev, "EEPROM read error while reading MAC"
716 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
717 device_printf(dev, "Invalid MAC address\n");
722 /* Disable ULP support */
723 e1000_disable_ulp_lpt_lp(&sc->hw, TRUE);
725 /* Determine if we have to control management hardware */
726 if (e1000_enable_mng_pass_thru(&sc->hw))
727 sc->flags |= EMX_FLAG_HAS_MGMT;
732 apme_mask = EMX_EEPROM_APME;
734 switch (sc->hw.mac.type) {
736 sc->flags |= EMX_FLAG_HAS_AMT;
741 case e1000_80003es2lan:
742 if (sc->hw.bus.func == 1) {
743 e1000_read_nvm(&sc->hw,
744 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
746 e1000_read_nvm(&sc->hw,
747 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
752 e1000_read_nvm(&sc->hw,
753 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
756 if (eeprom_data & apme_mask)
757 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
760 * We have the eeprom settings, now apply the special cases
761 * where the eeprom may be wrong or the board won't support
762 * wake on lan on a particular port
764 device_id = pci_get_device(dev);
766 case E1000_DEV_ID_82571EB_FIBER:
768 * Wake events only supported on port A for dual fiber
769 * regardless of eeprom setting
771 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
776 case E1000_DEV_ID_82571EB_QUAD_COPPER:
777 case E1000_DEV_ID_82571EB_QUAD_FIBER:
778 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
779 /* if quad port sc, disable WoL on all but port A */
780 if (emx_global_quad_port_a != 0)
782 /* Reset for multiple quad port adapters */
783 if (++emx_global_quad_port_a == 4)
784 emx_global_quad_port_a = 0;
788 /* XXX disable wol */
793 * NPOLLING RX CPU offset
795 if (sc->rx_ring_cnt == ncpus2) {
798 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
799 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
800 if (offset >= ncpus2 ||
801 offset % sc->rx_ring_cnt != 0) {
802 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
807 sc->rx_npoll_off = offset;
810 * NPOLLING TX CPU offset
812 if (sc->tx_ring_cnt == ncpus2) {
815 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
816 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
817 if (offset >= ncpus2 ||
818 offset % sc->tx_ring_cnt != 0) {
819 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
824 sc->tx_npoll_off = offset;
826 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
828 /* Setup OS specific network interface */
831 /* Add sysctl tree, must after em_setup_ifp() */
834 /* Reset the hardware */
835 error = emx_reset(sc);
838 * Some 82573 parts fail the first reset, call it again,
839 * if it fails a second time its a real issue.
841 error = emx_reset(sc);
843 device_printf(dev, "Unable to reset the hardware\n");
844 ether_ifdetach(&sc->arpcom.ac_if);
849 /* Initialize statistics */
850 emx_update_stats(sc);
852 sc->hw.mac.get_link_status = 1;
853 emx_update_link_status(sc);
855 /* Non-AMT based hardware can now take control from firmware */
856 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
858 emx_get_hw_control(sc);
861 * Missing Interrupt Following ICR read:
863 * 82571/82572 specification update errata #76
864 * 82573 specification update errata #31
865 * 82574 specification update errata #12
867 intr_func = emx_intr;
868 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
869 (sc->hw.mac.type == e1000_82571 ||
870 sc->hw.mac.type == e1000_82572 ||
871 sc->hw.mac.type == e1000_82573 ||
872 sc->hw.mac.type == e1000_82574))
873 intr_func = emx_intr_mask;
875 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
876 &sc->intr_tag, &sc->main_serialize);
878 device_printf(dev, "Failed to register interrupt handler");
879 ether_ifdetach(&sc->arpcom.ac_if);
889 emx_detach(device_t dev)
891 struct emx_softc *sc = device_get_softc(dev);
893 if (device_is_attached(dev)) {
894 struct ifnet *ifp = &sc->arpcom.ac_if;
896 ifnet_serialize_all(ifp);
900 e1000_phy_hw_reset(&sc->hw);
903 emx_rel_hw_control(sc);
906 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
907 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
911 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
913 ifnet_deserialize_all(ifp);
916 } else if (sc->memory != NULL) {
917 emx_rel_hw_control(sc);
920 ifmedia_removeall(&sc->media);
921 bus_generic_detach(dev);
923 if (sc->intr_res != NULL) {
924 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
928 if (sc->intr_type == PCI_INTR_TYPE_MSI)
929 pci_release_msi(dev);
931 if (sc->memory != NULL) {
932 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
936 if (sc->flash != NULL) {
937 bus_release_resource(dev, SYS_RES_MEMORY, sc->flash_rid,
944 kfree(sc->mta, M_DEVBUF);
950 emx_shutdown(device_t dev)
952 return emx_suspend(dev);
956 emx_suspend(device_t dev)
958 struct emx_softc *sc = device_get_softc(dev);
959 struct ifnet *ifp = &sc->arpcom.ac_if;
961 ifnet_serialize_all(ifp);
966 emx_rel_hw_control(sc);
969 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
970 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
974 ifnet_deserialize_all(ifp);
976 return bus_generic_suspend(dev);
980 emx_resume(device_t dev)
982 struct emx_softc *sc = device_get_softc(dev);
983 struct ifnet *ifp = &sc->arpcom.ac_if;
986 ifnet_serialize_all(ifp);
990 for (i = 0; i < sc->tx_ring_inuse; ++i)
991 ifsq_devstart_sched(sc->tx_data[i].ifsq);
993 ifnet_deserialize_all(ifp);
995 return bus_generic_resume(dev);
999 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1001 struct emx_softc *sc = ifp->if_softc;
1002 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1003 struct mbuf *m_head;
1004 int idx = -1, nsegs = 0;
1006 KKASSERT(tdata->ifsq == ifsq);
1007 ASSERT_SERIALIZED(&tdata->tx_serialize);
1009 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1012 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
1017 while (!ifsq_is_empty(ifsq)) {
1018 /* Now do we at least have a minimal? */
1019 if (EMX_IS_OACTIVE(tdata)) {
1020 emx_tx_collect(tdata);
1021 if (EMX_IS_OACTIVE(tdata)) {
1022 ifsq_set_oactive(ifsq);
1028 m_head = ifsq_dequeue(ifsq);
1032 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
1033 IFNET_STAT_INC(ifp, oerrors, 1);
1034 emx_tx_collect(tdata);
1038 if (nsegs >= tdata->tx_wreg_nsegs) {
1039 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1044 /* Send a copy of the frame to the BPF listener */
1045 ETHER_BPF_MTAP(ifp, m_head);
1047 /* Set timeout in case hardware has problems transmitting. */
1048 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1051 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1055 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1057 struct emx_softc *sc = ifp->if_softc;
1058 struct ifreq *ifr = (struct ifreq *)data;
1059 uint16_t eeprom_data = 0;
1060 int max_frame_size, mask, reinit;
1063 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1067 switch (sc->hw.mac.type) {
1070 * 82573 only supports jumbo frames
1071 * if ASPM is disabled.
1073 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1075 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1076 max_frame_size = ETHER_MAX_LEN;
1081 /* Limit Jumbo Frame size */
1086 case e1000_80003es2lan:
1087 max_frame_size = 9234;
1091 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1094 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1100 ifp->if_mtu = ifr->ifr_mtu;
1101 sc->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1104 if (ifp->if_flags & IFF_RUNNING)
1109 if (ifp->if_flags & IFF_UP) {
1110 if ((ifp->if_flags & IFF_RUNNING)) {
1111 if ((ifp->if_flags ^ sc->if_flags) &
1112 (IFF_PROMISC | IFF_ALLMULTI)) {
1113 emx_disable_promisc(sc);
1114 emx_set_promisc(sc);
1119 } else if (ifp->if_flags & IFF_RUNNING) {
1122 sc->if_flags = ifp->if_flags;
1127 if (ifp->if_flags & IFF_RUNNING) {
1128 emx_disable_intr(sc);
1130 #ifdef IFPOLL_ENABLE
1131 if (!(ifp->if_flags & IFF_NPOLLING))
1133 emx_enable_intr(sc);
1138 /* Check SOL/IDER usage */
1139 if (e1000_check_reset_block(&sc->hw)) {
1140 device_printf(sc->dev, "Media change is"
1141 " blocked due to SOL/IDER session.\n");
1147 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1152 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1153 if (mask & IFCAP_RXCSUM) {
1154 ifp->if_capenable ^= IFCAP_RXCSUM;
1157 if (mask & IFCAP_VLAN_HWTAGGING) {
1158 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1161 if (mask & IFCAP_TXCSUM) {
1162 ifp->if_capenable ^= IFCAP_TXCSUM;
1163 if (ifp->if_capenable & IFCAP_TXCSUM)
1164 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1166 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1168 if (mask & IFCAP_TSO) {
1169 ifp->if_capenable ^= IFCAP_TSO;
1170 if (ifp->if_capenable & IFCAP_TSO)
1171 ifp->if_hwassist |= CSUM_TSO;
1173 ifp->if_hwassist &= ~CSUM_TSO;
1175 if (mask & IFCAP_RSS)
1176 ifp->if_capenable ^= IFCAP_RSS;
1177 if (reinit && (ifp->if_flags & IFF_RUNNING))
1182 error = ether_ioctl(ifp, command, data);
1189 emx_watchdog(struct ifaltq_subque *ifsq)
1191 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1192 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1193 struct emx_softc *sc = ifp->if_softc;
1196 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1199 * The timer is set to 5 every time start queues a packet.
1200 * Then txeof keeps resetting it as long as it cleans at
1201 * least one descriptor.
1202 * Finally, anytime all descriptors are clean the timer is
1206 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1207 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1209 * If we reach here, all TX jobs are completed and
1210 * the TX engine should have been idled for some time.
1211 * We don't need to call ifsq_devstart_sched() here.
1213 ifsq_clr_oactive(ifsq);
1214 tdata->tx_watchdog.wd_timer = 0;
1219 * If we are in this routine because of pause frames, then
1220 * don't reset the hardware.
1222 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1223 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1227 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1229 IFNET_STAT_INC(ifp, oerrors, 1);
1232 for (i = 0; i < sc->tx_ring_inuse; ++i)
1233 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1239 struct emx_softc *sc = xsc;
1240 struct ifnet *ifp = &sc->arpcom.ac_if;
1241 device_t dev = sc->dev;
1245 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1249 /* Get the latest mac address, User can use a LAA */
1250 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1252 /* Put the address into the Receive Address Array */
1253 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1256 * With the 82571 sc, RAR[0] may be overwritten
1257 * when the other port is reset, we make a duplicate
1258 * in RAR[14] for that eventuality, this assures
1259 * the interface continues to function.
1261 if (sc->hw.mac.type == e1000_82571) {
1262 e1000_set_laa_state_82571(&sc->hw, TRUE);
1263 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1264 E1000_RAR_ENTRIES - 1);
1267 /* Initialize the hardware */
1268 if (emx_reset(sc)) {
1269 device_printf(dev, "Unable to reset the hardware\n");
1270 /* XXX emx_stop()? */
1273 emx_update_link_status(sc);
1275 /* Setup VLAN support, basic and offload if available */
1276 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1278 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1281 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1282 ctrl |= E1000_CTRL_VME;
1283 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1286 /* Configure for OS presence */
1290 #ifdef IFPOLL_ENABLE
1291 if (ifp->if_flags & IFF_NPOLLING)
1294 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1295 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
1297 /* Prepare transmit descriptors and buffers */
1298 for (i = 0; i < sc->tx_ring_inuse; ++i)
1299 emx_init_tx_ring(&sc->tx_data[i]);
1300 emx_init_tx_unit(sc);
1302 /* Setup Multicast table */
1305 /* Prepare receive descriptors and buffers */
1306 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1307 if (emx_init_rx_ring(&sc->rx_data[i])) {
1309 "Could not setup receive structures\n");
1314 emx_init_rx_unit(sc);
1316 /* Don't lose promiscuous settings */
1317 emx_set_promisc(sc);
1319 ifp->if_flags |= IFF_RUNNING;
1320 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1321 ifsq_clr_oactive(sc->tx_data[i].ifsq);
1322 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog);
1325 callout_reset(&sc->timer, hz, emx_timer, sc);
1326 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1328 /* MSI/X configuration for 82574 */
1329 if (sc->hw.mac.type == e1000_82574) {
1332 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1333 tmp |= E1000_CTRL_EXT_PBA_CLR;
1334 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1337 * Set the IVAR - interrupt vector routing.
1338 * Each nibble represents a vector, high bit
1339 * is enable, other 3 bits are the MSIX table
1340 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1341 * Link (other) to 2, hence the magic number.
1343 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1347 * Only enable interrupts if we are not polling, make sure
1348 * they are off otherwise.
1351 emx_disable_intr(sc);
1353 emx_enable_intr(sc);
1355 /* AMT based hardware can now take control from firmware */
1356 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1357 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1358 emx_get_hw_control(sc);
1364 emx_intr_body(xsc, TRUE);
1368 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1370 struct ifnet *ifp = &sc->arpcom.ac_if;
1374 ASSERT_SERIALIZED(&sc->main_serialize);
1376 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1378 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1384 * XXX: some laptops trigger several spurious interrupts
1385 * on emx(4) when in the resume cycle. The ICR register
1386 * reports all-ones value in this case. Processing such
1387 * interrupts would lead to a freeze. I don't know why.
1389 if (reg_icr == 0xffffffff) {
1394 if (ifp->if_flags & IFF_RUNNING) {
1396 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1399 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1400 lwkt_serialize_enter(
1401 &sc->rx_data[i].rx_serialize);
1402 emx_rxeof(&sc->rx_data[i], -1);
1403 lwkt_serialize_exit(
1404 &sc->rx_data[i].rx_serialize);
1407 if (reg_icr & E1000_ICR_TXDW) {
1408 struct emx_txdata *tdata = &sc->tx_data[0];
1410 lwkt_serialize_enter(&tdata->tx_serialize);
1412 if (!ifsq_is_empty(tdata->ifsq))
1413 ifsq_devstart(tdata->ifsq);
1414 lwkt_serialize_exit(&tdata->tx_serialize);
1418 /* Link status change */
1419 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1420 emx_serialize_skipmain(sc);
1422 callout_stop(&sc->timer);
1423 sc->hw.mac.get_link_status = 1;
1424 emx_update_link_status(sc);
1426 /* Deal with TX cruft when link lost */
1429 callout_reset(&sc->timer, hz, emx_timer, sc);
1431 emx_deserialize_skipmain(sc);
1434 if (reg_icr & E1000_ICR_RXO)
1441 emx_intr_mask(void *xsc)
1443 struct emx_softc *sc = xsc;
1445 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1448 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1449 * so don't check it.
1451 emx_intr_body(sc, FALSE);
1452 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1456 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1458 struct emx_softc *sc = ifp->if_softc;
1460 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1462 emx_update_link_status(sc);
1464 ifmr->ifm_status = IFM_AVALID;
1465 ifmr->ifm_active = IFM_ETHER;
1467 if (!sc->link_active)
1470 ifmr->ifm_status |= IFM_ACTIVE;
1472 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1473 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1474 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1476 switch (sc->link_speed) {
1478 ifmr->ifm_active |= IFM_10_T;
1481 ifmr->ifm_active |= IFM_100_TX;
1485 ifmr->ifm_active |= IFM_1000_T;
1488 if (sc->link_duplex == FULL_DUPLEX)
1489 ifmr->ifm_active |= IFM_FDX;
1491 ifmr->ifm_active |= IFM_HDX;
1496 emx_media_change(struct ifnet *ifp)
1498 struct emx_softc *sc = ifp->if_softc;
1499 struct ifmedia *ifm = &sc->media;
1501 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1503 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1506 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1508 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1509 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1515 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1516 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1520 sc->hw.mac.autoneg = FALSE;
1521 sc->hw.phy.autoneg_advertised = 0;
1522 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1523 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1525 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1529 sc->hw.mac.autoneg = FALSE;
1530 sc->hw.phy.autoneg_advertised = 0;
1531 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1532 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1534 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1538 if_printf(ifp, "Unsupported media type\n");
1548 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1549 int *segs_used, int *idx)
1551 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1553 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1554 struct e1000_tx_desc *ctxd = NULL;
1555 struct mbuf *m_head = *m_headp;
1556 uint32_t txd_upper, txd_lower, cmd = 0;
1557 int maxsegs, nsegs, i, j, first, last = 0, error;
1559 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1560 error = emx_tso_pullup(tdata, m_headp);
1566 txd_upper = txd_lower = 0;
1569 * Capture the first descriptor index, this descriptor
1570 * will have the index of the EOP which is the only one
1571 * that now gets a DONE bit writeback.
1573 first = tdata->next_avail_tx_desc;
1574 tx_buffer = &tdata->tx_buf[first];
1575 tx_buffer_mapped = tx_buffer;
1576 map = tx_buffer->map;
1578 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1579 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1580 if (maxsegs > EMX_MAX_SCATTER)
1581 maxsegs = EMX_MAX_SCATTER;
1583 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1584 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1590 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1593 tdata->tx_nsegs += nsegs;
1594 *segs_used += nsegs;
1596 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1597 /* TSO will consume one TX desc */
1598 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1599 tdata->tx_nsegs += i;
1601 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1602 /* TX csum offloading will consume one TX desc */
1603 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1604 tdata->tx_nsegs += i;
1608 /* Handle VLAN tag */
1609 if (m_head->m_flags & M_VLANTAG) {
1610 /* Set the vlan id. */
1611 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16);
1612 /* Tell hardware to add tag */
1613 txd_lower |= htole32(E1000_TXD_CMD_VLE);
1616 i = tdata->next_avail_tx_desc;
1618 /* Set up our transmit descriptors */
1619 for (j = 0; j < nsegs; j++) {
1620 tx_buffer = &tdata->tx_buf[i];
1621 ctxd = &tdata->tx_desc_base[i];
1623 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1624 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1625 txd_lower | segs[j].ds_len);
1626 ctxd->upper.data = htole32(txd_upper);
1629 if (++i == tdata->num_tx_desc)
1633 tdata->next_avail_tx_desc = i;
1635 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1636 tdata->num_tx_desc_avail -= nsegs;
1638 tx_buffer->m_head = m_head;
1639 tx_buffer_mapped->map = tx_buffer->map;
1640 tx_buffer->map = map;
1642 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1643 tdata->tx_nsegs = 0;
1646 * Report Status (RS) is turned on
1647 * every tx_intr_nsegs descriptors.
1649 cmd = E1000_TXD_CMD_RS;
1652 * Keep track of the descriptor, which will
1653 * be written back by hardware.
1655 tdata->tx_dd[tdata->tx_dd_tail] = last;
1656 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1657 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1661 * Last Descriptor of Packet needs End Of Packet (EOP)
1663 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1666 * Defer TDT updating, until enough descriptors are setup
1670 #ifdef EMX_TSS_DEBUG
1678 emx_set_promisc(struct emx_softc *sc)
1680 struct ifnet *ifp = &sc->arpcom.ac_if;
1683 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1685 if (ifp->if_flags & IFF_PROMISC) {
1686 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1687 /* Turn this on if you want to see bad packets */
1689 reg_rctl |= E1000_RCTL_SBP;
1690 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1691 } else if (ifp->if_flags & IFF_ALLMULTI) {
1692 reg_rctl |= E1000_RCTL_MPE;
1693 reg_rctl &= ~E1000_RCTL_UPE;
1694 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1699 emx_disable_promisc(struct emx_softc *sc)
1703 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1705 reg_rctl &= ~E1000_RCTL_UPE;
1706 reg_rctl &= ~E1000_RCTL_MPE;
1707 reg_rctl &= ~E1000_RCTL_SBP;
1708 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1712 emx_set_multi(struct emx_softc *sc)
1714 struct ifnet *ifp = &sc->arpcom.ac_if;
1715 struct ifmultiaddr *ifma;
1716 uint32_t reg_rctl = 0;
1721 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1723 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1724 if (ifma->ifma_addr->sa_family != AF_LINK)
1727 if (mcnt == EMX_MCAST_ADDR_MAX)
1730 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1731 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1735 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1736 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1737 reg_rctl |= E1000_RCTL_MPE;
1738 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1740 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1745 * This routine checks for link status and updates statistics.
1748 emx_timer(void *xsc)
1750 struct emx_softc *sc = xsc;
1751 struct ifnet *ifp = &sc->arpcom.ac_if;
1753 lwkt_serialize_enter(&sc->main_serialize);
1755 emx_update_link_status(sc);
1756 emx_update_stats(sc);
1758 /* Reset LAA into RAR[0] on 82571 */
1759 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1760 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1762 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1763 emx_print_hw_stats(sc);
1767 callout_reset(&sc->timer, hz, emx_timer, sc);
1769 lwkt_serialize_exit(&sc->main_serialize);
1773 emx_update_link_status(struct emx_softc *sc)
1775 struct e1000_hw *hw = &sc->hw;
1776 struct ifnet *ifp = &sc->arpcom.ac_if;
1777 device_t dev = sc->dev;
1778 uint32_t link_check = 0;
1780 /* Get the cached link value or read phy for real */
1781 switch (hw->phy.media_type) {
1782 case e1000_media_type_copper:
1783 if (hw->mac.get_link_status) {
1784 /* Do the work to read phy */
1785 e1000_check_for_link(hw);
1786 link_check = !hw->mac.get_link_status;
1787 if (link_check) /* ESB2 fix */
1788 e1000_cfg_on_link_up(hw);
1794 case e1000_media_type_fiber:
1795 e1000_check_for_link(hw);
1796 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1799 case e1000_media_type_internal_serdes:
1800 e1000_check_for_link(hw);
1801 link_check = sc->hw.mac.serdes_has_link;
1804 case e1000_media_type_unknown:
1809 /* Now check for a transition */
1810 if (link_check && sc->link_active == 0) {
1811 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1815 * Check if we should enable/disable SPEED_MODE bit on
1818 if (sc->link_speed != SPEED_1000 &&
1819 (hw->mac.type == e1000_82571 ||
1820 hw->mac.type == e1000_82572)) {
1823 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1824 tarc0 &= ~EMX_TARC_SPEED_MODE;
1825 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1828 device_printf(dev, "Link is up %d Mbps %s\n",
1830 ((sc->link_duplex == FULL_DUPLEX) ?
1831 "Full Duplex" : "Half Duplex"));
1833 sc->link_active = 1;
1835 ifp->if_baudrate = sc->link_speed * 1000000;
1836 ifp->if_link_state = LINK_STATE_UP;
1837 if_link_state_change(ifp);
1838 } else if (!link_check && sc->link_active == 1) {
1839 ifp->if_baudrate = sc->link_speed = 0;
1840 sc->link_duplex = 0;
1842 device_printf(dev, "Link is Down\n");
1843 sc->link_active = 0;
1844 ifp->if_link_state = LINK_STATE_DOWN;
1845 if_link_state_change(ifp);
1850 emx_stop(struct emx_softc *sc)
1852 struct ifnet *ifp = &sc->arpcom.ac_if;
1855 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1857 emx_disable_intr(sc);
1859 callout_stop(&sc->timer);
1861 ifp->if_flags &= ~IFF_RUNNING;
1862 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1863 struct emx_txdata *tdata = &sc->tx_data[i];
1865 ifsq_clr_oactive(tdata->ifsq);
1866 ifsq_watchdog_stop(&tdata->tx_watchdog);
1867 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
1871 * Disable multiple receive queues.
1874 * We should disable multiple receive queues before
1875 * resetting the hardware.
1877 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1879 e1000_reset_hw(&sc->hw);
1880 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1882 for (i = 0; i < sc->tx_ring_cnt; ++i)
1883 emx_free_tx_ring(&sc->tx_data[i]);
1884 for (i = 0; i < sc->rx_ring_cnt; ++i)
1885 emx_free_rx_ring(&sc->rx_data[i]);
1889 emx_reset(struct emx_softc *sc)
1891 device_t dev = sc->dev;
1892 uint16_t rx_buffer_size;
1895 /* Set up smart power down as default off on newer adapters. */
1896 if (!emx_smart_pwr_down &&
1897 (sc->hw.mac.type == e1000_82571 ||
1898 sc->hw.mac.type == e1000_82572)) {
1899 uint16_t phy_tmp = 0;
1901 /* Speed up time to link by disabling smart power down. */
1902 e1000_read_phy_reg(&sc->hw,
1903 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1904 phy_tmp &= ~IGP02E1000_PM_SPD;
1905 e1000_write_phy_reg(&sc->hw,
1906 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1910 * Packet Buffer Allocation (PBA)
1911 * Writing PBA sets the receive portion of the buffer
1912 * the remainder is used for the transmit buffer.
1914 switch (sc->hw.mac.type) {
1915 /* Total Packet Buffer on these is 48K */
1918 case e1000_80003es2lan:
1919 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1922 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1923 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1927 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1931 pba = E1000_PBA_26K;
1935 /* Devices before 82547 had a Packet Buffer of 64K. */
1936 if (sc->hw.mac.max_frame_size > 8192)
1937 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1939 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1941 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1944 * These parameters control the automatic generation (Tx) and
1945 * response (Rx) to Ethernet PAUSE frames.
1946 * - High water mark should allow for at least two frames to be
1947 * received after sending an XOFF.
1948 * - Low water mark works best when it is very near the high water mark.
1949 * This allows the receiver to restart by sending XON when it has
1950 * drained a bit. Here we use an arbitary value of 1500 which will
1951 * restart after one full frame is pulled from the buffer. There
1952 * could be several smaller frames in the buffer and if so they will
1953 * not trigger the XON until their total number reduces the buffer
1955 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1957 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1959 sc->hw.fc.high_water = rx_buffer_size -
1960 roundup2(sc->hw.mac.max_frame_size, 1024);
1961 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1963 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1964 sc->hw.fc.send_xon = TRUE;
1965 sc->hw.fc.requested_mode = e1000_fc_full;
1968 * Device specific overrides/settings
1970 if (sc->hw.mac.type == e1000_pch_lpt) {
1971 sc->hw.fc.high_water = 0x5C20;
1972 sc->hw.fc.low_water = 0x5048;
1973 sc->hw.fc.pause_time = 0x0650;
1974 sc->hw.fc.refresh_time = 0x0400;
1975 /* Jumbos need adjusted PBA */
1976 if (sc->arpcom.ac_if.if_mtu > ETHERMTU)
1977 E1000_WRITE_REG(&sc->hw, E1000_PBA, 12);
1979 E1000_WRITE_REG(&sc->hw, E1000_PBA, 26);
1980 } else if (sc->hw.mac.type == e1000_80003es2lan) {
1981 sc->hw.fc.pause_time = 0xFFFF;
1984 /* Issue a global reset */
1985 e1000_reset_hw(&sc->hw);
1986 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1987 emx_disable_aspm(sc);
1989 if (e1000_init_hw(&sc->hw) < 0) {
1990 device_printf(dev, "Hardware Initialization Failed\n");
1994 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1995 e1000_get_phy_info(&sc->hw);
1996 e1000_check_for_link(&sc->hw);
2002 emx_setup_ifp(struct emx_softc *sc)
2004 struct ifnet *ifp = &sc->arpcom.ac_if;
2007 if_initname(ifp, device_get_name(sc->dev),
2008 device_get_unit(sc->dev));
2010 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2011 ifp->if_init = emx_init;
2012 ifp->if_ioctl = emx_ioctl;
2013 ifp->if_start = emx_start;
2014 #ifdef IFPOLL_ENABLE
2015 ifp->if_npoll = emx_npoll;
2017 ifp->if_serialize = emx_serialize;
2018 ifp->if_deserialize = emx_deserialize;
2019 ifp->if_tryserialize = emx_tryserialize;
2021 ifp->if_serialize_assert = emx_serialize_assert;
2024 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
2025 ifq_set_ready(&ifp->if_snd);
2026 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
2028 ifp->if_mapsubq = ifq_mapsubq_mask;
2029 ifq_set_subq_mask(&ifp->if_snd, 0);
2031 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
2033 ifp->if_capabilities = IFCAP_HWCSUM |
2034 IFCAP_VLAN_HWTAGGING |
2037 if (sc->rx_ring_cnt > 1)
2038 ifp->if_capabilities |= IFCAP_RSS;
2039 ifp->if_capenable = ifp->if_capabilities;
2040 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
2043 * Tell the upper layer(s) we support long frames.
2045 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2047 for (i = 0; i < sc->tx_ring_cnt; ++i) {
2048 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2049 struct emx_txdata *tdata = &sc->tx_data[i];
2051 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
2052 ifsq_set_priv(ifsq, tdata);
2053 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
2056 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
2060 * Specify the media types supported by this sc and register
2061 * callbacks to update media and link information
2063 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2064 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2065 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2067 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
2069 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2070 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2072 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2073 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2075 if (sc->hw.phy.type != e1000_phy_ife) {
2076 ifmedia_add(&sc->media,
2077 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2078 ifmedia_add(&sc->media,
2079 IFM_ETHER | IFM_1000_T, 0, NULL);
2082 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2083 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
2087 * Workaround for SmartSpeed on 82541 and 82547 controllers
2090 emx_smartspeed(struct emx_softc *sc)
2094 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2095 sc->hw.mac.autoneg == 0 ||
2096 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2099 if (sc->smartspeed == 0) {
2101 * If Master/Slave config fault is asserted twice,
2102 * we assume back-to-back
2104 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2105 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2107 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2108 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2109 e1000_read_phy_reg(&sc->hw,
2110 PHY_1000T_CTRL, &phy_tmp);
2111 if (phy_tmp & CR_1000T_MS_ENABLE) {
2112 phy_tmp &= ~CR_1000T_MS_ENABLE;
2113 e1000_write_phy_reg(&sc->hw,
2114 PHY_1000T_CTRL, phy_tmp);
2116 if (sc->hw.mac.autoneg &&
2117 !e1000_phy_setup_autoneg(&sc->hw) &&
2118 !e1000_read_phy_reg(&sc->hw,
2119 PHY_CONTROL, &phy_tmp)) {
2120 phy_tmp |= MII_CR_AUTO_NEG_EN |
2121 MII_CR_RESTART_AUTO_NEG;
2122 e1000_write_phy_reg(&sc->hw,
2123 PHY_CONTROL, phy_tmp);
2128 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2129 /* If still no link, perhaps using 2/3 pair cable */
2130 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2131 phy_tmp |= CR_1000T_MS_ENABLE;
2132 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2133 if (sc->hw.mac.autoneg &&
2134 !e1000_phy_setup_autoneg(&sc->hw) &&
2135 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2136 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2137 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2141 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2142 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2147 emx_create_tx_ring(struct emx_txdata *tdata)
2149 device_t dev = tdata->sc->dev;
2150 struct emx_txbuf *tx_buffer;
2151 int error, i, tsize, ntxd;
2154 * Validate number of transmit descriptors. It must not exceed
2155 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2157 ntxd = device_getenv_int(dev, "txd", emx_txd);
2158 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2159 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2160 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2161 EMX_DEFAULT_TXD, ntxd);
2162 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2164 tdata->num_tx_desc = ntxd;
2168 * Allocate Transmit Descriptor ring
2170 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2172 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2173 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2174 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2175 &tdata->tx_desc_paddr);
2176 if (tdata->tx_desc_base == NULL) {
2177 device_printf(dev, "Unable to allocate tx_desc memory\n");
2181 tsize = __VM_CACHELINE_ALIGN(
2182 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2183 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2186 * Create DMA tags for tx buffers
2188 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2189 1, 0, /* alignment, bounds */
2190 BUS_SPACE_MAXADDR, /* lowaddr */
2191 BUS_SPACE_MAXADDR, /* highaddr */
2192 NULL, NULL, /* filter, filterarg */
2193 EMX_TSO_SIZE, /* maxsize */
2194 EMX_MAX_SCATTER, /* nsegments */
2195 EMX_MAX_SEGSIZE, /* maxsegsize */
2196 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2197 BUS_DMA_ONEBPAGE, /* flags */
2200 device_printf(dev, "Unable to allocate TX DMA tag\n");
2201 kfree(tdata->tx_buf, M_DEVBUF);
2202 tdata->tx_buf = NULL;
2207 * Create DMA maps for tx buffers
2209 for (i = 0; i < tdata->num_tx_desc; i++) {
2210 tx_buffer = &tdata->tx_buf[i];
2212 error = bus_dmamap_create(tdata->txtag,
2213 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2216 device_printf(dev, "Unable to create TX DMA map\n");
2217 emx_destroy_tx_ring(tdata, i);
2223 * Setup TX parameters
2225 tdata->spare_tx_desc = EMX_TX_SPARE;
2226 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2229 * Keep following relationship between spare_tx_desc, oact_tx_desc
2230 * and tx_intr_nsegs:
2231 * (spare_tx_desc + EMX_TX_RESERVED) <=
2232 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2234 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2235 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2236 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2237 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2238 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2240 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2241 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2242 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2245 * Pullup extra 4bytes into the first data segment for TSO, see:
2246 * 82571/82572 specification update errata #7
2248 * Same applies to I217 (and maybe I218).
2251 * 4bytes instead of 2bytes, which are mentioned in the errata,
2252 * are pulled; mainly to keep rest of the data properly aligned.
2254 if (tdata->sc->hw.mac.type == e1000_82571 ||
2255 tdata->sc->hw.mac.type == e1000_82572 ||
2256 tdata->sc->hw.mac.type == e1000_pch_lpt)
2257 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2263 emx_init_tx_ring(struct emx_txdata *tdata)
2265 /* Clear the old ring contents */
2266 bzero(tdata->tx_desc_base,
2267 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2270 tdata->next_avail_tx_desc = 0;
2271 tdata->next_tx_to_clean = 0;
2272 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2274 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2275 if (tdata->sc->tx_ring_inuse > 1) {
2276 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2278 if_printf(&tdata->sc->arpcom.ac_if,
2279 "TX %d force ctx setup\n", tdata->idx);
2285 emx_init_tx_unit(struct emx_softc *sc)
2287 uint32_t tctl, tarc, tipg = 0, txdctl;
2290 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2291 struct emx_txdata *tdata = &sc->tx_data[i];
2294 /* Setup the Base and Length of the Tx Descriptor Ring */
2295 bus_addr = tdata->tx_desc_paddr;
2296 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2297 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2298 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2299 (uint32_t)(bus_addr >> 32));
2300 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2301 (uint32_t)bus_addr);
2302 /* Setup the HW Tx Head and Tail descriptor pointers */
2303 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2304 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2307 /* Set the default values for the Tx Inter Packet Gap timer */
2308 switch (sc->hw.mac.type) {
2309 case e1000_80003es2lan:
2310 tipg = DEFAULT_82543_TIPG_IPGR1;
2311 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2312 E1000_TIPG_IPGR2_SHIFT;
2316 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2317 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2318 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2320 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2321 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2322 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2326 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2328 /* NOTE: 0 is not allowed for TIDV */
2329 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2330 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2333 * Errata workaround (obtained from Linux). This is necessary
2334 * to make multiple TX queues work on 82574.
2335 * XXX can't find it in any published errata though.
2337 txdctl = E1000_READ_REG(&sc->hw, E1000_TXDCTL(0));
2338 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(1), txdctl);
2340 if (sc->hw.mac.type == e1000_82571 ||
2341 sc->hw.mac.type == e1000_82572) {
2342 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2343 tarc |= EMX_TARC_SPEED_MODE;
2344 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2345 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2346 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2348 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2349 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2351 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2354 /* Program the Transmit Control Register */
2355 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2356 tctl &= ~E1000_TCTL_CT;
2357 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2358 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2359 tctl |= E1000_TCTL_MULR;
2361 /* This write will effectively turn on the transmit unit. */
2362 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2364 if (sc->hw.mac.type == e1000_82571 ||
2365 sc->hw.mac.type == e1000_82572 ||
2366 sc->hw.mac.type == e1000_80003es2lan) {
2367 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2368 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2370 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2373 if (sc->tx_ring_inuse > 1) {
2374 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2375 tarc &= ~EMX_TARC_COUNT_MASK;
2377 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2379 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2380 tarc &= ~EMX_TARC_COUNT_MASK;
2382 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2387 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2389 struct emx_txbuf *tx_buffer;
2392 /* Free Transmit Descriptor ring */
2393 if (tdata->tx_desc_base) {
2394 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2395 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2396 tdata->tx_desc_dmap);
2397 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2399 tdata->tx_desc_base = NULL;
2402 if (tdata->tx_buf == NULL)
2405 for (i = 0; i < ndesc; i++) {
2406 tx_buffer = &tdata->tx_buf[i];
2408 KKASSERT(tx_buffer->m_head == NULL);
2409 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2411 bus_dma_tag_destroy(tdata->txtag);
2413 kfree(tdata->tx_buf, M_DEVBUF);
2414 tdata->tx_buf = NULL;
2418 * The offload context needs to be set when we transfer the first
2419 * packet of a particular protocol (TCP/UDP). This routine has been
2420 * enhanced to deal with inserted VLAN headers.
2422 * If the new packet's ether header length, ip header length and
2423 * csum offloading type are same as the previous packet, we should
2424 * avoid allocating a new csum context descriptor; mainly to take
2425 * advantage of the pipeline effect of the TX data read request.
2427 * This function returns number of TX descrptors allocated for
2431 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2432 uint32_t *txd_upper, uint32_t *txd_lower)
2434 struct e1000_context_desc *TXD;
2435 int curr_txd, ehdrlen, csum_flags;
2436 uint32_t cmd, hdr_len, ip_hlen;
2438 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2439 ip_hlen = mp->m_pkthdr.csum_iphlen;
2440 ehdrlen = mp->m_pkthdr.csum_lhlen;
2442 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2443 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2444 tdata->csum_flags == csum_flags) {
2446 * Same csum offload context as the previous packets;
2449 *txd_upper = tdata->csum_txd_upper;
2450 *txd_lower = tdata->csum_txd_lower;
2455 * Setup a new csum offload context.
2458 curr_txd = tdata->next_avail_tx_desc;
2459 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2463 /* Setup of IP header checksum. */
2464 if (csum_flags & CSUM_IP) {
2466 * Start offset for header checksum calculation.
2467 * End offset for header checksum calculation.
2468 * Offset of place to put the checksum.
2470 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2471 TXD->lower_setup.ip_fields.ipcse =
2472 htole16(ehdrlen + ip_hlen - 1);
2473 TXD->lower_setup.ip_fields.ipcso =
2474 ehdrlen + offsetof(struct ip, ip_sum);
2475 cmd |= E1000_TXD_CMD_IP;
2476 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2478 hdr_len = ehdrlen + ip_hlen;
2480 if (csum_flags & CSUM_TCP) {
2482 * Start offset for payload checksum calculation.
2483 * End offset for payload checksum calculation.
2484 * Offset of place to put the checksum.
2486 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2487 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2488 TXD->upper_setup.tcp_fields.tucso =
2489 hdr_len + offsetof(struct tcphdr, th_sum);
2490 cmd |= E1000_TXD_CMD_TCP;
2491 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2492 } else if (csum_flags & CSUM_UDP) {
2494 * Start offset for header checksum calculation.
2495 * End offset for header checksum calculation.
2496 * Offset of place to put the checksum.
2498 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2499 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2500 TXD->upper_setup.tcp_fields.tucso =
2501 hdr_len + offsetof(struct udphdr, uh_sum);
2502 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2505 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2506 E1000_TXD_DTYP_D; /* Data descr */
2508 /* Save the information for this csum offloading context */
2509 tdata->csum_lhlen = ehdrlen;
2510 tdata->csum_iphlen = ip_hlen;
2511 tdata->csum_flags = csum_flags;
2512 tdata->csum_txd_upper = *txd_upper;
2513 tdata->csum_txd_lower = *txd_lower;
2515 TXD->tcp_seg_setup.data = htole32(0);
2516 TXD->cmd_and_length =
2517 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2519 if (++curr_txd == tdata->num_tx_desc)
2522 KKASSERT(tdata->num_tx_desc_avail > 0);
2523 tdata->num_tx_desc_avail--;
2525 tdata->next_avail_tx_desc = curr_txd;
2530 emx_txeof(struct emx_txdata *tdata)
2532 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
2533 struct emx_txbuf *tx_buffer;
2534 int first, num_avail;
2536 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2539 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2542 num_avail = tdata->num_tx_desc_avail;
2543 first = tdata->next_tx_to_clean;
2545 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2546 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2547 struct e1000_tx_desc *tx_desc;
2549 tx_desc = &tdata->tx_desc_base[dd_idx];
2550 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2551 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2553 if (++dd_idx == tdata->num_tx_desc)
2556 while (first != dd_idx) {
2561 tx_buffer = &tdata->tx_buf[first];
2562 if (tx_buffer->m_head) {
2563 IFNET_STAT_INC(ifp, opackets, 1);
2564 bus_dmamap_unload(tdata->txtag,
2566 m_freem(tx_buffer->m_head);
2567 tx_buffer->m_head = NULL;
2570 if (++first == tdata->num_tx_desc)
2577 tdata->next_tx_to_clean = first;
2578 tdata->num_tx_desc_avail = num_avail;
2580 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2581 tdata->tx_dd_head = 0;
2582 tdata->tx_dd_tail = 0;
2585 if (!EMX_IS_OACTIVE(tdata)) {
2586 ifsq_clr_oactive(tdata->ifsq);
2588 /* All clean, turn off the timer */
2589 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2590 tdata->tx_watchdog.wd_timer = 0;
2595 emx_tx_collect(struct emx_txdata *tdata)
2597 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
2598 struct emx_txbuf *tx_buffer;
2599 int tdh, first, num_avail, dd_idx = -1;
2601 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2604 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2605 if (tdh == tdata->next_tx_to_clean)
2608 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2609 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2611 num_avail = tdata->num_tx_desc_avail;
2612 first = tdata->next_tx_to_clean;
2614 while (first != tdh) {
2619 tx_buffer = &tdata->tx_buf[first];
2620 if (tx_buffer->m_head) {
2621 IFNET_STAT_INC(ifp, opackets, 1);
2622 bus_dmamap_unload(tdata->txtag,
2624 m_freem(tx_buffer->m_head);
2625 tx_buffer->m_head = NULL;
2628 if (first == dd_idx) {
2629 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2630 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2631 tdata->tx_dd_head = 0;
2632 tdata->tx_dd_tail = 0;
2635 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2639 if (++first == tdata->num_tx_desc)
2642 tdata->next_tx_to_clean = first;
2643 tdata->num_tx_desc_avail = num_avail;
2645 if (!EMX_IS_OACTIVE(tdata)) {
2646 ifsq_clr_oactive(tdata->ifsq);
2648 /* All clean, turn off the timer */
2649 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2650 tdata->tx_watchdog.wd_timer = 0;
2655 * When Link is lost sometimes there is work still in the TX ring
2656 * which will result in a watchdog, rather than allow that do an
2657 * attempted cleanup and then reinit here. Note that this has been
2658 * seens mostly with fiber adapters.
2661 emx_tx_purge(struct emx_softc *sc)
2665 if (sc->link_active)
2668 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2669 struct emx_txdata *tdata = &sc->tx_data[i];
2671 if (tdata->tx_watchdog.wd_timer) {
2672 emx_tx_collect(tdata);
2673 if (tdata->tx_watchdog.wd_timer) {
2674 if_printf(&sc->arpcom.ac_if,
2675 "Link lost, TX pending, reinit\n");
2684 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2687 bus_dma_segment_t seg;
2689 struct emx_rxbuf *rx_buffer;
2692 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2695 if_printf(&rdata->sc->arpcom.ac_if,
2696 "Unable to allocate RX mbuf\n");
2700 m->m_len = m->m_pkthdr.len = MCLBYTES;
2702 if (rdata->sc->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN)
2703 m_adj(m, ETHER_ALIGN);
2705 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2706 rdata->rx_sparemap, m,
2707 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2711 if_printf(&rdata->sc->arpcom.ac_if,
2712 "Unable to load RX mbuf\n");
2717 rx_buffer = &rdata->rx_buf[i];
2718 if (rx_buffer->m_head != NULL)
2719 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2721 map = rx_buffer->map;
2722 rx_buffer->map = rdata->rx_sparemap;
2723 rdata->rx_sparemap = map;
2725 rx_buffer->m_head = m;
2726 rx_buffer->paddr = seg.ds_addr;
2728 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2733 emx_create_rx_ring(struct emx_rxdata *rdata)
2735 device_t dev = rdata->sc->dev;
2736 struct emx_rxbuf *rx_buffer;
2737 int i, error, rsize, nrxd;
2740 * Validate number of receive descriptors. It must not exceed
2741 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2743 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2744 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2745 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2746 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2747 EMX_DEFAULT_RXD, nrxd);
2748 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2750 rdata->num_rx_desc = nrxd;
2754 * Allocate Receive Descriptor ring
2756 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2758 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2759 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2760 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2761 &rdata->rx_desc_paddr);
2762 if (rdata->rx_desc == NULL) {
2763 device_printf(dev, "Unable to allocate rx_desc memory\n");
2767 rsize = __VM_CACHELINE_ALIGN(
2768 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2769 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2772 * Create DMA tag for rx buffers
2774 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2775 1, 0, /* alignment, bounds */
2776 BUS_SPACE_MAXADDR, /* lowaddr */
2777 BUS_SPACE_MAXADDR, /* highaddr */
2778 NULL, NULL, /* filter, filterarg */
2779 MCLBYTES, /* maxsize */
2781 MCLBYTES, /* maxsegsize */
2782 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2785 device_printf(dev, "Unable to allocate RX DMA tag\n");
2786 kfree(rdata->rx_buf, M_DEVBUF);
2787 rdata->rx_buf = NULL;
2792 * Create spare DMA map for rx buffers
2794 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2795 &rdata->rx_sparemap);
2797 device_printf(dev, "Unable to create spare RX DMA map\n");
2798 bus_dma_tag_destroy(rdata->rxtag);
2799 kfree(rdata->rx_buf, M_DEVBUF);
2800 rdata->rx_buf = NULL;
2805 * Create DMA maps for rx buffers
2807 for (i = 0; i < rdata->num_rx_desc; i++) {
2808 rx_buffer = &rdata->rx_buf[i];
2810 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2813 device_printf(dev, "Unable to create RX DMA map\n");
2814 emx_destroy_rx_ring(rdata, i);
2822 emx_free_rx_ring(struct emx_rxdata *rdata)
2826 for (i = 0; i < rdata->num_rx_desc; i++) {
2827 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2829 if (rx_buffer->m_head != NULL) {
2830 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2831 m_freem(rx_buffer->m_head);
2832 rx_buffer->m_head = NULL;
2836 if (rdata->fmp != NULL)
2837 m_freem(rdata->fmp);
2843 emx_free_tx_ring(struct emx_txdata *tdata)
2847 for (i = 0; i < tdata->num_tx_desc; i++) {
2848 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
2850 if (tx_buffer->m_head != NULL) {
2851 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
2852 m_freem(tx_buffer->m_head);
2853 tx_buffer->m_head = NULL;
2857 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
2859 tdata->csum_flags = 0;
2860 tdata->csum_lhlen = 0;
2861 tdata->csum_iphlen = 0;
2862 tdata->csum_thlen = 0;
2863 tdata->csum_mss = 0;
2864 tdata->csum_pktlen = 0;
2866 tdata->tx_dd_head = 0;
2867 tdata->tx_dd_tail = 0;
2868 tdata->tx_nsegs = 0;
2872 emx_init_rx_ring(struct emx_rxdata *rdata)
2876 /* Reset descriptor ring */
2877 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2879 /* Allocate new ones. */
2880 for (i = 0; i < rdata->num_rx_desc; i++) {
2881 error = emx_newbuf(rdata, i, 1);
2886 /* Setup our descriptor pointers */
2887 rdata->next_rx_desc_to_check = 0;
2893 emx_init_rx_unit(struct emx_softc *sc)
2895 struct ifnet *ifp = &sc->arpcom.ac_if;
2897 uint32_t rctl, itr, rfctl;
2901 * Make sure receives are disabled while setting
2902 * up the descriptor ring
2904 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2905 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2908 * Set the interrupt throttling rate. Value is calculated
2909 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2911 if (sc->int_throttle_ceil)
2912 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2915 emx_set_itr(sc, itr);
2917 /* Use extended RX descriptor */
2918 rfctl = E1000_RFCTL_EXTEN;
2920 /* Disable accelerated ackknowledge */
2921 if (sc->hw.mac.type == e1000_82574)
2922 rfctl |= E1000_RFCTL_ACK_DIS;
2924 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2927 * Receive Checksum Offload for TCP and UDP
2929 * Checksum offloading is also enabled if multiple receive
2930 * queue is to be supported, since we need it to figure out
2933 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2934 sc->rx_ring_cnt > 1) {
2937 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2941 * PCSD must be enabled to enable multiple
2944 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2946 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2950 * Configure multiple receive queue (RSS)
2952 if (sc->rx_ring_cnt > 1) {
2953 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2956 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2957 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2961 * When we reach here, RSS has already been disabled
2962 * in emx_stop(), so we could safely configure RSS key
2963 * and redirect table.
2969 toeplitz_get_key(key, sizeof(key));
2970 for (i = 0; i < EMX_NRSSRK; ++i) {
2973 rssrk = EMX_RSSRK_VAL(key, i);
2974 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2976 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2980 * Configure RSS redirect table in following fashion:
2981 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2984 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2987 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2988 reta |= q << (8 * i);
2990 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2992 for (i = 0; i < EMX_NRETA; ++i)
2993 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2996 * Enable multiple receive queues.
2997 * Enable IPv4 RSS standard hash functions.
2998 * Disable RSS interrupt.
3000 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
3001 E1000_MRQC_ENABLE_RSS_2Q |
3002 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3003 E1000_MRQC_RSS_FIELD_IPV4);
3007 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3008 * long latencies are observed, like Lenovo X60. This
3009 * change eliminates the problem, but since having positive
3010 * values in RDTR is a known source of problems on other
3011 * platforms another solution is being sought.
3013 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
3014 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
3015 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
3018 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3019 struct emx_rxdata *rdata = &sc->rx_data[i];
3022 * Setup the Base and Length of the Rx Descriptor Ring
3024 bus_addr = rdata->rx_desc_paddr;
3025 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
3026 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
3027 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
3028 (uint32_t)(bus_addr >> 32));
3029 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
3030 (uint32_t)bus_addr);
3033 * Setup the HW Rx Head and Tail Descriptor Pointers
3035 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
3036 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
3037 sc->rx_data[i].num_rx_desc - 1);
3040 if (sc->hw.mac.type >= e1000_pch2lan) {
3041 if (ifp->if_mtu > ETHERMTU)
3042 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, TRUE);
3044 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, FALSE);
3047 /* Setup the Receive Control Register */
3048 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3049 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3050 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
3051 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3053 /* Make sure VLAN Filters are off */
3054 rctl &= ~E1000_RCTL_VFE;
3056 /* Don't store bad paket */
3057 rctl &= ~E1000_RCTL_SBP;
3060 rctl |= E1000_RCTL_SZ_2048;
3062 if (ifp->if_mtu > ETHERMTU)
3063 rctl |= E1000_RCTL_LPE;
3065 rctl &= ~E1000_RCTL_LPE;
3067 /* Enable Receives */
3068 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3072 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
3074 struct emx_rxbuf *rx_buffer;
3077 /* Free Receive Descriptor ring */
3078 if (rdata->rx_desc) {
3079 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
3080 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
3081 rdata->rx_desc_dmap);
3082 bus_dma_tag_destroy(rdata->rx_desc_dtag);
3084 rdata->rx_desc = NULL;
3087 if (rdata->rx_buf == NULL)
3090 for (i = 0; i < ndesc; i++) {
3091 rx_buffer = &rdata->rx_buf[i];
3093 KKASSERT(rx_buffer->m_head == NULL);
3094 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3096 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3097 bus_dma_tag_destroy(rdata->rxtag);
3099 kfree(rdata->rx_buf, M_DEVBUF);
3100 rdata->rx_buf = NULL;
3104 emx_rxeof(struct emx_rxdata *rdata, int count)
3106 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3108 emx_rxdesc_t *current_desc;
3110 int i, cpuid = mycpuid;
3112 i = rdata->next_rx_desc_to_check;
3113 current_desc = &rdata->rx_desc[i];
3114 staterr = le32toh(current_desc->rxd_staterr);
3116 if (!(staterr & E1000_RXD_STAT_DD))
3119 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3120 struct pktinfo *pi = NULL, pi0;
3121 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3122 struct mbuf *m = NULL;
3127 mp = rx_buf->m_head;
3130 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3131 * needs to access the last received byte in the mbuf.
3133 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3134 BUS_DMASYNC_POSTREAD);
3136 len = le16toh(current_desc->rxd_length);
3137 if (staterr & E1000_RXD_STAT_EOP) {
3144 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3146 uint32_t mrq, rss_hash;
3149 * Save several necessary information,
3150 * before emx_newbuf() destroy it.
3152 if ((staterr & E1000_RXD_STAT_VP) && eop)
3153 vlan = le16toh(current_desc->rxd_vlan);
3155 mrq = le32toh(current_desc->rxd_mrq);
3156 rss_hash = le32toh(current_desc->rxd_rss);
3158 EMX_RSS_DPRINTF(rdata->sc, 10,
3159 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3160 rdata->idx, mrq, rss_hash);
3162 if (emx_newbuf(rdata, i, 0) != 0) {
3163 IFNET_STAT_INC(ifp, iqdrops, 1);
3167 /* Assign correct length to the current fragment */
3170 if (rdata->fmp == NULL) {
3171 mp->m_pkthdr.len = len;
3172 rdata->fmp = mp; /* Store the first mbuf */
3176 * Chain mbuf's together
3178 rdata->lmp->m_next = mp;
3179 rdata->lmp = rdata->lmp->m_next;
3180 rdata->fmp->m_pkthdr.len += len;
3184 rdata->fmp->m_pkthdr.rcvif = ifp;
3185 IFNET_STAT_INC(ifp, ipackets, 1);
3187 if (ifp->if_capenable & IFCAP_RXCSUM)
3188 emx_rxcsum(staterr, rdata->fmp);
3190 if (staterr & E1000_RXD_STAT_VP) {
3191 rdata->fmp->m_pkthdr.ether_vlantag =
3193 rdata->fmp->m_flags |= M_VLANTAG;
3199 if (ifp->if_capenable & IFCAP_RSS) {
3200 pi = emx_rssinfo(m, &pi0, mrq,
3203 #ifdef EMX_RSS_DEBUG
3208 IFNET_STAT_INC(ifp, ierrors, 1);
3210 emx_setup_rxdesc(current_desc, rx_buf);
3211 if (rdata->fmp != NULL) {
3212 m_freem(rdata->fmp);
3220 ifp->if_input(ifp, m, pi, cpuid);
3222 /* Advance our pointers to the next descriptor. */
3223 if (++i == rdata->num_rx_desc)
3226 current_desc = &rdata->rx_desc[i];
3227 staterr = le32toh(current_desc->rxd_staterr);
3229 rdata->next_rx_desc_to_check = i;
3231 /* Advance the E1000's Receive Queue "Tail Pointer". */
3233 i = rdata->num_rx_desc - 1;
3234 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3238 emx_enable_intr(struct emx_softc *sc)
3240 uint32_t ims_mask = IMS_ENABLE_MASK;
3242 lwkt_serialize_handler_enable(&sc->main_serialize);
3245 if (sc->hw.mac.type == e1000_82574) {
3246 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3247 ims_mask |= EM_MSIX_MASK;
3250 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3254 emx_disable_intr(struct emx_softc *sc)
3256 if (sc->hw.mac.type == e1000_82574)
3257 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3258 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3260 lwkt_serialize_handler_disable(&sc->main_serialize);
3264 * Bit of a misnomer, what this really means is
3265 * to enable OS management of the system... aka
3266 * to disable special hardware management features
3269 emx_get_mgmt(struct emx_softc *sc)
3271 /* A shared code workaround */
3272 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3273 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3274 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3276 /* disable hardware interception of ARP */
3277 manc &= ~(E1000_MANC_ARP_EN);
3279 /* enable receiving management packets to the host */
3280 manc |= E1000_MANC_EN_MNG2HOST;
3281 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3282 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3283 manc2h |= E1000_MNG2HOST_PORT_623;
3284 manc2h |= E1000_MNG2HOST_PORT_664;
3285 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3287 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3292 * Give control back to hardware management
3293 * controller if there is one.
3296 emx_rel_mgmt(struct emx_softc *sc)
3298 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3299 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3301 /* re-enable hardware interception of ARP */
3302 manc |= E1000_MANC_ARP_EN;
3303 manc &= ~E1000_MANC_EN_MNG2HOST;
3305 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3310 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3311 * For ASF and Pass Through versions of f/w this means that
3312 * the driver is loaded. For AMT version (only with 82573)
3313 * of the f/w this means that the network i/f is open.
3316 emx_get_hw_control(struct emx_softc *sc)
3318 /* Let firmware know the driver has taken over */
3319 if (sc->hw.mac.type == e1000_82573) {
3322 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3323 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3324 swsm | E1000_SWSM_DRV_LOAD);
3328 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3329 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3330 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3332 sc->flags |= EMX_FLAG_HW_CTRL;
3336 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3337 * For ASF and Pass Through versions of f/w this means that the
3338 * driver is no longer loaded. For AMT version (only with 82573)
3339 * of the f/w this means that the network i/f is closed.
3342 emx_rel_hw_control(struct emx_softc *sc)
3344 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3346 sc->flags &= ~EMX_FLAG_HW_CTRL;
3348 /* Let firmware taken over control of h/w */
3349 if (sc->hw.mac.type == e1000_82573) {
3352 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3353 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3354 swsm & ~E1000_SWSM_DRV_LOAD);
3358 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3359 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3360 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3365 emx_is_valid_eaddr(const uint8_t *addr)
3367 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3369 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3376 * Enable PCI Wake On Lan capability
3379 emx_enable_wol(device_t dev)
3381 uint16_t cap, status;
3384 /* First find the capabilities pointer*/
3385 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3387 /* Read the PM Capabilities */
3388 id = pci_read_config(dev, cap, 1);
3389 if (id != PCIY_PMG) /* Something wrong */
3393 * OK, we have the power capabilities,
3394 * so now get the status register
3396 cap += PCIR_POWER_STATUS;
3397 status = pci_read_config(dev, cap, 2);
3398 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3399 pci_write_config(dev, cap, status, 2);
3403 emx_update_stats(struct emx_softc *sc)
3405 struct ifnet *ifp = &sc->arpcom.ac_if;
3407 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3408 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3409 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3410 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3412 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3413 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3414 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3415 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3417 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3418 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3419 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3420 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3421 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3422 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3423 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3424 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3425 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3426 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3427 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3428 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3429 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3430 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3431 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3432 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3433 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3434 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3435 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3436 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3438 /* For the 64-bit byte counters the low dword must be read first. */
3439 /* Both registers clear on the read of the high dword */
3441 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3442 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3444 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3445 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3446 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3447 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3448 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3450 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3451 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3453 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3454 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3455 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3456 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3457 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3458 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3459 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3460 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3461 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3462 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3464 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3465 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3466 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3467 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3468 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3469 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3471 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3474 IFNET_STAT_SET(ifp, ierrors,
3475 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3476 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3479 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3483 emx_print_debug_info(struct emx_softc *sc)
3485 device_t dev = sc->dev;
3486 uint8_t *hw_addr = sc->hw.hw_addr;
3489 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3490 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3491 E1000_READ_REG(&sc->hw, E1000_CTRL),
3492 E1000_READ_REG(&sc->hw, E1000_RCTL));
3493 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3494 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3495 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3496 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3497 sc->hw.fc.high_water, sc->hw.fc.low_water);
3498 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3499 E1000_READ_REG(&sc->hw, E1000_TIDV),
3500 E1000_READ_REG(&sc->hw, E1000_TADV));
3501 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3502 E1000_READ_REG(&sc->hw, E1000_RDTR),
3503 E1000_READ_REG(&sc->hw, E1000_RADV));
3505 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3506 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3507 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3508 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3510 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3511 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3512 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3513 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3516 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3517 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3518 sc->tx_data[i].num_tx_desc_avail);
3519 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3520 sc->tx_data[i].tso_segments);
3521 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3522 sc->tx_data[i].tso_ctx_reused);
3527 emx_print_hw_stats(struct emx_softc *sc)
3529 device_t dev = sc->dev;
3531 device_printf(dev, "Excessive collisions = %lld\n",
3532 (long long)sc->stats.ecol);
3533 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3534 device_printf(dev, "Symbol errors = %lld\n",
3535 (long long)sc->stats.symerrs);
3537 device_printf(dev, "Sequence errors = %lld\n",
3538 (long long)sc->stats.sec);
3539 device_printf(dev, "Defer count = %lld\n",
3540 (long long)sc->stats.dc);
3541 device_printf(dev, "Missed Packets = %lld\n",
3542 (long long)sc->stats.mpc);
3543 device_printf(dev, "Receive No Buffers = %lld\n",
3544 (long long)sc->stats.rnbc);
3545 /* RLEC is inaccurate on some hardware, calculate our own. */
3546 device_printf(dev, "Receive Length Errors = %lld\n",
3547 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3548 device_printf(dev, "Receive errors = %lld\n",
3549 (long long)sc->stats.rxerrc);
3550 device_printf(dev, "Crc errors = %lld\n",
3551 (long long)sc->stats.crcerrs);
3552 device_printf(dev, "Alignment errors = %lld\n",
3553 (long long)sc->stats.algnerrc);
3554 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3555 (long long)sc->stats.cexterr);
3556 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3557 device_printf(dev, "XON Rcvd = %lld\n",
3558 (long long)sc->stats.xonrxc);
3559 device_printf(dev, "XON Xmtd = %lld\n",
3560 (long long)sc->stats.xontxc);
3561 device_printf(dev, "XOFF Rcvd = %lld\n",
3562 (long long)sc->stats.xoffrxc);
3563 device_printf(dev, "XOFF Xmtd = %lld\n",
3564 (long long)sc->stats.xofftxc);
3565 device_printf(dev, "Good Packets Rcvd = %lld\n",
3566 (long long)sc->stats.gprc);
3567 device_printf(dev, "Good Packets Xmtd = %lld\n",
3568 (long long)sc->stats.gptc);
3572 emx_print_nvm_info(struct emx_softc *sc)
3574 uint16_t eeprom_data;
3577 /* Its a bit crude, but it gets the job done */
3578 kprintf("\nInterface EEPROM Dump:\n");
3579 kprintf("Offset\n0x0000 ");
3580 for (i = 0, j = 0; i < 32; i++, j++) {
3581 if (j == 8) { /* Make the offset block */
3583 kprintf("\n0x00%x0 ",row);
3585 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3586 kprintf("%04x ", eeprom_data);
3592 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3594 struct emx_softc *sc;
3599 error = sysctl_handle_int(oidp, &result, 0, req);
3600 if (error || !req->newptr)
3603 sc = (struct emx_softc *)arg1;
3604 ifp = &sc->arpcom.ac_if;
3606 ifnet_serialize_all(ifp);
3609 emx_print_debug_info(sc);
3612 * This value will cause a hex dump of the
3613 * first 32 16-bit words of the EEPROM to
3617 emx_print_nvm_info(sc);
3619 ifnet_deserialize_all(ifp);
3625 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3630 error = sysctl_handle_int(oidp, &result, 0, req);
3631 if (error || !req->newptr)
3635 struct emx_softc *sc = (struct emx_softc *)arg1;
3636 struct ifnet *ifp = &sc->arpcom.ac_if;
3638 ifnet_serialize_all(ifp);
3639 emx_print_hw_stats(sc);
3640 ifnet_deserialize_all(ifp);
3646 emx_add_sysctl(struct emx_softc *sc)
3648 struct sysctl_ctx_list *ctx;
3649 struct sysctl_oid *tree;
3650 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG)
3655 ctx = device_get_sysctl_ctx(sc->dev);
3656 tree = device_get_sysctl_tree(sc->dev);
3657 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3658 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3659 emx_sysctl_debug_info, "I", "Debug Information");
3661 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3662 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3663 emx_sysctl_stats, "I", "Statistics");
3665 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3666 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3668 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3669 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3672 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3673 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3674 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3675 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3676 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3677 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3678 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3679 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3680 emx_sysctl_tx_wreg_nsegs, "I",
3681 "# segments sent before write to hardware register");
3683 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3684 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3686 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3687 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3689 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3690 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3691 "# of TX rings used");
3693 #ifdef IFPOLL_ENABLE
3694 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3695 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3696 sc, 0, emx_sysctl_npoll_rxoff, "I",
3697 "NPOLLING RX cpu offset");
3698 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3699 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3700 sc, 0, emx_sysctl_npoll_txoff, "I",
3701 "NPOLLING TX cpu offset");
3704 #ifdef EMX_RSS_DEBUG
3705 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3706 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3707 0, "RSS debug level");
3708 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3709 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3710 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3711 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3715 #ifdef EMX_TSS_DEBUG
3716 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3717 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3718 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3719 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3726 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3728 struct emx_softc *sc = (void *)arg1;
3729 struct ifnet *ifp = &sc->arpcom.ac_if;
3730 int error, throttle;
3732 throttle = sc->int_throttle_ceil;
3733 error = sysctl_handle_int(oidp, &throttle, 0, req);
3734 if (error || req->newptr == NULL)
3736 if (throttle < 0 || throttle > 1000000000 / 256)
3741 * Set the interrupt throttling rate in 256ns increments,
3742 * recalculate sysctl value assignment to get exact frequency.
3744 throttle = 1000000000 / 256 / throttle;
3746 /* Upper 16bits of ITR is reserved and should be zero */
3747 if (throttle & 0xffff0000)
3751 ifnet_serialize_all(ifp);
3754 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3756 sc->int_throttle_ceil = 0;
3758 if (ifp->if_flags & IFF_RUNNING)
3759 emx_set_itr(sc, throttle);
3761 ifnet_deserialize_all(ifp);
3764 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3765 sc->int_throttle_ceil);
3771 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3773 struct emx_softc *sc = (void *)arg1;
3774 struct ifnet *ifp = &sc->arpcom.ac_if;
3775 struct emx_txdata *tdata = &sc->tx_data[0];
3778 segs = tdata->tx_intr_nsegs;
3779 error = sysctl_handle_int(oidp, &segs, 0, req);
3780 if (error || req->newptr == NULL)
3785 ifnet_serialize_all(ifp);
3788 * Don't allow tx_intr_nsegs to become:
3789 * o Less the oact_tx_desc
3790 * o Too large that no TX desc will cause TX interrupt to
3791 * be generated (OACTIVE will never recover)
3792 * o Too small that will cause tx_dd[] overflow
3794 if (segs < tdata->oact_tx_desc ||
3795 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3796 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
3802 for (i = 0; i < sc->tx_ring_cnt; ++i)
3803 sc->tx_data[i].tx_intr_nsegs = segs;
3806 ifnet_deserialize_all(ifp);
3812 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3814 struct emx_softc *sc = (void *)arg1;
3815 struct ifnet *ifp = &sc->arpcom.ac_if;
3816 int error, nsegs, i;
3818 nsegs = sc->tx_data[0].tx_wreg_nsegs;
3819 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3820 if (error || req->newptr == NULL)
3823 ifnet_serialize_all(ifp);
3824 for (i = 0; i < sc->tx_ring_cnt; ++i)
3825 sc->tx_data[i].tx_wreg_nsegs =nsegs;
3826 ifnet_deserialize_all(ifp);
3831 #ifdef IFPOLL_ENABLE
3834 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3836 struct emx_softc *sc = (void *)arg1;
3837 struct ifnet *ifp = &sc->arpcom.ac_if;
3840 off = sc->rx_npoll_off;
3841 error = sysctl_handle_int(oidp, &off, 0, req);
3842 if (error || req->newptr == NULL)
3847 ifnet_serialize_all(ifp);
3848 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3852 sc->rx_npoll_off = off;
3854 ifnet_deserialize_all(ifp);
3860 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3862 struct emx_softc *sc = (void *)arg1;
3863 struct ifnet *ifp = &sc->arpcom.ac_if;
3866 off = sc->tx_npoll_off;
3867 error = sysctl_handle_int(oidp, &off, 0, req);
3868 if (error || req->newptr == NULL)
3873 ifnet_serialize_all(ifp);
3874 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3878 sc->tx_npoll_off = off;
3880 ifnet_deserialize_all(ifp);
3885 #endif /* IFPOLL_ENABLE */
3888 emx_dma_alloc(struct emx_softc *sc)
3893 * Create top level busdma tag
3895 error = bus_dma_tag_create(NULL, 1, 0,
3896 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3898 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3899 0, &sc->parent_dtag);
3901 device_printf(sc->dev, "could not create top level DMA tag\n");
3906 * Allocate transmit descriptors ring and buffers
3908 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3909 error = emx_create_tx_ring(&sc->tx_data[i]);
3911 device_printf(sc->dev,
3912 "Could not setup transmit structures\n");
3918 * Allocate receive descriptors ring and buffers
3920 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3921 error = emx_create_rx_ring(&sc->rx_data[i]);
3923 device_printf(sc->dev,
3924 "Could not setup receive structures\n");
3932 emx_dma_free(struct emx_softc *sc)
3936 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3937 emx_destroy_tx_ring(&sc->tx_data[i],
3938 sc->tx_data[i].num_tx_desc);
3941 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3942 emx_destroy_rx_ring(&sc->rx_data[i],
3943 sc->rx_data[i].num_rx_desc);
3946 /* Free top level busdma tag */
3947 if (sc->parent_dtag != NULL)
3948 bus_dma_tag_destroy(sc->parent_dtag);
3952 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3954 struct emx_softc *sc = ifp->if_softc;
3956 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz);
3960 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3962 struct emx_softc *sc = ifp->if_softc;
3964 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz);
3968 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3970 struct emx_softc *sc = ifp->if_softc;
3972 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz);
3976 emx_serialize_skipmain(struct emx_softc *sc)
3978 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3982 emx_deserialize_skipmain(struct emx_softc *sc)
3984 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3990 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3991 boolean_t serialized)
3993 struct emx_softc *sc = ifp->if_softc;
3995 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3999 #endif /* INVARIANTS */
4001 #ifdef IFPOLL_ENABLE
4004 emx_npoll_status(struct ifnet *ifp)
4006 struct emx_softc *sc = ifp->if_softc;
4009 ASSERT_SERIALIZED(&sc->main_serialize);
4011 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4012 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4013 callout_stop(&sc->timer);
4014 sc->hw.mac.get_link_status = 1;
4015 emx_update_link_status(sc);
4016 callout_reset(&sc->timer, hz, emx_timer, sc);
4021 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
4023 struct emx_txdata *tdata = arg;
4025 ASSERT_SERIALIZED(&tdata->tx_serialize);
4028 if (!ifsq_is_empty(tdata->ifsq))
4029 ifsq_devstart(tdata->ifsq);
4033 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
4035 struct emx_rxdata *rdata = arg;
4037 ASSERT_SERIALIZED(&rdata->rx_serialize);
4039 emx_rxeof(rdata, cycle);
4043 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
4045 struct emx_softc *sc = ifp->if_softc;
4048 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4053 info->ifpi_status.status_func = emx_npoll_status;
4054 info->ifpi_status.serializer = &sc->main_serialize;
4056 txr_cnt = emx_get_txring_inuse(sc, TRUE);
4057 off = sc->tx_npoll_off;
4058 for (i = 0; i < txr_cnt; ++i) {
4059 struct emx_txdata *tdata = &sc->tx_data[i];
4062 KKASSERT(idx < ncpus2);
4063 info->ifpi_tx[idx].poll_func = emx_npoll_tx;
4064 info->ifpi_tx[idx].arg = tdata;
4065 info->ifpi_tx[idx].serializer = &tdata->tx_serialize;
4066 ifsq_set_cpuid(tdata->ifsq, idx);
4069 off = sc->rx_npoll_off;
4070 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4071 struct emx_rxdata *rdata = &sc->rx_data[i];
4074 KKASSERT(idx < ncpus2);
4075 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
4076 info->ifpi_rx[idx].arg = rdata;
4077 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
4080 if (ifp->if_flags & IFF_RUNNING) {
4081 if (txr_cnt == sc->tx_ring_inuse)
4082 emx_disable_intr(sc);
4087 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4088 struct emx_txdata *tdata = &sc->tx_data[i];
4090 ifsq_set_cpuid(tdata->ifsq,
4091 rman_get_cpuid(sc->intr_res));
4094 if (ifp->if_flags & IFF_RUNNING) {
4095 txr_cnt = emx_get_txring_inuse(sc, FALSE);
4096 if (txr_cnt == sc->tx_ring_inuse)
4097 emx_enable_intr(sc);
4104 #endif /* IFPOLL_ENABLE */
4107 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4109 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4110 if (sc->hw.mac.type == e1000_82574) {
4114 * When using MSIX interrupts we need to
4115 * throttle using the EITR register
4117 for (i = 0; i < 4; ++i)
4118 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4123 * Disable the L0s, 82574L Errata #20
4126 emx_disable_aspm(struct emx_softc *sc)
4128 uint16_t link_cap, link_ctrl, disable;
4129 uint8_t pcie_ptr, reg;
4130 device_t dev = sc->dev;
4132 switch (sc->hw.mac.type) {
4137 * 82573 specification update
4138 * errata #8 disable L0s
4139 * errata #41 disable L1
4141 * 82571/82572 specification update
4142 # errata #13 disable L1
4143 * errata #68 disable L0s
4145 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4150 * 82574 specification update errata #20
4152 * There is no need to disable L1
4154 disable = PCIEM_LNKCTL_ASPM_L0S;
4161 pcie_ptr = pci_get_pciecap_ptr(dev);
4165 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4166 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4170 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4172 reg = pcie_ptr + PCIER_LINKCTRL;
4173 link_ctrl = pci_read_config(dev, reg, 2);
4174 link_ctrl &= ~disable;
4175 pci_write_config(dev, reg, link_ctrl, 2);
4179 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4181 int iphlen, hoff, thoff, ex = 0;
4186 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4188 iphlen = m->m_pkthdr.csum_iphlen;
4189 thoff = m->m_pkthdr.csum_thlen;
4190 hoff = m->m_pkthdr.csum_lhlen;
4192 KASSERT(iphlen > 0, ("invalid ip hlen"));
4193 KASSERT(thoff > 0, ("invalid tcp hlen"));
4194 KASSERT(hoff > 0, ("invalid ether hlen"));
4196 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4199 if (m->m_len < hoff + iphlen + thoff + ex) {
4200 m = m_pullup(m, hoff + iphlen + thoff + ex);
4207 ip = mtodoff(m, struct ip *, hoff);
4214 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4215 uint32_t *txd_upper, uint32_t *txd_lower)
4217 struct e1000_context_desc *TXD;
4218 int hoff, iphlen, thoff, hlen;
4219 int mss, pktlen, curr_txd;
4221 #ifdef EMX_TSO_DEBUG
4222 tdata->tso_segments++;
4225 iphlen = mp->m_pkthdr.csum_iphlen;
4226 thoff = mp->m_pkthdr.csum_thlen;
4227 hoff = mp->m_pkthdr.csum_lhlen;
4228 mss = mp->m_pkthdr.tso_segsz;
4229 pktlen = mp->m_pkthdr.len;
4231 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4232 tdata->csum_flags == CSUM_TSO &&
4233 tdata->csum_iphlen == iphlen &&
4234 tdata->csum_lhlen == hoff &&
4235 tdata->csum_thlen == thoff &&
4236 tdata->csum_mss == mss &&
4237 tdata->csum_pktlen == pktlen) {
4238 *txd_upper = tdata->csum_txd_upper;
4239 *txd_lower = tdata->csum_txd_lower;
4240 #ifdef EMX_TSO_DEBUG
4241 tdata->tso_ctx_reused++;
4245 hlen = hoff + iphlen + thoff;
4248 * Setup a new TSO context.
4251 curr_txd = tdata->next_avail_tx_desc;
4252 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4254 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4255 E1000_TXD_DTYP_D | /* Data descr type */
4256 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4258 /* IP and/or TCP header checksum calculation and insertion. */
4259 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4262 * Start offset for header checksum calculation.
4263 * End offset for header checksum calculation.
4264 * Offset of place put the checksum.
4266 TXD->lower_setup.ip_fields.ipcss = hoff;
4267 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4268 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4271 * Start offset for payload checksum calculation.
4272 * End offset for payload checksum calculation.
4273 * Offset of place to put the checksum.
4275 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4276 TXD->upper_setup.tcp_fields.tucse = 0;
4277 TXD->upper_setup.tcp_fields.tucso =
4278 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4281 * Payload size per packet w/o any headers.
4282 * Length of all headers up to payload.
4284 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4285 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4286 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4287 E1000_TXD_CMD_DEXT | /* Extended descr */
4288 E1000_TXD_CMD_TSE | /* TSE context */
4289 E1000_TXD_CMD_IP | /* Do IP csum */
4290 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4291 (pktlen - hlen)); /* Total len */
4293 /* Save the information for this TSO context */
4294 tdata->csum_flags = CSUM_TSO;
4295 tdata->csum_lhlen = hoff;
4296 tdata->csum_iphlen = iphlen;
4297 tdata->csum_thlen = thoff;
4298 tdata->csum_mss = mss;
4299 tdata->csum_pktlen = pktlen;
4300 tdata->csum_txd_upper = *txd_upper;
4301 tdata->csum_txd_lower = *txd_lower;
4303 if (++curr_txd == tdata->num_tx_desc)
4306 KKASSERT(tdata->num_tx_desc_avail > 0);
4307 tdata->num_tx_desc_avail--;
4309 tdata->next_avail_tx_desc = curr_txd;
4314 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4317 return sc->tx_ring_cnt;