8849680c7076b5970f15144b82f66c5c52ab26bf
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
1 /*-
2  * Copyright (c) 2006-2007 Broadcom Corporation
3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15  *    may be used to endorse or promote products derived from this software
16  *    without specific prior written consent.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28  * THE POSSIBILITY OF SUCH DAMAGE.
29  *
30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
31  */
32
33 /*
34  * The following controllers are supported by this driver:
35  *   BCM5706C A2, A3
36  *   BCM5706S A2, A3
37  *   BCM5708C B1, B2
38  *   BCM5708S B1, B2
39  *   BCM5709C A1, C0
40  *   BCM5716  C0
41  *
42  * The following controllers are not supported by this driver:
43  *   BCM5706C A0, A1
44  *   BCM5706S A0, A1
45  *   BCM5708C A0, B0
46  *   BCM5708S A0, B0
47  *   BCM5709C A0, B0, B1
48  *   BCM5709S A0, A1, B0, B1, B2, C0
49  */
50
51 #include "opt_bce.h"
52 #include "opt_polling.h"
53
54 #include <sys/param.h>
55 #include <sys/bus.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
59 #include <sys/mbuf.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
62 #ifdef BCE_DEBUG
63 #include <sys/random.h>
64 #endif
65 #include <sys/rman.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
70
71 #include <net/bpf.h>
72 #include <net/ethernet.h>
73 #include <net/if.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ifq_var.h>
79 #include <net/vlan/if_vlan_var.h>
80 #include <net/vlan/if_vlan_ether.h>
81
82 #include <dev/netif/mii_layer/mii.h>
83 #include <dev/netif/mii_layer/miivar.h>
84
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87
88 #include "miibus_if.h"
89
90 #include <dev/netif/bce/if_bcereg.h>
91 #include <dev/netif/bce/if_bcefw.h>
92
93 /****************************************************************************/
94 /* BCE Debug Options                                                        */
95 /****************************************************************************/
96 #ifdef BCE_DEBUG
97
98 static uint32_t bce_debug = BCE_WARN;
99
100 /*
101  *          0 = Never             
102  *          1 = 1 in 2,147,483,648
103  *        256 = 1 in     8,388,608
104  *       2048 = 1 in     1,048,576
105  *      65536 = 1 in        32,768
106  *    1048576 = 1 in         2,048
107  *  268435456 = 1 in             8
108  *  536870912 = 1 in             4
109  * 1073741824 = 1 in             2
110  *
111  * bce_debug_l2fhdr_status_check:
112  *     How often the l2_fhdr frame error check will fail.
113  *
114  * bce_debug_unexpected_attention:
115  *     How often the unexpected attention check will fail.
116  *
117  * bce_debug_mbuf_allocation_failure:
118  *     How often to simulate an mbuf allocation failure.
119  *
120  * bce_debug_dma_map_addr_failure:
121  *     How often to simulate a DMA mapping failure.
122  *
123  * bce_debug_bootcode_running_failure:
124  *     How often to simulate a bootcode failure.
125  */
126 static int      bce_debug_l2fhdr_status_check = 0;
127 static int      bce_debug_unexpected_attention = 0;
128 static int      bce_debug_mbuf_allocation_failure = 0;
129 static int      bce_debug_dma_map_addr_failure = 0;
130 static int      bce_debug_bootcode_running_failure = 0;
131
132 #endif  /* BCE_DEBUG */
133
134
135 /****************************************************************************/
136 /* PCI Device ID Table                                                      */
137 /*                                                                          */
138 /* Used by bce_probe() to identify the devices supported by this driver.    */
139 /****************************************************************************/
140 #define BCE_DEVDESC_MAX         64
141
142 static struct bce_type bce_devs[] = {
143         /* BCM5706C Controllers and OEM boards. */
144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
145                 "HP NC370T Multifunction Gigabit Server Adapter" },
146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
147                 "HP NC370i Multifunction Gigabit Server Adapter" },
148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
149                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
151                 "HP NC371i Multifunction Gigabit Server Adapter" },
152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
153                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
154
155         /* BCM5706S controllers and OEM boards. */
156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
157                 "HP NC370F Multifunction Gigabit Server Adapter" },
158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
159                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
160
161         /* BCM5708C controllers and OEM boards. */
162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
163                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
165                 "HP NC373i Multifunction Gigabit Server Adapter" },
166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
167                 "HP NC374m PCIe Multifunction Adapter" },
168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
169                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
170
171         /* BCM5708S controllers and OEM boards. */
172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
173                 "HP NC373m Multifunction Gigabit Server Adapter" },
174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
175                 "HP NC373i Multifunction Gigabit Server Adapter" },
176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
177                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
179                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
180
181         /* BCM5709C controllers and OEM boards. */
182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
183                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
185                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
187                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
188
189         /* BCM5709S controllers and OEM boards. */
190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
191                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
193                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
195                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
196
197         /* BCM5716 controllers and OEM boards. */
198         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
199                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
200
201         { 0, 0, 0, 0, NULL }
202 };
203
204
205 /****************************************************************************/
206 /* Supported Flash NVRAM device data.                                       */
207 /****************************************************************************/
208 static const struct flash_spec flash_table[] =
209 {
210 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
211 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
212
213         /* Slow EEPROM */
214         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
215          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
216          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
217          "EEPROM - slow"},
218         /* Expansion entry 0001 */
219         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
220          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
221          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
222          "Entry 0001"},
223         /* Saifun SA25F010 (non-buffered flash) */
224         /* strap, cfg1, & write1 need updates */
225         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
226          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
227          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
228          "Non-buffered flash (128kB)"},
229         /* Saifun SA25F020 (non-buffered flash) */
230         /* strap, cfg1, & write1 need updates */
231         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
232          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
233          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
234          "Non-buffered flash (256kB)"},
235         /* Expansion entry 0100 */
236         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
237          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
238          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
239          "Entry 0100"},
240         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
241         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
242          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
243          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
244          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
245         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
246         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
247          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
248          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
249          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
250         /* Saifun SA25F005 (non-buffered flash) */
251         /* strap, cfg1, & write1 need updates */
252         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
253          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
254          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
255          "Non-buffered flash (64kB)"},
256         /* Fast EEPROM */
257         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
258          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
259          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
260          "EEPROM - fast"},
261         /* Expansion entry 1001 */
262         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
263          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
264          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
265          "Entry 1001"},
266         /* Expansion entry 1010 */
267         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
268          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
269          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
270          "Entry 1010"},
271         /* ATMEL AT45DB011B (buffered flash) */
272         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
273          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
274          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
275          "Buffered flash (128kB)"},
276         /* Expansion entry 1100 */
277         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
278          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
279          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
280          "Entry 1100"},
281         /* Expansion entry 1101 */
282         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
283          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
284          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
285          "Entry 1101"},
286         /* Ateml Expansion entry 1110 */
287         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
288          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
289          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
290          "Entry 1110 (Atmel)"},
291         /* ATMEL AT45DB021B (buffered flash) */
292         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
293          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
294          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
295          "Buffered flash (256kB)"},
296 };
297
298 /*
299  * The BCM5709 controllers transparently handle the
300  * differences between Atmel 264 byte pages and all
301  * flash devices which use 256 byte pages, so no
302  * logical-to-physical mapping is required in the
303  * driver.
304  */
305 static struct flash_spec flash_5709 = {
306         .flags          = BCE_NV_BUFFERED,
307         .page_bits      = BCM5709_FLASH_PAGE_BITS,
308         .page_size      = BCM5709_FLASH_PAGE_SIZE,
309         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
310         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
311         .name           = "5709/5716 buffered flash (256kB)",
312 };
313
314
315 /****************************************************************************/
316 /* DragonFly device entry points.                                           */
317 /****************************************************************************/
318 static int      bce_probe(device_t);
319 static int      bce_attach(device_t);
320 static int      bce_detach(device_t);
321 static void     bce_shutdown(device_t);
322
323 /****************************************************************************/
324 /* BCE Debug Data Structure Dump Routines                                   */
325 /****************************************************************************/
326 #ifdef BCE_DEBUG
327 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
328 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
329 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
330 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
331 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
332 static void     bce_dump_l2fhdr(struct bce_softc *, int,
333                                 struct l2_fhdr *) __unused;
334 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
335 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
336 static void     bce_dump_status_block(struct bce_softc *);
337 static void     bce_dump_driver_state(struct bce_softc *);
338 static void     bce_dump_stats_block(struct bce_softc *) __unused;
339 static void     bce_dump_hw_state(struct bce_softc *);
340 static void     bce_dump_txp_state(struct bce_softc *);
341 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
342 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
343 static void     bce_freeze_controller(struct bce_softc *) __unused;
344 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
345 static void     bce_breakpoint(struct bce_softc *);
346 #endif  /* BCE_DEBUG */
347
348
349 /****************************************************************************/
350 /* BCE Register/Memory Access Routines                                      */
351 /****************************************************************************/
352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
353 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
354 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
355 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
356 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
357 static int      bce_miibus_read_reg(device_t, int, int);
358 static int      bce_miibus_write_reg(device_t, int, int, int);
359 static void     bce_miibus_statchg(device_t);
360
361
362 /****************************************************************************/
363 /* BCE NVRAM Access Routines                                                */
364 /****************************************************************************/
365 static int      bce_acquire_nvram_lock(struct bce_softc *);
366 static int      bce_release_nvram_lock(struct bce_softc *);
367 static void     bce_enable_nvram_access(struct bce_softc *);
368 static void     bce_disable_nvram_access(struct bce_softc *);
369 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
370                                      uint32_t);
371 static int      bce_init_nvram(struct bce_softc *);
372 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
373 static int      bce_nvram_test(struct bce_softc *);
374
375 /****************************************************************************/
376 /* BCE DMA Allocate/Free Routines                                           */
377 /****************************************************************************/
378 static int      bce_dma_alloc(struct bce_softc *);
379 static void     bce_dma_free(struct bce_softc *);
380 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
381
382 /****************************************************************************/
383 /* BCE Firmware Synchronization and Load                                    */
384 /****************************************************************************/
385 static int      bce_fw_sync(struct bce_softc *, uint32_t);
386 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
387                                  uint32_t, uint32_t);
388 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
389                                 struct fw_info *);
390 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
391 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
392 static void     bce_start_rxp_cpu(struct bce_softc *);
393 static void     bce_init_rxp_cpu(struct bce_softc *);
394 static void     bce_init_txp_cpu(struct bce_softc *);
395 static void     bce_init_tpat_cpu(struct bce_softc *);
396 static void     bce_init_cp_cpu(struct bce_softc *);
397 static void     bce_init_com_cpu(struct bce_softc *);
398 static void     bce_init_cpus(struct bce_softc *);
399
400 static void     bce_stop(struct bce_softc *);
401 static int      bce_reset(struct bce_softc *, uint32_t);
402 static int      bce_chipinit(struct bce_softc *);
403 static int      bce_blockinit(struct bce_softc *);
404 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
405                                uint32_t *, int);
406 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
407 static void     bce_probe_pci_caps(struct bce_softc *);
408 static void     bce_print_adapter_info(struct bce_softc *);
409 static void     bce_get_media(struct bce_softc *);
410
411 static void     bce_init_tx_context(struct bce_softc *);
412 static int      bce_init_tx_chain(struct bce_softc *);
413 static void     bce_init_rx_context(struct bce_softc *);
414 static int      bce_init_rx_chain(struct bce_softc *);
415 static void     bce_free_rx_chain(struct bce_softc *);
416 static void     bce_free_tx_chain(struct bce_softc *);
417
418 static int      bce_encap(struct bce_softc *, struct mbuf **);
419 static void     bce_start(struct ifnet *);
420 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
421 static void     bce_watchdog(struct ifnet *);
422 static int      bce_ifmedia_upd(struct ifnet *);
423 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
424 static void     bce_init(void *);
425 static void     bce_mgmt_init(struct bce_softc *);
426
427 static int      bce_init_ctx(struct bce_softc *);
428 static void     bce_get_mac_addr(struct bce_softc *);
429 static void     bce_set_mac_addr(struct bce_softc *);
430 static void     bce_phy_intr(struct bce_softc *);
431 static void     bce_rx_intr(struct bce_softc *, int);
432 static void     bce_tx_intr(struct bce_softc *);
433 static void     bce_disable_intr(struct bce_softc *);
434 static void     bce_enable_intr(struct bce_softc *, int);
435
436 #ifdef DEVICE_POLLING
437 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
438 #endif
439 static void     bce_intr(void *);
440 static void     bce_set_rx_mode(struct bce_softc *);
441 static void     bce_stats_update(struct bce_softc *);
442 static void     bce_tick(void *);
443 static void     bce_tick_serialized(struct bce_softc *);
444 static void     bce_pulse(void *);
445 static void     bce_add_sysctls(struct bce_softc *);
446
447 static void     bce_coal_change(struct bce_softc *);
448 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
449 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
450 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
451 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
452 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
453 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
454 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
455 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
456 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
457                                        uint32_t *, uint32_t);
458
459 /*
460  * NOTE:
461  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
462  * takes 1023 as the TX ticks limit.  However, using 1023 will
463  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
464  * there is _no_ network activity on the NIC.
465  */
466 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
467 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
468 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
469 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
470 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
471 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
472 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
473 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
474
475 static int      bce_msi_enable = 1;
476
477 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
478 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
479 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
480 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
481 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
482 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
483 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
484 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
485 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
486
487 /****************************************************************************/
488 /* DragonFly device dispatch table.                                         */
489 /****************************************************************************/
490 static device_method_t bce_methods[] = {
491         /* Device interface */
492         DEVMETHOD(device_probe,         bce_probe),
493         DEVMETHOD(device_attach,        bce_attach),
494         DEVMETHOD(device_detach,        bce_detach),
495         DEVMETHOD(device_shutdown,      bce_shutdown),
496
497         /* bus interface */
498         DEVMETHOD(bus_print_child,      bus_generic_print_child),
499         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
500
501         /* MII interface */
502         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
503         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
504         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
505
506         { 0, 0 }
507 };
508
509 static driver_t bce_driver = {
510         "bce",
511         bce_methods,
512         sizeof(struct bce_softc)
513 };
514
515 static devclass_t bce_devclass;
516
517
518 DECLARE_DUMMY_MODULE(if_bce);
519 MODULE_DEPEND(bce, miibus, 1, 1, 1);
520 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
521 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
522
523
524 /****************************************************************************/
525 /* Device probe function.                                                   */
526 /*                                                                          */
527 /* Compares the device to the driver's list of supported devices and        */
528 /* reports back to the OS whether this is the right driver for the device.  */
529 /*                                                                          */
530 /* Returns:                                                                 */
531 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
532 /****************************************************************************/
533 static int
534 bce_probe(device_t dev)
535 {
536         struct bce_type *t;
537         uint16_t vid, did, svid, sdid;
538
539         /* Get the data for the device to be probed. */
540         vid  = pci_get_vendor(dev);
541         did  = pci_get_device(dev);
542         svid = pci_get_subvendor(dev);
543         sdid = pci_get_subdevice(dev);
544
545         /* Look through the list of known devices for a match. */
546         for (t = bce_devs; t->bce_name != NULL; ++t) {
547                 if (vid == t->bce_vid && did == t->bce_did && 
548                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
549                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
550                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
551                         char *descbuf;
552
553                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
554
555                         /* Print out the device identity. */
556                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
557                                   t->bce_name,
558                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
559
560                         device_set_desc_copy(dev, descbuf);
561                         kfree(descbuf, M_TEMP);
562                         return 0;
563                 }
564         }
565         return ENXIO;
566 }
567
568
569 /****************************************************************************/
570 /* PCI Capabilities Probe Function.                                         */
571 /*                                                                          */
572 /* Walks the PCI capabiites list for the device to find what features are   */
573 /* supported.                                                               */
574 /*                                                                          */
575 /* Returns:                                                                 */
576 /*   None.                                                                  */
577 /****************************************************************************/
578 static void
579 bce_print_adapter_info(struct bce_softc *sc)
580 {
581         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
582
583         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
584                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
585
586         /* Bus info. */
587         if (sc->bce_flags & BCE_PCIE_FLAG) {
588                 kprintf("Bus (PCIe x%d, ", sc->link_width);
589                 switch (sc->link_speed) {
590                 case 1:
591                         kprintf("2.5Gbps); ");
592                         break;
593                 case 2:
594                         kprintf("5Gbps); ");
595                         break;
596                 default:
597                         kprintf("Unknown link speed); ");
598                         break;
599                 }
600         } else {
601                 kprintf("Bus (PCI%s, %s, %dMHz); ",
602                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
603                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
604                     sc->bus_speed_mhz);
605         }
606
607         /* Firmware version and device features. */
608         kprintf("B/C (%s)", sc->bce_bc_ver);
609
610         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
611             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
612                 kprintf("; Flags(");
613                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
614                         kprintf("MFW[%s]", sc->bce_mfw_ver);
615                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
616                         kprintf(" 2.5G");
617                 kprintf(")");
618         }
619         kprintf("\n");
620 }
621
622
623 /****************************************************************************/
624 /* PCI Capabilities Probe Function.                                         */
625 /*                                                                          */
626 /* Walks the PCI capabiites list for the device to find what features are   */
627 /* supported.                                                               */
628 /*                                                                          */
629 /* Returns:                                                                 */
630 /*   None.                                                                  */
631 /****************************************************************************/
632 static void
633 bce_probe_pci_caps(struct bce_softc *sc)
634 {
635         device_t dev = sc->bce_dev;
636         uint8_t ptr;
637
638         if (pci_is_pcix(dev))
639                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
640
641         ptr = pci_get_pciecap_ptr(dev);
642         if (ptr) {
643                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
644
645                 sc->link_speed = link_status & 0xf;
646                 sc->link_width = (link_status >> 4) & 0x3f;
647                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
648                 sc->bce_flags |= BCE_PCIE_FLAG;
649         }
650 }
651
652
653 /****************************************************************************/
654 /* Device attach function.                                                  */
655 /*                                                                          */
656 /* Allocates device resources, performs secondary chip identification,      */
657 /* resets and initializes the hardware, and initializes driver instance     */
658 /* variables.                                                               */
659 /*                                                                          */
660 /* Returns:                                                                 */
661 /*   0 on success, positive value on failure.                               */
662 /****************************************************************************/
663 static int
664 bce_attach(device_t dev)
665 {
666         struct bce_softc *sc = device_get_softc(dev);
667         struct ifnet *ifp = &sc->arpcom.ac_if;
668         uint32_t val;
669         u_int irq_flags;
670         int rid, rc = 0;
671         int i, j;
672
673         sc->bce_dev = dev;
674         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
675
676         pci_enable_busmaster(dev);
677
678         bce_probe_pci_caps(sc);
679
680         /* Allocate PCI memory resources. */
681         rid = PCIR_BAR(0);
682         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
683                                                  RF_ACTIVE | PCI_RF_DENSE);
684         if (sc->bce_res_mem == NULL) {
685                 device_printf(dev, "PCI memory allocation failed\n");
686                 return ENXIO;
687         }
688         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
689         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
690
691         /* Allocate PCI IRQ resources. */
692         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
693             &sc->bce_irq_rid, &irq_flags);
694
695         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
696             &sc->bce_irq_rid, irq_flags);
697         if (sc->bce_res_irq == NULL) {
698                 device_printf(dev, "PCI map interrupt failed\n");
699                 rc = ENXIO;
700                 goto fail;
701         }
702
703         /*
704          * Configure byte swap and enable indirect register access.
705          * Rely on CPU to do target byte swapping on big endian systems.
706          * Access to registers outside of PCI configurtion space are not
707          * valid until this is done.
708          */
709         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
710                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
711                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
712
713         /* Save ASIC revsion info. */
714         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
715
716         /* Weed out any non-production controller revisions. */
717         switch (BCE_CHIP_ID(sc)) {
718         case BCE_CHIP_ID_5706_A0:
719         case BCE_CHIP_ID_5706_A1:
720         case BCE_CHIP_ID_5708_A0:
721         case BCE_CHIP_ID_5708_B0:
722         case BCE_CHIP_ID_5709_A0:
723         case BCE_CHIP_ID_5709_B0:
724         case BCE_CHIP_ID_5709_B1:
725 #ifdef foo
726         /* 5709C B2 seems to work fine */
727         case BCE_CHIP_ID_5709_B2:
728 #endif
729                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
730                               BCE_CHIP_ID(sc));
731                 rc = ENODEV;
732                 goto fail;
733         }
734
735         /*
736          * Find the base address for shared memory access.
737          * Newer versions of bootcode use a signature and offset
738          * while older versions use a fixed address.
739          */
740         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
741         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
742             BCE_SHM_HDR_SIGNATURE_SIG) {
743                 /* Multi-port devices use different offsets in shared memory. */
744                 sc->bce_shmem_base = REG_RD_IND(sc,
745                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
746         } else {
747                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
748         }
749         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
750
751         /* Fetch the bootcode revision. */
752         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
753         for (i = 0, j = 0; i < 3; i++) {
754                 uint8_t num;
755                 int k, skip0;
756
757                 num = (uint8_t)(val >> (24 - (i * 8)));
758                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
759                         if (num >= k || !skip0 || k == 1) {
760                                 sc->bce_bc_ver[j++] = (num / k) + '0';
761                                 skip0 = 0;
762                         }
763                 }
764                 if (i != 2)
765                         sc->bce_bc_ver[j++] = '.';
766         }
767
768         /* Check if any management firwmare is running. */
769         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
770         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
771                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
772
773                 /* Allow time for firmware to enter the running state. */
774                 for (i = 0; i < 30; i++) {
775                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
776                         if (val & BCE_CONDITION_MFW_RUN_MASK)
777                                 break;
778                         DELAY(10000);
779                 }
780         }
781
782         /* Check the current bootcode state. */
783         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
784             BCE_CONDITION_MFW_RUN_MASK;
785         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
786             val != BCE_CONDITION_MFW_RUN_NONE) {
787                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
788
789                 for (i = 0, j = 0; j < 3; j++) {
790                         val = bce_reg_rd_ind(sc, addr + j * 4);
791                         val = bswap32(val);
792                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
793                         i += 4;
794                 }
795         }
796
797         /* Get PCI bus information (speed and type). */
798         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
799         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
800                 uint32_t clkreg;
801
802                 sc->bce_flags |= BCE_PCIX_FLAG;
803
804                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
805                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
806                 switch (clkreg) {
807                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
808                         sc->bus_speed_mhz = 133;
809                         break;
810
811                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
812                         sc->bus_speed_mhz = 100;
813                         break;
814
815                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
816                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
817                         sc->bus_speed_mhz = 66;
818                         break;
819
820                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
821                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
822                         sc->bus_speed_mhz = 50;
823                         break;
824
825                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
826                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
827                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
828                         sc->bus_speed_mhz = 33;
829                         break;
830                 }
831         } else {
832                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
833                         sc->bus_speed_mhz = 66;
834                 else
835                         sc->bus_speed_mhz = 33;
836         }
837
838         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
839                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
840
841         /* Reset the controller. */
842         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
843         if (rc != 0)
844                 goto fail;
845
846         /* Initialize the controller. */
847         rc = bce_chipinit(sc);
848         if (rc != 0) {
849                 device_printf(dev, "Controller initialization failed!\n");
850                 goto fail;
851         }
852
853         /* Perform NVRAM test. */
854         rc = bce_nvram_test(sc);
855         if (rc != 0) {
856                 device_printf(dev, "NVRAM test failed!\n");
857                 goto fail;
858         }
859
860         /* Fetch the permanent Ethernet MAC address. */
861         bce_get_mac_addr(sc);
862
863         /*
864          * Trip points control how many BDs
865          * should be ready before generating an
866          * interrupt while ticks control how long
867          * a BD can sit in the chain before
868          * generating an interrupt.  Set the default 
869          * values for the RX and TX rings.
870          */
871
872 #ifdef BCE_DRBUG
873         /* Force more frequent interrupts. */
874         sc->bce_tx_quick_cons_trip_int = 1;
875         sc->bce_tx_quick_cons_trip     = 1;
876         sc->bce_tx_ticks_int           = 0;
877         sc->bce_tx_ticks               = 0;
878
879         sc->bce_rx_quick_cons_trip_int = 1;
880         sc->bce_rx_quick_cons_trip     = 1;
881         sc->bce_rx_ticks_int           = 0;
882         sc->bce_rx_ticks               = 0;
883 #else
884         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
885         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
886         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
887         sc->bce_tx_ticks               = bce_tx_ticks;
888
889         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
890         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
891         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
892         sc->bce_rx_ticks               = bce_rx_ticks;
893 #endif
894
895         /* Update statistics once every second. */
896         sc->bce_stats_ticks = 1000000 & 0xffff00;
897
898         /* Find the media type for the adapter. */
899         bce_get_media(sc);
900
901         /* Allocate DMA memory resources. */
902         rc = bce_dma_alloc(sc);
903         if (rc != 0) {
904                 device_printf(dev, "DMA resource allocation failed!\n");
905                 goto fail;
906         }
907
908         /* Initialize the ifnet interface. */
909         ifp->if_softc = sc;
910         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
911         ifp->if_ioctl = bce_ioctl;
912         ifp->if_start = bce_start;
913         ifp->if_init = bce_init;
914         ifp->if_watchdog = bce_watchdog;
915 #ifdef DEVICE_POLLING
916         ifp->if_poll = bce_poll;
917 #endif
918         ifp->if_mtu = ETHERMTU;
919         ifp->if_hwassist = BCE_IF_HWASSIST;
920         ifp->if_capabilities = BCE_IF_CAPABILITIES;
921         ifp->if_capenable = ifp->if_capabilities;
922         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
923         ifq_set_ready(&ifp->if_snd);
924
925         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
926                 ifp->if_baudrate = IF_Gbps(2.5);
927         else
928                 ifp->if_baudrate = IF_Gbps(1);
929
930         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
931         sc->mbuf_alloc_size  = MCLBYTES;
932
933         /* Look for our PHY. */
934         rc = mii_phy_probe(dev, &sc->bce_miibus,
935                            bce_ifmedia_upd, bce_ifmedia_sts);
936         if (rc != 0) {
937                 device_printf(dev, "PHY probe failed!\n");
938                 goto fail;
939         }
940
941         /* Attach to the Ethernet interface list. */
942         ether_ifattach(ifp, sc->eaddr, NULL);
943
944         callout_init_mp(&sc->bce_tick_callout);
945         callout_init_mp(&sc->bce_pulse_callout);
946
947         /* Hookup IRQ last. */
948         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
949                             &sc->bce_intrhand, ifp->if_serializer);
950         if (rc != 0) {
951                 device_printf(dev, "Failed to setup IRQ!\n");
952                 ether_ifdetach(ifp);
953                 goto fail;
954         }
955
956         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
957         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
958
959         /* Print some important debugging info. */
960         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
961
962         /* Add the supported sysctls to the kernel. */
963         bce_add_sysctls(sc);
964
965         /*
966          * The chip reset earlier notified the bootcode that
967          * a driver is present.  We now need to start our pulse
968          * routine so that the bootcode is reminded that we're
969          * still running.
970          */
971         bce_pulse(sc);
972
973         /* Get the firmware running so IPMI still works */
974         bce_mgmt_init(sc);
975
976         if (bootverbose)
977                 bce_print_adapter_info(sc);
978
979         return 0;
980 fail:
981         bce_detach(dev);
982         return(rc);
983 }
984
985
986 /****************************************************************************/
987 /* Device detach function.                                                  */
988 /*                                                                          */
989 /* Stops the controller, resets the controller, and releases resources.     */
990 /*                                                                          */
991 /* Returns:                                                                 */
992 /*   0 on success, positive value on failure.                               */
993 /****************************************************************************/
994 static int
995 bce_detach(device_t dev)
996 {
997         struct bce_softc *sc = device_get_softc(dev);
998
999         if (device_is_attached(dev)) {
1000                 struct ifnet *ifp = &sc->arpcom.ac_if;
1001                 uint32_t msg;
1002
1003                 /* Stop and reset the controller. */
1004                 lwkt_serialize_enter(ifp->if_serializer);
1005                 callout_stop(&sc->bce_pulse_callout);
1006                 bce_stop(sc);
1007                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1008                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1009                 else
1010                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1011                 bce_reset(sc, msg);
1012                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1013                 lwkt_serialize_exit(ifp->if_serializer);
1014
1015                 ether_ifdetach(ifp);
1016         }
1017
1018         /* If we have a child device on the MII bus remove it too. */
1019         if (sc->bce_miibus)
1020                 device_delete_child(dev, sc->bce_miibus);
1021         bus_generic_detach(dev);
1022
1023         if (sc->bce_res_irq != NULL) {
1024                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1025                     sc->bce_res_irq);
1026         }
1027
1028         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1029                 pci_release_msi(dev);
1030
1031         if (sc->bce_res_mem != NULL) {
1032                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1033                                      sc->bce_res_mem);
1034         }
1035
1036         bce_dma_free(sc);
1037
1038         if (sc->bce_sysctl_tree != NULL)
1039                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1040
1041         return 0;
1042 }
1043
1044
1045 /****************************************************************************/
1046 /* Device shutdown function.                                                */
1047 /*                                                                          */
1048 /* Stops and resets the controller.                                         */
1049 /*                                                                          */
1050 /* Returns:                                                                 */
1051 /*   Nothing                                                                */
1052 /****************************************************************************/
1053 static void
1054 bce_shutdown(device_t dev)
1055 {
1056         struct bce_softc *sc = device_get_softc(dev);
1057         struct ifnet *ifp = &sc->arpcom.ac_if;
1058         uint32_t msg;
1059
1060         lwkt_serialize_enter(ifp->if_serializer);
1061         bce_stop(sc);
1062         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1063                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1064         else
1065                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1066         bce_reset(sc, msg);
1067         lwkt_serialize_exit(ifp->if_serializer);
1068 }
1069
1070
1071 /****************************************************************************/
1072 /* Indirect register read.                                                  */
1073 /*                                                                          */
1074 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1075 /* configuration space.  Using this mechanism avoids issues with posted     */
1076 /* reads but is much slower than memory-mapped I/O.                         */
1077 /*                                                                          */
1078 /* Returns:                                                                 */
1079 /*   The value of the register.                                             */
1080 /****************************************************************************/
1081 static uint32_t
1082 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1083 {
1084         device_t dev = sc->bce_dev;
1085
1086         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1087 #ifdef BCE_DEBUG
1088         {
1089                 uint32_t val;
1090                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1091                 DBPRINT(sc, BCE_EXCESSIVE,
1092                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1093                         __func__, offset, val);
1094                 return val;
1095         }
1096 #else
1097         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1098 #endif
1099 }
1100
1101
1102 /****************************************************************************/
1103 /* Indirect register write.                                                 */
1104 /*                                                                          */
1105 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1106 /* configuration space.  Using this mechanism avoids issues with posted     */
1107 /* writes but is muchh slower than memory-mapped I/O.                       */
1108 /*                                                                          */
1109 /* Returns:                                                                 */
1110 /*   Nothing.                                                               */
1111 /****************************************************************************/
1112 static void
1113 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1114 {
1115         device_t dev = sc->bce_dev;
1116
1117         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1118                 __func__, offset, val);
1119
1120         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1121         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1122 }
1123
1124
1125 /****************************************************************************/
1126 /* Shared memory write.                                                     */
1127 /*                                                                          */
1128 /* Writes NetXtreme II shared memory region.                                */
1129 /*                                                                          */
1130 /* Returns:                                                                 */
1131 /*   Nothing.                                                               */
1132 /****************************************************************************/
1133 static void
1134 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1135 {
1136         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1137 }
1138
1139
1140 /****************************************************************************/
1141 /* Shared memory read.                                                      */
1142 /*                                                                          */
1143 /* Reads NetXtreme II shared memory region.                                 */
1144 /*                                                                          */
1145 /* Returns:                                                                 */
1146 /*   The 32 bit value read.                                                 */
1147 /****************************************************************************/
1148 static u32
1149 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1150 {
1151         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1152 }
1153
1154
1155 /****************************************************************************/
1156 /* Context memory write.                                                    */
1157 /*                                                                          */
1158 /* The NetXtreme II controller uses context memory to track connection      */
1159 /* information for L2 and higher network protocols.                         */
1160 /*                                                                          */
1161 /* Returns:                                                                 */
1162 /*   Nothing.                                                               */
1163 /****************************************************************************/
1164 static void
1165 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1166     uint32_t ctx_val)
1167 {
1168         uint32_t idx, offset = ctx_offset + cid_addr;
1169         uint32_t val, retry_cnt = 5;
1170
1171         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1172             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1173                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1174                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1175
1176                 for (idx = 0; idx < retry_cnt; idx++) {
1177                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1178                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1179                                 break;
1180                         DELAY(5);
1181                 }
1182
1183                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1184                         device_printf(sc->bce_dev,
1185                             "Unable to write CTX memory: "
1186                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1187                             cid_addr, ctx_offset);
1188                 }
1189         } else {
1190                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1191                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1192         }
1193 }
1194
1195
1196 /****************************************************************************/
1197 /* PHY register read.                                                       */
1198 /*                                                                          */
1199 /* Implements register reads on the MII bus.                                */
1200 /*                                                                          */
1201 /* Returns:                                                                 */
1202 /*   The value of the register.                                             */
1203 /****************************************************************************/
1204 static int
1205 bce_miibus_read_reg(device_t dev, int phy, int reg)
1206 {
1207         struct bce_softc *sc = device_get_softc(dev);
1208         uint32_t val;
1209         int i;
1210
1211         /* Make sure we are accessing the correct PHY address. */
1212         if (phy != sc->bce_phy_addr) {
1213                 DBPRINT(sc, BCE_VERBOSE,
1214                         "Invalid PHY address %d for PHY read!\n", phy);
1215                 return 0;
1216         }
1217
1218         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1219                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1220                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1221
1222                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1223                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1224
1225                 DELAY(40);
1226         }
1227
1228         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1229               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1230               BCE_EMAC_MDIO_COMM_START_BUSY;
1231         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1232
1233         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1234                 DELAY(10);
1235
1236                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1237                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1238                         DELAY(5);
1239
1240                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1241                         val &= BCE_EMAC_MDIO_COMM_DATA;
1242                         break;
1243                 }
1244         }
1245
1246         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1247                 if_printf(&sc->arpcom.ac_if,
1248                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1249                           phy, reg);
1250                 val = 0x0;
1251         } else {
1252                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1253         }
1254
1255         DBPRINT(sc, BCE_EXCESSIVE,
1256                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1257                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1258
1259         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1260                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1261                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1262
1263                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1264                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1265
1266                 DELAY(40);
1267         }
1268         return (val & 0xffff);
1269 }
1270
1271
1272 /****************************************************************************/
1273 /* PHY register write.                                                      */
1274 /*                                                                          */
1275 /* Implements register writes on the MII bus.                               */
1276 /*                                                                          */
1277 /* Returns:                                                                 */
1278 /*   The value of the register.                                             */
1279 /****************************************************************************/
1280 static int
1281 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1282 {
1283         struct bce_softc *sc = device_get_softc(dev);
1284         uint32_t val1;
1285         int i;
1286
1287         /* Make sure we are accessing the correct PHY address. */
1288         if (phy != sc->bce_phy_addr) {
1289                 DBPRINT(sc, BCE_WARN,
1290                         "Invalid PHY address %d for PHY write!\n", phy);
1291                 return(0);
1292         }
1293
1294         DBPRINT(sc, BCE_EXCESSIVE,
1295                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1296                 __func__, phy, (uint16_t)(reg & 0xffff),
1297                 (uint16_t)(val & 0xffff));
1298
1299         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1300                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1301                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1302
1303                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1304                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1305
1306                 DELAY(40);
1307         }
1308
1309         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1310                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1311                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1312         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1313
1314         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1315                 DELAY(10);
1316
1317                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1318                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1319                         DELAY(5);
1320                         break;
1321                 }
1322         }
1323
1324         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1325                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1326
1327         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1328                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1329                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1330
1331                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1332                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1333
1334                 DELAY(40);
1335         }
1336         return 0;
1337 }
1338
1339
1340 /****************************************************************************/
1341 /* MII bus status change.                                                   */
1342 /*                                                                          */
1343 /* Called by the MII bus driver when the PHY establishes link to set the    */
1344 /* MAC interface registers.                                                 */
1345 /*                                                                          */
1346 /* Returns:                                                                 */
1347 /*   Nothing.                                                               */
1348 /****************************************************************************/
1349 static void
1350 bce_miibus_statchg(device_t dev)
1351 {
1352         struct bce_softc *sc = device_get_softc(dev);
1353         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1354
1355         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1356                 mii->mii_media_active);
1357
1358 #ifdef BCE_DEBUG
1359         /* Decode the interface media flags. */
1360         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1361         switch(IFM_TYPE(mii->mii_media_active)) {
1362         case IFM_ETHER:
1363                 kprintf("Ethernet )");
1364                 break;
1365         default:
1366                 kprintf("Unknown )");
1367                 break;
1368         }
1369
1370         kprintf(" Media Options: ( ");
1371         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1372         case IFM_AUTO:
1373                 kprintf("Autoselect )");
1374                 break;
1375         case IFM_MANUAL:
1376                 kprintf("Manual )");
1377                 break;
1378         case IFM_NONE:
1379                 kprintf("None )");
1380                 break;
1381         case IFM_10_T:
1382                 kprintf("10Base-T )");
1383                 break;
1384         case IFM_100_TX:
1385                 kprintf("100Base-TX )");
1386                 break;
1387         case IFM_1000_SX:
1388                 kprintf("1000Base-SX )");
1389                 break;
1390         case IFM_1000_T:
1391                 kprintf("1000Base-T )");
1392                 break;
1393         default:
1394                 kprintf("Other )");
1395                 break;
1396         }
1397
1398         kprintf(" Global Options: (");
1399         if (mii->mii_media_active & IFM_FDX)
1400                 kprintf(" FullDuplex");
1401         if (mii->mii_media_active & IFM_HDX)
1402                 kprintf(" HalfDuplex");
1403         if (mii->mii_media_active & IFM_LOOP)
1404                 kprintf(" Loopback");
1405         if (mii->mii_media_active & IFM_FLAG0)
1406                 kprintf(" Flag0");
1407         if (mii->mii_media_active & IFM_FLAG1)
1408                 kprintf(" Flag1");
1409         if (mii->mii_media_active & IFM_FLAG2)
1410                 kprintf(" Flag2");
1411         kprintf(" )\n");
1412 #endif
1413
1414         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1415
1416         /*
1417          * Set MII or GMII interface based on the speed negotiated
1418          * by the PHY.
1419          */
1420         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 
1421             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1422                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1423                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1424         } else {
1425                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1426                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1427         }
1428
1429         /*
1430          * Set half or full duplex based on the duplicity negotiated
1431          * by the PHY.
1432          */
1433         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1434                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1435                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1436         } else {
1437                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1438                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1439         }
1440 }
1441
1442
1443 /****************************************************************************/
1444 /* Acquire NVRAM lock.                                                      */
1445 /*                                                                          */
1446 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1447 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1448 /* for use by the driver.                                                   */
1449 /*                                                                          */
1450 /* Returns:                                                                 */
1451 /*   0 on success, positive value on failure.                               */
1452 /****************************************************************************/
1453 static int
1454 bce_acquire_nvram_lock(struct bce_softc *sc)
1455 {
1456         uint32_t val;
1457         int j;
1458
1459         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1460
1461         /* Request access to the flash interface. */
1462         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1463         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1464                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1465                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1466                         break;
1467
1468                 DELAY(5);
1469         }
1470
1471         if (j >= NVRAM_TIMEOUT_COUNT) {
1472                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1473                 return EBUSY;
1474         }
1475         return 0;
1476 }
1477
1478
1479 /****************************************************************************/
1480 /* Release NVRAM lock.                                                      */
1481 /*                                                                          */
1482 /* When the caller is finished accessing NVRAM the lock must be released.   */
1483 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1484 /* for use by the driver.                                                   */
1485 /*                                                                          */
1486 /* Returns:                                                                 */
1487 /*   0 on success, positive value on failure.                               */
1488 /****************************************************************************/
1489 static int
1490 bce_release_nvram_lock(struct bce_softc *sc)
1491 {
1492         int j;
1493         uint32_t val;
1494
1495         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1496
1497         /*
1498          * Relinquish nvram interface.
1499          */
1500         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1501
1502         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1503                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1504                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1505                         break;
1506
1507                 DELAY(5);
1508         }
1509
1510         if (j >= NVRAM_TIMEOUT_COUNT) {
1511                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1512                 return EBUSY;
1513         }
1514         return 0;
1515 }
1516
1517
1518 /****************************************************************************/
1519 /* Enable NVRAM access.                                                     */
1520 /*                                                                          */
1521 /* Before accessing NVRAM for read or write operations the caller must      */
1522 /* enabled NVRAM access.                                                    */
1523 /*                                                                          */
1524 /* Returns:                                                                 */
1525 /*   Nothing.                                                               */
1526 /****************************************************************************/
1527 static void
1528 bce_enable_nvram_access(struct bce_softc *sc)
1529 {
1530         uint32_t val;
1531
1532         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1533
1534         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1535         /* Enable both bits, even on read. */
1536         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1537                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1538 }
1539
1540
1541 /****************************************************************************/
1542 /* Disable NVRAM access.                                                    */
1543 /*                                                                          */
1544 /* When the caller is finished accessing NVRAM access must be disabled.     */
1545 /*                                                                          */
1546 /* Returns:                                                                 */
1547 /*   Nothing.                                                               */
1548 /****************************************************************************/
1549 static void
1550 bce_disable_nvram_access(struct bce_softc *sc)
1551 {
1552         uint32_t val;
1553
1554         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1555
1556         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1557
1558         /* Disable both bits, even after read. */
1559         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1560                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1561 }
1562
1563
1564 /****************************************************************************/
1565 /* Read a dword (32 bits) from NVRAM.                                       */
1566 /*                                                                          */
1567 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1568 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1569 /*                                                                          */
1570 /* Returns:                                                                 */
1571 /*   0 on success and the 32 bit value read, positive value on failure.     */
1572 /****************************************************************************/
1573 static int
1574 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1575                      uint32_t cmd_flags)
1576 {
1577         uint32_t cmd;
1578         int i, rc = 0;
1579
1580         /* Build the command word. */
1581         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1582
1583         /* Calculate the offset for buffered flash. */
1584         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1585                 offset = ((offset / sc->bce_flash_info->page_size) <<
1586                           sc->bce_flash_info->page_bits) +
1587                          (offset % sc->bce_flash_info->page_size);
1588         }
1589
1590         /*
1591          * Clear the DONE bit separately, set the address to read,
1592          * and issue the read.
1593          */
1594         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1595         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1596         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1597
1598         /* Wait for completion. */
1599         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1600                 uint32_t val;
1601
1602                 DELAY(5);
1603
1604                 val = REG_RD(sc, BCE_NVM_COMMAND);
1605                 if (val & BCE_NVM_COMMAND_DONE) {
1606                         val = REG_RD(sc, BCE_NVM_READ);
1607
1608                         val = be32toh(val);
1609                         memcpy(ret_val, &val, 4);
1610                         break;
1611                 }
1612         }
1613
1614         /* Check for errors. */
1615         if (i >= NVRAM_TIMEOUT_COUNT) {
1616                 if_printf(&sc->arpcom.ac_if,
1617                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1618                           offset);
1619                 rc = EBUSY;
1620         }
1621         return rc;
1622 }
1623
1624
1625 /****************************************************************************/
1626 /* Initialize NVRAM access.                                                 */
1627 /*                                                                          */
1628 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1629 /* access that device.                                                      */
1630 /*                                                                          */
1631 /* Returns:                                                                 */
1632 /*   0 on success, positive value on failure.                               */
1633 /****************************************************************************/
1634 static int
1635 bce_init_nvram(struct bce_softc *sc)
1636 {
1637         uint32_t val;
1638         int j, entry_count, rc = 0;
1639         const struct flash_spec *flash;
1640
1641         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1642
1643         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1644             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1645                 sc->bce_flash_info = &flash_5709;
1646                 goto bce_init_nvram_get_flash_size;
1647         }
1648
1649         /* Determine the selected interface. */
1650         val = REG_RD(sc, BCE_NVM_CFG1);
1651
1652         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1653
1654         /*
1655          * Flash reconfiguration is required to support additional
1656          * NVRAM devices not directly supported in hardware.
1657          * Check if the flash interface was reconfigured
1658          * by the bootcode.
1659          */
1660
1661         if (val & 0x40000000) {
1662                 /* Flash interface reconfigured by bootcode. */
1663
1664                 DBPRINT(sc, BCE_INFO_LOAD, 
1665                         "%s(): Flash WAS reconfigured.\n", __func__);
1666
1667                 for (j = 0, flash = flash_table; j < entry_count;
1668                      j++, flash++) {
1669                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1670                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1671                                 sc->bce_flash_info = flash;
1672                                 break;
1673                         }
1674                 }
1675         } else {
1676                 /* Flash interface not yet reconfigured. */
1677                 uint32_t mask;
1678
1679                 DBPRINT(sc, BCE_INFO_LOAD, 
1680                         "%s(): Flash was NOT reconfigured.\n", __func__);
1681
1682                 if (val & (1 << 23))
1683                         mask = FLASH_BACKUP_STRAP_MASK;
1684                 else
1685                         mask = FLASH_STRAP_MASK;
1686
1687                 /* Look for the matching NVRAM device configuration data. */
1688                 for (j = 0, flash = flash_table; j < entry_count;
1689                      j++, flash++) {
1690                         /* Check if the device matches any of the known devices. */
1691                         if ((val & mask) == (flash->strapping & mask)) {
1692                                 /* Found a device match. */
1693                                 sc->bce_flash_info = flash;
1694
1695                                 /* Request access to the flash interface. */
1696                                 rc = bce_acquire_nvram_lock(sc);
1697                                 if (rc != 0)
1698                                         return rc;
1699
1700                                 /* Reconfigure the flash interface. */
1701                                 bce_enable_nvram_access(sc);
1702                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1703                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1704                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1705                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1706                                 bce_disable_nvram_access(sc);
1707                                 bce_release_nvram_lock(sc);
1708                                 break;
1709                         }
1710                 }
1711         }
1712
1713         /* Check if a matching device was found. */
1714         if (j == entry_count) {
1715                 sc->bce_flash_info = NULL;
1716                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1717                 return ENODEV;
1718         }
1719
1720 bce_init_nvram_get_flash_size:
1721         /* Write the flash config data to the shared memory interface. */
1722         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1723             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1724         if (val)
1725                 sc->bce_flash_size = val;
1726         else
1727                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1728
1729         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1730                 __func__, sc->bce_flash_info->total_size);
1731
1732         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1733
1734         return rc;
1735 }
1736
1737
1738 /****************************************************************************/
1739 /* Read an arbitrary range of data from NVRAM.                              */
1740 /*                                                                          */
1741 /* Prepares the NVRAM interface for access and reads the requested data     */
1742 /* into the supplied buffer.                                                */
1743 /*                                                                          */
1744 /* Returns:                                                                 */
1745 /*   0 on success and the data read, positive value on failure.             */
1746 /****************************************************************************/
1747 static int
1748 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1749                int buf_size)
1750 {
1751         uint32_t cmd_flags, offset32, len32, extra;
1752         int rc = 0;
1753
1754         if (buf_size == 0)
1755                 return 0;
1756
1757         /* Request access to the flash interface. */
1758         rc = bce_acquire_nvram_lock(sc);
1759         if (rc != 0)
1760                 return rc;
1761
1762         /* Enable access to flash interface */
1763         bce_enable_nvram_access(sc);
1764
1765         len32 = buf_size;
1766         offset32 = offset;
1767         extra = 0;
1768
1769         cmd_flags = 0;
1770
1771         /* XXX should we release nvram lock if read_dword() fails? */
1772         if (offset32 & 3) {
1773                 uint8_t buf[4];
1774                 uint32_t pre_len;
1775
1776                 offset32 &= ~3;
1777                 pre_len = 4 - (offset & 3);
1778
1779                 if (pre_len >= len32) {
1780                         pre_len = len32;
1781                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1782                 } else {
1783                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1784                 }
1785
1786                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1787                 if (rc)
1788                         return rc;
1789
1790                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1791
1792                 offset32 += 4;
1793                 ret_buf += pre_len;
1794                 len32 -= pre_len;
1795         }
1796
1797         if (len32 & 3) {
1798                 extra = 4 - (len32 & 3);
1799                 len32 = (len32 + 4) & ~3;
1800         }
1801
1802         if (len32 == 4) {
1803                 uint8_t buf[4];
1804
1805                 if (cmd_flags)
1806                         cmd_flags = BCE_NVM_COMMAND_LAST;
1807                 else
1808                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1809                                     BCE_NVM_COMMAND_LAST;
1810
1811                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1812
1813                 memcpy(ret_buf, buf, 4 - extra);
1814         } else if (len32 > 0) {
1815                 uint8_t buf[4];
1816
1817                 /* Read the first word. */
1818                 if (cmd_flags)
1819                         cmd_flags = 0;
1820                 else
1821                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1822
1823                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1824
1825                 /* Advance to the next dword. */
1826                 offset32 += 4;
1827                 ret_buf += 4;
1828                 len32 -= 4;
1829
1830                 while (len32 > 4 && rc == 0) {
1831                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1832
1833                         /* Advance to the next dword. */
1834                         offset32 += 4;
1835                         ret_buf += 4;
1836                         len32 -= 4;
1837                 }
1838
1839                 if (rc)
1840                         goto bce_nvram_read_locked_exit;
1841
1842                 cmd_flags = BCE_NVM_COMMAND_LAST;
1843                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1844
1845                 memcpy(ret_buf, buf, 4 - extra);
1846         }
1847
1848 bce_nvram_read_locked_exit:
1849         /* Disable access to flash interface and release the lock. */
1850         bce_disable_nvram_access(sc);
1851         bce_release_nvram_lock(sc);
1852
1853         return rc;
1854 }
1855
1856
1857 /****************************************************************************/
1858 /* Verifies that NVRAM is accessible and contains valid data.               */
1859 /*                                                                          */
1860 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1861 /* correct.                                                                 */
1862 /*                                                                          */
1863 /* Returns:                                                                 */
1864 /*   0 on success, positive value on failure.                               */
1865 /****************************************************************************/
1866 static int
1867 bce_nvram_test(struct bce_softc *sc)
1868 {
1869         uint32_t buf[BCE_NVRAM_SIZE / 4];
1870         uint32_t magic, csum;
1871         uint8_t *data = (uint8_t *)buf;
1872         int rc = 0;
1873
1874         /*
1875          * Check that the device NVRAM is valid by reading
1876          * the magic value at offset 0.
1877          */
1878         rc = bce_nvram_read(sc, 0, data, 4);
1879         if (rc != 0)
1880                 return rc;
1881
1882         magic = be32toh(buf[0]);
1883         if (magic != BCE_NVRAM_MAGIC) {
1884                 if_printf(&sc->arpcom.ac_if,
1885                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1886                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1887                 return ENODEV;
1888         }
1889
1890         /*
1891          * Verify that the device NVRAM includes valid
1892          * configuration data.
1893          */
1894         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1895         if (rc != 0)
1896                 return rc;
1897
1898         csum = ether_crc32_le(data, 0x100);
1899         if (csum != BCE_CRC32_RESIDUAL) {
1900                 if_printf(&sc->arpcom.ac_if,
1901                           "Invalid Manufacturing Information NVRAM CRC! "
1902                           "Expected: 0x%08X, Found: 0x%08X\n",
1903                           BCE_CRC32_RESIDUAL, csum);
1904                 return ENODEV;
1905         }
1906
1907         csum = ether_crc32_le(data + 0x100, 0x100);
1908         if (csum != BCE_CRC32_RESIDUAL) {
1909                 if_printf(&sc->arpcom.ac_if,
1910                           "Invalid Feature Configuration Information "
1911                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1912                           BCE_CRC32_RESIDUAL, csum);
1913                 rc = ENODEV;
1914         }
1915         return rc;
1916 }
1917
1918
1919 /****************************************************************************/
1920 /* Identifies the current media type of the controller and sets the PHY     */
1921 /* address.                                                                 */
1922 /*                                                                          */
1923 /* Returns:                                                                 */
1924 /*   Nothing.                                                               */
1925 /****************************************************************************/
1926 static void
1927 bce_get_media(struct bce_softc *sc)
1928 {
1929         uint32_t val;
1930
1931         sc->bce_phy_addr = 1;
1932
1933         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1934             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1935                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1936                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1937                 uint32_t strap;
1938
1939                 /*
1940                  * The BCM5709S is software configurable
1941                  * for Copper or SerDes operation.
1942                  */
1943                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1944                         return;
1945                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1946                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1947                         return;
1948                 }
1949
1950                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1951                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1952                 } else {
1953                         strap =
1954                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1955                 }
1956
1957                 if (pci_get_function(sc->bce_dev) == 0) {
1958                         switch (strap) {
1959                         case 0x4:
1960                         case 0x5:
1961                         case 0x6:
1962                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1963                                 break;
1964                         }
1965                 } else {
1966                         switch (strap) {
1967                         case 0x1:
1968                         case 0x2:
1969                         case 0x4:
1970                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1971                                 break;
1972                         }
1973                 }
1974         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1975                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1976         }
1977
1978         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1979                 sc->bce_flags |= BCE_NO_WOL_FLAG;
1980                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1981                         sc->bce_phy_addr = 2;
1982                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1983                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1984                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1985                 }
1986         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1987             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1988                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1989         }
1990 }
1991
1992
1993 /****************************************************************************/
1994 /* Free any DMA memory owned by the driver.                                 */
1995 /*                                                                          */
1996 /* Scans through each data structre that requires DMA memory and frees      */
1997 /* the memory if allocated.                                                 */
1998 /*                                                                          */
1999 /* Returns:                                                                 */
2000 /*   Nothing.                                                               */
2001 /****************************************************************************/
2002 static void
2003 bce_dma_free(struct bce_softc *sc)
2004 {
2005         int i;
2006
2007         /* Destroy the status block. */
2008         if (sc->status_tag != NULL) {
2009                 if (sc->status_block != NULL) {
2010                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2011                         bus_dmamem_free(sc->status_tag, sc->status_block,
2012                                         sc->status_map);
2013                 }
2014                 bus_dma_tag_destroy(sc->status_tag);
2015         }
2016
2017
2018         /* Destroy the statistics block. */
2019         if (sc->stats_tag != NULL) {
2020                 if (sc->stats_block != NULL) {
2021                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2022                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2023                                         sc->stats_map);
2024                 }
2025                 bus_dma_tag_destroy(sc->stats_tag);
2026         }
2027
2028         /* Destroy the CTX DMA stuffs. */
2029         if (sc->ctx_tag != NULL) {
2030                 for (i = 0; i < sc->ctx_pages; i++) {
2031                         if (sc->ctx_block[i] != NULL) {
2032                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2033                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2034                                                 sc->ctx_map[i]);
2035                         }
2036                 }
2037                 bus_dma_tag_destroy(sc->ctx_tag);
2038         }
2039
2040         /* Destroy the TX buffer descriptor DMA stuffs. */
2041         if (sc->tx_bd_chain_tag != NULL) {
2042                 for (i = 0; i < TX_PAGES; i++) {
2043                         if (sc->tx_bd_chain[i] != NULL) {
2044                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2045                                                   sc->tx_bd_chain_map[i]);
2046                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2047                                                 sc->tx_bd_chain[i],
2048                                                 sc->tx_bd_chain_map[i]);
2049                         }
2050                 }
2051                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2052         }
2053
2054         /* Destroy the RX buffer descriptor DMA stuffs. */
2055         if (sc->rx_bd_chain_tag != NULL) {
2056                 for (i = 0; i < RX_PAGES; i++) {
2057                         if (sc->rx_bd_chain[i] != NULL) {
2058                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2059                                                   sc->rx_bd_chain_map[i]);
2060                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2061                                                 sc->rx_bd_chain[i],
2062                                                 sc->rx_bd_chain_map[i]);
2063                         }
2064                 }
2065                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2066         }
2067
2068         /* Destroy the TX mbuf DMA stuffs. */
2069         if (sc->tx_mbuf_tag != NULL) {
2070                 for (i = 0; i < TOTAL_TX_BD; i++) {
2071                         /* Must have been unloaded in bce_stop() */
2072                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2073                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2074                                            sc->tx_mbuf_map[i]);
2075                 }
2076                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2077         }
2078
2079         /* Destroy the RX mbuf DMA stuffs. */
2080         if (sc->rx_mbuf_tag != NULL) {
2081                 for (i = 0; i < TOTAL_RX_BD; i++) {
2082                         /* Must have been unloaded in bce_stop() */
2083                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2084                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2085                                            sc->rx_mbuf_map[i]);
2086                 }
2087                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2088                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2089         }
2090
2091         /* Destroy the parent tag */
2092         if (sc->parent_tag != NULL)
2093                 bus_dma_tag_destroy(sc->parent_tag);
2094 }
2095
2096
2097 /****************************************************************************/
2098 /* Get DMA memory from the OS.                                              */
2099 /*                                                                          */
2100 /* Validates that the OS has provided DMA buffers in response to a          */
2101 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2102 /* When the callback is used the OS will return 0 for the mapping function  */
2103 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2104 /* failures back to the caller.                                             */
2105 /*                                                                          */
2106 /* Returns:                                                                 */
2107 /*   Nothing.                                                               */
2108 /****************************************************************************/
2109 static void
2110 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2111 {
2112         bus_addr_t *busaddr = arg;
2113
2114         /*
2115          * Simulate a mapping failure.
2116          * XXX not correct.
2117          */
2118         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2119                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2120                         __FILE__, __LINE__);
2121                 error = ENOMEM);
2122                 
2123         /* Check for an error and signal the caller that an error occurred. */
2124         if (error)
2125                 return;
2126
2127         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2128         *busaddr = segs->ds_addr;
2129 }
2130
2131
2132 /****************************************************************************/
2133 /* Allocate any DMA memory needed by the driver.                            */
2134 /*                                                                          */
2135 /* Allocates DMA memory needed for the various global structures needed by  */
2136 /* hardware.                                                                */
2137 /*                                                                          */
2138 /* Memory alignment requirements:                                           */
2139 /* -----------------+----------+----------+----------+----------+           */
2140 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2141 /* -----------------+----------+----------+----------+----------+           */
2142 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2143 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2144 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2145 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2146 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2147 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2148 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2149 /* -----------------+----------+----------+----------+----------+           */
2150 /*                                                                          */
2151 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2152 /*                                                                          */
2153 /* Returns:                                                                 */
2154 /*   0 for success, positive value for failure.                             */
2155 /****************************************************************************/
2156 static int
2157 bce_dma_alloc(struct bce_softc *sc)
2158 {
2159         struct ifnet *ifp = &sc->arpcom.ac_if;
2160         int i, j, rc = 0;
2161         bus_addr_t busaddr, max_busaddr;
2162         bus_size_t status_align, stats_align;
2163
2164         /* 
2165          * The embedded PCIe to PCI-X bridge (EPB) 
2166          * in the 5708 cannot address memory above 
2167          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 
2168          */
2169         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2170                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2171         else
2172                 max_busaddr = BUS_SPACE_MAXADDR;
2173
2174         /*
2175          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2176          */
2177         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2178             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2179                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2180                 if (sc->ctx_pages == 0)
2181                         sc->ctx_pages = 1;
2182                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2183                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2184                             sc->ctx_pages);
2185                         return ENOMEM;
2186                 }
2187                 status_align = 16;
2188                 stats_align = 16;
2189         } else {
2190                 status_align = 8;
2191                 stats_align = 8;
2192         }
2193
2194         /*
2195          * Allocate the parent bus DMA tag appropriate for PCI.
2196          */
2197         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2198                                 max_busaddr, BUS_SPACE_MAXADDR,
2199                                 NULL, NULL,
2200                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2201                                 BUS_SPACE_MAXSIZE_32BIT,
2202                                 0, &sc->parent_tag);
2203         if (rc != 0) {
2204                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2205                 return rc;
2206         }
2207
2208         /*
2209          * Allocate status block.
2210          */
2211         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2212                                 status_align, BCE_STATUS_BLK_SZ,
2213                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2214                                 &sc->status_tag, &sc->status_map,
2215                                 &sc->status_block_paddr);
2216         if (sc->status_block == NULL) {
2217                 if_printf(ifp, "Could not allocate status block!\n");
2218                 return ENOMEM;
2219         }
2220
2221         /*
2222          * Allocate statistics block.
2223          */
2224         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2225                                 stats_align, BCE_STATS_BLK_SZ,
2226                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2227                                 &sc->stats_tag, &sc->stats_map,
2228                                 &sc->stats_block_paddr);
2229         if (sc->stats_block == NULL) {
2230                 if_printf(ifp, "Could not allocate statistics block!\n");
2231                 return ENOMEM;
2232         }
2233
2234         /*
2235          * Allocate context block, if needed
2236          */
2237         if (sc->ctx_pages != 0) {
2238                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2239                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2240                                         NULL, NULL,
2241                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2242                                         0, &sc->ctx_tag);
2243                 if (rc != 0) {
2244                         if_printf(ifp, "Could not allocate "
2245                                   "context block DMA tag!\n");
2246                         return rc;
2247                 }
2248
2249                 for (i = 0; i < sc->ctx_pages; i++) {
2250                         rc = bus_dmamem_alloc(sc->ctx_tag,
2251                                               (void **)&sc->ctx_block[i],
2252                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2253                                               BUS_DMA_COHERENT,
2254                                               &sc->ctx_map[i]);
2255                         if (rc != 0) {
2256                                 if_printf(ifp, "Could not allocate %dth context "
2257                                           "DMA memory!\n", i);
2258                                 return rc;
2259                         }
2260
2261                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2262                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2263                                              bce_dma_map_addr, &busaddr,
2264                                              BUS_DMA_WAITOK);
2265                         if (rc != 0) {
2266                                 if (rc == EINPROGRESS) {
2267                                         panic("%s coherent memory loading "
2268                                               "is still in progress!", ifp->if_xname);
2269                                 }
2270                                 if_printf(ifp, "Could not map %dth context "
2271                                           "DMA memory!\n", i);
2272                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2273                                                 sc->ctx_map[i]);
2274                                 sc->ctx_block[i] = NULL;
2275                                 return rc;
2276                         }
2277                         sc->ctx_paddr[i] = busaddr;
2278                 }
2279         }
2280
2281         /*
2282          * Create a DMA tag for the TX buffer descriptor chain,
2283          * allocate and clear the  memory, and fetch the
2284          * physical address of the block.
2285          */
2286         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2287                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2288                                 NULL, NULL,
2289                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2290                                 0, &sc->tx_bd_chain_tag);
2291         if (rc != 0) {
2292                 if_printf(ifp, "Could not allocate "
2293                           "TX descriptor chain DMA tag!\n");
2294                 return rc;
2295         }
2296
2297         for (i = 0; i < TX_PAGES; i++) {
2298                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2299                                       (void **)&sc->tx_bd_chain[i],
2300                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2301                                       BUS_DMA_COHERENT,
2302                                       &sc->tx_bd_chain_map[i]);
2303                 if (rc != 0) {
2304                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2305                                   "chain DMA memory!\n", i);
2306                         return rc;
2307                 }
2308
2309                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2310                                      sc->tx_bd_chain_map[i],
2311                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2312                                      bce_dma_map_addr, &busaddr,
2313                                      BUS_DMA_WAITOK);
2314                 if (rc != 0) {
2315                         if (rc == EINPROGRESS) {
2316                                 panic("%s coherent memory loading "
2317                                       "is still in progress!", ifp->if_xname);
2318                         }
2319                         if_printf(ifp, "Could not map %dth TX descriptor "
2320                                   "chain DMA memory!\n", i);
2321                         bus_dmamem_free(sc->tx_bd_chain_tag,
2322                                         sc->tx_bd_chain[i],
2323                                         sc->tx_bd_chain_map[i]);
2324                         sc->tx_bd_chain[i] = NULL;
2325                         return rc;
2326                 }
2327
2328                 sc->tx_bd_chain_paddr[i] = busaddr;
2329                 /* DRC - Fix for 64 bit systems. */
2330                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 
2331                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2332         }
2333
2334         /* Create a DMA tag for TX mbufs. */
2335         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2336                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2337                                 NULL, NULL,
2338                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2339                                 BCE_MAX_SEGMENTS, MCLBYTES,
2340                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2341                                 BUS_DMA_ONEBPAGE,
2342                                 &sc->tx_mbuf_tag);
2343         if (rc != 0) {
2344                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2345                 return rc;
2346         }
2347
2348         /* Create DMA maps for the TX mbufs clusters. */
2349         for (i = 0; i < TOTAL_TX_BD; i++) {
2350                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2351                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2352                                        &sc->tx_mbuf_map[i]);
2353                 if (rc != 0) {
2354                         for (j = 0; j < i; ++j) {
2355                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2356                                                    sc->tx_mbuf_map[i]);
2357                         }
2358                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2359                         sc->tx_mbuf_tag = NULL;
2360
2361                         if_printf(ifp, "Unable to create "
2362                                   "%dth TX mbuf DMA map!\n", i);
2363                         return rc;
2364                 }
2365         }
2366
2367         /*
2368          * Create a DMA tag for the RX buffer descriptor chain,
2369          * allocate and clear the  memory, and fetch the physical
2370          * address of the blocks.
2371          */
2372         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2373                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2374                                 NULL, NULL,
2375                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2376                                 0, &sc->rx_bd_chain_tag);
2377         if (rc != 0) {
2378                 if_printf(ifp, "Could not allocate "
2379                           "RX descriptor chain DMA tag!\n");
2380                 return rc;
2381         }
2382
2383         for (i = 0; i < RX_PAGES; i++) {
2384                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2385                                       (void **)&sc->rx_bd_chain[i],
2386                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2387                                       BUS_DMA_COHERENT,
2388                                       &sc->rx_bd_chain_map[i]);
2389                 if (rc != 0) {
2390                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2391                                   "chain DMA memory!\n", i);
2392                         return rc;
2393                 }
2394
2395                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2396                                      sc->rx_bd_chain_map[i],
2397                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2398                                      bce_dma_map_addr, &busaddr,
2399                                      BUS_DMA_WAITOK);
2400                 if (rc != 0) {
2401                         if (rc == EINPROGRESS) {
2402                                 panic("%s coherent memory loading "
2403                                       "is still in progress!", ifp->if_xname);
2404                         }
2405                         if_printf(ifp, "Could not map %dth RX descriptor "
2406                                   "chain DMA memory!\n", i);
2407                         bus_dmamem_free(sc->rx_bd_chain_tag,
2408                                         sc->rx_bd_chain[i],
2409                                         sc->rx_bd_chain_map[i]);
2410                         sc->rx_bd_chain[i] = NULL;
2411                         return rc;
2412                 }
2413
2414                 sc->rx_bd_chain_paddr[i] = busaddr;
2415                 /* DRC - Fix for 64 bit systems. */
2416                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2417                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2418         }
2419
2420         /* Create a DMA tag for RX mbufs. */
2421         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2422                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2423                                 NULL, NULL,
2424                                 MCLBYTES, 1, MCLBYTES,
2425                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2426                                 BUS_DMA_WAITOK,
2427                                 &sc->rx_mbuf_tag);
2428         if (rc != 0) {
2429                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2430                 return rc;
2431         }
2432
2433         /* Create tmp DMA map for RX mbuf clusters. */
2434         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2435                                &sc->rx_mbuf_tmpmap);
2436         if (rc != 0) {
2437                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2438                 sc->rx_mbuf_tag = NULL;
2439
2440                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2441                 return rc;
2442         }
2443
2444         /* Create DMA maps for the RX mbuf clusters. */
2445         for (i = 0; i < TOTAL_RX_BD; i++) {
2446                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2447                                        &sc->rx_mbuf_map[i]);
2448                 if (rc != 0) {
2449                         for (j = 0; j < i; ++j) {
2450                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2451                                                    sc->rx_mbuf_map[j]);
2452                         }
2453                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2454                         sc->rx_mbuf_tag = NULL;
2455
2456                         if_printf(ifp, "Unable to create "
2457                                   "%dth RX mbuf DMA map!\n", i);
2458                         return rc;
2459                 }
2460         }
2461         return 0;
2462 }
2463
2464
2465 /****************************************************************************/
2466 /* Firmware synchronization.                                                */
2467 /*                                                                          */
2468 /* Before performing certain events such as a chip reset, synchronize with  */
2469 /* the firmware first.                                                      */
2470 /*                                                                          */
2471 /* Returns:                                                                 */
2472 /*   0 for success, positive value for failure.                             */
2473 /****************************************************************************/
2474 static int
2475 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2476 {
2477         int i, rc = 0;
2478         uint32_t val;
2479
2480         /* Don't waste any time if we've timed out before. */
2481         if (sc->bce_fw_timed_out)
2482                 return EBUSY;
2483
2484         /* Increment the message sequence number. */
2485         sc->bce_fw_wr_seq++;
2486         msg_data |= sc->bce_fw_wr_seq;
2487
2488         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2489
2490         /* Send the message to the bootcode driver mailbox. */
2491         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2492
2493         /* Wait for the bootcode to acknowledge the message. */
2494         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2495                 /* Check for a response in the bootcode firmware mailbox. */
2496                 val = bce_shmem_rd(sc, BCE_FW_MB);
2497                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2498                         break;
2499                 DELAY(1000);
2500         }
2501
2502         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2503         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2504             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2505                 if_printf(&sc->arpcom.ac_if,
2506                           "Firmware synchronization timeout! "
2507                           "msg_data = 0x%08X\n", msg_data);
2508
2509                 msg_data &= ~BCE_DRV_MSG_CODE;
2510                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2511
2512                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2513
2514                 sc->bce_fw_timed_out = 1;
2515                 rc = EBUSY;
2516         }
2517         return rc;
2518 }
2519
2520
2521 /****************************************************************************/
2522 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2523 /*                                                                          */
2524 /* Returns:                                                                 */
2525 /*   Nothing.                                                               */
2526 /****************************************************************************/
2527 static void
2528 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2529                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2530 {
2531         int i;
2532         uint32_t val;
2533
2534         for (i = 0; i < rv2p_code_len; i += 8) {
2535                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2536                 rv2p_code++;
2537                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2538                 rv2p_code++;
2539
2540                 if (rv2p_proc == RV2P_PROC1) {
2541                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2542                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2543                 } else {
2544                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2545                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2546                 }
2547         }
2548
2549         /* Reset the processor, un-stall is done later. */
2550         if (rv2p_proc == RV2P_PROC1)
2551                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2552         else
2553                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2554 }
2555
2556
2557 /****************************************************************************/
2558 /* Load RISC processor firmware.                                            */
2559 /*                                                                          */
2560 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2561 /* associated with a particular processor.                                  */
2562 /*                                                                          */
2563 /* Returns:                                                                 */
2564 /*   Nothing.                                                               */
2565 /****************************************************************************/
2566 static void
2567 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2568                 struct fw_info *fw)
2569 {
2570         uint32_t offset;
2571         int j;
2572
2573         bce_halt_cpu(sc, cpu_reg);
2574
2575         /* Load the Text area. */
2576         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2577         if (fw->text) {
2578                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2579                         REG_WR_IND(sc, offset, fw->text[j]);
2580         }
2581
2582         /* Load the Data area. */
2583         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2584         if (fw->data) {
2585                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2586                         REG_WR_IND(sc, offset, fw->data[j]);
2587         }
2588
2589         /* Load the SBSS area. */
2590         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2591         if (fw->sbss) {
2592                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2593                         REG_WR_IND(sc, offset, fw->sbss[j]);
2594         }
2595
2596         /* Load the BSS area. */
2597         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2598         if (fw->bss) {
2599                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2600                         REG_WR_IND(sc, offset, fw->bss[j]);
2601         }
2602
2603         /* Load the Read-Only area. */
2604         offset = cpu_reg->spad_base +
2605                 (fw->rodata_addr - cpu_reg->mips_view_base);
2606         if (fw->rodata) {
2607                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2608                         REG_WR_IND(sc, offset, fw->rodata[j]);
2609         }
2610
2611         /* Clear the pre-fetch instruction and set the FW start address. */
2612         REG_WR_IND(sc, cpu_reg->inst, 0);
2613         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2614 }
2615
2616
2617 /****************************************************************************/
2618 /* Starts the RISC processor.                                               */
2619 /*                                                                          */
2620 /* Assumes the CPU starting address has already been set.                   */
2621 /*                                                                          */
2622 /* Returns:                                                                 */
2623 /*   Nothing.                                                               */
2624 /****************************************************************************/
2625 static void
2626 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2627 {
2628         uint32_t val;
2629
2630         /* Start the CPU. */
2631         val = REG_RD_IND(sc, cpu_reg->mode);
2632         val &= ~cpu_reg->mode_value_halt;
2633         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2634         REG_WR_IND(sc, cpu_reg->mode, val);
2635 }
2636
2637
2638 /****************************************************************************/
2639 /* Halts the RISC processor.                                                */
2640 /*                                                                          */
2641 /* Returns:                                                                 */
2642 /*   Nothing.                                                               */
2643 /****************************************************************************/
2644 static void
2645 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2646 {
2647         uint32_t val;
2648
2649         /* Halt the CPU. */
2650         val = REG_RD_IND(sc, cpu_reg->mode);
2651         val |= cpu_reg->mode_value_halt;
2652         REG_WR_IND(sc, cpu_reg->mode, val);
2653         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2654 }
2655
2656
2657 /****************************************************************************/
2658 /* Start the RX CPU.                                                        */
2659 /*                                                                          */
2660 /* Returns:                                                                 */
2661 /*   Nothing.                                                               */
2662 /****************************************************************************/
2663 static void
2664 bce_start_rxp_cpu(struct bce_softc *sc)
2665 {
2666         struct cpu_reg cpu_reg;
2667
2668         cpu_reg.mode = BCE_RXP_CPU_MODE;
2669         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2670         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2671         cpu_reg.state = BCE_RXP_CPU_STATE;
2672         cpu_reg.state_value_clear = 0xffffff;
2673         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2674         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2675         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2676         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2677         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2678         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2679         cpu_reg.mips_view_base = 0x8000000;
2680
2681         bce_start_cpu(sc, &cpu_reg);
2682 }
2683
2684
2685 /****************************************************************************/
2686 /* Initialize the RX CPU.                                                   */
2687 /*                                                                          */
2688 /* Returns:                                                                 */
2689 /*   Nothing.                                                               */
2690 /****************************************************************************/
2691 static void
2692 bce_init_rxp_cpu(struct bce_softc *sc)
2693 {
2694         struct cpu_reg cpu_reg;
2695         struct fw_info fw;
2696
2697         cpu_reg.mode = BCE_RXP_CPU_MODE;
2698         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2699         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2700         cpu_reg.state = BCE_RXP_CPU_STATE;
2701         cpu_reg.state_value_clear = 0xffffff;
2702         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2703         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2704         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2705         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2706         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2707         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2708         cpu_reg.mips_view_base = 0x8000000;
2709
2710         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2711             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2712                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2713                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2714                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2715                 fw.start_addr = bce_RXP_b09FwStartAddr;
2716
2717                 fw.text_addr = bce_RXP_b09FwTextAddr;
2718                 fw.text_len = bce_RXP_b09FwTextLen;
2719                 fw.text_index = 0;
2720                 fw.text = bce_RXP_b09FwText;
2721
2722                 fw.data_addr = bce_RXP_b09FwDataAddr;
2723                 fw.data_len = bce_RXP_b09FwDataLen;
2724                 fw.data_index = 0;
2725                 fw.data = bce_RXP_b09FwData;
2726
2727                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2728                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2729                 fw.sbss_index = 0;
2730                 fw.sbss = bce_RXP_b09FwSbss;
2731
2732                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2733                 fw.bss_len = bce_RXP_b09FwBssLen;
2734                 fw.bss_index = 0;
2735                 fw.bss = bce_RXP_b09FwBss;
2736
2737                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2738                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2739                 fw.rodata_index = 0;
2740                 fw.rodata = bce_RXP_b09FwRodata;
2741         } else {
2742                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2743                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2744                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2745                 fw.start_addr = bce_RXP_b06FwStartAddr;
2746
2747                 fw.text_addr = bce_RXP_b06FwTextAddr;
2748                 fw.text_len = bce_RXP_b06FwTextLen;
2749                 fw.text_index = 0;
2750                 fw.text = bce_RXP_b06FwText;
2751
2752                 fw.data_addr = bce_RXP_b06FwDataAddr;
2753                 fw.data_len = bce_RXP_b06FwDataLen;
2754                 fw.data_index = 0;
2755                 fw.data = bce_RXP_b06FwData;
2756
2757                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2758                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2759                 fw.sbss_index = 0;
2760                 fw.sbss = bce_RXP_b06FwSbss;
2761
2762                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2763                 fw.bss_len = bce_RXP_b06FwBssLen;
2764                 fw.bss_index = 0;
2765                 fw.bss = bce_RXP_b06FwBss;
2766
2767                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2768                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2769                 fw.rodata_index = 0;
2770                 fw.rodata = bce_RXP_b06FwRodata;
2771         }
2772
2773         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2774         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2775         /* Delay RXP start until initialization is complete. */
2776 }
2777
2778
2779 /****************************************************************************/
2780 /* Initialize the TX CPU.                                                   */
2781 /*                                                                          */
2782 /* Returns:                                                                 */
2783 /*   Nothing.                                                               */
2784 /****************************************************************************/
2785 static void
2786 bce_init_txp_cpu(struct bce_softc *sc)
2787 {
2788         struct cpu_reg cpu_reg;
2789         struct fw_info fw;
2790
2791         cpu_reg.mode = BCE_TXP_CPU_MODE;
2792         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2793         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2794         cpu_reg.state = BCE_TXP_CPU_STATE;
2795         cpu_reg.state_value_clear = 0xffffff;
2796         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2797         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2798         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2799         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2800         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2801         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2802         cpu_reg.mips_view_base = 0x8000000;
2803
2804         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2805             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2806                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2807                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2808                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2809                 fw.start_addr = bce_TXP_b09FwStartAddr;
2810
2811                 fw.text_addr = bce_TXP_b09FwTextAddr;
2812                 fw.text_len = bce_TXP_b09FwTextLen;
2813                 fw.text_index = 0;
2814                 fw.text = bce_TXP_b09FwText;
2815
2816                 fw.data_addr = bce_TXP_b09FwDataAddr;
2817                 fw.data_len = bce_TXP_b09FwDataLen;
2818                 fw.data_index = 0;
2819                 fw.data = bce_TXP_b09FwData;
2820
2821                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2822                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2823                 fw.sbss_index = 0;
2824                 fw.sbss = bce_TXP_b09FwSbss;
2825
2826                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2827                 fw.bss_len = bce_TXP_b09FwBssLen;
2828                 fw.bss_index = 0;
2829                 fw.bss = bce_TXP_b09FwBss;
2830
2831                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2832                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2833                 fw.rodata_index = 0;
2834                 fw.rodata = bce_TXP_b09FwRodata;
2835         } else {
2836                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2837                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2838                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2839                 fw.start_addr = bce_TXP_b06FwStartAddr;
2840
2841                 fw.text_addr = bce_TXP_b06FwTextAddr;
2842                 fw.text_len = bce_TXP_b06FwTextLen;
2843                 fw.text_index = 0;
2844                 fw.text = bce_TXP_b06FwText;
2845
2846                 fw.data_addr = bce_TXP_b06FwDataAddr;
2847                 fw.data_len = bce_TXP_b06FwDataLen;
2848                 fw.data_index = 0;
2849                 fw.data = bce_TXP_b06FwData;
2850
2851                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2852                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2853                 fw.sbss_index = 0;
2854                 fw.sbss = bce_TXP_b06FwSbss;
2855
2856                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2857                 fw.bss_len = bce_TXP_b06FwBssLen;
2858                 fw.bss_index = 0;
2859                 fw.bss = bce_TXP_b06FwBss;
2860
2861                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2862                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2863                 fw.rodata_index = 0;
2864                 fw.rodata = bce_TXP_b06FwRodata;
2865         }
2866
2867         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2868         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2869         bce_start_cpu(sc, &cpu_reg);
2870 }
2871
2872
2873 /****************************************************************************/
2874 /* Initialize the TPAT CPU.                                                 */
2875 /*                                                                          */
2876 /* Returns:                                                                 */
2877 /*   Nothing.                                                               */
2878 /****************************************************************************/
2879 static void
2880 bce_init_tpat_cpu(struct bce_softc *sc)
2881 {
2882         struct cpu_reg cpu_reg;
2883         struct fw_info fw;
2884
2885         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2886         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2887         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2888         cpu_reg.state = BCE_TPAT_CPU_STATE;
2889         cpu_reg.state_value_clear = 0xffffff;
2890         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2891         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2892         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2893         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2894         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2895         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2896         cpu_reg.mips_view_base = 0x8000000;
2897
2898         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2899             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2900                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2901                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2902                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2903                 fw.start_addr = bce_TPAT_b09FwStartAddr;
2904
2905                 fw.text_addr = bce_TPAT_b09FwTextAddr;
2906                 fw.text_len = bce_TPAT_b09FwTextLen;
2907                 fw.text_index = 0;
2908                 fw.text = bce_TPAT_b09FwText;
2909
2910                 fw.data_addr = bce_TPAT_b09FwDataAddr;
2911                 fw.data_len = bce_TPAT_b09FwDataLen;
2912                 fw.data_index = 0;
2913                 fw.data = bce_TPAT_b09FwData;
2914
2915                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2916                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2917                 fw.sbss_index = 0;
2918                 fw.sbss = bce_TPAT_b09FwSbss;
2919
2920                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2921                 fw.bss_len = bce_TPAT_b09FwBssLen;
2922                 fw.bss_index = 0;
2923                 fw.bss = bce_TPAT_b09FwBss;
2924
2925                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2926                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2927                 fw.rodata_index = 0;
2928                 fw.rodata = bce_TPAT_b09FwRodata;
2929         } else {
2930                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2931                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2932                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2933                 fw.start_addr = bce_TPAT_b06FwStartAddr;
2934
2935                 fw.text_addr = bce_TPAT_b06FwTextAddr;
2936                 fw.text_len = bce_TPAT_b06FwTextLen;
2937                 fw.text_index = 0;
2938                 fw.text = bce_TPAT_b06FwText;
2939
2940                 fw.data_addr = bce_TPAT_b06FwDataAddr;
2941                 fw.data_len = bce_TPAT_b06FwDataLen;
2942                 fw.data_index = 0;
2943                 fw.data = bce_TPAT_b06FwData;
2944
2945                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2946                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2947                 fw.sbss_index = 0;
2948                 fw.sbss = bce_TPAT_b06FwSbss;
2949
2950                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2951                 fw.bss_len = bce_TPAT_b06FwBssLen;
2952                 fw.bss_index = 0;
2953                 fw.bss = bce_TPAT_b06FwBss;
2954
2955                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2956                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2957                 fw.rodata_index = 0;
2958                 fw.rodata = bce_TPAT_b06FwRodata;
2959         }
2960
2961         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2962         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2963         bce_start_cpu(sc, &cpu_reg);
2964 }
2965
2966
2967 /****************************************************************************/
2968 /* Initialize the CP CPU.                                                   */
2969 /*                                                                          */
2970 /* Returns:                                                                 */
2971 /*   Nothing.                                                               */
2972 /****************************************************************************/
2973 static void
2974 bce_init_cp_cpu(struct bce_softc *sc)
2975 {
2976         struct cpu_reg cpu_reg;
2977         struct fw_info fw;
2978
2979         cpu_reg.mode = BCE_CP_CPU_MODE;
2980         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2981         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2982         cpu_reg.state = BCE_CP_CPU_STATE;
2983         cpu_reg.state_value_clear = 0xffffff;
2984         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
2985         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
2986         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
2987         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
2988         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
2989         cpu_reg.spad_base = BCE_CP_SCRATCH;
2990         cpu_reg.mips_view_base = 0x8000000;
2991
2992         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2993             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2994                 fw.ver_major = bce_CP_b09FwReleaseMajor;
2995                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
2996                 fw.ver_fix = bce_CP_b09FwReleaseFix;
2997                 fw.start_addr = bce_CP_b09FwStartAddr;
2998
2999                 fw.text_addr = bce_CP_b09FwTextAddr;
3000                 fw.text_len = bce_CP_b09FwTextLen;
3001                 fw.text_index = 0;
3002                 fw.text = bce_CP_b09FwText;
3003
3004                 fw.data_addr = bce_CP_b09FwDataAddr;
3005                 fw.data_len = bce_CP_b09FwDataLen;
3006                 fw.data_index = 0;
3007                 fw.data = bce_CP_b09FwData;
3008
3009                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3010                 fw.sbss_len = bce_CP_b09FwSbssLen;
3011                 fw.sbss_index = 0;
3012                 fw.sbss = bce_CP_b09FwSbss;
3013
3014                 fw.bss_addr = bce_CP_b09FwBssAddr;
3015                 fw.bss_len = bce_CP_b09FwBssLen;
3016                 fw.bss_index = 0;
3017                 fw.bss = bce_CP_b09FwBss;
3018
3019                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3020                 fw.rodata_len = bce_CP_b09FwRodataLen;
3021                 fw.rodata_index = 0;
3022                 fw.rodata = bce_CP_b09FwRodata;
3023         } else {
3024                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3025                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3026                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3027                 fw.start_addr = bce_CP_b06FwStartAddr;
3028
3029                 fw.text_addr = bce_CP_b06FwTextAddr;
3030                 fw.text_len = bce_CP_b06FwTextLen;
3031                 fw.text_index = 0;
3032                 fw.text = bce_CP_b06FwText;
3033
3034                 fw.data_addr = bce_CP_b06FwDataAddr;
3035                 fw.data_len = bce_CP_b06FwDataLen;
3036                 fw.data_index = 0;
3037                 fw.data = bce_CP_b06FwData;
3038
3039                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3040                 fw.sbss_len = bce_CP_b06FwSbssLen;
3041                 fw.sbss_index = 0;
3042                 fw.sbss = bce_CP_b06FwSbss;
3043
3044                 fw.bss_addr = bce_CP_b06FwBssAddr;
3045                 fw.bss_len = bce_CP_b06FwBssLen;
3046                 fw.bss_index = 0;
3047                 fw.bss = bce_CP_b06FwBss;
3048
3049                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3050                 fw.rodata_len = bce_CP_b06FwRodataLen;
3051                 fw.rodata_index = 0;
3052                 fw.rodata = bce_CP_b06FwRodata;
3053         }
3054
3055         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3056         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3057         bce_start_cpu(sc, &cpu_reg);
3058 }
3059
3060
3061 /****************************************************************************/
3062 /* Initialize the COM CPU.                                                 */
3063 /*                                                                          */
3064 /* Returns:                                                                 */
3065 /*   Nothing.                                                               */
3066 /****************************************************************************/
3067 static void
3068 bce_init_com_cpu(struct bce_softc *sc)
3069 {
3070         struct cpu_reg cpu_reg;
3071         struct fw_info fw;
3072
3073         cpu_reg.mode = BCE_COM_CPU_MODE;
3074         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3075         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3076         cpu_reg.state = BCE_COM_CPU_STATE;
3077         cpu_reg.state_value_clear = 0xffffff;
3078         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3079         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3080         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3081         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3082         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3083         cpu_reg.spad_base = BCE_COM_SCRATCH;
3084         cpu_reg.mips_view_base = 0x8000000;
3085
3086         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3087             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3088                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3089                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3090                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3091                 fw.start_addr = bce_COM_b09FwStartAddr;
3092
3093                 fw.text_addr = bce_COM_b09FwTextAddr;
3094                 fw.text_len = bce_COM_b09FwTextLen;
3095                 fw.text_index = 0;
3096                 fw.text = bce_COM_b09FwText;
3097
3098                 fw.data_addr = bce_COM_b09FwDataAddr;
3099                 fw.data_len = bce_COM_b09FwDataLen;
3100                 fw.data_index = 0;
3101                 fw.data = bce_COM_b09FwData;
3102
3103                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3104                 fw.sbss_len = bce_COM_b09FwSbssLen;
3105                 fw.sbss_index = 0;
3106                 fw.sbss = bce_COM_b09FwSbss;
3107
3108                 fw.bss_addr = bce_COM_b09FwBssAddr;
3109                 fw.bss_len = bce_COM_b09FwBssLen;
3110                 fw.bss_index = 0;
3111                 fw.bss = bce_COM_b09FwBss;
3112
3113                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3114                 fw.rodata_len = bce_COM_b09FwRodataLen;
3115                 fw.rodata_index = 0;
3116                 fw.rodata = bce_COM_b09FwRodata;
3117         } else {
3118                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3119                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3120                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3121                 fw.start_addr = bce_COM_b06FwStartAddr;
3122
3123                 fw.text_addr = bce_COM_b06FwTextAddr;
3124                 fw.text_len = bce_COM_b06FwTextLen;
3125                 fw.text_index = 0;
3126                 fw.text = bce_COM_b06FwText;
3127
3128                 fw.data_addr = bce_COM_b06FwDataAddr;
3129                 fw.data_len = bce_COM_b06FwDataLen;
3130                 fw.data_index = 0;
3131                 fw.data = bce_COM_b06FwData;
3132
3133                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3134                 fw.sbss_len = bce_COM_b06FwSbssLen;
3135                 fw.sbss_index = 0;
3136                 fw.sbss = bce_COM_b06FwSbss;
3137
3138                 fw.bss_addr = bce_COM_b06FwBssAddr;
3139                 fw.bss_len = bce_COM_b06FwBssLen;
3140                 fw.bss_index = 0;
3141                 fw.bss = bce_COM_b06FwBss;
3142
3143                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3144                 fw.rodata_len = bce_COM_b06FwRodataLen;
3145                 fw.rodata_index = 0;
3146                 fw.rodata = bce_COM_b06FwRodata;
3147         }
3148
3149         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3150         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3151         bce_start_cpu(sc, &cpu_reg);
3152 }
3153
3154
3155 /****************************************************************************/
3156 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3157 /*                                                                          */
3158 /* Loads the firmware for each CPU and starts the CPU.                      */
3159 /*                                                                          */
3160 /* Returns:                                                                 */
3161 /*   Nothing.                                                               */
3162 /****************************************************************************/
3163 static void
3164 bce_init_cpus(struct bce_softc *sc)
3165 {
3166         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3167             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3168                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3169                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3170                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3171                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3172                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3173                 } else {
3174                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3175                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3176                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3177                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3178                 }
3179         } else {
3180                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3181                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3182                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3183                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3184         }
3185
3186         bce_init_rxp_cpu(sc);
3187         bce_init_txp_cpu(sc);
3188         bce_init_tpat_cpu(sc);
3189         bce_init_com_cpu(sc);
3190         bce_init_cp_cpu(sc);
3191 }
3192
3193
3194 /****************************************************************************/
3195 /* Initialize context memory.                                               */
3196 /*                                                                          */
3197 /* Clears the memory associated with each Context ID (CID).                 */
3198 /*                                                                          */
3199 /* Returns:                                                                 */
3200 /*   Nothing.                                                               */
3201 /****************************************************************************/
3202 static int
3203 bce_init_ctx(struct bce_softc *sc)
3204 {
3205         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3206             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3207                 /* DRC: Replace this constant value with a #define. */
3208                 int i, retry_cnt = 10;
3209                 uint32_t val;
3210
3211                 /*
3212                  * BCM5709 context memory may be cached
3213                  * in host memory so prepare the host memory
3214                  * for access.
3215                  */
3216                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3217                     (1 << 12);
3218                 val |= (BCM_PAGE_BITS - 8) << 16;
3219                 REG_WR(sc, BCE_CTX_COMMAND, val);
3220
3221                 /* Wait for mem init command to complete. */
3222                 for (i = 0; i < retry_cnt; i++) {
3223                         val = REG_RD(sc, BCE_CTX_COMMAND);
3224                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3225                                 break;
3226                         DELAY(2);
3227                 }
3228                 if (i == retry_cnt) {
3229                         device_printf(sc->bce_dev,
3230                             "Context memory initialization failed!\n");
3231                         return ETIMEDOUT;
3232                 }
3233
3234                 for (i = 0; i < sc->ctx_pages; i++) {
3235                         int j;
3236
3237                         /*
3238                          * Set the physical address of the context
3239                          * memory cache.
3240                          */
3241                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3242                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3243                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3244                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3245                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3246                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3247                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3248
3249                         /*
3250                          * Verify that the context memory write was successful.
3251                          */
3252                         for (j = 0; j < retry_cnt; j++) {
3253                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3254                                 if ((val &
3255                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3256                                         break;
3257                                 DELAY(5);
3258                         }
3259                         if (j == retry_cnt) {
3260                                 device_printf(sc->bce_dev,
3261                                     "Failed to initialize context page!\n");
3262                                 return ETIMEDOUT;
3263                         }
3264                 }
3265         } else {
3266                 uint32_t vcid_addr, offset;
3267
3268                 /*
3269                  * For the 5706/5708, context memory is local to
3270                  * the controller, so initialize the controller
3271                  * context memory.
3272                  */
3273
3274                 vcid_addr = GET_CID_ADDR(96);
3275                 while (vcid_addr) {
3276                         vcid_addr -= PHY_CTX_SIZE;
3277
3278                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3279                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3280
3281                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3282                                 CTX_WR(sc, 0x00, offset, 0);
3283
3284                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3285                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3286                 }
3287         }
3288         return 0;
3289 }
3290
3291
3292 /****************************************************************************/
3293 /* Fetch the permanent MAC address of the controller.                       */
3294 /*                                                                          */
3295 /* Returns:                                                                 */
3296 /*   Nothing.                                                               */
3297 /****************************************************************************/
3298 static void
3299 bce_get_mac_addr(struct bce_softc *sc)
3300 {
3301         uint32_t mac_lo = 0, mac_hi = 0;
3302
3303         /*
3304          * The NetXtreme II bootcode populates various NIC
3305          * power-on and runtime configuration items in a
3306          * shared memory area.  The factory configured MAC
3307          * address is available from both NVRAM and the
3308          * shared memory area so we'll read the value from
3309          * shared memory for speed.
3310          */
3311
3312         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3313         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3314
3315         if (mac_lo == 0 && mac_hi == 0) {
3316                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3317         } else {
3318                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3319                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3320                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3321                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3322                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3323                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3324         }
3325
3326         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3327 }
3328
3329
3330 /****************************************************************************/
3331 /* Program the MAC address.                                                 */
3332 /*                                                                          */
3333 /* Returns:                                                                 */
3334 /*   Nothing.                                                               */
3335 /****************************************************************************/
3336 static void
3337 bce_set_mac_addr(struct bce_softc *sc)
3338 {
3339         const uint8_t *mac_addr = sc->eaddr;
3340         uint32_t val;
3341
3342         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3343                 sc->eaddr, ":");
3344
3345         val = (mac_addr[0] << 8) | mac_addr[1];
3346         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3347
3348         val = (mac_addr[2] << 24) |
3349               (mac_addr[3] << 16) |
3350               (mac_addr[4] << 8) |
3351               mac_addr[5];
3352         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3353 }
3354
3355
3356 /****************************************************************************/
3357 /* Stop the controller.                                                     */
3358 /*                                                                          */
3359 /* Returns:                                                                 */
3360 /*   Nothing.                                                               */
3361 /****************************************************************************/
3362 static void
3363 bce_stop(struct bce_softc *sc)
3364 {
3365         struct ifnet *ifp = &sc->arpcom.ac_if;
3366
3367         ASSERT_SERIALIZED(ifp->if_serializer);
3368
3369         callout_stop(&sc->bce_tick_callout);
3370
3371         /* Disable the transmit/receive blocks. */
3372         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3373         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3374         DELAY(20);
3375
3376         bce_disable_intr(sc);
3377
3378         /* Free the RX lists. */
3379         bce_free_rx_chain(sc);
3380
3381         /* Free TX buffers. */
3382         bce_free_tx_chain(sc);
3383
3384         sc->bce_link = 0;
3385         sc->bce_coalchg_mask = 0;
3386
3387         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3388         ifp->if_timer = 0;
3389 }
3390
3391
3392 static int
3393 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3394 {
3395         uint32_t val;
3396         int i, rc = 0;
3397
3398         /* Wait for pending PCI transactions to complete. */
3399         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3400                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3401                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3402                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3403                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3404         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3405         DELAY(5);
3406
3407         /* Disable DMA */
3408         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3409             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3410                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3411                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3412                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3413         }
3414
3415         /* Assume bootcode is running. */
3416         sc->bce_fw_timed_out = 0;
3417         sc->bce_drv_cardiac_arrest = 0;
3418
3419         /* Give the firmware a chance to prepare for the reset. */
3420         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3421         if (rc) {
3422                 if_printf(&sc->arpcom.ac_if,
3423                           "Firmware is not ready for reset\n");
3424                 return rc;
3425         }
3426
3427         /* Set a firmware reminder that this is a soft reset. */
3428         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3429             BCE_DRV_RESET_SIGNATURE_MAGIC);
3430
3431         /* Dummy read to force the chip to complete all current transactions. */
3432         val = REG_RD(sc, BCE_MISC_ID);
3433
3434         /* Chip reset. */
3435         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3436             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3437                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3438                 REG_RD(sc, BCE_MISC_COMMAND);
3439                 DELAY(5);
3440
3441                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3442                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3443
3444                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3445         } else {
3446                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3447                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3448                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3449                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3450
3451                 /* Allow up to 30us for reset to complete. */
3452                 for (i = 0; i < 10; i++) {
3453                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3454                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3455                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3456                                 break;
3457                         DELAY(10);
3458                 }
3459
3460                 /* Check that reset completed successfully. */
3461                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3462                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3463                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3464                         return EBUSY;
3465                 }
3466         }
3467
3468         /* Make sure byte swapping is properly configured. */
3469         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3470         if (val != 0x01020304) {
3471                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3472                 return ENODEV;
3473         }
3474
3475         /* Just completed a reset, assume that firmware is running again. */
3476         sc->bce_fw_timed_out = 0;
3477         sc->bce_drv_cardiac_arrest = 0;
3478
3479         /* Wait for the firmware to finish its initialization. */
3480         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3481         if (rc) {
3482                 if_printf(&sc->arpcom.ac_if,
3483                           "Firmware did not complete initialization!\n");
3484         }
3485         return rc;
3486 }
3487
3488
3489 static int
3490 bce_chipinit(struct bce_softc *sc)
3491 {
3492         uint32_t val;
3493         int rc = 0;
3494
3495         /* Make sure the interrupt is not active. */
3496         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3497         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3498
3499         /*
3500          * Initialize DMA byte/word swapping, configure the number of DMA
3501          * channels and PCI clock compensation delay.
3502          */
3503         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3504               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3505 #if BYTE_ORDER == BIG_ENDIAN
3506               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3507 #endif
3508               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3509               DMA_READ_CHANS << 12 |
3510               DMA_WRITE_CHANS << 16;
3511
3512         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3513
3514         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3515                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3516
3517         /*
3518          * This setting resolves a problem observed on certain Intel PCI
3519          * chipsets that cannot handle multiple outstanding DMA operations.
3520          * See errata E9_5706A1_65.
3521          */
3522         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3523             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3524             !(sc->bce_flags & BCE_PCIX_FLAG))
3525                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3526
3527         REG_WR(sc, BCE_DMA_CONFIG, val);
3528
3529         /* Enable the RX_V2P and Context state machines before access. */
3530         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3531                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3532                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3533                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3534
3535         /* Initialize context mapping and zero out the quick contexts. */
3536         rc = bce_init_ctx(sc);
3537         if (rc != 0)
3538                 return rc;
3539
3540         /* Initialize the on-boards CPUs */
3541         bce_init_cpus(sc);
3542
3543         /* Enable management frames (NC-SI) to flow to the MCP. */
3544         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3545                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3546                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3547                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3548         }
3549
3550         /* Prepare NVRAM for access. */
3551         rc = bce_init_nvram(sc);
3552         if (rc != 0)
3553                 return rc;
3554
3555         /* Set the kernel bypass block size */
3556         val = REG_RD(sc, BCE_MQ_CONFIG);
3557         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3558         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3559
3560         /* Enable bins used on the 5709/5716. */
3561         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3562             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3563                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3564                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3565                         val |= BCE_MQ_CONFIG_HALT_DIS;
3566         }
3567
3568         REG_WR(sc, BCE_MQ_CONFIG, val);
3569
3570         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3571         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3572         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3573
3574         /* Set the page size and clear the RV2P processor stall bits. */
3575         val = (BCM_PAGE_BITS - 8) << 24;
3576         REG_WR(sc, BCE_RV2P_CONFIG, val);
3577
3578         /* Configure page size. */
3579         val = REG_RD(sc, BCE_TBDR_CONFIG);
3580         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3581         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3582         REG_WR(sc, BCE_TBDR_CONFIG, val);
3583
3584         /* Set the perfect match control register to default. */
3585         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3586
3587         return 0;
3588 }
3589
3590
3591 /****************************************************************************/
3592 /* Initialize the controller in preparation to send/receive traffic.        */
3593 /*                                                                          */
3594 /* Returns:                                                                 */
3595 /*   0 for success, positive value for failure.                             */
3596 /****************************************************************************/
3597 static int
3598 bce_blockinit(struct bce_softc *sc)
3599 {
3600         uint32_t reg, val;
3601         int rc = 0;
3602
3603         /* Load the hardware default MAC address. */
3604         bce_set_mac_addr(sc);
3605
3606         /* Set the Ethernet backoff seed value */
3607         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3608               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3609         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3610
3611         sc->last_status_idx = 0;
3612         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3613
3614         /* Set up link change interrupt generation. */
3615         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3616
3617         /* Program the physical address of the status block. */
3618         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3619         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3620
3621         /* Program the physical address of the statistics block. */
3622         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3623                BCE_ADDR_LO(sc->stats_block_paddr));
3624         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3625                BCE_ADDR_HI(sc->stats_block_paddr));
3626
3627         /* Program various host coalescing parameters. */
3628         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3629                (sc->bce_tx_quick_cons_trip_int << 16) |
3630                sc->bce_tx_quick_cons_trip);
3631         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3632                (sc->bce_rx_quick_cons_trip_int << 16) |
3633                sc->bce_rx_quick_cons_trip);
3634         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3635                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3636         REG_WR(sc, BCE_HC_TX_TICKS,
3637                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3638         REG_WR(sc, BCE_HC_RX_TICKS,
3639                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3640         REG_WR(sc, BCE_HC_COM_TICKS,
3641                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3642         REG_WR(sc, BCE_HC_CMD_TICKS,
3643                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3644         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3645         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3646         REG_WR(sc, BCE_HC_CONFIG,
3647                BCE_HC_CONFIG_TX_TMR_MODE |
3648                BCE_HC_CONFIG_COLLECT_STATS);
3649
3650         /* Clear the internal statistics counters. */
3651         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3652
3653         /* Verify that bootcode is running. */
3654         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3655
3656         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3657                 if_printf(&sc->arpcom.ac_if,
3658                           "%s(%d): Simulating bootcode failure.\n",
3659                           __FILE__, __LINE__);
3660                 reg = 0);
3661
3662         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3663             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3664                 if_printf(&sc->arpcom.ac_if,
3665                           "Bootcode not running! Found: 0x%08X, "
3666                           "Expected: 08%08X\n",
3667                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3668                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3669                 return ENODEV;
3670         }
3671
3672         /* Enable DMA */
3673         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||