sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  */
  32
  33 /*
  34  * The following controllers are supported by this driver:
  35  *   BCM5706C A2, A3
  36  *   BCM5706S A2, A3
  37  *   BCM5708C B1, B2
  38  *   BCM5708S B1, B2
  39  *   BCM5709C A1, C0
  40  *   BCM5716  C0
  41  *
  42  * The following controllers are not supported by this driver:
  43  *   BCM5706C A0, A1
  44  *   BCM5706S A0, A1
  45  *   BCM5708C A0, B0
  46  *   BCM5708S A0, B0
  47  *   BCM5709C A0, B0, B1
  48  *   BCM5709S A0, A1, B0, B1, B2, C0
  49  */
  50
  51 #include "opt_bce.h"
  52 #include "opt_polling.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/bus.h>
  56 #include <sys/endian.h>
  57 #include <sys/kernel.h>
  58 #include <sys/interrupt.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/queue.h>
  62 #ifdef BCE_DEBUG
  63 #include <sys/random.h>
  64 #endif
  65 #include <sys/rman.h>
  66 #include <sys/serialize.h>
  67 #include <sys/socket.h>
  68 #include <sys/sockio.h>
  69 #include <sys/sysctl.h>
  70
  71 #include <net/bpf.h>
  72 #include <net/ethernet.h>
  73 #include <net/if.h>
  74 #include <net/if_arp.h>
  75 #include <net/if_dl.h>
  76 #include <net/if_media.h>
  77 #include <net/if_types.h>
  78 #include <net/ifq_var.h>
  79 #include <net/vlan/if_vlan_var.h>
  80 #include <net/vlan/if_vlan_ether.h>
  81
  82 #include <dev/netif/mii_layer/mii.h>
  83 #include <dev/netif/mii_layer/miivar.h>
  84
  85 #include <bus/pci/pcireg.h>
  86 #include <bus/pci/pcivar.h>
  87
  88 #include "miibus_if.h"
  89
  90 #include <dev/netif/bce/if_bcereg.h>
  91 #include <dev/netif/bce/if_bcefw.h>
  92
  93 /****************************************************************************/
  94 /* BCE Debug Options                                                        */
  95 /****************************************************************************/
  96 #ifdef BCE_DEBUG
  97
  98 static uint32_t bce_debug = BCE_WARN;
  99
 100 /*
 101  *          0 = Never
 102  *          1 = 1 in 2,147,483,648
 103  *        256 = 1 in     8,388,608
 104  *       2048 = 1 in     1,048,576
 105  *      65536 = 1 in        32,768
 106  *    1048576 = 1 in         2,048
 107  *  268435456 = 1 in             8
 108  *  536870912 = 1 in             4
 109  * 1073741824 = 1 in             2
 110  *
 111  * bce_debug_l2fhdr_status_check:
 112  *     How often the l2_fhdr frame error check will fail.
 113  *
 114  * bce_debug_unexpected_attention:
 115  *     How often the unexpected attention check will fail.
 116  *
 117  * bce_debug_mbuf_allocation_failure:
 118  *     How often to simulate an mbuf allocation failure.
 119  *
 120  * bce_debug_dma_map_addr_failure:
 121  *     How often to simulate a DMA mapping failure.
 122  *
 123  * bce_debug_bootcode_running_failure:
 124  *     How often to simulate a bootcode failure.
 125  */
 126 static int      bce_debug_l2fhdr_status_check = 0;
 127 static int      bce_debug_unexpected_attention = 0;
 128 static int      bce_debug_mbuf_allocation_failure = 0;
 129 static int      bce_debug_dma_map_addr_failure = 0;
 130 static int      bce_debug_bootcode_running_failure = 0;
 131
 132 #endif  /* BCE_DEBUG */
 133
 134
 135 /****************************************************************************/
 136 /* PCI Device ID Table                                                      */
 137 /*                                                                          */
 138 /* Used by bce_probe() to identify the devices supported by this driver.    */
 139 /****************************************************************************/
 140 #define BCE_DEVDESC_MAX         64
 141
 142 static struct bce_type bce_devs[] = {
 143         /* BCM5706C Controllers and OEM boards. */
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 145                 "HP NC370T Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 147                 "HP NC370i Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 149                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 151                 "HP NC371i Multifunction Gigabit Server Adapter" },
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 153                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 154
 155         /* BCM5706S controllers and OEM boards. */
 156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 157                 "HP NC370F Multifunction Gigabit Server Adapter" },
 158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 159                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 160
 161         /* BCM5708C controllers and OEM boards. */
 162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 163                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 165                 "HP NC373i Multifunction Gigabit Server Adapter" },
 166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 167                 "HP NC374m PCIe Multifunction Adapter" },
 168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 169                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 170
 171         /* BCM5708S controllers and OEM boards. */
 172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 173                 "HP NC373m Multifunction Gigabit Server Adapter" },
 174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 175                 "HP NC373i Multifunction Gigabit Server Adapter" },
 176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 177                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 179                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 180
 181         /* BCM5709C controllers and OEM boards. */
 182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 183                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 185                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 187                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 188
 189         /* BCM5709S controllers and OEM boards. */
 190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 191                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 193                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 195                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 196
 197         /* BCM5716 controllers and OEM boards. */
 198         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
 199                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 200
 201         { 0, 0, 0, 0, NULL }
 202 };
 203
 204
 205 /****************************************************************************/
 206 /* Supported Flash NVRAM device data.                                       */
 207 /****************************************************************************/
 208 static const struct flash_spec flash_table[] =
 209 {
 210 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 211 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 212
 213         /* Slow EEPROM */
 214         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 215          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 216          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 217          "EEPROM - slow"},
 218         /* Expansion entry 0001 */
 219         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 220          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 221          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 222          "Entry 0001"},
 223         /* Saifun SA25F010 (non-buffered flash) */
 224         /* strap, cfg1, & write1 need updates */
 225         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 226          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 227          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 228          "Non-buffered flash (128kB)"},
 229         /* Saifun SA25F020 (non-buffered flash) */
 230         /* strap, cfg1, & write1 need updates */
 231         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 232          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 233          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 234          "Non-buffered flash (256kB)"},
 235         /* Expansion entry 0100 */
 236         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 237          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 238          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 239          "Entry 0100"},
 240         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 241         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 242          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 243          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 244          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 245         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 246         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 247          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 248          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 249          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 250         /* Saifun SA25F005 (non-buffered flash) */
 251         /* strap, cfg1, & write1 need updates */
 252         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 253          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 254          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 255          "Non-buffered flash (64kB)"},
 256         /* Fast EEPROM */
 257         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 258          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 259          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 260          "EEPROM - fast"},
 261         /* Expansion entry 1001 */
 262         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 263          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 264          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 265          "Entry 1001"},
 266         /* Expansion entry 1010 */
 267         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 268          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 269          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 270          "Entry 1010"},
 271         /* ATMEL AT45DB011B (buffered flash) */
 272         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 273          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 274          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 275          "Buffered flash (128kB)"},
 276         /* Expansion entry 1100 */
 277         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 278          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 279          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 280          "Entry 1100"},
 281         /* Expansion entry 1101 */
 282         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 283          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 284          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 285          "Entry 1101"},
 286         /* Ateml Expansion entry 1110 */
 287         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 288          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 289          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 290          "Entry 1110 (Atmel)"},
 291         /* ATMEL AT45DB021B (buffered flash) */
 292         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 293          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 294          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 295          "Buffered flash (256kB)"},
 296 };
 297
 298 /*
 299  * The BCM5709 controllers transparently handle the
 300  * differences between Atmel 264 byte pages and all
 301  * flash devices which use 256 byte pages, so no
 302  * logical-to-physical mapping is required in the
 303  * driver.
 304  */
 305 static struct flash_spec flash_5709 = {
 306         .flags          = BCE_NV_BUFFERED,
 307         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 308         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 309         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 310         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 311         .name           = "5709/5716 buffered flash (256kB)",
 312 };
 313
 314
 315 /****************************************************************************/
 316 /* DragonFly device entry points.                                           */
 317 /****************************************************************************/
 318 static int      bce_probe(device_t);
 319 static int      bce_attach(device_t);
 320 static int      bce_detach(device_t);
 321 static void     bce_shutdown(device_t);
 322
 323 /****************************************************************************/
 324 /* BCE Debug Data Structure Dump Routines                                   */
 325 /****************************************************************************/
 326 #ifdef BCE_DEBUG
 327 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 328 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 329 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 330 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 331 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 332 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 333                                 struct l2_fhdr *) __unused;
 334 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 335 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 336 static void     bce_dump_status_block(struct bce_softc *);
 337 static void     bce_dump_driver_state(struct bce_softc *);
 338 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 339 static void     bce_dump_hw_state(struct bce_softc *);
 340 static void     bce_dump_txp_state(struct bce_softc *);
 341 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 342 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 343 static void     bce_freeze_controller(struct bce_softc *) __unused;
 344 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 345 static void     bce_breakpoint(struct bce_softc *);
 346 #endif  /* BCE_DEBUG */
 347
 348
 349 /****************************************************************************/
 350 /* BCE Register/Memory Access Routines                                      */
 351 /****************************************************************************/
 352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 353 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 354 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
 355 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
 356 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 357 static int      bce_miibus_read_reg(device_t, int, int);
 358 static int      bce_miibus_write_reg(device_t, int, int, int);
 359 static void     bce_miibus_statchg(device_t);
 360
 361
 362 /****************************************************************************/
 363 /* BCE NVRAM Access Routines                                                */
 364 /****************************************************************************/
 365 static int      bce_acquire_nvram_lock(struct bce_softc *);
 366 static int      bce_release_nvram_lock(struct bce_softc *);
 367 static void     bce_enable_nvram_access(struct bce_softc *);
 368 static void     bce_disable_nvram_access(struct bce_softc *);
 369 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 370                                      uint32_t);
 371 static int      bce_init_nvram(struct bce_softc *);
 372 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 373 static int      bce_nvram_test(struct bce_softc *);
 374
 375 /****************************************************************************/
 376 /* BCE DMA Allocate/Free Routines                                           */
 377 /****************************************************************************/
 378 static int      bce_dma_alloc(struct bce_softc *);
 379 static void     bce_dma_free(struct bce_softc *);
 380 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 381
 382 /****************************************************************************/
 383 /* BCE Firmware Synchronization and Load                                    */
 384 /****************************************************************************/
 385 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 386 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 387                                  uint32_t, uint32_t);
 388 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 389                                 struct fw_info *);
 390 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
 391 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
 392 static void     bce_start_rxp_cpu(struct bce_softc *);
 393 static void     bce_init_rxp_cpu(struct bce_softc *);
 394 static void     bce_init_txp_cpu(struct bce_softc *);
 395 static void     bce_init_tpat_cpu(struct bce_softc *);
 396 static void     bce_init_cp_cpu(struct bce_softc *);
 397 static void     bce_init_com_cpu(struct bce_softc *);
 398 static void     bce_init_cpus(struct bce_softc *);
 399
 400 static void     bce_stop(struct bce_softc *);
 401 static int      bce_reset(struct bce_softc *, uint32_t);
 402 static int      bce_chipinit(struct bce_softc *);
 403 static int      bce_blockinit(struct bce_softc *);
 404 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
 405                                uint32_t *, int);
 406 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
 407 static void     bce_probe_pci_caps(struct bce_softc *);
 408 static void     bce_print_adapter_info(struct bce_softc *);
 409 static void     bce_get_media(struct bce_softc *);
 410
 411 static void     bce_init_tx_context(struct bce_softc *);
 412 static int      bce_init_tx_chain(struct bce_softc *);
 413 static void     bce_init_rx_context(struct bce_softc *);
 414 static int      bce_init_rx_chain(struct bce_softc *);
 415 static void     bce_free_rx_chain(struct bce_softc *);
 416 static void     bce_free_tx_chain(struct bce_softc *);
 417
 418 static int      bce_encap(struct bce_softc *, struct mbuf **);
 419 static void     bce_start(struct ifnet *);
 420 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 421 static void     bce_watchdog(struct ifnet *);
 422 static int      bce_ifmedia_upd(struct ifnet *);
 423 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 424 static void     bce_init(void *);
 425 static void     bce_mgmt_init(struct bce_softc *);
 426
 427 static int      bce_init_ctx(struct bce_softc *);
 428 static void     bce_get_mac_addr(struct bce_softc *);
 429 static void     bce_set_mac_addr(struct bce_softc *);
 430 static void     bce_phy_intr(struct bce_softc *);
 431 static void     bce_rx_intr(struct bce_softc *, int);
 432 static void     bce_tx_intr(struct bce_softc *);
 433 static void     bce_disable_intr(struct bce_softc *);
 434 static void     bce_enable_intr(struct bce_softc *, int);
 435
 436 #ifdef DEVICE_POLLING
 437 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 438 #endif
 439 static void     bce_intr(void *);
 440 static void     bce_set_rx_mode(struct bce_softc *);
 441 static void     bce_stats_update(struct bce_softc *);
 442 static void     bce_tick(void *);
 443 static void     bce_tick_serialized(struct bce_softc *);
 444 static void     bce_pulse(void *);
 445 static void     bce_add_sysctls(struct bce_softc *);
 446
 447 static void     bce_coal_change(struct bce_softc *);
 448 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 449 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 450 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 451 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 452 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 453 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 454 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 455 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 456 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 457                                        uint32_t *, uint32_t);
 458
 459 /*
 460  * NOTE:
 461  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 462  * takes 1023 as the TX ticks limit.  However, using 1023 will
 463  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 464  * there is _no_ network activity on the NIC.
 465  */
 466 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 467 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 468 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 469 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 470 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 471 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
 472 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
 473 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
 474
 475 static int      bce_msi_enable = 1;
 476
 477 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 478 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 479 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 480 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 481 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 482 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 483 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 484 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 485 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
 486
 487 /****************************************************************************/
 488 /* DragonFly device dispatch table.                                         */
 489 /****************************************************************************/
 490 static device_method_t bce_methods[] = {
 491         /* Device interface */
 492         DEVMETHOD(device_probe,         bce_probe),
 493         DEVMETHOD(device_attach,        bce_attach),
 494         DEVMETHOD(device_detach,        bce_detach),
 495         DEVMETHOD(device_shutdown,      bce_shutdown),
 496
 497         /* bus interface */
 498         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 499         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 500
 501         /* MII interface */
 502         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 503         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 504         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 505
 506         { 0, 0 }
 507 };
 508
 509 static driver_t bce_driver = {
 510         "bce",
 511         bce_methods,
 512         sizeof(struct bce_softc)
 513 };
 514
 515 static devclass_t bce_devclass;
 516
 517
 518 DECLARE_DUMMY_MODULE(if_bce);
 519 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 520 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
 521 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 522
 523
 524 /****************************************************************************/
 525 /* Device probe function.                                                   */
 526 /*                                                                          */
 527 /* Compares the device to the driver's list of supported devices and        */
 528 /* reports back to the OS whether this is the right driver for the device.  */
 529 /*                                                                          */
 530 /* Returns:                                                                 */
 531 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 532 /****************************************************************************/
 533 static int
 534 bce_probe(device_t dev)
 535 {
 536         struct bce_type *t;
 537         uint16_t vid, did, svid, sdid;
 538
 539         /* Get the data for the device to be probed. */
 540         vid  = pci_get_vendor(dev);
 541         did  = pci_get_device(dev);
 542         svid = pci_get_subvendor(dev);
 543         sdid = pci_get_subdevice(dev);
 544
 545         /* Look through the list of known devices for a match. */
 546         for (t = bce_devs; t->bce_name != NULL; ++t) {
 547                 if (vid == t->bce_vid && did == t->bce_did &&
 548                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 549                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 550                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 551                         char *descbuf;
 552
 553                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 554
 555                         /* Print out the device identity. */
 556                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 557                                   t->bce_name,
 558                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 559
 560                         device_set_desc_copy(dev, descbuf);
 561                         kfree(descbuf, M_TEMP);
 562                         return 0;
 563                 }
 564         }
 565         return ENXIO;
 566 }
 567
 568
 569 /****************************************************************************/
 570 /* PCI Capabilities Probe Function.                                         */
 571 /*                                                                          */
 572 /* Walks the PCI capabiites list for the device to find what features are   */
 573 /* supported.                                                               */
 574 /*                                                                          */
 575 /* Returns:                                                                 */
 576 /*   None.                                                                  */
 577 /****************************************************************************/
 578 static void
 579 bce_print_adapter_info(struct bce_softc *sc)
 580 {
 581         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
 582
 583         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 584                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 585
 586         /* Bus info. */
 587         if (sc->bce_flags & BCE_PCIE_FLAG) {
 588                 kprintf("Bus (PCIe x%d, ", sc->link_width);
 589                 switch (sc->link_speed) {
 590                 case 1:
 591                         kprintf("2.5Gbps); ");
 592                         break;
 593                 case 2:
 594                         kprintf("5Gbps); ");
 595                         break;
 596                 default:
 597                         kprintf("Unknown link speed); ");
 598                         break;
 599                 }
 600         } else {
 601                 kprintf("Bus (PCI%s, %s, %dMHz); ",
 602                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 603                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
 604                     sc->bus_speed_mhz);
 605         }
 606
 607         /* Firmware version and device features. */
 608         kprintf("B/C (%s)", sc->bce_bc_ver);
 609
 610         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
 611             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 612                 kprintf("; Flags(");
 613                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
 614                         kprintf("MFW[%s]", sc->bce_mfw_ver);
 615                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 616                         kprintf(" 2.5G");
 617                 kprintf(")");
 618         }
 619         kprintf("\n");
 620 }
 621
 622
 623 /****************************************************************************/
 624 /* PCI Capabilities Probe Function.                                         */
 625 /*                                                                          */
 626 /* Walks the PCI capabiites list for the device to find what features are   */
 627 /* supported.                                                               */
 628 /*                                                                          */
 629 /* Returns:                                                                 */
 630 /*   None.                                                                  */
 631 /****************************************************************************/
 632 static void
 633 bce_probe_pci_caps(struct bce_softc *sc)
 634 {
 635         device_t dev = sc->bce_dev;
 636         uint8_t ptr;
 637
 638         if (pci_is_pcix(dev))
 639                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 640
 641         ptr = pci_get_pciecap_ptr(dev);
 642         if (ptr) {
 643                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
 644
 645                 sc->link_speed = link_status & 0xf;
 646                 sc->link_width = (link_status >> 4) & 0x3f;
 647                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 648                 sc->bce_flags |= BCE_PCIE_FLAG;
 649         }
 650 }
 651
 652
 653 /****************************************************************************/
 654 /* Device attach function.                                                  */
 655 /*                                                                          */
 656 /* Allocates device resources, performs secondary chip identification,      */
 657 /* resets and initializes the hardware, and initializes driver instance     */
 658 /* variables.                                                               */
 659 /*                                                                          */
 660 /* Returns:                                                                 */
 661 /*   0 on success, positive value on failure.                               */
 662 /****************************************************************************/
 663 static int
 664 bce_attach(device_t dev)
 665 {
 666         struct bce_softc *sc = device_get_softc(dev);
 667         struct ifnet *ifp = &sc->arpcom.ac_if;
 668         uint32_t val;
 669         u_int irq_flags;
 670         int rid, rc = 0;
 671         int i, j;
 672
 673         sc->bce_dev = dev;
 674         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 675
 676         pci_enable_busmaster(dev);
 677
 678         bce_probe_pci_caps(sc);
 679
 680         /* Allocate PCI memory resources. */
 681         rid = PCIR_BAR(0);
 682         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 683                                                  RF_ACTIVE | PCI_RF_DENSE);
 684         if (sc->bce_res_mem == NULL) {
 685                 device_printf(dev, "PCI memory allocation failed\n");
 686                 return ENXIO;
 687         }
 688         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 689         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 690
 691         /* Allocate PCI IRQ resources. */
 692         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
 693             &sc->bce_irq_rid, &irq_flags);
 694
 695         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 696             &sc->bce_irq_rid, irq_flags);
 697         if (sc->bce_res_irq == NULL) {
 698                 device_printf(dev, "PCI map interrupt failed\n");
 699                 rc = ENXIO;
 700                 goto fail;
 701         }
 702
 703         /*
 704          * Configure byte swap and enable indirect register access.
 705          * Rely on CPU to do target byte swapping on big endian systems.
 706          * Access to registers outside of PCI configurtion space are not
 707          * valid until this is done.
 708          */
 709         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 710                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 711                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 712
 713         /* Save ASIC revsion info. */
 714         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 715
 716         /* Weed out any non-production controller revisions. */
 717         switch (BCE_CHIP_ID(sc)) {
 718         case BCE_CHIP_ID_5706_A0:
 719         case BCE_CHIP_ID_5706_A1:
 720         case BCE_CHIP_ID_5708_A0:
 721         case BCE_CHIP_ID_5708_B0:
 722         case BCE_CHIP_ID_5709_A0:
 723         case BCE_CHIP_ID_5709_B0:
 724         case BCE_CHIP_ID_5709_B1:
 725 #ifdef foo
 726         /* 5709C B2 seems to work fine */
 727         case BCE_CHIP_ID_5709_B2:
 728 #endif
 729                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 730                               BCE_CHIP_ID(sc));
 731                 rc = ENODEV;
 732                 goto fail;
 733         }
 734
 735         /*
 736          * Find the base address for shared memory access.
 737          * Newer versions of bootcode use a signature and offset
 738          * while older versions use a fixed address.
 739          */
 740         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 741         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
 742             BCE_SHM_HDR_SIGNATURE_SIG) {
 743                 /* Multi-port devices use different offsets in shared memory. */
 744                 sc->bce_shmem_base = REG_RD_IND(sc,
 745                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
 746         } else {
 747                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 748         }
 749         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 750
 751         /* Fetch the bootcode revision. */
 752         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
 753         for (i = 0, j = 0; i < 3; i++) {
 754                 uint8_t num;
 755                 int k, skip0;
 756
 757                 num = (uint8_t)(val >> (24 - (i * 8)));
 758                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
 759                         if (num >= k || !skip0 || k == 1) {
 760                                 sc->bce_bc_ver[j++] = (num / k) + '0';
 761                                 skip0 = 0;
 762                         }
 763                 }
 764                 if (i != 2)
 765                         sc->bce_bc_ver[j++] = '.';
 766         }
 767
 768         /* Check if any management firwmare is running. */
 769         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
 770         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
 771                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 772
 773                 /* Allow time for firmware to enter the running state. */
 774                 for (i = 0; i < 30; i++) {
 775                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 776                         if (val & BCE_CONDITION_MFW_RUN_MASK)
 777                                 break;
 778                         DELAY(10000);
 779                 }
 780         }
 781
 782         /* Check the current bootcode state. */
 783         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
 784             BCE_CONDITION_MFW_RUN_MASK;
 785         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
 786             val != BCE_CONDITION_MFW_RUN_NONE) {
 787                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
 788
 789                 for (i = 0, j = 0; j < 3; j++) {
 790                         val = bce_reg_rd_ind(sc, addr + j * 4);
 791                         val = bswap32(val);
 792                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
 793                         i += 4;
 794                 }
 795         }
 796
 797         /* Get PCI bus information (speed and type). */
 798         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 799         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 800                 uint32_t clkreg;
 801
 802                 sc->bce_flags |= BCE_PCIX_FLAG;
 803
 804                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 805                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 806                 switch (clkreg) {
 807                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 808                         sc->bus_speed_mhz = 133;
 809                         break;
 810
 811                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 812                         sc->bus_speed_mhz = 100;
 813                         break;
 814
 815                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 816                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 817                         sc->bus_speed_mhz = 66;
 818                         break;
 819
 820                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 821                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 822                         sc->bus_speed_mhz = 50;
 823                         break;
 824
 825                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 826                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 827                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 828                         sc->bus_speed_mhz = 33;
 829                         break;
 830                 }
 831         } else {
 832                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 833                         sc->bus_speed_mhz = 66;
 834                 else
 835                         sc->bus_speed_mhz = 33;
 836         }
 837
 838         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 839                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 840
 841         /* Reset the controller. */
 842         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 843         if (rc != 0)
 844                 goto fail;
 845
 846         /* Initialize the controller. */
 847         rc = bce_chipinit(sc);
 848         if (rc != 0) {
 849                 device_printf(dev, "Controller initialization failed!\n");
 850                 goto fail;
 851         }
 852
 853         /* Perform NVRAM test. */
 854         rc = bce_nvram_test(sc);
 855         if (rc != 0) {
 856                 device_printf(dev, "NVRAM test failed!\n");
 857                 goto fail;
 858         }
 859
 860         /* Fetch the permanent Ethernet MAC address. */
 861         bce_get_mac_addr(sc);
 862
 863         /*
 864          * Trip points control how many BDs
 865          * should be ready before generating an
 866          * interrupt while ticks control how long
 867          * a BD can sit in the chain before
 868          * generating an interrupt.  Set the default
 869          * values for the RX and TX rings.
 870          */
 871
 872 #ifdef BCE_DRBUG
 873         /* Force more frequent interrupts. */
 874         sc->bce_tx_quick_cons_trip_int = 1;
 875         sc->bce_tx_quick_cons_trip     = 1;
 876         sc->bce_tx_ticks_int           = 0;
 877         sc->bce_tx_ticks               = 0;
 878
 879         sc->bce_rx_quick_cons_trip_int = 1;
 880         sc->bce_rx_quick_cons_trip     = 1;
 881         sc->bce_rx_ticks_int           = 0;
 882         sc->bce_rx_ticks               = 0;
 883 #else
 884         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 885         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 886         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 887         sc->bce_tx_ticks               = bce_tx_ticks;
 888
 889         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 890         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 891         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 892         sc->bce_rx_ticks               = bce_rx_ticks;
 893 #endif
 894
 895         /* Update statistics once every second. */
 896         sc->bce_stats_ticks = 1000000 & 0xffff00;
 897
 898         /* Find the media type for the adapter. */
 899         bce_get_media(sc);
 900
 901         /* Allocate DMA memory resources. */
 902         rc = bce_dma_alloc(sc);
 903         if (rc != 0) {
 904                 device_printf(dev, "DMA resource allocation failed!\n");
 905                 goto fail;
 906         }
 907
 908         /* Initialize the ifnet interface. */
 909         ifp->if_softc = sc;
 910         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 911         ifp->if_ioctl = bce_ioctl;
 912         ifp->if_start = bce_start;
 913         ifp->if_init = bce_init;
 914         ifp->if_watchdog = bce_watchdog;
 915 #ifdef DEVICE_POLLING
 916         ifp->if_poll = bce_poll;
 917 #endif
 918         ifp->if_mtu = ETHERMTU;
 919         ifp->if_hwassist = BCE_IF_HWASSIST;
 920         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 921         ifp->if_capenable = ifp->if_capabilities;
 922         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
 923         ifq_set_ready(&ifp->if_snd);
 924
 925         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 926                 ifp->if_baudrate = IF_Gbps(2.5);
 927         else
 928                 ifp->if_baudrate = IF_Gbps(1);
 929
 930         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 931         sc->mbuf_alloc_size  = MCLBYTES;
 932
 933         /* Look for our PHY. */
 934         rc = mii_phy_probe(dev, &sc->bce_miibus,
 935                            bce_ifmedia_upd, bce_ifmedia_sts);
 936         if (rc != 0) {
 937                 device_printf(dev, "PHY probe failed!\n");
 938                 goto fail;
 939         }
 940
 941         /* Attach to the Ethernet interface list. */
 942         ether_ifattach(ifp, sc->eaddr, NULL);
 943
 944         callout_init_mp(&sc->bce_tick_callout);
 945         callout_init_mp(&sc->bce_pulse_callout);
 946
 947         /* Hookup IRQ last. */
 948         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
 949                             &sc->bce_intrhand, ifp->if_serializer);
 950         if (rc != 0) {
 951                 device_printf(dev, "Failed to setup IRQ!\n");
 952                 ether_ifdetach(ifp);
 953                 goto fail;
 954         }
 955
 956         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
 957         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 958
 959         /* Print some important debugging info. */
 960         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 961
 962         /* Add the supported sysctls to the kernel. */
 963         bce_add_sysctls(sc);
 964
 965         /*
 966          * The chip reset earlier notified the bootcode that
 967          * a driver is present.  We now need to start our pulse
 968          * routine so that the bootcode is reminded that we're
 969          * still running.
 970          */
 971         bce_pulse(sc);
 972
 973         /* Get the firmware running so IPMI still works */
 974         bce_mgmt_init(sc);
 975
 976         if (bootverbose)
 977                 bce_print_adapter_info(sc);
 978
 979         return 0;
 980 fail:
 981         bce_detach(dev);
 982         return(rc);
 983 }
 984
 985
 986 /****************************************************************************/
 987 /* Device detach function.                                                  */
 988 /*                                                                          */
 989 /* Stops the controller, resets the controller, and releases resources.     */
 990 /*                                                                          */
 991 /* Returns:                                                                 */
 992 /*   0 on success, positive value on failure.                               */
 993 /****************************************************************************/
 994 static int
 995 bce_detach(device_t dev)
 996 {
 997         struct bce_softc *sc = device_get_softc(dev);
 998
 999         if (device_is_attached(dev)) {
1000                 struct ifnet *ifp = &sc->arpcom.ac_if;
1001                 uint32_t msg;
1002
1003                 /* Stop and reset the controller. */
1004                 lwkt_serialize_enter(ifp->if_serializer);
1005                 callout_stop(&sc->bce_pulse_callout);
1006                 bce_stop(sc);
1007                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1008                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1009                 else
1010                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1011                 bce_reset(sc, msg);
1012                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1013                 lwkt_serialize_exit(ifp->if_serializer);
1014
1015                 ether_ifdetach(ifp);
1016         }
1017
1018         /* If we have a child device on the MII bus remove it too. */
1019         if (sc->bce_miibus)
1020                 device_delete_child(dev, sc->bce_miibus);
1021         bus_generic_detach(dev);
1022
1023         if (sc->bce_res_irq != NULL) {
1024                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1025                     sc->bce_res_irq);
1026         }
1027
1028         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1029                 pci_release_msi(dev);
1030
1031         if (sc->bce_res_mem != NULL) {
1032                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1033                                      sc->bce_res_mem);
1034         }
1035
1036         bce_dma_free(sc);
1037
1038         if (sc->bce_sysctl_tree != NULL)
1039                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1040
1041         return 0;
1042 }
1043
1044
1045 /****************************************************************************/
1046 /* Device shutdown function.                                                */
1047 /*                                                                          */
1048 /* Stops and resets the controller.                                         */
1049 /*                                                                          */
1050 /* Returns:                                                                 */
1051 /*   Nothing                                                                */
1052 /****************************************************************************/
1053 static void
1054 bce_shutdown(device_t dev)
1055 {
1056         struct bce_softc *sc = device_get_softc(dev);
1057         struct ifnet *ifp = &sc->arpcom.ac_if;
1058         uint32_t msg;
1059
1060         lwkt_serialize_enter(ifp->if_serializer);
1061         bce_stop(sc);
1062         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1063                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1064         else
1065                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1066         bce_reset(sc, msg);
1067         lwkt_serialize_exit(ifp->if_serializer);
1068 }
1069
1070
1071 /****************************************************************************/
1072 /* Indirect register read.                                                  */
1073 /*                                                                          */
1074 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1075 /* configuration space.  Using this mechanism avoids issues with posted     */
1076 /* reads but is much slower than memory-mapped I/O.                         */
1077 /*                                                                          */
1078 /* Returns:                                                                 */
1079 /*   The value of the register.                                             */
1080 /****************************************************************************/
1081 static uint32_t
1082 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1083 {
1084         device_t dev = sc->bce_dev;
1085
1086         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1087 #ifdef BCE_DEBUG
1088         {
1089                 uint32_t val;
1090                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1091                 DBPRINT(sc, BCE_EXCESSIVE,
1092                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1093                         __func__, offset, val);
1094                 return val;
1095         }
1096 #else
1097         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1098 #endif
1099 }
1100
1101
1102 /****************************************************************************/
1103 /* Indirect register write.                                                 */
1104 /*                                                                          */
1105 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1106 /* configuration space.  Using this mechanism avoids issues with posted     */
1107 /* writes but is muchh slower than memory-mapped I/O.                       */
1108 /*                                                                          */
1109 /* Returns:                                                                 */
1110 /*   Nothing.                                                               */
1111 /****************************************************************************/
1112 static void
1113 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1114 {
1115         device_t dev = sc->bce_dev;
1116
1117         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1118                 __func__, offset, val);
1119
1120         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1121         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1122 }
1123
1124
1125 /****************************************************************************/
1126 /* Shared memory write.                                                     */
1127 /*                                                                          */
1128 /* Writes NetXtreme II shared memory region.                                */
1129 /*                                                                          */
1130 /* Returns:                                                                 */
1131 /*   Nothing.                                                               */
1132 /****************************************************************************/
1133 static void
1134 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1135 {
1136         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1137 }
1138
1139
1140 /****************************************************************************/
1141 /* Shared memory read.                                                      */
1142 /*                                                                          */
1143 /* Reads NetXtreme II shared memory region.                                 */
1144 /*                                                                          */
1145 /* Returns:                                                                 */
1146 /*   The 32 bit value read.                                                 */
1147 /****************************************************************************/
1148 static u32
1149 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1150 {
1151         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1152 }
1153
1154
1155 /****************************************************************************/
1156 /* Context memory write.                                                    */
1157 /*                                                                          */
1158 /* The NetXtreme II controller uses context memory to track connection      */
1159 /* information for L2 and higher network protocols.                         */
1160 /*                                                                          */
1161 /* Returns:                                                                 */
1162 /*   Nothing.                                                               */
1163 /****************************************************************************/
1164 static void
1165 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1166     uint32_t ctx_val)
1167 {
1168         uint32_t idx, offset = ctx_offset + cid_addr;
1169         uint32_t val, retry_cnt = 5;
1170
1171         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1172             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1173                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1174                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1175
1176                 for (idx = 0; idx < retry_cnt; idx++) {
1177                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1178                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1179                                 break;
1180                         DELAY(5);
1181                 }
1182
1183                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1184                         device_printf(sc->bce_dev,
1185                             "Unable to write CTX memory: "
1186                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1187                             cid_addr, ctx_offset);
1188                 }
1189         } else {
1190                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1191                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1192         }
1193 }
1194
1195
1196 /****************************************************************************/
1197 /* PHY register read.                                                       */
1198 /*                                                                          */
1199 /* Implements register reads on the MII bus.                                */
1200 /*                                                                          */
1201 /* Returns:                                                                 */
1202 /*   The value of the register.                                             */
1203 /****************************************************************************/
1204 static int
1205 bce_miibus_read_reg(device_t dev, int phy, int reg)
1206 {
1207         struct bce_softc *sc = device_get_softc(dev);
1208         uint32_t val;
1209         int i;
1210
1211         /* Make sure we are accessing the correct PHY address. */
1212         if (phy != sc->bce_phy_addr) {
1213                 DBPRINT(sc, BCE_VERBOSE,
1214                         "Invalid PHY address %d for PHY read!\n", phy);
1215                 return 0;
1216         }
1217
1218         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1219                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1220                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1221
1222                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1223                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1224
1225                 DELAY(40);
1226         }
1227
1228         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1229               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1230               BCE_EMAC_MDIO_COMM_START_BUSY;
1231         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1232
1233         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1234                 DELAY(10);
1235
1236                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1237                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1238                         DELAY(5);
1239
1240                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1241                         val &= BCE_EMAC_MDIO_COMM_DATA;
1242                         break;
1243                 }
1244         }
1245
1246         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1247                 if_printf(&sc->arpcom.ac_if,
1248                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1249                           phy, reg);
1250                 val = 0x0;
1251         } else {
1252                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1253         }
1254
1255         DBPRINT(sc, BCE_EXCESSIVE,
1256                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1257                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1258
1259         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1260                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1261                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1262
1263                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1264                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1265
1266                 DELAY(40);
1267         }
1268         return (val & 0xffff);
1269 }
1270
1271
1272 /****************************************************************************/
1273 /* PHY register write.                                                      */
1274 /*                                                                          */
1275 /* Implements register writes on the MII bus.                               */
1276 /*                                                                          */
1277 /* Returns:                                                                 */
1278 /*   The value of the register.                                             */
1279 /****************************************************************************/
1280 static int
1281 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1282 {
1283         struct bce_softc *sc = device_get_softc(dev);
1284         uint32_t val1;
1285         int i;
1286
1287         /* Make sure we are accessing the correct PHY address. */
1288         if (phy != sc->bce_phy_addr) {
1289                 DBPRINT(sc, BCE_WARN,
1290                         "Invalid PHY address %d for PHY write!\n", phy);
1291                 return(0);
1292         }
1293
1294         DBPRINT(sc, BCE_EXCESSIVE,
1295                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1296                 __func__, phy, (uint16_t)(reg & 0xffff),
1297                 (uint16_t)(val & 0xffff));
1298
1299         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1300                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1301                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1302
1303                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1304                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1305
1306                 DELAY(40);
1307         }
1308
1309         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1310                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1311                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1312         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1313
1314         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1315                 DELAY(10);
1316
1317                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1318                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1319                         DELAY(5);
1320                         break;
1321                 }
1322         }
1323
1324         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1325                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1326
1327         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1328                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1329                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1330
1331                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1332                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1333
1334                 DELAY(40);
1335         }
1336         return 0;
1337 }
1338
1339
1340 /****************************************************************************/
1341 /* MII bus status change.                                                   */
1342 /*                                                                          */
1343 /* Called by the MII bus driver when the PHY establishes link to set the    */
1344 /* MAC interface registers.                                                 */
1345 /*                                                                          */
1346 /* Returns:                                                                 */
1347 /*   Nothing.                                                               */
1348 /****************************************************************************/
1349 static void
1350 bce_miibus_statchg(device_t dev)
1351 {
1352         struct bce_softc *sc = device_get_softc(dev);
1353         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1354
1355         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1356                 mii->mii_media_active);
1357
1358 #ifdef BCE_DEBUG
1359         /* Decode the interface media flags. */
1360         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1361         switch(IFM_TYPE(mii->mii_media_active)) {
1362         case IFM_ETHER:
1363                 kprintf("Ethernet )");
1364                 break;
1365         default:
1366                 kprintf("Unknown )");
1367                 break;
1368         }
1369
1370         kprintf(" Media Options: ( ");
1371         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1372         case IFM_AUTO:
1373                 kprintf("Autoselect )");
1374                 break;
1375         case IFM_MANUAL:
1376                 kprintf("Manual )");
1377                 break;
1378         case IFM_NONE:
1379                 kprintf("None )");
1380                 break;
1381         case IFM_10_T:
1382                 kprintf("10Base-T )");
1383                 break;
1384         case IFM_100_TX:
1385                 kprintf("100Base-TX )");
1386                 break;
1387         case IFM_1000_SX:
1388                 kprintf("1000Base-SX )");
1389                 break;
1390         case IFM_1000_T:
1391                 kprintf("1000Base-T )");
1392                 break;
1393         default:
1394                 kprintf("Other )");
1395                 break;
1396         }
1397
1398         kprintf(" Global Options: (");
1399         if (mii->mii_media_active & IFM_FDX)
1400                 kprintf(" FullDuplex");
1401         if (mii->mii_media_active & IFM_HDX)
1402                 kprintf(" HalfDuplex");
1403         if (mii->mii_media_active & IFM_LOOP)
1404                 kprintf(" Loopback");
1405         if (mii->mii_media_active & IFM_FLAG0)
1406                 kprintf(" Flag0");
1407         if (mii->mii_media_active & IFM_FLAG1)
1408                 kprintf(" Flag1");
1409         if (mii->mii_media_active & IFM_FLAG2)
1410                 kprintf(" Flag2");
1411         kprintf(" )\n");
1412 #endif
1413
1414         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1415
1416         /*
1417          * Set MII or GMII interface based on the speed negotiated
1418          * by the PHY.
1419          */
1420         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1421             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1422                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1423                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1424         } else {
1425                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1426                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1427         }
1428
1429         /*
1430          * Set half or full duplex based on the duplicity negotiated
1431          * by the PHY.
1432          */
1433         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1434                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1435                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1436         } else {
1437                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1438                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1439         }
1440 }
1441
1442
1443 /****************************************************************************/
1444 /* Acquire NVRAM lock.                                                      */
1445 /*                                                                          */
1446 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1447 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1448 /* for use by the driver.                                                   */
1449 /*                                                                          */
1450 /* Returns:                                                                 */
1451 /*   0 on success, positive value on failure.                               */
1452 /****************************************************************************/
1453 static int
1454 bce_acquire_nvram_lock(struct bce_softc *sc)
1455 {
1456         uint32_t val;
1457         int j;
1458
1459         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1460
1461         /* Request access to the flash interface. */
1462         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1463         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1464                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1465                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1466                         break;
1467
1468                 DELAY(5);
1469         }
1470
1471         if (j >= NVRAM_TIMEOUT_COUNT) {
1472                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1473                 return EBUSY;
1474         }
1475         return 0;
1476 }
1477
1478
1479 /****************************************************************************/
1480 /* Release NVRAM lock.                                                      */
1481 /*                                                                          */
1482 /* When the caller is finished accessing NVRAM the lock must be released.   */
1483 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1484 /* for use by the driver.                                                   */
1485 /*                                                                          */
1486 /* Returns:                                                                 */
1487 /*   0 on success, positive value on failure.                               */
1488 /****************************************************************************/
1489 static int
1490 bce_release_nvram_lock(struct bce_softc *sc)
1491 {
1492         int j;
1493         uint32_t val;
1494
1495         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1496
1497         /*
1498          * Relinquish nvram interface.
1499          */
1500         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1501
1502         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1503                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1504                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1505                         break;
1506
1507                 DELAY(5);
1508         }
1509
1510         if (j >= NVRAM_TIMEOUT_COUNT) {
1511                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1512                 return EBUSY;
1513         }
1514         return 0;
1515 }
1516
1517
1518 /****************************************************************************/
1519 /* Enable NVRAM access.                                                     */
1520 /*                                                                          */
1521 /* Before accessing NVRAM for read or write operations the caller must      */
1522 /* enabled NVRAM access.                                                    */
1523 /*                                                                          */
1524 /* Returns:                                                                 */
1525 /*   Nothing.                                                               */
1526 /****************************************************************************/
1527 static void
1528 bce_enable_nvram_access(struct bce_softc *sc)
1529 {
1530         uint32_t val;
1531
1532         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1533
1534         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1535         /* Enable both bits, even on read. */
1536         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1537                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1538 }
1539
1540
1541 /****************************************************************************/
1542 /* Disable NVRAM access.                                                    */
1543 /*                                                                          */
1544 /* When the caller is finished accessing NVRAM access must be disabled.     */
1545 /*                                                                          */
1546 /* Returns:                                                                 */
1547 /*   Nothing.                                                               */
1548 /****************************************************************************/
1549 static void
1550 bce_disable_nvram_access(struct bce_softc *sc)
1551 {
1552         uint32_t val;
1553
1554         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1555
1556         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1557
1558         /* Disable both bits, even after read. */
1559         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1560                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1561 }
1562
1563
1564 /****************************************************************************/
1565 /* Read a dword (32 bits) from NVRAM.                                       */
1566 /*                                                                          */
1567 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1568 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1569 /*                                                                          */
1570 /* Returns:                                                                 */
1571 /*   0 on success and the 32 bit value read, positive value on failure.     */
1572 /****************************************************************************/
1573 static int
1574 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1575                      uint32_t cmd_flags)
1576 {
1577         uint32_t cmd;
1578         int i, rc = 0;
1579
1580         /* Build the command word. */
1581         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1582
1583         /* Calculate the offset for buffered flash. */
1584         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1585                 offset = ((offset / sc->bce_flash_info->page_size) <<
1586                           sc->bce_flash_info->page_bits) +
1587                          (offset % sc->bce_flash_info->page_size);
1588         }
1589
1590         /*
1591          * Clear the DONE bit separately, set the address to read,
1592          * and issue the read.
1593          */
1594         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1595         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1596         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1597
1598         /* Wait for completion. */
1599         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1600                 uint32_t val;
1601
1602                 DELAY(5);
1603
1604                 val = REG_RD(sc, BCE_NVM_COMMAND);
1605                 if (val & BCE_NVM_COMMAND_DONE) {
1606                         val = REG_RD(sc, BCE_NVM_READ);
1607
1608                         val = be32toh(val);
1609                         memcpy(ret_val, &val, 4);
1610                         break;
1611                 }
1612         }
1613
1614         /* Check for errors. */
1615         if (i >= NVRAM_TIMEOUT_COUNT) {
1616                 if_printf(&sc->arpcom.ac_if,
1617                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1618                           offset);
1619                 rc = EBUSY;
1620         }
1621         return rc;
1622 }
1623
1624
1625 /****************************************************************************/
1626 /* Initialize NVRAM access.                                                 */
1627 /*                                                                          */
1628 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1629 /* access that device.                                                      */
1630 /*                                                                          */
1631 /* Returns:                                                                 */
1632 /*   0 on success, positive value on failure.                               */
1633 /****************************************************************************/
1634 static int
1635 bce_init_nvram(struct bce_softc *sc)
1636 {
1637         uint32_t val;
1638         int j, entry_count, rc = 0;
1639         const struct flash_spec *flash;
1640
1641         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1642
1643         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1644             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1645                 sc->bce_flash_info = &flash_5709;
1646                 goto bce_init_nvram_get_flash_size;
1647         }
1648
1649         /* Determine the selected interface. */
1650         val = REG_RD(sc, BCE_NVM_CFG1);
1651
1652         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1653
1654         /*
1655          * Flash reconfiguration is required to support additional
1656          * NVRAM devices not directly supported in hardware.
1657          * Check if the flash interface was reconfigured
1658          * by the bootcode.
1659          */
1660
1661         if (val & 0x40000000) {
1662                 /* Flash interface reconfigured by bootcode. */
1663
1664                 DBPRINT(sc, BCE_INFO_LOAD,
1665                         "%s(): Flash WAS reconfigured.\n", __func__);
1666
1667                 for (j = 0, flash = flash_table; j < entry_count;
1668                      j++, flash++) {
1669                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1670                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1671                                 sc->bce_flash_info = flash;
1672                                 break;
1673                         }
1674                 }
1675         } else {
1676                 /* Flash interface not yet reconfigured. */
1677                 uint32_t mask;
1678
1679                 DBPRINT(sc, BCE_INFO_LOAD,
1680                         "%s(): Flash was NOT reconfigured.\n", __func__);
1681
1682                 if (val & (1 << 23))
1683                         mask = FLASH_BACKUP_STRAP_MASK;
1684                 else
1685                         mask = FLASH_STRAP_MASK;
1686
1687                 /* Look for the matching NVRAM device configuration data. */
1688                 for (j = 0, flash = flash_table; j < entry_count;
1689                      j++, flash++) {
1690                         /* Check if the device matches any of the known devices. */
1691                         if ((val & mask) == (flash->strapping & mask)) {
1692                                 /* Found a device match. */
1693                                 sc->bce_flash_info = flash;
1694
1695                                 /* Request access to the flash interface. */
1696                                 rc = bce_acquire_nvram_lock(sc);
1697                                 if (rc != 0)
1698                                         return rc;
1699
1700                                 /* Reconfigure the flash interface. */
1701                                 bce_enable_nvram_access(sc);
1702                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1703                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1704                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1705                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1706                                 bce_disable_nvram_access(sc);
1707                                 bce_release_nvram_lock(sc);
1708                                 break;
1709                         }
1710                 }
1711         }
1712
1713         /* Check if a matching device was found. */
1714         if (j == entry_count) {
1715                 sc->bce_flash_info = NULL;
1716                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1717                 return ENODEV;
1718         }
1719
1720 bce_init_nvram_get_flash_size:
1721         /* Write the flash config data to the shared memory interface. */
1722         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1723             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1724         if (val)
1725                 sc->bce_flash_size = val;
1726         else
1727                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1728
1729         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1730                 __func__, sc->bce_flash_info->total_size);
1731
1732         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1733
1734         return rc;
1735 }
1736
1737
1738 /****************************************************************************/
1739 /* Read an arbitrary range of data from NVRAM.                              */
1740 /*                                                                          */
1741 /* Prepares the NVRAM interface for access and reads the requested data     */
1742 /* into the supplied buffer.                                                */
1743 /*                                                                          */
1744 /* Returns:                                                                 */
1745 /*   0 on success and the data read, positive value on failure.             */
1746 /****************************************************************************/
1747 static int
1748 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1749                int buf_size)
1750 {
1751         uint32_t cmd_flags, offset32, len32, extra;
1752         int rc = 0;
1753
1754         if (buf_size == 0)
1755                 return 0;
1756
1757         /* Request access to the flash interface. */
1758         rc = bce_acquire_nvram_lock(sc);
1759         if (rc != 0)
1760                 return rc;
1761
1762         /* Enable access to flash interface */
1763         bce_enable_nvram_access(sc);
1764
1765         len32 = buf_size;
1766         offset32 = offset;
1767         extra = 0;
1768
1769         cmd_flags = 0;
1770
1771         /* XXX should we release nvram lock if read_dword() fails? */
1772         if (offset32 & 3) {
1773                 uint8_t buf[4];
1774                 uint32_t pre_len;
1775
1776                 offset32 &= ~3;
1777                 pre_len = 4 - (offset & 3);
1778
1779                 if (pre_len >= len32) {
1780                         pre_len = len32;
1781                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1782                 } else {
1783                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1784                 }
1785
1786                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1787                 if (rc)
1788                         return rc;
1789
1790                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1791
1792                 offset32 += 4;
1793                 ret_buf += pre_len;
1794                 len32 -= pre_len;
1795         }
1796
1797         if (len32 & 3) {
1798                 extra = 4 - (len32 & 3);
1799                 len32 = (len32 + 4) & ~3;
1800         }
1801
1802         if (len32 == 4) {
1803                 uint8_t buf[4];
1804
1805                 if (cmd_flags)
1806                         cmd_flags = BCE_NVM_COMMAND_LAST;
1807                 else
1808                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1809                                     BCE_NVM_COMMAND_LAST;
1810
1811                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1812
1813                 memcpy(ret_buf, buf, 4 - extra);
1814         } else if (len32 > 0) {
1815                 uint8_t buf[4];
1816
1817                 /* Read the first word. */
1818                 if (cmd_flags)
1819                         cmd_flags = 0;
1820                 else
1821                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1822
1823                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1824
1825                 /* Advance to the next dword. */
1826                 offset32 += 4;
1827                 ret_buf += 4;
1828                 len32 -= 4;
1829
1830                 while (len32 > 4 && rc == 0) {
1831                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1832
1833                         /* Advance to the next dword. */
1834                         offset32 += 4;
1835                         ret_buf += 4;
1836                         len32 -= 4;
1837                 }
1838
1839                 if (rc)
1840                         goto bce_nvram_read_locked_exit;
1841
1842                 cmd_flags = BCE_NVM_COMMAND_LAST;
1843                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1844
1845                 memcpy(ret_buf, buf, 4 - extra);
1846         }
1847
1848 bce_nvram_read_locked_exit:
1849         /* Disable access to flash interface and release the lock. */
1850         bce_disable_nvram_access(sc);
1851         bce_release_nvram_lock(sc);
1852
1853         return rc;
1854 }
1855
1856
1857 /****************************************************************************/
1858 /* Verifies that NVRAM is accessible and contains valid data.               */
1859 /*                                                                          */
1860 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1861 /* correct.                                                                 */
1862 /*                                                                          */
1863 /* Returns:                                                                 */
1864 /*   0 on success, positive value on failure.                               */
1865 /****************************************************************************/
1866 static int
1867 bce_nvram_test(struct bce_softc *sc)
1868 {
1869         uint32_t buf[BCE_NVRAM_SIZE / 4];
1870         uint32_t magic, csum;
1871         uint8_t *data = (uint8_t *)buf;
1872         int rc = 0;
1873
1874         /*
1875          * Check that the device NVRAM is valid by reading
1876          * the magic value at offset 0.
1877          */
1878         rc = bce_nvram_read(sc, 0, data, 4);
1879         if (rc != 0)
1880                 return rc;
1881
1882         magic = be32toh(buf[0]);
1883         if (magic != BCE_NVRAM_MAGIC) {
1884                 if_printf(&sc->arpcom.ac_if,
1885                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1886                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1887                 return ENODEV;
1888         }
1889
1890         /*
1891          * Verify that the device NVRAM includes valid
1892          * configuration data.
1893          */
1894         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1895         if (rc != 0)
1896                 return rc;
1897
1898         csum = ether_crc32_le(data, 0x100);
1899         if (csum != BCE_CRC32_RESIDUAL) {
1900                 if_printf(&sc->arpcom.ac_if,
1901                           "Invalid Manufacturing Information NVRAM CRC! "
1902                           "Expected: 0x%08X, Found: 0x%08X\n",
1903                           BCE_CRC32_RESIDUAL, csum);
1904                 return ENODEV;
1905         }
1906
1907         csum = ether_crc32_le(data + 0x100, 0x100);
1908         if (csum != BCE_CRC32_RESIDUAL) {
1909                 if_printf(&sc->arpcom.ac_if,
1910                           "Invalid Feature Configuration Information "
1911                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1912                           BCE_CRC32_RESIDUAL, csum);
1913                 rc = ENODEV;
1914         }
1915         return rc;
1916 }
1917
1918
1919 /****************************************************************************/
1920 /* Identifies the current media type of the controller and sets the PHY     */
1921 /* address.                                                                 */
1922 /*                                                                          */
1923 /* Returns:                                                                 */
1924 /*   Nothing.                                                               */
1925 /****************************************************************************/
1926 static void
1927 bce_get_media(struct bce_softc *sc)
1928 {
1929         uint32_t val;
1930
1931         sc->bce_phy_addr = 1;
1932
1933         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1934             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1935                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1936                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1937                 uint32_t strap;
1938
1939                 /*
1940                  * The BCM5709S is software configurable
1941                  * for Copper or SerDes operation.
1942                  */
1943                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1944                         return;
1945                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1946                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1947                         return;
1948                 }
1949
1950                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1951                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1952                 } else {
1953                         strap =
1954                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1955                 }
1956
1957                 if (pci_get_function(sc->bce_dev) == 0) {
1958                         switch (strap) {
1959                         case 0x4:
1960                         case 0x5:
1961                         case 0x6:
1962                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1963                                 break;
1964                         }
1965                 } else {
1966                         switch (strap) {
1967                         case 0x1:
1968                         case 0x2:
1969                         case 0x4:
1970                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1971                                 break;
1972                         }
1973                 }
1974         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1975                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1976         }
1977
1978         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1979                 sc->bce_flags |= BCE_NO_WOL_FLAG;
1980                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1981                         sc->bce_phy_addr = 2;
1982                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1983                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1984                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1985                 }
1986         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1987             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1988                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1989         }
1990 }
1991
1992
1993 /****************************************************************************/
1994 /* Free any DMA memory owned by the driver.                                 */
1995 /*                                                                          */
1996 /* Scans through each data structre that requires DMA memory and frees      */
1997 /* the memory if allocated.                                                 */
1998 /*                                                                          */
1999 /* Returns:                                                                 */
2000 /*   Nothing.                                                               */
2001 /****************************************************************************/
2002 static void
2003 bce_dma_free(struct bce_softc *sc)
2004 {
2005         int i;
2006
2007         /* Destroy the status block. */
2008         if (sc->status_tag != NULL) {
2009                 if (sc->status_block != NULL) {
2010                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2011                         bus_dmamem_free(sc->status_tag, sc->status_block,
2012                                         sc->status_map);
2013                 }
2014                 bus_dma_tag_destroy(sc->status_tag);
2015         }
2016
2017
2018         /* Destroy the statistics block. */
2019         if (sc->stats_tag != NULL) {
2020                 if (sc->stats_block != NULL) {
2021                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2022                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2023                                         sc->stats_map);
2024                 }
2025                 bus_dma_tag_destroy(sc->stats_tag);
2026         }
2027
2028         /* Destroy the CTX DMA stuffs. */
2029         if (sc->ctx_tag != NULL) {
2030                 for (i = 0; i < sc->ctx_pages; i++) {
2031                         if (sc->ctx_block[i] != NULL) {
2032                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2033                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2034                                                 sc->ctx_map[i]);
2035                         }
2036                 }
2037                 bus_dma_tag_destroy(sc->ctx_tag);
2038         }
2039
2040         /* Destroy the TX buffer descriptor DMA stuffs. */
2041         if (sc->tx_bd_chain_tag != NULL) {
2042                 for (i = 0; i < TX_PAGES; i++) {
2043                         if (sc->tx_bd_chain[i] != NULL) {
2044                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2045                                                   sc->tx_bd_chain_map[i]);
2046                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2047                                                 sc->tx_bd_chain[i],
2048                                                 sc->tx_bd_chain_map[i]);
2049                         }
2050                 }
2051                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2052         }
2053
2054         /* Destroy the RX buffer descriptor DMA stuffs. */
2055         if (sc->rx_bd_chain_tag != NULL) {
2056                 for (i = 0; i < RX_PAGES; i++) {
2057                         if (sc->rx_bd_chain[i] != NULL) {
2058                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2059                                                   sc->rx_bd_chain_map[i]);
2060                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2061                                                 sc->rx_bd_chain[i],
2062                                                 sc->rx_bd_chain_map[i]);
2063                         }
2064                 }
2065                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2066         }
2067
2068         /* Destroy the TX mbuf DMA stuffs. */
2069         if (sc->tx_mbuf_tag != NULL) {
2070                 for (i = 0; i < TOTAL_TX_BD; i++) {
2071                         /* Must have been unloaded in bce_stop() */
2072                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2073                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2074                                            sc->tx_mbuf_map[i]);
2075                 }
2076                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2077         }
2078
2079         /* Destroy the RX mbuf DMA stuffs. */
2080         if (sc->rx_mbuf_tag != NULL) {
2081                 for (i = 0; i < TOTAL_RX_BD; i++) {
2082                         /* Must have been unloaded in bce_stop() */
2083                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2084                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2085                                            sc->rx_mbuf_map[i]);
2086                 }
2087                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2088                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2089         }
2090
2091         /* Destroy the parent tag */
2092         if (sc->parent_tag != NULL)
2093                 bus_dma_tag_destroy(sc->parent_tag);
2094 }
2095
2096
2097 /****************************************************************************/
2098 /* Get DMA memory from the OS.                                              */
2099 /*                                                                          */
2100 /* Validates that the OS has provided DMA buffers in response to a          */
2101 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2102 /* When the callback is used the OS will return 0 for the mapping function  */
2103 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2104 /* failures back to the caller.                                             */
2105 /*                                                                          */
2106 /* Returns:                                                                 */
2107 /*   Nothing.                                                               */
2108 /****************************************************************************/
2109 static void
2110 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2111 {
2112         bus_addr_t *busaddr = arg;
2113
2114         /*
2115          * Simulate a mapping failure.
2116          * XXX not correct.
2117          */
2118         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2119                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2120                         __FILE__, __LINE__);
2121                 error = ENOMEM);
2122
2123         /* Check for an error and signal the caller that an error occurred. */
2124         if (error)
2125                 return;
2126
2127         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2128         *busaddr = segs->ds_addr;
2129 }
2130
2131
2132 /****************************************************************************/
2133 /* Allocate any DMA memory needed by the driver.                            */
2134 /*                                                                          */
2135 /* Allocates DMA memory needed for the various global structures needed by  */
2136 /* hardware.                                                                */
2137 /*                                                                          */
2138 /* Memory alignment requirements:                                           */
2139 /* -----------------+----------+----------+----------+----------+           */
2140 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2141 /* -----------------+----------+----------+----------+----------+           */
2142 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2143 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2144 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2145 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2146 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2147 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2148 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2149 /* -----------------+----------+----------+----------+----------+           */
2150 /*                                                                          */
2151 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2152 /*                                                                          */
2153 /* Returns:                                                                 */
2154 /*   0 for success, positive value for failure.                             */
2155 /****************************************************************************/
2156 static int
2157 bce_dma_alloc(struct bce_softc *sc)
2158 {
2159         struct ifnet *ifp = &sc->arpcom.ac_if;
2160         int i, j, rc = 0;
2161         bus_addr_t busaddr, max_busaddr;
2162         bus_size_t status_align, stats_align;
2163
2164         /*
2165          * The embedded PCIe to PCI-X bridge (EPB)
2166          * in the 5708 cannot address memory above
2167          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2168          */
2169         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2170                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2171         else
2172                 max_busaddr = BUS_SPACE_MAXADDR;
2173
2174         /*
2175          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2176          */
2177         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2178             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2179                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2180                 if (sc->ctx_pages == 0)
2181                         sc->ctx_pages = 1;
2182                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2183                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2184                             sc->ctx_pages);
2185                         return ENOMEM;
2186                 }
2187                 status_align = 16;
2188                 stats_align = 16;
2189         } else {
2190                 status_align = 8;
2191                 stats_align = 8;
2192         }
2193
2194         /*
2195          * Allocate the parent bus DMA tag appropriate for PCI.
2196          */
2197         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2198                                 max_busaddr, BUS_SPACE_MAXADDR,
2199                                 NULL, NULL,
2200                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2201                                 BUS_SPACE_MAXSIZE_32BIT,
2202                                 0, &sc->parent_tag);
2203         if (rc != 0) {
2204                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2205                 return rc;
2206         }
2207
2208         /*
2209          * Allocate status block.
2210          */
2211         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2212                                 status_align, BCE_STATUS_BLK_SZ,
2213                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2214                                 &sc->status_tag, &sc->status_map,
2215                                 &sc->status_block_paddr);
2216         if (sc->status_block == NULL) {
2217                 if_printf(ifp, "Could not allocate status block!\n");
2218                 return ENOMEM;
2219         }
2220
2221         /*
2222          * Allocate statistics block.
2223          */
2224         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2225                                 stats_align, BCE_STATS_BLK_SZ,
2226                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2227                                 &sc->stats_tag, &sc->stats_map,
2228                                 &sc->stats_block_paddr);
2229         if (sc->stats_block == NULL) {
2230                 if_printf(ifp, "Could not allocate statistics block!\n");
2231                 return ENOMEM;
2232         }
2233
2234         /*
2235          * Allocate context block, if needed
2236          */
2237         if (sc->ctx_pages != 0) {
2238                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2239                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2240                                         NULL, NULL,
2241                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2242                                         0, &sc->ctx_tag);
2243                 if (rc != 0) {
2244                         if_printf(ifp, "Could not allocate "
2245                                   "context block DMA tag!\n");
2246                         return rc;
2247                 }
2248
2249                 for (i = 0; i < sc->ctx_pages; i++) {
2250                         rc = bus_dmamem_alloc(sc->ctx_tag,
2251                                               (void **)&sc->ctx_block[i],
2252                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2253                                               BUS_DMA_COHERENT,
2254                                               &sc->ctx_map[i]);
2255                         if (rc != 0) {
2256                                 if_printf(ifp, "Could not allocate %dth context "
2257                                           "DMA memory!\n", i);
2258                                 return rc;
2259                         }
2260
2261                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2262                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2263                                              bce_dma_map_addr, &busaddr,
2264                                              BUS_DMA_WAITOK);
2265                         if (rc != 0) {
2266                                 if (rc == EINPROGRESS) {
2267                                         panic("%s coherent memory loading "
2268                                               "is still in progress!", ifp->if_xname);
2269                                 }
2270                                 if_printf(ifp, "Could not map %dth context "
2271                                           "DMA memory!\n", i);
2272                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2273                                                 sc->ctx_map[i]);
2274                                 sc->ctx_block[i] = NULL;
2275                                 return rc;
2276                         }
2277                         sc->ctx_paddr[i] = busaddr;
2278                 }
2279         }
2280
2281         /*
2282          * Create a DMA tag for the TX buffer descriptor chain,
2283          * allocate and clear the  memory, and fetch the
2284          * physical address of the block.
2285          */
2286         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2287                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2288                                 NULL, NULL,
2289                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2290                                 0, &sc->tx_bd_chain_tag);
2291         if (rc != 0) {
2292                 if_printf(ifp, "Could not allocate "
2293                           "TX descriptor chain DMA tag!\n");
2294                 return rc;
2295         }
2296
2297         for (i = 0; i < TX_PAGES; i++) {
2298                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2299                                       (void **)&sc->tx_bd_chain[i],
2300                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2301                                       BUS_DMA_COHERENT,
2302                                       &sc->tx_bd_chain_map[i]);
2303                 if (rc != 0) {
2304                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2305                                   "chain DMA memory!\n", i);
2306                         return rc;
2307                 }
2308
2309                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2310                                      sc->tx_bd_chain_map[i],
2311                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2312                                      bce_dma_map_addr, &busaddr,
2313                                      BUS_DMA_WAITOK);
2314                 if (rc != 0) {
2315                         if (rc == EINPROGRESS) {
2316                                 panic("%s coherent memory loading "
2317                                       "is still in progress!", ifp->if_xname);
2318                         }
2319                         if_printf(ifp, "Could not map %dth TX descriptor "
2320                                   "chain DMA memory!\n", i);
2321                         bus_dmamem_free(sc->tx_bd_chain_tag,
2322                                         sc->tx_bd_chain[i],
2323                                         sc->tx_bd_chain_map[i]);
2324                         sc->tx_bd_chain[i] = NULL;
2325                         return rc;
2326                 }
2327
2328                 sc->tx_bd_chain_paddr[i] = busaddr;
2329                 /* DRC - Fix for 64 bit systems. */
2330                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2331                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2332         }
2333
2334         /* Create a DMA tag for TX mbufs. */
2335         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2336                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2337                                 NULL, NULL,
2338                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2339                                 BCE_MAX_SEGMENTS, MCLBYTES,
2340                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2341                                 BUS_DMA_ONEBPAGE,
2342                                 &sc->tx_mbuf_tag);
2343         if (rc != 0) {
2344                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2345                 return rc;
2346         }
2347
2348         /* Create DMA maps for the TX mbufs clusters. */
2349         for (i = 0; i < TOTAL_TX_BD; i++) {
2350                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2351                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2352                                        &sc->tx_mbuf_map[i]);
2353                 if (rc != 0) {
2354                         for (j = 0; j < i; ++j) {
2355                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2356                                                    sc->tx_mbuf_map[i]);
2357                         }
2358                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2359                         sc->tx_mbuf_tag = NULL;
2360
2361                         if_printf(ifp, "Unable to create "
2362                                   "%dth TX mbuf DMA map!\n", i);
2363                         return rc;
2364                 }
2365         }
2366
2367         /*
2368          * Create a DMA tag for the RX buffer descriptor chain,
2369          * allocate and clear the  memory, and fetch the physical
2370          * address of the blocks.
2371          */
2372         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2373                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2374                                 NULL, NULL,
2375                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2376                                 0, &sc->rx_bd_chain_tag);
2377         if (rc != 0) {
2378                 if_printf(ifp, "Could not allocate "
2379                           "RX descriptor chain DMA tag!\n");
2380                 return rc;
2381         }
2382
2383         for (i = 0; i < RX_PAGES; i++) {
2384                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2385                                       (void **)&sc->rx_bd_chain[i],
2386                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2387                                       BUS_DMA_COHERENT,
2388                                       &sc->rx_bd_chain_map[i]);
2389                 if (rc != 0) {
2390                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2391                                   "chain DMA memory!\n", i);
2392                         return rc;
2393                 }
2394
2395                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2396                                      sc->rx_bd_chain_map[i],
2397                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2398                                      bce_dma_map_addr, &busaddr,
2399                                      BUS_DMA_WAITOK);
2400                 if (rc != 0) {
2401                         if (rc == EINPROGRESS) {
2402                                 panic("%s coherent memory loading "
2403                                       "is still in progress!", ifp->if_xname);
2404                         }
2405                         if_printf(ifp, "Could not map %dth RX descriptor "
2406                                   "chain DMA memory!\n", i);
2407                         bus_dmamem_free(sc->rx_bd_chain_tag,
2408                                         sc->rx_bd_chain[i],
2409                                         sc->rx_bd_chain_map[i]);
2410                         sc->rx_bd_chain[i] = NULL;
2411                         return rc;
2412                 }
2413
2414                 sc->rx_bd_chain_paddr[i] = busaddr;
2415                 /* DRC - Fix for 64 bit systems. */
2416                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2417                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2418         }
2419
2420         /* Create a DMA tag for RX mbufs. */
2421         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2422                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2423                                 NULL, NULL,
2424                                 MCLBYTES, 1, MCLBYTES,
2425                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2426                                 BUS_DMA_WAITOK,
2427                                 &sc->rx_mbuf_tag);
2428         if (rc != 0) {
2429                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2430                 return rc;
2431         }
2432
2433         /* Create tmp DMA map for RX mbuf clusters. */
2434         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2435                                &sc->rx_mbuf_tmpmap);
2436         if (rc != 0) {
2437                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2438                 sc->rx_mbuf_tag = NULL;
2439
2440                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2441                 return rc;
2442         }
2443
2444         /* Create DMA maps for the RX mbuf clusters. */
2445         for (i = 0; i < TOTAL_RX_BD; i++) {
2446                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2447                                        &sc->rx_mbuf_map[i]);
2448                 if (rc != 0) {
2449                         for (j = 0; j < i; ++j) {
2450                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2451                                                    sc->rx_mbuf_map[j]);
2452                         }
2453                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2454                         sc->rx_mbuf_tag = NULL;
2455
2456                         if_printf(ifp, "Unable to create "
2457                                   "%dth RX mbuf DMA map!\n", i);
2458                         return rc;
2459                 }
2460         }
2461         return 0;
2462 }
2463
2464
2465 /****************************************************************************/
2466 /* Firmware synchronization.                                                */
2467 /*                                                                          */
2468 /* Before performing certain events such as a chip reset, synchronize with  */
2469 /* the firmware first.                                                      */
2470 /*                                                                          */
2471 /* Returns:                                                                 */
2472 /*   0 for success, positive value for failure.                             */
2473 /****************************************************************************/
2474 static int
2475 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2476 {
2477         int i, rc = 0;
2478         uint32_t val;
2479
2480         /* Don't waste any time if we've timed out before. */
2481         if (sc->bce_fw_timed_out)
2482                 return EBUSY;
2483
2484         /* Increment the message sequence number. */
2485         sc->bce_fw_wr_seq++;
2486         msg_data |= sc->bce_fw_wr_seq;
2487
2488         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2489
2490         /* Send the message to the bootcode driver mailbox. */
2491         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2492
2493         /* Wait for the bootcode to acknowledge the message. */
2494         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2495                 /* Check for a response in the bootcode firmware mailbox. */
2496                 val = bce_shmem_rd(sc, BCE_FW_MB);
2497                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2498                         break;
2499                 DELAY(1000);
2500         }
2501
2502         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2503         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2504             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2505                 if_printf(&sc->arpcom.ac_if,
2506                           "Firmware synchronization timeout! "
2507                           "msg_data = 0x%08X\n", msg_data);
2508
2509                 msg_data &= ~BCE_DRV_MSG_CODE;
2510                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2511
2512                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2513
2514                 sc->bce_fw_timed_out = 1;
2515                 rc = EBUSY;
2516         }
2517         return rc;
2518 }
2519
2520
2521 /****************************************************************************/
2522 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2523 /*                                                                          */
2524 /* Returns:                                                                 */
2525 /*   Nothing.                                                               */
2526 /****************************************************************************/
2527 static void
2528 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2529                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2530 {
2531         int i;
2532         uint32_t val;
2533
2534         for (i = 0; i < rv2p_code_len; i += 8) {
2535                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2536                 rv2p_code++;
2537                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2538                 rv2p_code++;
2539
2540                 if (rv2p_proc == RV2P_PROC1) {
2541                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2542                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2543                 } else {
2544                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2545                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2546                 }
2547         }
2548
2549         /* Reset the processor, un-stall is done later. */
2550         if (rv2p_proc == RV2P_PROC1)
2551                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2552         else
2553                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2554 }
2555
2556
2557 /****************************************************************************/
2558 /* Load RISC processor firmware.                                            */
2559 /*                                                                          */
2560 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2561 /* associated with a particular processor.                                  */
2562 /*                                                                          */
2563 /* Returns:                                                                 */
2564 /*   Nothing.                                                               */
2565 /****************************************************************************/
2566 static void
2567 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2568                 struct fw_info *fw)
2569 {
2570         uint32_t offset;
2571         int j;
2572
2573         bce_halt_cpu(sc, cpu_reg);
2574
2575         /* Load the Text area. */
2576         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2577         if (fw->text) {
2578                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2579                         REG_WR_IND(sc, offset, fw->text[j]);
2580         }
2581
2582         /* Load the Data area. */
2583         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2584         if (fw->data) {
2585                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2586                         REG_WR_IND(sc, offset, fw->data[j]);
2587         }
2588
2589         /* Load the SBSS area. */
2590         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2591         if (fw->sbss) {
2592                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2593                         REG_WR_IND(sc, offset, fw->sbss[j]);
2594         }
2595
2596         /* Load the BSS area. */
2597         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2598         if (fw->bss) {
2599                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2600                         REG_WR_IND(sc, offset, fw->bss[j]);
2601         }
2602
2603         /* Load the Read-Only area. */
2604         offset = cpu_reg->spad_base +
2605                 (fw->rodata_addr - cpu_reg->mips_view_base);
2606         if (fw->rodata) {
2607                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2608                         REG_WR_IND(sc, offset, fw->rodata[j]);
2609         }
2610
2611         /* Clear the pre-fetch instruction and set the FW start address. */
2612         REG_WR_IND(sc, cpu_reg->inst, 0);
2613         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2614 }
2615
2616
2617 /****************************************************************************/
2618 /* Starts the RISC processor.                                               */
2619 /*                                                                          */
2620 /* Assumes the CPU starting address has already been set.                   */
2621 /*                                                                          */
2622 /* Returns:                                                                 */
2623 /*   Nothing.                                                               */
2624 /****************************************************************************/
2625 static void
2626 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2627 {
2628         uint32_t val;
2629
2630         /* Start the CPU. */
2631         val = REG_RD_IND(sc, cpu_reg->mode);
2632         val &= ~cpu_reg->mode_value_halt;
2633         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2634         REG_WR_IND(sc, cpu_reg->mode, val);
2635 }
2636
2637
2638 /****************************************************************************/
2639 /* Halts the RISC processor.                                                */
2640 /*                                                                          */
2641 /* Returns:                                                                 */
2642 /*   Nothing.                                                               */
2643 /****************************************************************************/
2644 static void
2645 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2646 {
2647         uint32_t val;
2648
2649         /* Halt the CPU. */
2650         val = REG_RD_IND(sc, cpu_reg->mode);
2651         val |= cpu_reg->mode_value_halt;
2652         REG_WR_IND(sc, cpu_reg->mode, val);
2653         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2654 }
2655
2656
2657 /****************************************************************************/
2658 /* Start the RX CPU.                                                        */
2659 /*                                                                          */
2660 /* Returns:                                                                 */
2661 /*   Nothing.                                                               */
2662 /****************************************************************************/
2663 static void
2664 bce_start_rxp_cpu(struct bce_softc *sc)
2665 {
2666         struct cpu_reg cpu_reg;
2667
2668         cpu_reg.mode = BCE_RXP_CPU_MODE;
2669         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2670         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2671         cpu_reg.state = BCE_RXP_CPU_STATE;
2672         cpu_reg.state_value_clear = 0xffffff;
2673         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2674         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2675         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2676         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2677         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2678         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2679         cpu_reg.mips_view_base = 0x8000000;
2680
2681         bce_start_cpu(sc, &cpu_reg);
2682 }
2683
2684
2685 /****************************************************************************/
2686 /* Initialize the RX CPU.                                                   */
2687 /*                                                                          */
2688 /* Returns:                                                                 */
2689 /*   Nothing.                                                               */
2690 /****************************************************************************/
2691 static void
2692 bce_init_rxp_cpu(struct bce_softc *sc)
2693 {
2694         struct cpu_reg cpu_reg;
2695         struct fw_info fw;
2696
2697         cpu_reg.mode = BCE_RXP_CPU_MODE;
2698         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2699         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2700         cpu_reg.state = BCE_RXP_CPU_STATE;
2701         cpu_reg.state_value_clear = 0xffffff;
2702         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2703         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2704         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2705         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2706         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2707         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2708         cpu_reg.mips_view_base = 0x8000000;
2709
2710         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2711             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2712                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2713                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2714                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2715                 fw.start_addr = bce_RXP_b09FwStartAddr;
2716
2717                 fw.text_addr = bce_RXP_b09FwTextAddr;
2718                 fw.text_len = bce_RXP_b09FwTextLen;
2719                 fw.text_index = 0;
2720                 fw.text = bce_RXP_b09FwText;
2721
2722                 fw.data_addr = bce_RXP_b09FwDataAddr;
2723                 fw.data_len = bce_RXP_b09FwDataLen;
2724                 fw.data_index = 0;
2725                 fw.data = bce_RXP_b09FwData;
2726
2727                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2728                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2729                 fw.sbss_index = 0;
2730                 fw.sbss = bce_RXP_b09FwSbss;
2731
2732                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2733                 fw.bss_len = bce_RXP_b09FwBssLen;
2734                 fw.bss_index = 0;
2735                 fw.bss = bce_RXP_b09FwBss;
2736
2737                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2738                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2739                 fw.rodata_index = 0;
2740                 fw.rodata = bce_RXP_b09FwRodata;
2741         } else {
2742                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2743                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2744                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2745                 fw.start_addr = bce_RXP_b06FwStartAddr;
2746
2747                 fw.text_addr = bce_RXP_b06FwTextAddr;
2748                 fw.text_len = bce_RXP_b06FwTextLen;
2749                 fw.text_index = 0;
2750                 fw.text = bce_RXP_b06FwText;
2751
2752                 fw.data_addr = bce_RXP_b06FwDataAddr;
2753                 fw.data_len = bce_RXP_b06FwDataLen;
2754                 fw.data_index = 0;
2755                 fw.data = bce_RXP_b06FwData;
2756
2757                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2758                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2759                 fw.sbss_index = 0;
2760                 fw.sbss = bce_RXP_b06FwSbss;
2761
2762                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2763                 fw.bss_len = bce_RXP_b06FwBssLen;
2764                 fw.bss_index = 0;
2765                 fw.bss = bce_RXP_b06FwBss;
2766
2767                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2768                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2769                 fw.rodata_index = 0;
2770                 fw.rodata = bce_RXP_b06FwRodata;
2771         }
2772
2773         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2774         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2775         /* Delay RXP start until initialization is complete. */
2776 }
2777
2778
2779 /****************************************************************************/
2780 /* Initialize the TX CPU.                                                   */
2781 /*                                                                          */
2782 /* Returns:                                                                 */
2783 /*   Nothing.                                                               */
2784 /****************************************************************************/
2785 static void
2786 bce_init_txp_cpu(struct bce_softc *sc)
2787 {
2788         struct cpu_reg cpu_reg;
2789         struct fw_info fw;
2790
2791         cpu_reg.mode = BCE_TXP_CPU_MODE;
2792         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2793         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2794         cpu_reg.state = BCE_TXP_CPU_STATE;
2795         cpu_reg.state_value_clear = 0xffffff;
2796         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2797         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2798         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2799         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2800         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2801         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2802         cpu_reg.mips_view_base = 0x8000000;
2803
2804         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2805             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2806                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2807                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2808                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2809                 fw.start_addr = bce_TXP_b09FwStartAddr;
2810
2811                 fw.text_addr = bce_TXP_b09FwTextAddr;
2812                 fw.text_len = bce_TXP_b09FwTextLen;
2813                 fw.text_index = 0;
2814                 fw.text = bce_TXP_b09FwText;
2815
2816                 fw.data_addr = bce_TXP_b09FwDataAddr;
2817                 fw.data_len = bce_TXP_b09FwDataLen;
2818                 fw.data_index = 0;
2819                 fw.data = bce_TXP_b09FwData;
2820
2821                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2822                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2823                 fw.sbss_index = 0;
2824                 fw.sbss = bce_TXP_b09FwSbss;
2825
2826                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2827                 fw.bss_len = bce_TXP_b09FwBssLen;
2828                 fw.bss_index = 0;
2829                 fw.bss = bce_TXP_b09FwBss;
2830
2831                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2832                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2833                 fw.rodata_index = 0;
2834                 fw.rodata = bce_TXP_b09FwRodata;
2835         } else {
2836                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2837                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2838                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2839                 fw.start_addr = bce_TXP_b06FwStartAddr;
2840
2841                 fw.text_addr = bce_TXP_b06FwTextAddr;
2842                 fw.text_len = bce_TXP_b06FwTextLen;
2843                 fw.text_index = 0;
2844                 fw.text = bce_TXP_b06FwText;
2845
2846                 fw.data_addr = bce_TXP_b06FwDataAddr;
2847                 fw.data_len = bce_TXP_b06FwDataLen;
2848                 fw.data_index = 0;
2849                 fw.data = bce_TXP_b06FwData;
2850
2851                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2852                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2853                 fw.sbss_index = 0;
2854                 fw.sbss = bce_TXP_b06FwSbss;
2855
2856                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2857                 fw.bss_len = bce_TXP_b06FwBssLen;
2858                 fw.bss_index = 0;
2859                 fw.bss = bce_TXP_b06FwBss;
2860
2861                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2862                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2863                 fw.rodata_index = 0;
2864                 fw.rodata = bce_TXP_b06FwRodata;
2865         }
2866
2867         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2868         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2869         bce_start_cpu(sc, &cpu_reg);
2870 }
2871
2872
2873 /****************************************************************************/
2874 /* Initialize the TPAT CPU.                                                 */
2875 /*                                                                          */
2876 /* Returns:                                                                 */
2877 /*   Nothing.                                                               */
2878 /****************************************************************************/
2879 static void
2880 bce_init_tpat_cpu(struct bce_softc *sc)
2881 {
2882         struct cpu_reg cpu_reg;
2883         struct fw_info fw;
2884
2885         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2886         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2887         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2888         cpu_reg.state = BCE_TPAT_CPU_STATE;
2889         cpu_reg.state_value_clear = 0xffffff;
2890         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2891         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2892         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2893         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2894         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2895         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2896         cpu_reg.mips_view_base = 0x8000000;
2897
2898         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2899             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2900                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2901                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2902                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2903                 fw.start_addr = bce_TPAT_b09FwStartAddr;
2904
2905                 fw.text_addr = bce_TPAT_b09FwTextAddr;
2906                 fw.text_len = bce_TPAT_b09FwTextLen;
2907                 fw.text_index = 0;
2908                 fw.text = bce_TPAT_b09FwText;
2909
2910                 fw.data_addr = bce_TPAT_b09FwDataAddr;
2911                 fw.data_len = bce_TPAT_b09FwDataLen;
2912                 fw.data_index = 0;
2913                 fw.data = bce_TPAT_b09FwData;
2914
2915                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2916                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2917                 fw.sbss_index = 0;
2918                 fw.sbss = bce_TPAT_b09FwSbss;
2919
2920                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2921                 fw.bss_len = bce_TPAT_b09FwBssLen;
2922                 fw.bss_index = 0;
2923                 fw.bss = bce_TPAT_b09FwBss;
2924
2925                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2926                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2927                 fw.rodata_index = 0;
2928                 fw.rodata = bce_TPAT_b09FwRodata;
2929         } else {
2930                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2931                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2932                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2933                 fw.start_addr = bce_TPAT_b06FwStartAddr;
2934
2935                 fw.text_addr = bce_TPAT_b06FwTextAddr;
2936                 fw.text_len = bce_TPAT_b06FwTextLen;
2937                 fw.text_index = 0;
2938                 fw.text = bce_TPAT_b06FwText;
2939
2940                 fw.data_addr = bce_TPAT_b06FwDataAddr;
2941                 fw.data_len = bce_TPAT_b06FwDataLen;
2942                 fw.data_index = 0;
2943                 fw.data = bce_TPAT_b06FwData;
2944
2945                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2946                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2947                 fw.sbss_index = 0;
2948                 fw.sbss = bce_TPAT_b06FwSbss;
2949
2950                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2951                 fw.bss_len = bce_TPAT_b06FwBssLen;
2952                 fw.bss_index = 0;
2953                 fw.bss = bce_TPAT_b06FwBss;
2954
2955                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2956                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2957                 fw.rodata_index = 0;
2958                 fw.rodata = bce_TPAT_b06FwRodata;
2959         }
2960
2961         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2962         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2963         bce_start_cpu(sc, &cpu_reg);
2964 }
2965
2966
2967 /****************************************************************************/
2968 /* Initialize the CP CPU.                                                   */
2969 /*                                                                          */
2970 /* Returns:                                                                 */
2971 /*   Nothing.                                                               */
2972 /****************************************************************************/
2973 static void
2974 bce_init_cp_cpu(struct bce_softc *sc)
2975 {
2976         struct cpu_reg cpu_reg;
2977         struct fw_info fw;
2978
2979         cpu_reg.mode = BCE_CP_CPU_MODE;
2980         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2981         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2982         cpu_reg.state = BCE_CP_CPU_STATE;
2983         cpu_reg.state_value_clear = 0xffffff;
2984         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
2985         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
2986         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
2987         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
2988         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
2989         cpu_reg.spad_base = BCE_CP_SCRATCH;
2990         cpu_reg.mips_view_base = 0x8000000;
2991
2992         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2993             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2994                 fw.ver_major = bce_CP_b09FwReleaseMajor;
2995                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
2996                 fw.ver_fix = bce_CP_b09FwReleaseFix;
2997                 fw.start_addr = bce_CP_b09FwStartAddr;
2998
2999                 fw.text_addr = bce_CP_b09FwTextAddr;
3000                 fw.text_len = bce_CP_b09FwTextLen;
3001                 fw.text_index = 0;
3002                 fw.text = bce_CP_b09FwText;
3003
3004                 fw.data_addr = bce_CP_b09FwDataAddr;
3005                 fw.data_len = bce_CP_b09FwDataLen;
3006                 fw.data_index = 0;
3007                 fw.data = bce_CP_b09FwData;
3008
3009                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3010                 fw.sbss_len = bce_CP_b09FwSbssLen;
3011                 fw.sbss_index = 0;
3012                 fw.sbss = bce_CP_b09FwSbss;
3013
3014                 fw.bss_addr = bce_CP_b09FwBssAddr;
3015                 fw.bss_len = bce_CP_b09FwBssLen;
3016                 fw.bss_index = 0;
3017                 fw.bss = bce_CP_b09FwBss;
3018
3019                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3020                 fw.rodata_len = bce_CP_b09FwRodataLen;
3021                 fw.rodata_index = 0;
3022                 fw.rodata = bce_CP_b09FwRodata;
3023         } else {
3024                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3025                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3026                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3027                 fw.start_addr = bce_CP_b06FwStartAddr;
3028
3029                 fw.text_addr = bce_CP_b06FwTextAddr;
3030                 fw.text_len = bce_CP_b06FwTextLen;
3031                 fw.text_index = 0;
3032                 fw.text = bce_CP_b06FwText;
3033
3034                 fw.data_addr = bce_CP_b06FwDataAddr;
3035                 fw.data_len = bce_CP_b06FwDataLen;
3036                 fw.data_index = 0;
3037                 fw.data = bce_CP_b06FwData;
3038
3039                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3040                 fw.sbss_len = bce_CP_b06FwSbssLen;
3041                 fw.sbss_index = 0;
3042                 fw.sbss = bce_CP_b06FwSbss;
3043
3044                 fw.bss_addr = bce_CP_b06FwBssAddr;
3045                 fw.bss_len = bce_CP_b06FwBssLen;
3046                 fw.bss_index = 0;
3047                 fw.bss = bce_CP_b06FwBss;
3048
3049                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3050                 fw.rodata_len = bce_CP_b06FwRodataLen;
3051                 fw.rodata_index = 0;
3052                 fw.rodata = bce_CP_b06FwRodata;
3053         }
3054
3055         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3056         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3057         bce_start_cpu(sc, &cpu_reg);
3058 }
3059
3060
3061 /****************************************************************************/
3062 /* Initialize the COM CPU.                                                 */
3063 /*                                                                          */
3064 /* Returns:                                                                 */
3065 /*   Nothing.                                                               */
3066 /****************************************************************************/
3067 static void
3068 bce_init_com_cpu(struct bce_softc *sc)
3069 {
3070         struct cpu_reg cpu_reg;
3071         struct fw_info fw;
3072
3073         cpu_reg.mode = BCE_COM_CPU_MODE;
3074         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3075         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3076         cpu_reg.state = BCE_COM_CPU_STATE;
3077         cpu_reg.state_value_clear = 0xffffff;
3078         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3079         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3080         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3081         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3082         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3083         cpu_reg.spad_base = BCE_COM_SCRATCH;
3084         cpu_reg.mips_view_base = 0x8000000;
3085
3086         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3087             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3088                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3089                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3090                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3091                 fw.start_addr = bce_COM_b09FwStartAddr;
3092
3093                 fw.text_addr = bce_COM_b09FwTextAddr;
3094                 fw.text_len = bce_COM_b09FwTextLen;
3095                 fw.text_index = 0;
3096                 fw.text = bce_COM_b09FwText;
3097
3098                 fw.data_addr = bce_COM_b09FwDataAddr;
3099                 fw.data_len = bce_COM_b09FwDataLen;
3100                 fw.data_index = 0;
3101                 fw.data = bce_COM_b09FwData;
3102
3103                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3104                 fw.sbss_len = bce_COM_b09FwSbssLen;
3105                 fw.sbss_index = 0;
3106                 fw.sbss = bce_COM_b09FwSbss;
3107
3108                 fw.bss_addr = bce_COM_b09FwBssAddr;
3109                 fw.bss_len = bce_COM_b09FwBssLen;
3110                 fw.bss_index = 0;
3111                 fw.bss = bce_COM_b09FwBss;
3112
3113                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3114                 fw.rodata_len = bce_COM_b09FwRodataLen;
3115                 fw.rodata_index = 0;
3116                 fw.rodata = bce_COM_b09FwRodata;
3117         } else {
3118                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3119                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3120                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3121                 fw.start_addr = bce_COM_b06FwStartAddr;
3122
3123                 fw.text_addr = bce_COM_b06FwTextAddr;
3124                 fw.text_len = bce_COM_b06FwTextLen;
3125                 fw.text_index = 0;
3126                 fw.text = bce_COM_b06FwText;
3127
3128                 fw.data_addr = bce_COM_b06FwDataAddr;
3129                 fw.data_len = bce_COM_b06FwDataLen;
3130                 fw.data_index = 0;
3131                 fw.data = bce_COM_b06FwData;
3132
3133                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3134                 fw.sbss_len = bce_COM_b06FwSbssLen;
3135                 fw.sbss_index = 0;
3136                 fw.sbss = bce_COM_b06FwSbss;
3137
3138                 fw.bss_addr = bce_COM_b06FwBssAddr;
3139                 fw.bss_len = bce_COM_b06FwBssLen;
3140                 fw.bss_index = 0;
3141                 fw.bss = bce_COM_b06FwBss;
3142
3143                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3144                 fw.rodata_len = bce_COM_b06FwRodataLen;
3145                 fw.rodata_index = 0;
3146                 fw.rodata = bce_COM_b06FwRodata;
3147         }
3148
3149         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3150         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3151         bce_start_cpu(sc, &cpu_reg);
3152 }
3153
3154
3155 /****************************************************************************/
3156 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3157 /*                                                                          */
3158 /* Loads the firmware for each CPU and starts the CPU.                      */
3159 /*                                                                          */
3160 /* Returns:                                                                 */
3161 /*   Nothing.                                                               */
3162 /****************************************************************************/
3163 static void
3164 bce_init_cpus(struct bce_softc *sc)
3165 {
3166         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3167             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3168                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3169                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3170                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3171                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3172                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3173                 } else {
3174                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3175                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3176                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3177                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3178                 }
3179         } else {
3180                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3181                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3182                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3183                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3184         }
3185
3186         bce_init_rxp_cpu(sc);
3187         bce_init_txp_cpu(sc);
3188         bce_init_tpat_cpu(sc);
3189         bce_init_com_cpu(sc);
3190         bce_init_cp_cpu(sc);
3191 }
3192
3193
3194 /****************************************************************************/
3195 /* Initialize context memory.                                               */
3196 /*                                                                          */
3197 /* Clears the memory associated with each Context ID (CID).                 */
3198 /*                                                                          */
3199 /* Returns:                                                                 */
3200 /*   Nothing.                                                               */
3201 /****************************************************************************/
3202 static int
3203 bce_init_ctx(struct bce_softc *sc)
3204 {
3205         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3206             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3207                 /* DRC: Replace this constant value with a #define. */
3208                 int i, retry_cnt = 10;
3209                 uint32_t val;
3210
3211                 /*
3212                  * BCM5709 context memory may be cached
3213                  * in host memory so prepare the host memory
3214                  * for access.
3215                  */
3216                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3217                     (1 << 12);
3218                 val |= (BCM_PAGE_BITS - 8) << 16;
3219                 REG_WR(sc, BCE_CTX_COMMAND, val);
3220
3221                 /* Wait for mem init command to complete. */
3222                 for (i = 0; i < retry_cnt; i++) {
3223                         val = REG_RD(sc, BCE_CTX_COMMAND);
3224                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3225                                 break;
3226                         DELAY(2);
3227                 }
3228                 if (i == retry_cnt) {
3229                         device_printf(sc->bce_dev,
3230                             "Context memory initialization failed!\n");
3231                         return ETIMEDOUT;
3232                 }
3233
3234                 for (i = 0; i < sc->ctx_pages; i++) {
3235                         int j;
3236
3237                         /*
3238                          * Set the physical address of the context
3239                          * memory cache.
3240                          */
3241                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3242                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3243                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3244                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3245                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3246                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3247                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3248
3249                         /*
3250                          * Verify that the context memory write was successful.
3251                          */
3252                         for (j = 0; j < retry_cnt; j++) {
3253                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3254                                 if ((val &
3255                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3256                                         break;
3257                                 DELAY(5);
3258                         }
3259                         if (j == retry_cnt) {
3260                                 device_printf(sc->bce_dev,
3261                                     "Failed to initialize context page!\n");
3262                                 return ETIMEDOUT;
3263                         }
3264                 }
3265         } else {
3266                 uint32_t vcid_addr, offset;
3267
3268                 /*
3269                  * For the 5706/5708, context memory is local to
3270                  * the controller, so initialize the controller
3271                  * context memory.
3272                  */
3273
3274                 vcid_addr = GET_CID_ADDR(96);
3275                 while (vcid_addr) {
3276                         vcid_addr -= PHY_CTX_SIZE;
3277
3278                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3279                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3280
3281                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3282                                 CTX_WR(sc, 0x00, offset, 0);
3283
3284                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3285                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3286                 }
3287         }
3288         return 0;
3289 }
3290
3291
3292 /****************************************************************************/
3293 /* Fetch the permanent MAC address of the controller.                       */
3294 /*                                                                          */
3295 /* Returns:                                                                 */
3296 /*   Nothing.                                                               */
3297 /****************************************************************************/
3298 static void
3299 bce_get_mac_addr(struct bce_softc *sc)
3300 {
3301         uint32_t mac_lo = 0, mac_hi = 0;
3302
3303         /*
3304          * The NetXtreme II bootcode populates various NIC
3305          * power-on and runtime configuration items in a
3306          * shared memory area.  The factory configured MAC
3307          * address is available from both NVRAM and the
3308          * shared memory area so we'll read the value from
3309          * shared memory for speed.
3310          */
3311
3312         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3313         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3314
3315         if (mac_lo == 0 && mac_hi == 0) {
3316                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3317         } else {
3318                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3319                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3320                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3321                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3322                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3323                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3324         }
3325
3326         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3327 }
3328
3329
3330 /****************************************************************************/
3331 /* Program the MAC address.                                                 */
3332 /*                                                                          */
3333 /* Returns:                                                                 */
3334 /*   Nothing.                                                               */
3335 /****************************************************************************/
3336 static void
3337 bce_set_mac_addr(struct bce_softc *sc)
3338 {
3339         const uint8_t *mac_addr = sc->eaddr;
3340         uint32_t val;
3341
3342         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3343                 sc->eaddr, ":");
3344
3345         val = (mac_addr[0] << 8) | mac_addr[1];
3346         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3347
3348         val = (mac_addr[2] << 24) |
3349               (mac_addr[3] << 16) |
3350               (mac_addr[4] << 8) |
3351               mac_addr[5];
3352         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3353 }
3354
3355
3356 /****************************************************************************/
3357 /* Stop the controller.                                                     */
3358 /*                                                                          */
3359 /* Returns:                                                                 */
3360 /*   Nothing.                                                               */
3361 /****************************************************************************/
3362 static void
3363 bce_stop(struct bce_softc *sc)
3364 {
3365         struct ifnet *ifp = &sc->arpcom.ac_if;
3366
3367         ASSERT_SERIALIZED(ifp->if_serializer);
3368
3369         callout_stop(&sc->bce_tick_callout);
3370
3371         /* Disable the transmit/receive blocks. */
3372         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3373         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3374         DELAY(20);
3375
3376         bce_disable_intr(sc);
3377
3378         /* Free the RX lists. */
3379         bce_free_rx_chain(sc);
3380
3381         /* Free TX buffers. */
3382         bce_free_tx_chain(sc);
3383
3384         sc->bce_link = 0;
3385         sc->bce_coalchg_mask = 0;
3386
3387         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3388         ifp->if_timer = 0;
3389 }
3390
3391
3392 static int
3393 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3394 {
3395         uint32_t val;
3396         int i, rc = 0;
3397
3398         /* Wait for pending PCI transactions to complete. */
3399         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3400                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3401                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3402                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3403                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3404         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3405         DELAY(5);
3406
3407         /* Disable DMA */
3408         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3409             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3410                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3411                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3412                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3413         }
3414
3415         /* Assume bootcode is running. */
3416         sc->bce_fw_timed_out = 0;
3417         sc->bce_drv_cardiac_arrest = 0;
3418
3419         /* Give the firmware a chance to prepare for the reset. */
3420         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3421         if (rc) {
3422                 if_printf(&sc->arpcom.ac_if,
3423                           "Firmware is not ready for reset\n");
3424                 return rc;
3425         }
3426
3427         /* Set a firmware reminder that this is a soft reset. */
3428         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3429             BCE_DRV_RESET_SIGNATURE_MAGIC);
3430
3431         /* Dummy read to force the chip to complete all current transactions. */
3432         val = REG_RD(sc, BCE_MISC_ID);
3433
3434         /* Chip reset. */
3435         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3436             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3437                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3438                 REG_RD(sc, BCE_MISC_COMMAND);
3439                 DELAY(5);
3440
3441                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3442                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3443
3444                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3445         } else {
3446                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3447                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3448                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3449                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3450
3451                 /* Allow up to 30us for reset to complete. */
3452                 for (i = 0; i < 10; i++) {
3453                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3454                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3455                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3456                                 break;
3457                         DELAY(10);
3458                 }
3459
3460                 /* Check that reset completed successfully. */
3461                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3462                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3463                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3464                         return EBUSY;
3465                 }
3466         }
3467
3468         /* Make sure byte swapping is properly configured. */
3469         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3470         if (val != 0x01020304) {
3471                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3472                 return ENODEV;
3473         }
3474
3475         /* Just completed a reset, assume that firmware is running again. */
3476         sc->bce_fw_timed_out = 0;
3477         sc->bce_drv_cardiac_arrest = 0;
3478
3479         /* Wait for the firmware to finish its initialization. */
3480         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3481         if (rc) {
3482                 if_printf(&sc->arpcom.ac_if,
3483                           "Firmware did not complete initialization!\n");
3484         }
3485         return rc;
3486 }
3487
3488
3489 static int
3490 bce_chipinit(struct bce_softc *sc)
3491 {
3492         uint32_t val;
3493         int rc = 0;
3494
3495         /* Make sure the interrupt is not active. */
3496         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3497         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3498
3499         /*
3500          * Initialize DMA byte/word swapping, configure the number of DMA
3501          * channels and PCI clock compensation delay.
3502          */
3503         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3504               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3505 #if BYTE_ORDER == BIG_ENDIAN
3506               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3507 #endif
3508               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3509               DMA_READ_CHANS << 12 |
3510               DMA_WRITE_CHANS << 16;
3511
3512         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3513
3514         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3515                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3516
3517         /*
3518          * This setting resolves a problem observed on certain Intel PCI
3519          * chipsets that cannot handle multiple outstanding DMA operations.
3520          * See errata E9_5706A1_65.
3521          */
3522         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3523             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3524             !(sc->bce_flags & BCE_PCIX_FLAG))
3525                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3526
3527         REG_WR(sc, BCE_DMA_CONFIG, val);
3528
3529         /* Enable the RX_V2P and Context state machines before access. */
3530         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3531                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3532                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3533                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3534
3535         /* Initialize context mapping and zero out the quick contexts. */
3536         rc = bce_init_ctx(sc);
3537         if (rc != 0)
3538                 return rc;
3539
3540         /* Initialize the on-boards CPUs */
3541         bce_init_cpus(sc);
3542
3543         /* Enable management frames (NC-SI) to flow to the MCP. */
3544         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3545                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3546                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3547                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3548         }
3549
3550         /* Prepare NVRAM for access. */
3551         rc = bce_init_nvram(sc);
3552         if (rc != 0)
3553                 return rc;
3554
3555         /* Set the kernel bypass block size */
3556         val = REG_RD(sc, BCE_MQ_CONFIG);
3557         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3558         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3559
3560         /* Enable bins used on the 5709/5716. */
3561         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3562             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3563                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3564                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3565                         val |= BCE_MQ_CONFIG_HALT_DIS;
3566         }
3567
3568         REG_WR(sc, BCE_MQ_CONFIG, val);
3569
3570         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3571         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3572         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3573
3574         /* Set the page size and clear the RV2P processor stall bits. */
3575         val = (BCM_PAGE_BITS - 8) << 24;
3576         REG_WR(sc, BCE_RV2P_CONFIG, val);
3577
3578         /* Configure page size. */
3579         val = REG_RD(sc, BCE_TBDR_CONFIG);
3580         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3581         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3582         REG_WR(sc, BCE_TBDR_CONFIG, val);
3583
3584         /* Set the perfect match control register to default. */
3585         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3586
3587         return 0;
3588 }
3589
3590
3591 /****************************************************************************/
3592 /* Initialize the controller in preparation to send/receive traffic.        */
3593 /*                                                                          */
3594 /* Returns:                                                                 */
3595 /*   0 for success, positive value for failure.                             */
3596 /****************************************************************************/
3597 static int
3598 bce_blockinit(struct bce_softc *sc)
3599 {
3600         uint32_t reg, val;
3601         int rc = 0;
3602
3603         /* Load the hardware default MAC address. */
3604         bce_set_mac_addr(sc);
3605
3606         /* Set the Ethernet backoff seed value */
3607         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3608               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3609         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3610
3611         sc->last_status_idx = 0;
3612         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3613
3614         /* Set up link change interrupt generation. */
3615         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3616
3617         /* Program the physical address of the status block. */
3618         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3619         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3620
3621         /* Program the physical address of the statistics block. */
3622         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3623                BCE_ADDR_LO(sc->stats_block_paddr));
3624         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3625                BCE_ADDR_HI(sc->stats_block_paddr));
3626
3627         /* Program various host coalescing parameters. */
3628         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3629                (sc->bce_tx_quick_cons_trip_int << 16) |
3630                sc->bce_tx_quick_cons_trip);
3631         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3632                (sc->bce_rx_quick_cons_trip_int << 16) |
3633                sc->bce_rx_quick_cons_trip);
3634         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3635                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3636         REG_WR(sc, BCE_HC_TX_TICKS,
3637                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3638         REG_WR(sc, BCE_HC_RX_TICKS,
3639                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3640         REG_WR(sc, BCE_HC_COM_TICKS,
3641                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3642         REG_WR(sc, BCE_HC_CMD_TICKS,
3643                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3644         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3645         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3646         REG_WR(sc, BCE_HC_CONFIG,
3647                BCE_HC_CONFIG_TX_TMR_MODE |
3648                BCE_HC_CONFIG_COLLECT_STATS);
3649
3650         /* Clear the internal statistics counters. */
3651         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3652
3653         /* Verify that bootcode is running. */
3654         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3655
3656         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3657                 if_printf(&sc->arpcom.ac_if,
3658                           "%s(%d): Simulating bootcode failure.\n",
3659                           __FILE__, __LINE__);
3660                 reg = 0);
3661
3662         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3663             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3664                 if_printf(&sc->arpcom.ac_if,
3665                           "Bootcode not running! Found: 0x%08X, "
3666                           "Expected: 08%08X\n",
3667                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3668                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3669                 return ENODEV;
3670         }
3671
3672         /* Enable DMA */
3673         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3674             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3675                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3676                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3677                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3678         }
3679
3680         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3681         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3682
3683         /* Enable link state change interrupt generation. */
3684         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3685
3686         /* Enable the RXP. */
3687         bce_start_rxp_cpu(sc);
3688
3689         /* Disable management frames (NC-SI) from flowing to the MCP. */
3690         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3691                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3692                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3693                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3694         }
3695
3696         /* Enable all remaining blocks in the MAC. */
3697         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3698             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3699                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3700                     BCE_MISC_ENABLE_DEFAULT_XI);
3701         } else {
3702                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3703         }
3704         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3705         DELAY(20);
3706
3707         /* Save the current host coalescing block settings. */
3708         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3709
3710         return 0;
3711 }
3712
3713
3714 /****************************************************************************/
3715 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3716 /*                                                                          */
3717 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3718 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3719 /* necessary.                                                               */
3720 /*                                                                          */
3721 /* Returns:                                                                 */
3722 /*   0 for success, positive value for failure.                             */
3723 /****************************************************************************/
3724 static int
3725 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3726                uint32_t *prod_bseq, int init)
3727 {
3728         bus_dmamap_t map;
3729         bus_dma_segment_t seg;
3730         struct mbuf *m_new;
3731         int error, nseg;
3732 #ifdef BCE_DEBUG
3733         uint16_t debug_chain_prod = *chain_prod;
3734 #endif
3735
3736         /* Make sure the inputs are valid. */
3737         DBRUNIF((*chain_prod > MAX_RX_BD),
3738                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3739                           "RX producer out of range: 0x%04X > 0x%04X\n",
3740                           __FILE__, __LINE__,
3741                           *chain_prod, (uint16_t)MAX_RX_BD));
3742
3743         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3744                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3745
3746         DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3747                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3748                           "Simulating mbuf allocation failure.\n",
3749                           __FILE__, __LINE__);
3750                 sc->mbuf_alloc_failed++;
3751                 return ENOBUFS);
3752
3753         /* This is a new mbuf allocation. */
3754         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3755         if (m_new == NULL)
3756                 return ENOBUFS;
3757         DBRUNIF(1, sc->rx_mbuf_alloc++);
3758
3759         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3760
3761         /* Map the mbuf cluster into device memory. */
3762         error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3763                         sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3764                         BUS_DMA_NOWAIT);
3765         if (error) {
3766                 m_freem(m_new);
3767                 if (init) {
3768                         if_printf(&sc->arpcom.ac_if,
3769                                   "Error mapping mbuf into RX chain!\n");
3770                 }
3771                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3772                 return error;
3773         }
3774
3775         if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3776                 bus_dmamap_unload(sc->rx_mbuf_tag,
3777                                   sc->rx_mbuf_map[*chain_prod]);
3778         }
3779
3780         map = sc->rx_mbuf_map[*chain_prod];
3781         sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3782         sc->rx_mbuf_tmpmap = map;
3783
3784         /* Watch for overflow. */
3785         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3786                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3787                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3788                           __FILE__, __LINE__, sc->free_rx_bd,
3789                           (uint16_t)USABLE_RX_BD));
3790
3791         /* Update some debug statistic counters */
3792         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3793                 sc->rx_low_watermark = sc->free_rx_bd);
3794         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3795
3796         /* Save the mbuf and update our counter. */
3797         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3798         sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3799         sc->free_rx_bd--;
3800
3801         bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3802
3803         DBRUN(BCE_VERBOSE_RECV,
3804               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3805
3806         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3807                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3808
3809         return 0;
3810 }
3811
3812
3813 static void
3814 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3815 {
3816         struct rx_bd *rxbd;
3817         bus_addr_t paddr;
3818         int len;
3819
3820         paddr = sc->rx_mbuf_paddr[chain_prod];
3821         len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3822
3823         /* Setup the rx_bd for the first segment. */
3824         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3825
3826         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3827         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3828         rxbd->rx_bd_len = htole32(len);
3829         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3830         *prod_bseq += len;
3831
3832         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3833 }
3834
3835
3836 /****************************************************************************/
3837 /* Initialize the TX context memory.                                        */
3838 /*                                                                          */
3839 /* Returns:                                                                 */
3840 /*   Nothing                                                                */
3841 /****************************************************************************/
3842 static void
3843 bce_init_tx_context(struct bce_softc *sc)
3844 {
3845         uint32_t val;
3846
3847         /* Initialize the context ID for an L2 TX chain. */
3848         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3849             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3850                 /* Set the CID type to support an L2 connection. */
3851                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3852                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3853                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3854                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3855
3856                 /* Point the hardware to the first page in the chain. */
3857                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3858                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3859                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3860                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3861                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3862                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3863         } else {
3864                 /* Set the CID type to support an L2 connection. */
3865                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3866                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3867                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3868                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3869
3870                 /* Point the hardware to the first page in the chain. */
3871                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3872                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3873                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3874                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3875                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3876                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3877         }
3878 }
3879
3880
3881 /****************************************************************************/
3882 /* Allocate memory and initialize the TX data structures.                   */
3883 /*                                                                          */
3884 /* Returns:                                                                 */
3885 /*   0 for success, positive value for failure.                             */
3886 /****************************************************************************/
3887 static int
3888 bce_init_tx_chain(struct bce_softc *sc)
3889 {
3890         struct tx_bd *txbd;
3891         int i, rc = 0;
3892
3893         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3894
3895         /* Set the initial TX producer/consumer indices. */
3896         sc->tx_prod = 0;
3897         sc->tx_cons = 0;
3898         sc->tx_prod_bseq   = 0;
3899         sc->used_tx_bd = 0;
3900         sc->max_tx_bd = USABLE_TX_BD;
3901         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3902         DBRUNIF(1, sc->tx_full_count = 0);
3903
3904         /*
3905          * The NetXtreme II supports a linked-list structre called
3906          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3907          * consists of a series of 1 or more chain pages, each of which
3908          * consists of a fixed number of BD entries.
3909          * The last BD entry on each page is a pointer to the next page
3910          * in the chain, and the last pointer in the BD chain
3911          * points back to the beginning of the chain.
3912          */
3913
3914         /* Set the TX next pointer chain entries. */
3915         for (i = 0; i < TX_PAGES; i++) {
3916                 int j;
3917
3918                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3919
3920                 /* Check if we've reached the last page. */
3921                 if (i == (TX_PAGES - 1))
3922                         j = 0;
3923                 else
3924                         j = i + 1;
3925
3926                 txbd->tx_bd_haddr_hi =
3927                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3928                 txbd->tx_bd_haddr_lo =
3929                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3930         }
3931         bce_init_tx_context(sc);
3932
3933         return(rc);
3934 }
3935
3936
3937 /****************************************************************************/
3938 /* Free memory and clear the TX data structures.                            */
3939 /*                                                                          */
3940 /* Returns:                                                                 */
3941 /*   Nothing.                                                               */
3942 /****************************************************************************/
3943 static void
3944 bce_free_tx_chain(struct bce_softc *sc)
3945 {
3946         int i;
3947
3948         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3949
3950         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3951         for (i = 0; i < TOTAL_TX_BD; i++) {
3952                 if (sc->tx_mbuf_ptr[i] != NULL) {
3953                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3954                         m_freem(sc->tx_mbuf_ptr[i]);
3955                         sc->tx_mbuf_ptr[i] = NULL;
3956                         DBRUNIF(1, sc->tx_mbuf_alloc--);
3957                 }
3958         }
3959
3960         /* Clear each TX chain page. */
3961         for (i = 0; i < TX_PAGES; i++)
3962                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3963         sc->used_tx_bd = 0;
3964
3965         /* Check if we lost any mbufs in the process. */
3966         DBRUNIF((sc->tx_mbuf_alloc),
3967                 if_printf(&sc->arpcom.ac_if,
3968                           "%s(%d): Memory leak! "
3969                           "Lost %d mbufs from tx chain!\n",
3970                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
3971
3972         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3973 }
3974
3975
3976 /****************************************************************************/
3977 /* Initialize the RX context memory.                                        */
3978 /*                                                                          */
3979 /* Returns:                                                                 */
3980 /*   Nothing                                                                */
3981 /****************************************************************************/
3982 static void
3983 bce_init_rx_context(struct bce_softc *sc)
3984 {
3985         uint32_t val;
3986
3987         /* Initialize the context ID for an L2 RX chain. */
3988         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3989             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3990
3991         /*
3992          * Set the level for generating pause frames
3993          * when the number of available rx_bd's gets
3994          * too low (the low watermark) and the level
3995          * when pause frames can be stopped (the high
3996          * watermark).
3997          */
3998         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3999             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4000                 uint32_t lo_water, hi_water;
4001
4002                 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4003                 hi_water = USABLE_RX_BD / 4;
4004
4005                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4006                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4007
4008                 if (hi_water > 0xf)
4009                         hi_water = 0xf;
4010                 else if (hi_water == 0)
4011                         lo_water = 0;
4012                 val |= lo_water |
4013                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4014         }
4015
4016         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4017
4018         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4019         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4020             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4021                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4022                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4023         }
4024
4025         /* Point the hardware to the first page in the chain. */
4026         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4027         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4028         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4029         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4030 }
4031
4032
4033 /****************************************************************************/
4034 /* Allocate memory and initialize the RX data structures.                   */
4035 /*                                                                          */
4036 /* Returns:                                                                 */
4037 /*   0 for success, positive value for failure.                             */
4038 /****************************************************************************/
4039 static int
4040 bce_init_rx_chain(struct bce_softc *sc)
4041 {
4042         struct rx_bd *rxbd;
4043         int i, rc = 0;
4044         uint16_t prod, chain_prod;
4045         uint32_t prod_bseq;
4046
4047         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4048
4049         /* Initialize the RX producer and consumer indices. */
4050         sc->rx_prod = 0;
4051         sc->rx_cons = 0;
4052         sc->rx_prod_bseq = 0;
4053         sc->free_rx_bd = USABLE_RX_BD;
4054         sc->max_rx_bd = USABLE_RX_BD;
4055         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
4056         DBRUNIF(1, sc->rx_empty_count = 0);
4057
4058         /* Initialize the RX next pointer chain entries. */
4059         for (i = 0; i < RX_PAGES; i++) {
4060                 int j;
4061
4062                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4063
4064                 /* Check if we've reached the last page. */
4065                 if (i == (RX_PAGES - 1))
4066                         j = 0;
4067                 else
4068                         j = i + 1;
4069
4070                 /* Setup the chain page pointers. */
4071                 rxbd->rx_bd_haddr_hi =
4072                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4073                 rxbd->rx_bd_haddr_lo =
4074                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4075         }
4076
4077         /* Allocate mbuf clusters for the rx_bd chain. */
4078         prod = prod_bseq = 0;
4079         while (prod < TOTAL_RX_BD) {
4080                 chain_prod = RX_CHAIN_IDX(prod);
4081                 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4082                         if_printf(&sc->arpcom.ac_if,
4083                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
4084                                   chain_prod);
4085                         rc = ENOBUFS;
4086                         break;
4087                 }
4088                 prod = NEXT_RX_BD(prod);
4089         }
4090
4091         /* Save the RX chain producer index. */
4092         sc->rx_prod = prod;
4093         sc->rx_prod_bseq = prod_bseq;
4094
4095         /* Tell the chip about the waiting rx_bd's. */
4096         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4097             sc->rx_prod);
4098         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4099             sc->rx_prod_bseq);
4100
4101         bce_init_rx_context(sc);
4102
4103         return(rc);
4104 }
4105
4106
4107 /****************************************************************************/
4108 /* Free memory and clear the RX data structures.                            */
4109 /*                                                                          */
4110 /* Returns:                                                                 */
4111 /*   Nothing.                                                               */
4112 /****************************************************************************/
4113 static void
4114 bce_free_rx_chain(struct bce_softc *sc)
4115 {
4116         int i;
4117
4118         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4119
4120         /* Free any mbufs still in the RX mbuf chain. */
4121         for (i = 0; i < TOTAL_RX_BD; i++) {
4122                 if (sc->rx_mbuf_ptr[i] != NULL) {
4123                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4124                         m_freem(sc->rx_mbuf_ptr[i]);
4125                         sc->rx_mbuf_ptr[i] = NULL;
4126                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4127                 }
4128         }
4129
4130         /* Clear each RX chain page. */
4131         for (i = 0; i < RX_PAGES; i++)
4132                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4133
4134         /* Check if we lost any mbufs in the process. */
4135         DBRUNIF((sc->rx_mbuf_alloc),
4136                 if_printf(&sc->arpcom.ac_if,
4137                           "%s(%d): Memory leak! "
4138                           "Lost %d mbufs from rx chain!\n",
4139                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
4140
4141         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4142 }
4143
4144
4145 /****************************************************************************/
4146 /* Set media options.                                                       */
4147 /*                                                                          */
4148 /* Returns:                                                                 */
4149 /*   0 for success, positive value for failure.                             */
4150 /****************************************************************************/
4151 static int
4152 bce_ifmedia_upd(struct ifnet *ifp)
4153 {
4154         struct bce_softc *sc = ifp->if_softc;
4155         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4156         int error = 0;
4157
4158         /*
4159          * 'mii' will be NULL, when this function is called on following
4160          * code path: bce_attach() -> bce_mgmt_init()
4161          */
4162         if (mii != NULL) {
4163                 /* Make sure the MII bus has been enumerated. */
4164                 sc->bce_link = 0;
4165                 if (mii->mii_instance) {
4166                         struct mii_softc *miisc;
4167
4168                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4169                                 mii_phy_reset(miisc);
4170                 }
4171                 error = mii_mediachg(mii);
4172         }
4173         return error;
4174 }
4175
4176
4177 /****************************************************************************/
4178 /* Reports current media status.                                            */
4179 /*                                                                          */
4180 /* Returns:                                                                 */
4181 /*   Nothing.                                                               */
4182 /****************************************************************************/
4183 static void
4184 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4185 {
4186         struct bce_softc *sc = ifp->if_softc;
4187         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4188
4189         mii_pollstat(mii);
4190         ifmr->ifm_active = mii->mii_media_active;
4191         ifmr->ifm_status = mii->mii_media_status;
4192 }
4193
4194
4195 /****************************************************************************/
4196 /* Handles PHY generated interrupt events.                                  */
4197 /*                                                                          */
4198 /* Returns:                                                                 */
4199 /*   Nothing.                                                               */
4200 /****************************************************************************/
4201 static void
4202 bce_phy_intr(struct bce_softc *sc)
4203 {
4204         uint32_t new_link_state, old_link_state;
4205         struct ifnet *ifp = &sc->arpcom.ac_if;
4206
4207         ASSERT_SERIALIZED(ifp->if_serializer);
4208
4209         new_link_state = sc->status_block->status_attn_bits &
4210                          STATUS_ATTN_BITS_LINK_STATE;
4211         old_link_state = sc->status_block->status_attn_bits_ack &
4212                          STATUS_ATTN_BITS_LINK_STATE;
4213
4214         /* Handle any changes if the link state has changed. */
4215         if (new_link_state != old_link_state) { /* XXX redundant? */
4216                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4217
4218                 /* Update the status_attn_bits_ack field in the status block. */
4219                 if (new_link_state) {
4220                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4221                                STATUS_ATTN_BITS_LINK_STATE);
4222                         if (bootverbose)
4223                                 if_printf(ifp, "Link is now UP.\n");
4224                 } else {
4225                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4226                                STATUS_ATTN_BITS_LINK_STATE);
4227                         if (bootverbose)
4228                                 if_printf(ifp, "Link is now DOWN.\n");
4229                 }
4230
4231                 /*
4232                  * Assume link is down and allow tick routine to
4233                  * update the state based on the actual media state.
4234                  */
4235                 sc->bce_link = 0;
4236                 callout_stop(&sc->bce_tick_callout);
4237                 bce_tick_serialized(sc);
4238         }
4239
4240         /* Acknowledge the link change interrupt. */
4241         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4242 }
4243
4244
4245 /****************************************************************************/
4246 /* Reads the receive consumer value from the status block (skipping over    */
4247 /* chain page pointer if necessary).                                        */
4248 /*                                                                          */
4249 /* Returns:                                                                 */
4250 /*   hw_cons                                                                */
4251 /****************************************************************************/
4252 static __inline uint16_t
4253 bce_get_hw_rx_cons(struct bce_softc *sc)
4254 {
4255         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4256
4257         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4258                 hw_cons++;
4259         return hw_cons;
4260 }
4261
4262
4263 /****************************************************************************/
4264 /* Handles received frame interrupt events.                                 */
4265 /*                                                                          */
4266 /* Returns:                                                                 */
4267 /*   Nothing.                                                               */
4268 /****************************************************************************/
4269 static void
4270 bce_rx_intr(struct bce_softc *sc, int count)
4271 {
4272         struct ifnet *ifp = &sc->arpcom.ac_if;
4273         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4274         uint32_t sw_prod_bseq;
4275         struct mbuf_chain chain[MAXCPU];
4276
4277         ASSERT_SERIALIZED(ifp->if_serializer);
4278
4279         ether_input_chain_init(chain);
4280
4281         DBRUNIF(1, sc->rx_interrupts++);
4282
4283         /* Get the hardware's view of the RX consumer index. */
4284         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4285
4286         /* Get working copies of the driver's view of the RX indices. */
4287         sw_cons = sc->rx_cons;
4288         sw_prod = sc->rx_prod;
4289         sw_prod_bseq = sc->rx_prod_bseq;
4290
4291         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4292                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4293                 __func__, sw_prod, sw_cons, sw_prod_bseq);
4294
4295         /* Prevent speculative reads from getting ahead of the status block. */
4296         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4297                           BUS_SPACE_BARRIER_READ);
4298
4299         /* Update some debug statistics counters */
4300         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4301                 sc->rx_low_watermark = sc->free_rx_bd);
4302         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4303
4304         /* Scan through the receive chain as long as there is work to do. */
4305         while (sw_cons != hw_cons) {
4306                 struct mbuf *m = NULL;
4307                 struct l2_fhdr *l2fhdr = NULL;
4308                 struct rx_bd *rxbd;
4309                 unsigned int len;
4310                 uint32_t status = 0;
4311
4312 #ifdef DEVICE_POLLING
4313                 if (count >= 0 && count-- == 0) {
4314                         sc->hw_rx_cons = sw_cons;
4315                         break;
4316                 }
4317 #endif
4318
4319                 /*
4320                  * Convert the producer/consumer indices
4321                  * to an actual rx_bd index.
4322                  */
4323                 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
4324                 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
4325
4326                 /* Get the used rx_bd. */
4327                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4328                                        [RX_IDX(sw_chain_cons)];
4329                 sc->free_rx_bd++;
4330
4331                 DBRUN(BCE_VERBOSE_RECV,
4332                       if_printf(ifp, "%s(): ", __func__);
4333                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4334
4335                 /* The mbuf is stored with the last rx_bd entry of a packet. */
4336                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4337                         /* Validate that this is the last rx_bd. */
4338                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4339                                 if_printf(ifp, "%s(%d): "
4340                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4341                                 __FILE__, __LINE__, sw_chain_cons);
4342                                 bce_breakpoint(sc));
4343
4344                         if (sw_chain_cons != sw_chain_prod) {
4345                                 if_printf(ifp, "RX cons(%d) != prod(%d), "
4346                                           "drop!\n", sw_chain_cons,
4347                                           sw_chain_prod);
4348                                 ifp->if_ierrors++;
4349
4350                                 bce_setup_rxdesc_std(sc, sw_chain_cons,
4351                                                      &sw_prod_bseq);
4352                                 m = NULL;
4353                                 goto bce_rx_int_next_rx;
4354                         }
4355
4356                         /* Unmap the mbuf from DMA space. */
4357                         bus_dmamap_sync(sc->rx_mbuf_tag,
4358                                         sc->rx_mbuf_map[sw_chain_cons],
4359                                         BUS_DMASYNC_POSTREAD);
4360
4361                         /* Save the mbuf from the driver's chain. */
4362                         m = sc->rx_mbuf_ptr[sw_chain_cons];
4363
4364                         /*
4365                          * Frames received on the NetXteme II are prepended
4366                          * with an l2_fhdr structure which provides status
4367                          * information about the received frame (including
4368                          * VLAN tags and checksum info).  The frames are also
4369                          * automatically adjusted to align the IP header
4370                          * (i.e. two null bytes are inserted before the
4371                          * Ethernet header).  As a result the data DMA'd by
4372                          * the controller into the mbuf is as follows:
4373                          *
4374                          * +---------+-----+---------------------+-----+
4375                          * | l2_fhdr | pad | packet data         | FCS |
4376                          * +---------+-----+---------------------+-----+
4377                          *
4378                          * The l2_fhdr needs to be checked and skipped and the
4379                          * FCS needs to be stripped before sending the packet
4380                          * up the stack.
4381                          */
4382                         l2fhdr = mtod(m, struct l2_fhdr *);
4383
4384                         len = l2fhdr->l2_fhdr_pkt_len;
4385                         status = l2fhdr->l2_fhdr_status;
4386
4387                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4388                                 if_printf(ifp,
4389                                 "Simulating l2_fhdr status error.\n");
4390                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4391
4392                         /* Watch for unusual sized frames. */
4393                         DBRUNIF((len < BCE_MIN_MTU ||
4394                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4395                                 if_printf(ifp,
4396                                 "%s(%d): Unusual frame size found. "
4397                                 "Min(%d), Actual(%d), Max(%d)\n",
4398                                 __FILE__, __LINE__,
4399                                 (int)BCE_MIN_MTU, len,
4400                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4401                                 bce_dump_mbuf(sc, m);
4402                                 bce_breakpoint(sc));
4403
4404                         len -= ETHER_CRC_LEN;
4405
4406                         /* Check the received frame for errors. */
4407                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
4408                                       L2_FHDR_ERRORS_PHY_DECODE |
4409                                       L2_FHDR_ERRORS_ALIGNMENT |
4410                                       L2_FHDR_ERRORS_TOO_SHORT |
4411                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
4412                                 ifp->if_ierrors++;
4413                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
4414
4415                                 /* Reuse the mbuf for a new frame. */
4416                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4417                                                      &sw_prod_bseq);
4418                                 m = NULL;
4419                                 goto bce_rx_int_next_rx;
4420                         }
4421
4422                         /*
4423                          * Get a new mbuf for the rx_bd.   If no new
4424                          * mbufs are available then reuse the current mbuf,
4425                          * log an ierror on the interface, and generate
4426                          * an error in the system log.
4427                          */
4428                         if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4429                                            &sw_prod_bseq, 0)) {
4430                                 DBRUN(BCE_WARN,
4431                                       if_printf(ifp,
4432                                       "%s(%d): Failed to allocate new mbuf, "
4433                                       "incoming frame dropped!\n",
4434                                       __FILE__, __LINE__));
4435
4436                                 ifp->if_ierrors++;
4437
4438                                 /* Try and reuse the exisitng mbuf. */
4439                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4440                                                      &sw_prod_bseq);
4441                                 m = NULL;
4442                                 goto bce_rx_int_next_rx;
4443                         }
4444
4445                         /*
4446                          * Skip over the l2_fhdr when passing
4447                          * the data up the stack.
4448                          */
4449                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4450
4451                         m->m_pkthdr.len = m->m_len = len;
4452                         m->m_pkthdr.rcvif = ifp;
4453
4454                         DBRUN(BCE_VERBOSE_RECV,
4455                               struct ether_header *eh;
4456                               eh = mtod(m, struct ether_header *);
4457                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
4458                                         "type: 0x%04X\n", __func__,
4459                                         eh->ether_dhost, ":",
4460                                         eh->ether_shost, ":",
4461                                         htons(eh->ether_type)));
4462
4463                         /* Validate the checksum if offload enabled. */
4464                         if (ifp->if_capenable & IFCAP_RXCSUM) {
4465                                 /* Check for an IP datagram. */
4466                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4467                                         m->m_pkthdr.csum_flags |=
4468                                                 CSUM_IP_CHECKED;
4469
4470                                         /* Check if the IP checksum is valid. */
4471                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
4472                                              0xffff) == 0) {
4473                                                 m->m_pkthdr.csum_flags |=
4474                                                         CSUM_IP_VALID;
4475                                         } else {
4476                                                 DBPRINT(sc, BCE_WARN_RECV,
4477                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
4478                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
4479                                         }
4480                                 }
4481
4482                                 /* Check for a valid TCP/UDP frame. */
4483                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4484                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
4485
4486                                         /* Check for a good TCP/UDP checksum. */
4487                                         if ((status &
4488                                              (L2_FHDR_ERRORS_TCP_XSUM |
4489                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4490                                                 m->m_pkthdr.csum_data =
4491                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
4492                                                 m->m_pkthdr.csum_flags |=
4493                                                         CSUM_DATA_VALID |
4494                                                         CSUM_PSEUDO_HDR;
4495                                         } else {
4496                                                 DBPRINT(sc, BCE_WARN_RECV,
4497                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4498                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4499                                         }
4500                                 }
4501                         }
4502
4503                         ifp->if_ipackets++;
4504 bce_rx_int_next_rx:
4505                         sw_prod = NEXT_RX_BD(sw_prod);
4506                 }
4507
4508                 sw_cons = NEXT_RX_BD(sw_cons);
4509
4510                 /* If we have a packet, pass it up the stack */
4511                 if (m) {
4512                         DBPRINT(sc, BCE_VERBOSE_RECV,
4513                                 "%s(): Passing received frame up.\n", __func__);
4514
4515                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4516                                 m->m_flags |= M_VLANTAG;
4517                                 m->m_pkthdr.ether_vlantag =
4518                                         l2fhdr->l2_fhdr_vlan_tag;
4519                         }
4520                         ether_input_chain(ifp, m, NULL, chain);
4521
4522                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4523                 }
4524
4525                 /*
4526                  * If polling(4) is not enabled, refresh hw_cons to see
4527                  * whether there's new work.
4528                  *
4529                  * If polling(4) is enabled, i.e count >= 0, refreshing
4530                  * should not be performed, so that we would not spend
4531                  * too much time in RX processing.
4532                  */
4533                 if (count < 0 && sw_cons == hw_cons)
4534                         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4535
4536                 /*
4537                  * Prevent speculative reads from getting ahead
4538                  * of the status block.
4539                  */
4540                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4541                                   BUS_SPACE_BARRIER_READ);
4542         }
4543
4544         ether_input_dispatch(chain);
4545
4546         sc->rx_cons = sw_cons;
4547         sc->rx_prod = sw_prod;
4548         sc->rx_prod_bseq = sw_prod_bseq;
4549
4550         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4551             sc->rx_prod);
4552         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4553             sc->rx_prod_bseq);
4554
4555         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4556                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4557                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4558 }
4559
4560
4561 /****************************************************************************/
4562 /* Reads the transmit consumer value from the status block (skipping over   */
4563 /* chain page pointer if necessary).                                        */
4564 /*                                                                          */
4565 /* Returns:                                                                 */
4566 /*   hw_cons                                                                */
4567 /****************************************************************************/
4568 static __inline uint16_t
4569 bce_get_hw_tx_cons(struct bce_softc *sc)
4570 {
4571         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4572
4573         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4574                 hw_cons++;
4575         return hw_cons;
4576 }
4577
4578
4579 /****************************************************************************/
4580 /* Handles transmit completion interrupt events.                            */
4581 /*                                                                          */
4582 /* Returns:                                                                 */
4583 /*   Nothing.                                                               */
4584 /****************************************************************************/
4585 static void
4586 bce_tx_intr(struct bce_softc *sc)
4587 {
4588         struct ifnet *ifp = &sc->arpcom.ac_if;
4589         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4590
4591         ASSERT_SERIALIZED(ifp->if_serializer);
4592
4593         DBRUNIF(1, sc->tx_interrupts++);
4594
4595         /* Get the hardware's view of the TX consumer index. */
4596         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4597         sw_tx_cons = sc->tx_cons;
4598
4599         /* Prevent speculative reads from getting ahead of the status block. */
4600         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4601                           BUS_SPACE_BARRIER_READ);
4602
4603         /* Cycle through any completed TX chain page entries. */
4604         while (sw_tx_cons != hw_tx_cons) {
4605 #ifdef BCE_DEBUG
4606                 struct tx_bd *txbd = NULL;
4607 #endif
4608                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4609
4610                 DBPRINT(sc, BCE_INFO_SEND,
4611                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4612                         "sw_tx_chain_cons = 0x%04X\n",
4613                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4614
4615                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4616                         if_printf(ifp, "%s(%d): "
4617                                   "TX chain consumer out of range! "
4618                                   " 0x%04X > 0x%04X\n",
4619                                   __FILE__, __LINE__, sw_tx_chain_cons,
4620                                   (int)MAX_TX_BD);
4621                         bce_breakpoint(sc));
4622
4623                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4624                                 [TX_IDX(sw_tx_chain_cons)]);
4625
4626                 DBRUNIF((txbd == NULL),
4627                         if_printf(ifp, "%s(%d): "
4628                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4629                                   __FILE__, __LINE__, sw_tx_chain_cons);
4630                         bce_breakpoint(sc));
4631
4632                 DBRUN(BCE_INFO_SEND,
4633                       if_printf(ifp, "%s(): ", __func__);
4634                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4635
4636                 /*
4637                  * Free the associated mbuf. Remember
4638                  * that only the last tx_bd of a packet
4639                  * has an mbuf pointer and DMA map.
4640                  */
4641                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4642                         /* Validate that this is the last tx_bd. */
4643                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4644                                 if_printf(ifp, "%s(%d): "
4645                                 "tx_bd END flag not set but "
4646                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4647                                 bce_breakpoint(sc));
4648
4649                         DBRUN(BCE_INFO_SEND,
4650                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4651                                         "from tx_bd[0x%04X]\n", __func__,
4652                                         sw_tx_chain_cons));
4653
4654                         /* Unmap the mbuf. */
4655                         bus_dmamap_unload(sc->tx_mbuf_tag,
4656                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4657
4658                         /* Free the mbuf. */
4659                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4660                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4661                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4662
4663                         ifp->if_opackets++;
4664                 }
4665
4666                 sc->used_tx_bd--;
4667                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4668
4669                 if (sw_tx_cons == hw_tx_cons) {
4670                         /* Refresh hw_cons to see if there's new work. */
4671                         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4672                 }
4673
4674                 /*
4675                  * Prevent speculative reads from getting
4676                  * ahead of the status block.
4677                  */
4678                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4679                                   BUS_SPACE_BARRIER_READ);
4680         }
4681
4682         if (sc->used_tx_bd == 0) {
4683                 /* Clear the TX timeout timer. */
4684                 ifp->if_timer = 0;
4685         }
4686
4687         /* Clear the tx hardware queue full flag. */
4688         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4689                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4690                         DBPRINT(sc, BCE_WARN_SEND,
4691                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4692                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4693                 ifp->if_flags &= ~IFF_OACTIVE;
4694         }
4695         sc->tx_cons = sw_tx_cons;
4696 }
4697
4698
4699 /****************************************************************************/
4700 /* Disables interrupt generation.                                           */
4701 /*                                                                          */
4702 /* Returns:                                                                 */
4703 /*   Nothing.                                                               */
4704 /****************************************************************************/
4705 static void
4706 bce_disable_intr(struct bce_softc *sc)
4707 {
4708         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4709         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4710         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4711 }
4712
4713
4714 /****************************************************************************/
4715 /* Enables interrupt generation.                                            */
4716 /*                                                                          */
4717 /* Returns:                                                                 */
4718 /*   Nothing.                                                               */
4719 /****************************************************************************/
4720 static void
4721 bce_enable_intr(struct bce_softc *sc, int coal_now)
4722 {
4723         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4724
4725         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4726                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4727                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4728
4729         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4730                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4731
4732         if (coal_now) {
4733                 REG_WR(sc, BCE_HC_COMMAND,
4734                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4735         }
4736 }
4737
4738
4739 /****************************************************************************/
4740 /* Handles controller initialization.                                       */
4741 /*                                                                          */
4742 /* Returns:                                                                 */
4743 /*   Nothing.                                                               */
4744 /****************************************************************************/
4745 static void
4746 bce_init(void *xsc)
4747 {
4748         struct bce_softc *sc = xsc;
4749         struct ifnet *ifp = &sc->arpcom.ac_if;
4750         uint32_t ether_mtu;
4751         int error;
4752
4753         ASSERT_SERIALIZED(ifp->if_serializer);
4754
4755         /* Check if the driver is still running and bail out if it is. */
4756         if (ifp->if_flags & IFF_RUNNING)
4757                 return;
4758
4759         bce_stop(sc);
4760
4761         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4762         if (error) {
4763                 if_printf(ifp, "Controller reset failed!\n");
4764                 goto back;
4765         }
4766
4767         error = bce_chipinit(sc);
4768         if (error) {
4769                 if_printf(ifp, "Controller initialization failed!\n");
4770                 goto back;
4771         }
4772
4773         error = bce_blockinit(sc);
4774         if (error) {
4775                 if_printf(ifp, "Block initialization failed!\n");
4776                 goto back;
4777         }
4778
4779         /* Load our MAC address. */
4780         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4781         bce_set_mac_addr(sc);
4782
4783         /* Calculate and program the Ethernet MTU size. */
4784         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4785
4786         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4787
4788         /*
4789          * Program the mtu, enabling jumbo frame
4790          * support if necessary.  Also set the mbuf
4791          * allocation count for RX frames.
4792          */
4793         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4794 #ifdef notyet
4795                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4796                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4797                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4798                 sc->mbuf_alloc_size = MJUM9BYTES;
4799 #else
4800                 panic("jumbo buffer is not supported yet\n");
4801 #endif
4802         } else {
4803                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4804                 sc->mbuf_alloc_size = MCLBYTES;
4805         }
4806
4807         /* Calculate the RX Ethernet frame size for rx_bd's. */
4808         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4809
4810         DBPRINT(sc, BCE_INFO,
4811                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4812                 "max_frame_size = %d\n",
4813                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4814                 sc->max_frame_size);
4815
4816         /* Program appropriate promiscuous/multicast filtering. */
4817         bce_set_rx_mode(sc);
4818
4819         /* Init RX buffer descriptor chain. */
4820         bce_init_rx_chain(sc);  /* XXX return value */
4821
4822         /* Init TX buffer descriptor chain. */
4823         bce_init_tx_chain(sc);  /* XXX return value */
4824
4825 #ifdef DEVICE_POLLING
4826         /* Disable interrupts if we are polling. */
4827         if (ifp->if_flags & IFF_POLLING) {
4828                 bce_disable_intr(sc);
4829
4830                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4831                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4832                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4833                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4834         } else
4835 #endif
4836         /* Enable host interrupts. */
4837         bce_enable_intr(sc, 1);
4838
4839         bce_ifmedia_upd(ifp);
4840
4841         ifp->if_flags |= IFF_RUNNING;
4842         ifp->if_flags &= ~IFF_OACTIVE;
4843
4844         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4845 back:
4846         if (error)
4847                 bce_stop(sc);
4848 }
4849
4850
4851 /****************************************************************************/
4852 /* Initialize the controller just enough so that any management firmware    */
4853 /* running on the device will continue to operate corectly.                 */
4854 /*                                                                          */
4855 /* Returns:                                                                 */
4856 /*   Nothing.                                                               */
4857 /****************************************************************************/
4858 static void
4859 bce_mgmt_init(struct bce_softc *sc)
4860 {
4861         struct ifnet *ifp = &sc->arpcom.ac_if;
4862
4863         /* Bail out if management firmware is not running. */
4864         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4865                 return;
4866
4867         /* Enable all critical blocks in the MAC. */
4868         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4869             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4870                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4871                     BCE_MISC_ENABLE_DEFAULT_XI);
4872         } else {
4873                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4874         }
4875         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4876         DELAY(20);
4877
4878         bce_ifmedia_upd(ifp);
4879 }
4880
4881
4882 /****************************************************************************/
4883 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4884 /* memory visible to the controller.                                        */
4885 /*                                                                          */
4886 /* Returns:                                                                 */
4887 /*   0 for success, positive value for failure.                             */
4888 /****************************************************************************/
4889 static int
4890 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4891 {
4892         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4893         bus_dmamap_t map, tmp_map;
4894         struct mbuf *m0 = *m_head;
4895         struct tx_bd *txbd = NULL;
4896         uint16_t vlan_tag = 0, flags = 0;
4897         uint16_t chain_prod, chain_prod_start, prod;
4898         uint32_t prod_bseq;
4899         int i, error, maxsegs, nsegs;
4900 #ifdef BCE_DEBUG
4901         uint16_t debug_prod;
4902 #endif
4903
4904         /* Transfer any checksum offload flags to the bd. */
4905         if (m0->m_pkthdr.csum_flags) {
4906                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4907                         flags |= TX_BD_FLAGS_IP_CKSUM;
4908                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4909                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4910         }
4911
4912         /* Transfer any VLAN tags to the bd. */
4913         if (m0->m_flags & M_VLANTAG) {
4914                 flags |= TX_BD_FLAGS_VLAN_TAG;
4915                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4916         }
4917
4918         prod = sc->tx_prod;
4919         chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4920
4921         /* Map the mbuf into DMAable memory. */
4922         map = sc->tx_mbuf_map[chain_prod_start];
4923
4924         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4925         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4926                 ("not enough segements %d\n", maxsegs));
4927         if (maxsegs > BCE_MAX_SEGMENTS)
4928                 maxsegs = BCE_MAX_SEGMENTS;
4929
4930         /* Map the mbuf into our DMA address space. */
4931         error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4932                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4933         if (error)
4934                 goto back;
4935         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4936
4937         /* Reset m0 */
4938         m0 = *m_head;
4939
4940         /* prod points to an empty tx_bd at this point. */
4941         prod_bseq  = sc->tx_prod_bseq;
4942
4943 #ifdef BCE_DEBUG
4944         debug_prod = chain_prod;
4945 #endif
4946
4947         DBPRINT(sc, BCE_INFO_SEND,
4948                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4949                 "prod_bseq = 0x%08X\n",
4950                 __func__, prod, chain_prod, prod_bseq);
4951
4952         /*
4953          * Cycle through each mbuf segment that makes up
4954          * the outgoing frame, gathering the mapping info
4955          * for that segment and creating a tx_bd to for
4956          * the mbuf.
4957          */
4958         for (i = 0; i < nsegs; i++) {
4959                 chain_prod = TX_CHAIN_IDX(prod);
4960                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4961
4962                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4963                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4964                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4965                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4966                 txbd->tx_bd_flags = htole16(flags);
4967                 prod_bseq += segs[i].ds_len;
4968                 if (i == 0)
4969                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4970                 prod = NEXT_TX_BD(prod);
4971         }
4972
4973         /* Set the END flag on the last TX buffer descriptor. */
4974         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4975
4976         DBRUN(BCE_EXCESSIVE_SEND,
4977               bce_dump_tx_chain(sc, debug_prod, nsegs));
4978
4979         DBPRINT(sc, BCE_INFO_SEND,
4980                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4981                 "prod_bseq = 0x%08X\n",
4982                 __func__, prod, chain_prod, prod_bseq);
4983
4984         /*
4985          * Ensure that the mbuf pointer for this transmission
4986          * is placed at the array index of the last
4987          * descriptor in this chain.  This is done
4988          * because a single map is used for all
4989          * segments of the mbuf and we don't want to
4990          * unload the map before all of the segments
4991          * have been freed.
4992          */
4993         sc->tx_mbuf_ptr[chain_prod] = m0;
4994
4995         tmp_map = sc->tx_mbuf_map[chain_prod];
4996         sc->tx_mbuf_map[chain_prod] = map;
4997         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4998
4999         sc->used_tx_bd += nsegs;
5000
5001         /* Update some debug statistic counters */
5002         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
5003                 sc->tx_hi_watermark = sc->used_tx_bd);
5004         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
5005         DBRUNIF(1, sc->tx_mbuf_alloc++);
5006
5007         DBRUN(BCE_VERBOSE_SEND,
5008               bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
5009
5010         /* prod points to the next free tx_bd at this point. */
5011         sc->tx_prod = prod;
5012         sc->tx_prod_bseq = prod_bseq;
5013 back:
5014         if (error) {
5015                 m_freem(*m_head);
5016                 *m_head = NULL;
5017         }
5018         return error;
5019 }
5020
5021
5022 /****************************************************************************/
5023 /* Main transmit routine when called from another routine with a lock.      */
5024 /*                                                                          */
5025 /* Returns:                                                                 */
5026 /*   Nothing.                                                               */
5027 /****************************************************************************/
5028 static void
5029 bce_start(struct ifnet *ifp)
5030 {
5031         struct bce_softc *sc = ifp->if_softc;
5032         int count = 0;
5033
5034         ASSERT_SERIALIZED(ifp->if_serializer);
5035
5036         /* If there's no link or the transmit queue is empty then just exit. */
5037         if (!sc->bce_link) {
5038                 ifq_purge(&ifp->if_snd);
5039                 return;
5040         }
5041
5042         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
5043                 return;
5044
5045         DBPRINT(sc, BCE_INFO_SEND,
5046                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
5047                 "tx_prod_bseq = 0x%08X\n",
5048                 __func__,
5049                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5050
5051         for (;;) {
5052                 struct mbuf *m_head;
5053
5054                 /*
5055                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
5056                  * unlikely to fail.
5057                  */
5058                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
5059                         ifp->if_flags |= IFF_OACTIVE;
5060                         break;
5061                 }
5062
5063                 /* Check for any frames to send. */
5064                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
5065                 if (m_head == NULL)
5066                         break;
5067
5068                 /*
5069                  * Pack the data into the transmit ring. If we
5070                  * don't have room, place the mbuf back at the
5071                  * head of the queue and set the OACTIVE flag
5072                  * to wait for the NIC to drain the chain.
5073                  */
5074                 if (bce_encap(sc, &m_head)) {
5075                         ifp->if_oerrors++;
5076                         if (sc->used_tx_bd == 0) {
5077                                 continue;
5078                         } else {
5079                                 ifp->if_flags |= IFF_OACTIVE;
5080                                 break;
5081                         }
5082                 }
5083
5084                 count++;
5085
5086                 /* Send a copy of the frame to any BPF listeners. */
5087                 ETHER_BPF_MTAP(ifp, m_head);
5088         }
5089
5090         if (count == 0) {
5091                 /* no packets were dequeued */
5092                 DBPRINT(sc, BCE_VERBOSE_SEND,
5093                         "%s(): No packets were dequeued\n", __func__);
5094                 return;
5095         }
5096
5097         DBPRINT(sc, BCE_INFO_SEND,
5098                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
5099                 "tx_prod_bseq = 0x%08X\n",
5100                 __func__,
5101                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5102
5103         REG_WR(sc, BCE_MQ_COMMAND,
5104             REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5105
5106         /* Start the transmit. */
5107         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5108         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5109
5110         /* Set the tx timeout. */
5111         ifp->if_timer = BCE_TX_TIMEOUT;
5112 }
5113
5114
5115 /****************************************************************************/
5116 /* Handles any IOCTL calls from the operating system.                       */
5117 /*                                                                          */
5118 /* Returns:                                                                 */
5119 /*   0 for success, positive value for failure.                             */
5120 /****************************************************************************/
5121 static int
5122 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5123 {
5124         struct bce_softc *sc = ifp->if_softc;
5125         struct ifreq *ifr = (struct ifreq *)data;
5126         struct mii_data *mii;
5127         int mask, error = 0;
5128
5129         ASSERT_SERIALIZED(ifp->if_serializer);
5130
5131         switch(command) {
5132         case SIOCSIFMTU:
5133                 /* Check that the MTU setting is supported. */
5134                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5135 #ifdef notyet
5136                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5137 #else
5138                     ifr->ifr_mtu > ETHERMTU
5139 #endif
5140                    ) {
5141                         error = EINVAL;
5142                         break;
5143                 }
5144
5145                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5146
5147                 ifp->if_mtu = ifr->ifr_mtu;
5148                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5149                 bce_init(sc);
5150                 break;
5151
5152         case SIOCSIFFLAGS:
5153                 if (ifp->if_flags & IFF_UP) {
5154                         if (ifp->if_flags & IFF_RUNNING) {
5155                                 mask = ifp->if_flags ^ sc->bce_if_flags;
5156
5157                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5158                                         bce_set_rx_mode(sc);
5159                         } else {
5160                                 bce_init(sc);
5161                         }
5162                 } else if (ifp->if_flags & IFF_RUNNING) {
5163                         bce_stop(sc);
5164
5165                         /* If MFW is running, restart the controller a bit. */
5166                         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5167                                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5168                                 bce_chipinit(sc);
5169                                 bce_mgmt_init(sc);
5170                         }
5171                 }
5172                 sc->bce_if_flags = ifp->if_flags;
5173                 break;
5174
5175         case SIOCADDMULTI:
5176         case SIOCDELMULTI:
5177                 if (ifp->if_flags & IFF_RUNNING)
5178                         bce_set_rx_mode(sc);
5179                 break;
5180
5181         case SIOCSIFMEDIA:
5182         case SIOCGIFMEDIA:
5183                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5184                         sc->bce_phy_flags);
5185                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5186
5187                 mii = device_get_softc(sc->bce_miibus);
5188                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5189                 break;
5190
5191         case SIOCSIFCAP:
5192                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5193                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5194                         (uint32_t) mask);
5195
5196                 if (mask & IFCAP_HWCSUM) {
5197                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5198                         if (IFCAP_HWCSUM & ifp->if_capenable)
5199                                 ifp->if_hwassist = BCE_IF_HWASSIST;
5200                         else
5201                                 ifp->if_hwassist = 0;
5202                 }
5203                 break;
5204
5205         default:
5206                 error = ether_ioctl(ifp, command, data);
5207                 break;
5208         }
5209         return error;
5210 }
5211
5212
5213 /****************************************************************************/
5214 /* Transmit timeout handler.                                                */
5215 /*                                                                          */
5216 /* Returns:                                                                 */
5217 /*   Nothing.                                                               */
5218 /****************************************************************************/
5219 static void
5220 bce_watchdog(struct ifnet *ifp)
5221 {
5222         struct bce_softc *sc = ifp->if_softc;
5223
5224         ASSERT_SERIALIZED(ifp->if_serializer);
5225
5226         DBRUN(BCE_VERBOSE_SEND,
5227               bce_dump_driver_state(sc);
5228               bce_dump_status_block(sc));
5229
5230         /*
5231          * If we are in this routine because of pause frames, then
5232          * don't reset the hardware.
5233          */
5234         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5235                 return;
5236
5237         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5238
5239         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5240
5241         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5242         bce_init(sc);
5243
5244         ifp->if_oerrors++;
5245
5246         if (!ifq_is_empty(&ifp->if_snd))
5247                 if_devstart(ifp);
5248 }
5249
5250
5251 #ifdef DEVICE_POLLING
5252
5253 static void
5254 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5255 {
5256         struct bce_softc *sc = ifp->if_softc;
5257         struct status_block *sblk = sc->status_block;
5258         uint16_t hw_tx_cons, hw_rx_cons;
5259
5260         ASSERT_SERIALIZED(ifp->if_serializer);
5261
5262         switch (cmd) {
5263         case POLL_REGISTER:
5264                 bce_disable_intr(sc);
5265
5266                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5267                        (1 << 16) | sc->bce_rx_quick_cons_trip);
5268                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5269                        (1 << 16) | sc->bce_tx_quick_cons_trip);
5270                 return;
5271         case POLL_DEREGISTER:
5272                 bce_enable_intr(sc, 1);
5273
5274                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5275                        (sc->bce_tx_quick_cons_trip_int << 16) |
5276                        sc->bce_tx_quick_cons_trip);
5277                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5278                        (sc->bce_rx_quick_cons_trip_int << 16) |
5279                        sc->bce_rx_quick_cons_trip);
5280                 return;
5281         default:
5282                 break;
5283         }
5284
5285         if (cmd == POLL_AND_CHECK_STATUS) {
5286                 uint32_t status_attn_bits;
5287
5288                 status_attn_bits = sblk->status_attn_bits;
5289
5290                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5291                         if_printf(ifp,
5292                         "Simulating unexpected status attention bit set.");
5293                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5294
5295                 /* Was it a link change interrupt? */
5296                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5297                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5298                         bce_phy_intr(sc);
5299
5300                 /* Clear any transient status updates during link state change. */
5301                 REG_WR(sc, BCE_HC_COMMAND,
5302                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5303                 REG_RD(sc, BCE_HC_COMMAND);
5304
5305                 /*
5306                  * If any other attention is asserted then
5307                  * the chip is toast.
5308            &