2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
34 * The following controllers are supported by this driver:
42 * The following controllers are not supported by this driver:
48 * BCM5709S A0, A1, B0, B1, B2, C0
52 #include "opt_polling.h"
54 #include <sys/param.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
63 #include <sys/random.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ifq_var.h>
79 #include <net/vlan/if_vlan_var.h>
80 #include <net/vlan/if_vlan_ether.h>
82 #include <dev/netif/mii_layer/mii.h>
83 #include <dev/netif/mii_layer/miivar.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
88 #include "miibus_if.h"
90 #include <dev/netif/bce/if_bcereg.h>
91 #include <dev/netif/bce/if_bcefw.h>
93 /****************************************************************************/
94 /* BCE Debug Options */
95 /****************************************************************************/
98 static uint32_t bce_debug = BCE_WARN;
102 * 1 = 1 in 2,147,483,648
103 * 256 = 1 in 8,388,608
104 * 2048 = 1 in 1,048,576
105 * 65536 = 1 in 32,768
106 * 1048576 = 1 in 2,048
109 * 1073741824 = 1 in 2
111 * bce_debug_l2fhdr_status_check:
112 * How often the l2_fhdr frame error check will fail.
114 * bce_debug_unexpected_attention:
115 * How often the unexpected attention check will fail.
117 * bce_debug_mbuf_allocation_failure:
118 * How often to simulate an mbuf allocation failure.
120 * bce_debug_dma_map_addr_failure:
121 * How often to simulate a DMA mapping failure.
123 * bce_debug_bootcode_running_failure:
124 * How often to simulate a bootcode failure.
126 static int bce_debug_l2fhdr_status_check = 0;
127 static int bce_debug_unexpected_attention = 0;
128 static int bce_debug_mbuf_allocation_failure = 0;
129 static int bce_debug_dma_map_addr_failure = 0;
130 static int bce_debug_bootcode_running_failure = 0;
132 #endif /* BCE_DEBUG */
135 /****************************************************************************/
136 /* PCI Device ID Table */
138 /* Used by bce_probe() to identify the devices supported by this driver. */
139 /****************************************************************************/
140 #define BCE_DEVDESC_MAX 64
142 static struct bce_type bce_devs[] = {
143 /* BCM5706C Controllers and OEM boards. */
144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
145 "HP NC370T Multifunction Gigabit Server Adapter" },
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
147 "HP NC370i Multifunction Gigabit Server Adapter" },
148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
149 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
151 "HP NC371i Multifunction Gigabit Server Adapter" },
152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
153 "Broadcom NetXtreme II BCM5706 1000Base-T" },
155 /* BCM5706S controllers and OEM boards. */
156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
157 "HP NC370F Multifunction Gigabit Server Adapter" },
158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
159 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
161 /* BCM5708C controllers and OEM boards. */
162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
163 "HP NC373T PCIe Multifunction Gig Server Adapter" },
164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
165 "HP NC373i Multifunction Gigabit Server Adapter" },
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
167 "HP NC374m PCIe Multifunction Adapter" },
168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
169 "Broadcom NetXtreme II BCM5708 1000Base-T" },
171 /* BCM5708S controllers and OEM boards. */
172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
173 "HP NC373m Multifunction Gigabit Server Adapter" },
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
175 "HP NC373i Multifunction Gigabit Server Adapter" },
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
177 "HP NC373F PCIe Multifunc Giga Server Adapter" },
178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
179 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
181 /* BCM5709C controllers and OEM boards. */
182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
183 "HP NC382i DP Multifunction Gigabit Server Adapter" },
184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
185 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
187 "Broadcom NetXtreme II BCM5709 1000Base-T" },
189 /* BCM5709S controllers and OEM boards. */
190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
193 "HP NC382i DP Multifunction Gigabit Server Adapter" },
194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
195 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
197 /* BCM5716 controllers and OEM boards. */
198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
199 "Broadcom NetXtreme II BCM5716 1000Base-T" },
205 /****************************************************************************/
206 /* Supported Flash NVRAM device data. */
207 /****************************************************************************/
208 static const struct flash_spec flash_table[] =
210 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
211 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
218 /* Expansion entry 0001 */
219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
223 /* Saifun SA25F010 (non-buffered flash) */
224 /* strap, cfg1, & write1 need updates */
225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
228 "Non-buffered flash (128kB)"},
229 /* Saifun SA25F020 (non-buffered flash) */
230 /* strap, cfg1, & write1 need updates */
231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
234 "Non-buffered flash (256kB)"},
235 /* Expansion entry 0100 */
236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
244 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
249 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
250 /* Saifun SA25F005 (non-buffered flash) */
251 /* strap, cfg1, & write1 need updates */
252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
255 "Non-buffered flash (64kB)"},
257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
261 /* Expansion entry 1001 */
262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
266 /* Expansion entry 1010 */
267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
271 /* ATMEL AT45DB011B (buffered flash) */
272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
275 "Buffered flash (128kB)"},
276 /* Expansion entry 1100 */
277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
281 /* Expansion entry 1101 */
282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
286 /* Ateml Expansion entry 1110 */
287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
290 "Entry 1110 (Atmel)"},
291 /* ATMEL AT45DB021B (buffered flash) */
292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
295 "Buffered flash (256kB)"},
299 * The BCM5709 controllers transparently handle the
300 * differences between Atmel 264 byte pages and all
301 * flash devices which use 256 byte pages, so no
302 * logical-to-physical mapping is required in the
305 static struct flash_spec flash_5709 = {
306 .flags = BCE_NV_BUFFERED,
307 .page_bits = BCM5709_FLASH_PAGE_BITS,
308 .page_size = BCM5709_FLASH_PAGE_SIZE,
309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
311 .name = "5709/5716 buffered flash (256kB)",
315 /****************************************************************************/
316 /* DragonFly device entry points. */
317 /****************************************************************************/
318 static int bce_probe(device_t);
319 static int bce_attach(device_t);
320 static int bce_detach(device_t);
321 static void bce_shutdown(device_t);
323 /****************************************************************************/
324 /* BCE Debug Data Structure Dump Routines */
325 /****************************************************************************/
327 static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
328 static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
329 static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
330 static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
331 static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
332 static void bce_dump_l2fhdr(struct bce_softc *, int,
333 struct l2_fhdr *) __unused;
334 static void bce_dump_tx_chain(struct bce_softc *, int, int);
335 static void bce_dump_rx_chain(struct bce_softc *, int, int);
336 static void bce_dump_status_block(struct bce_softc *);
337 static void bce_dump_driver_state(struct bce_softc *);
338 static void bce_dump_stats_block(struct bce_softc *) __unused;
339 static void bce_dump_hw_state(struct bce_softc *);
340 static void bce_dump_txp_state(struct bce_softc *);
341 static void bce_dump_rxp_state(struct bce_softc *) __unused;
342 static void bce_dump_tpat_state(struct bce_softc *) __unused;
343 static void bce_freeze_controller(struct bce_softc *) __unused;
344 static void bce_unfreeze_controller(struct bce_softc *) __unused;
345 static void bce_breakpoint(struct bce_softc *);
346 #endif /* BCE_DEBUG */
349 /****************************************************************************/
350 /* BCE Register/Memory Access Routines */
351 /****************************************************************************/
352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
353 static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
354 static void bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
355 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
356 static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
357 static int bce_miibus_read_reg(device_t, int, int);
358 static int bce_miibus_write_reg(device_t, int, int, int);
359 static void bce_miibus_statchg(device_t);
362 /****************************************************************************/
363 /* BCE NVRAM Access Routines */
364 /****************************************************************************/
365 static int bce_acquire_nvram_lock(struct bce_softc *);
366 static int bce_release_nvram_lock(struct bce_softc *);
367 static void bce_enable_nvram_access(struct bce_softc *);
368 static void bce_disable_nvram_access(struct bce_softc *);
369 static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
371 static int bce_init_nvram(struct bce_softc *);
372 static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
373 static int bce_nvram_test(struct bce_softc *);
375 /****************************************************************************/
376 /* BCE DMA Allocate/Free Routines */
377 /****************************************************************************/
378 static int bce_dma_alloc(struct bce_softc *);
379 static void bce_dma_free(struct bce_softc *);
380 static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
382 /****************************************************************************/
383 /* BCE Firmware Synchronization and Load */
384 /****************************************************************************/
385 static int bce_fw_sync(struct bce_softc *, uint32_t);
386 static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
388 static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
390 static void bce_start_cpu(struct bce_softc *, struct cpu_reg *);
391 static void bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
392 static void bce_start_rxp_cpu(struct bce_softc *);
393 static void bce_init_rxp_cpu(struct bce_softc *);
394 static void bce_init_txp_cpu(struct bce_softc *);
395 static void bce_init_tpat_cpu(struct bce_softc *);
396 static void bce_init_cp_cpu(struct bce_softc *);
397 static void bce_init_com_cpu(struct bce_softc *);
398 static void bce_init_cpus(struct bce_softc *);
400 static void bce_stop(struct bce_softc *);
401 static int bce_reset(struct bce_softc *, uint32_t);
402 static int bce_chipinit(struct bce_softc *);
403 static int bce_blockinit(struct bce_softc *);
404 static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
406 static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
407 static void bce_probe_pci_caps(struct bce_softc *);
408 static void bce_print_adapter_info(struct bce_softc *);
409 static void bce_get_media(struct bce_softc *);
411 static void bce_init_tx_context(struct bce_softc *);
412 static int bce_init_tx_chain(struct bce_softc *);
413 static void bce_init_rx_context(struct bce_softc *);
414 static int bce_init_rx_chain(struct bce_softc *);
415 static void bce_free_rx_chain(struct bce_softc *);
416 static void bce_free_tx_chain(struct bce_softc *);
418 static int bce_encap(struct bce_softc *, struct mbuf **);
419 static void bce_start(struct ifnet *);
420 static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
421 static void bce_watchdog(struct ifnet *);
422 static int bce_ifmedia_upd(struct ifnet *);
423 static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
424 static void bce_init(void *);
425 static void bce_mgmt_init(struct bce_softc *);
427 static int bce_init_ctx(struct bce_softc *);
428 static void bce_get_mac_addr(struct bce_softc *);
429 static void bce_set_mac_addr(struct bce_softc *);
430 static void bce_phy_intr(struct bce_softc *);
431 static void bce_rx_intr(struct bce_softc *, int);
432 static void bce_tx_intr(struct bce_softc *);
433 static void bce_disable_intr(struct bce_softc *);
434 static void bce_enable_intr(struct bce_softc *, int);
436 #ifdef DEVICE_POLLING
437 static void bce_poll(struct ifnet *, enum poll_cmd, int);
439 static void bce_intr(void *);
440 static void bce_set_rx_mode(struct bce_softc *);
441 static void bce_stats_update(struct bce_softc *);
442 static void bce_tick(void *);
443 static void bce_tick_serialized(struct bce_softc *);
444 static void bce_pulse(void *);
445 static void bce_add_sysctls(struct bce_softc *);
447 static void bce_coal_change(struct bce_softc *);
448 static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
449 static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
450 static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
451 static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
452 static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
453 static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
454 static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
455 static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
456 static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
457 uint32_t *, uint32_t);
461 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
462 * takes 1023 as the TX ticks limit. However, using 1023 will
463 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
464 * there is _no_ network activity on the NIC.
466 static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
467 static uint32_t bce_tx_bds = 255; /* bcm: 20 */
468 static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
469 static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
470 static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
471 static uint32_t bce_rx_bds = 128; /* bcm: 6 */
472 static uint32_t bce_rx_ticks_int = 125; /* bcm: 18 */
473 static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
475 static int bce_msi_enable = 1;
477 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
478 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
479 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
480 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
481 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
482 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
483 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
484 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
485 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
487 /****************************************************************************/
488 /* DragonFly device dispatch table. */
489 /****************************************************************************/
490 static device_method_t bce_methods[] = {
491 /* Device interface */
492 DEVMETHOD(device_probe, bce_probe),
493 DEVMETHOD(device_attach, bce_attach),
494 DEVMETHOD(device_detach, bce_detach),
495 DEVMETHOD(device_shutdown, bce_shutdown),
498 DEVMETHOD(bus_print_child, bus_generic_print_child),
499 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
502 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
503 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
504 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
509 static driver_t bce_driver = {
512 sizeof(struct bce_softc)
515 static devclass_t bce_devclass;
518 DECLARE_DUMMY_MODULE(if_bce);
519 MODULE_DEPEND(bce, miibus, 1, 1, 1);
520 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
521 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
524 /****************************************************************************/
525 /* Device probe function. */
527 /* Compares the device to the driver's list of supported devices and */
528 /* reports back to the OS whether this is the right driver for the device. */
531 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
532 /****************************************************************************/
534 bce_probe(device_t dev)
537 uint16_t vid, did, svid, sdid;
539 /* Get the data for the device to be probed. */
540 vid = pci_get_vendor(dev);
541 did = pci_get_device(dev);
542 svid = pci_get_subvendor(dev);
543 sdid = pci_get_subdevice(dev);
545 /* Look through the list of known devices for a match. */
546 for (t = bce_devs; t->bce_name != NULL; ++t) {
547 if (vid == t->bce_vid && did == t->bce_did &&
548 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
549 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
550 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
553 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
555 /* Print out the device identity. */
556 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
558 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
560 device_set_desc_copy(dev, descbuf);
561 kfree(descbuf, M_TEMP);
569 /****************************************************************************/
570 /* PCI Capabilities Probe Function. */
572 /* Walks the PCI capabiites list for the device to find what features are */
577 /****************************************************************************/
579 bce_print_adapter_info(struct bce_softc *sc)
581 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
583 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
584 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
587 if (sc->bce_flags & BCE_PCIE_FLAG) {
588 kprintf("Bus (PCIe x%d, ", sc->link_width);
589 switch (sc->link_speed) {
591 kprintf("2.5Gbps); ");
597 kprintf("Unknown link speed); ");
601 kprintf("Bus (PCI%s, %s, %dMHz); ",
602 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
603 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
607 /* Firmware version and device features. */
608 kprintf("B/C (%s)", sc->bce_bc_ver);
610 if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
611 (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
613 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
614 kprintf("MFW[%s]", sc->bce_mfw_ver);
615 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
623 /****************************************************************************/
624 /* PCI Capabilities Probe Function. */
626 /* Walks the PCI capabiites list for the device to find what features are */
631 /****************************************************************************/
633 bce_probe_pci_caps(struct bce_softc *sc)
635 device_t dev = sc->bce_dev;
638 if (pci_is_pcix(dev))
639 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
641 ptr = pci_get_pciecap_ptr(dev);
643 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
645 sc->link_speed = link_status & 0xf;
646 sc->link_width = (link_status >> 4) & 0x3f;
647 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
648 sc->bce_flags |= BCE_PCIE_FLAG;
653 /****************************************************************************/
654 /* Device attach function. */
656 /* Allocates device resources, performs secondary chip identification, */
657 /* resets and initializes the hardware, and initializes driver instance */
661 /* 0 on success, positive value on failure. */
662 /****************************************************************************/
664 bce_attach(device_t dev)
666 struct bce_softc *sc = device_get_softc(dev);
667 struct ifnet *ifp = &sc->arpcom.ac_if;
674 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
676 pci_enable_busmaster(dev);
678 bce_probe_pci_caps(sc);
680 /* Allocate PCI memory resources. */
682 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
683 RF_ACTIVE | PCI_RF_DENSE);
684 if (sc->bce_res_mem == NULL) {
685 device_printf(dev, "PCI memory allocation failed\n");
688 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
689 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
691 /* Allocate PCI IRQ resources. */
692 sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
693 &sc->bce_irq_rid, &irq_flags);
695 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
696 &sc->bce_irq_rid, irq_flags);
697 if (sc->bce_res_irq == NULL) {
698 device_printf(dev, "PCI map interrupt failed\n");
704 * Configure byte swap and enable indirect register access.
705 * Rely on CPU to do target byte swapping on big endian systems.
706 * Access to registers outside of PCI configurtion space are not
707 * valid until this is done.
709 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
710 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
711 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
713 /* Save ASIC revsion info. */
714 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
716 /* Weed out any non-production controller revisions. */
717 switch (BCE_CHIP_ID(sc)) {
718 case BCE_CHIP_ID_5706_A0:
719 case BCE_CHIP_ID_5706_A1:
720 case BCE_CHIP_ID_5708_A0:
721 case BCE_CHIP_ID_5708_B0:
722 case BCE_CHIP_ID_5709_A0:
723 case BCE_CHIP_ID_5709_B0:
724 case BCE_CHIP_ID_5709_B1:
726 /* 5709C B2 seems to work fine */
727 case BCE_CHIP_ID_5709_B2:
729 device_printf(dev, "Unsupported chip id 0x%08x!\n",
736 * Find the base address for shared memory access.
737 * Newer versions of bootcode use a signature and offset
738 * while older versions use a fixed address.
740 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
741 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
742 BCE_SHM_HDR_SIGNATURE_SIG) {
743 /* Multi-port devices use different offsets in shared memory. */
744 sc->bce_shmem_base = REG_RD_IND(sc,
745 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
747 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
749 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
751 /* Fetch the bootcode revision. */
752 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
753 for (i = 0, j = 0; i < 3; i++) {
757 num = (uint8_t)(val >> (24 - (i * 8)));
758 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
759 if (num >= k || !skip0 || k == 1) {
760 sc->bce_bc_ver[j++] = (num / k) + '0';
765 sc->bce_bc_ver[j++] = '.';
768 /* Check if any management firwmare is running. */
769 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
770 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
771 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
773 /* Allow time for firmware to enter the running state. */
774 for (i = 0; i < 30; i++) {
775 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
776 if (val & BCE_CONDITION_MFW_RUN_MASK)
782 /* Check the current bootcode state. */
783 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
784 BCE_CONDITION_MFW_RUN_MASK;
785 if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
786 val != BCE_CONDITION_MFW_RUN_NONE) {
787 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
789 for (i = 0, j = 0; j < 3; j++) {
790 val = bce_reg_rd_ind(sc, addr + j * 4);
792 memcpy(&sc->bce_mfw_ver[i], &val, 4);
797 /* Get PCI bus information (speed and type). */
798 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
799 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
802 sc->bce_flags |= BCE_PCIX_FLAG;
804 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
805 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
807 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
808 sc->bus_speed_mhz = 133;
811 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
812 sc->bus_speed_mhz = 100;
815 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
816 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
817 sc->bus_speed_mhz = 66;
820 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
821 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
822 sc->bus_speed_mhz = 50;
825 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
826 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
827 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
828 sc->bus_speed_mhz = 33;
832 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
833 sc->bus_speed_mhz = 66;
835 sc->bus_speed_mhz = 33;
838 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
839 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
841 /* Reset the controller. */
842 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
846 /* Initialize the controller. */
847 rc = bce_chipinit(sc);
849 device_printf(dev, "Controller initialization failed!\n");
853 /* Perform NVRAM test. */
854 rc = bce_nvram_test(sc);
856 device_printf(dev, "NVRAM test failed!\n");
860 /* Fetch the permanent Ethernet MAC address. */
861 bce_get_mac_addr(sc);
864 * Trip points control how many BDs
865 * should be ready before generating an
866 * interrupt while ticks control how long
867 * a BD can sit in the chain before
868 * generating an interrupt. Set the default
869 * values for the RX and TX rings.
873 /* Force more frequent interrupts. */
874 sc->bce_tx_quick_cons_trip_int = 1;
875 sc->bce_tx_quick_cons_trip = 1;
876 sc->bce_tx_ticks_int = 0;
877 sc->bce_tx_ticks = 0;
879 sc->bce_rx_quick_cons_trip_int = 1;
880 sc->bce_rx_quick_cons_trip = 1;
881 sc->bce_rx_ticks_int = 0;
882 sc->bce_rx_ticks = 0;
884 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
885 sc->bce_tx_quick_cons_trip = bce_tx_bds;
886 sc->bce_tx_ticks_int = bce_tx_ticks_int;
887 sc->bce_tx_ticks = bce_tx_ticks;
889 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
890 sc->bce_rx_quick_cons_trip = bce_rx_bds;
891 sc->bce_rx_ticks_int = bce_rx_ticks_int;
892 sc->bce_rx_ticks = bce_rx_ticks;
895 /* Update statistics once every second. */
896 sc->bce_stats_ticks = 1000000 & 0xffff00;
898 /* Find the media type for the adapter. */
901 /* Allocate DMA memory resources. */
902 rc = bce_dma_alloc(sc);
904 device_printf(dev, "DMA resource allocation failed!\n");
908 /* Initialize the ifnet interface. */
910 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
911 ifp->if_ioctl = bce_ioctl;
912 ifp->if_start = bce_start;
913 ifp->if_init = bce_init;
914 ifp->if_watchdog = bce_watchdog;
915 #ifdef DEVICE_POLLING
916 ifp->if_poll = bce_poll;
918 ifp->if_mtu = ETHERMTU;
919 ifp->if_hwassist = BCE_IF_HWASSIST;
920 ifp->if_capabilities = BCE_IF_CAPABILITIES;
921 ifp->if_capenable = ifp->if_capabilities;
922 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
923 ifq_set_ready(&ifp->if_snd);
925 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
926 ifp->if_baudrate = IF_Gbps(2.5);
928 ifp->if_baudrate = IF_Gbps(1);
930 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
931 sc->mbuf_alloc_size = MCLBYTES;
933 /* Look for our PHY. */
934 rc = mii_phy_probe(dev, &sc->bce_miibus,
935 bce_ifmedia_upd, bce_ifmedia_sts);
937 device_printf(dev, "PHY probe failed!\n");
941 /* Attach to the Ethernet interface list. */
942 ether_ifattach(ifp, sc->eaddr, NULL);
944 callout_init_mp(&sc->bce_tick_callout);
945 callout_init_mp(&sc->bce_pulse_callout);
947 /* Hookup IRQ last. */
948 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
949 &sc->bce_intrhand, ifp->if_serializer);
951 device_printf(dev, "Failed to setup IRQ!\n");
956 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
957 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
959 /* Print some important debugging info. */
960 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
962 /* Add the supported sysctls to the kernel. */
966 * The chip reset earlier notified the bootcode that
967 * a driver is present. We now need to start our pulse
968 * routine so that the bootcode is reminded that we're
973 /* Get the firmware running so IPMI still works */
977 bce_print_adapter_info(sc);
986 /****************************************************************************/
987 /* Device detach function. */
989 /* Stops the controller, resets the controller, and releases resources. */
992 /* 0 on success, positive value on failure. */
993 /****************************************************************************/
995 bce_detach(device_t dev)
997 struct bce_softc *sc = device_get_softc(dev);
999 if (device_is_attached(dev)) {
1000 struct ifnet *ifp = &sc->arpcom.ac_if;
1003 /* Stop and reset the controller. */
1004 lwkt_serialize_enter(ifp->if_serializer);
1005 callout_stop(&sc->bce_pulse_callout);
1007 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1008 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1010 msg = BCE_DRV_MSG_CODE_UNLOAD;
1012 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1013 lwkt_serialize_exit(ifp->if_serializer);
1015 ether_ifdetach(ifp);
1018 /* If we have a child device on the MII bus remove it too. */
1020 device_delete_child(dev, sc->bce_miibus);
1021 bus_generic_detach(dev);
1023 if (sc->bce_res_irq != NULL) {
1024 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1028 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1029 pci_release_msi(dev);
1031 if (sc->bce_res_mem != NULL) {
1032 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1038 if (sc->bce_sysctl_tree != NULL)
1039 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1045 /****************************************************************************/
1046 /* Device shutdown function. */
1048 /* Stops and resets the controller. */
1052 /****************************************************************************/
1054 bce_shutdown(device_t dev)
1056 struct bce_softc *sc = device_get_softc(dev);
1057 struct ifnet *ifp = &sc->arpcom.ac_if;
1060 lwkt_serialize_enter(ifp->if_serializer);
1062 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1063 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1065 msg = BCE_DRV_MSG_CODE_UNLOAD;
1067 lwkt_serialize_exit(ifp->if_serializer);
1071 /****************************************************************************/
1072 /* Indirect register read. */
1074 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1075 /* configuration space. Using this mechanism avoids issues with posted */
1076 /* reads but is much slower than memory-mapped I/O. */
1079 /* The value of the register. */
1080 /****************************************************************************/
1082 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1084 device_t dev = sc->bce_dev;
1086 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1090 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1091 DBPRINT(sc, BCE_EXCESSIVE,
1092 "%s(); offset = 0x%08X, val = 0x%08X\n",
1093 __func__, offset, val);
1097 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1102 /****************************************************************************/
1103 /* Indirect register write. */
1105 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1106 /* configuration space. Using this mechanism avoids issues with posted */
1107 /* writes but is muchh slower than memory-mapped I/O. */
1111 /****************************************************************************/
1113 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1115 device_t dev = sc->bce_dev;
1117 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1118 __func__, offset, val);
1120 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1121 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1125 /****************************************************************************/
1126 /* Shared memory write. */
1128 /* Writes NetXtreme II shared memory region. */
1132 /****************************************************************************/
1134 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1136 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1140 /****************************************************************************/
1141 /* Shared memory read. */
1143 /* Reads NetXtreme II shared memory region. */
1146 /* The 32 bit value read. */
1147 /****************************************************************************/
1149 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1151 return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1155 /****************************************************************************/
1156 /* Context memory write. */
1158 /* The NetXtreme II controller uses context memory to track connection */
1159 /* information for L2 and higher network protocols. */
1163 /****************************************************************************/
1165 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1168 uint32_t idx, offset = ctx_offset + cid_addr;
1169 uint32_t val, retry_cnt = 5;
1171 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1172 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1173 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1174 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1176 for (idx = 0; idx < retry_cnt; idx++) {
1177 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1178 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1183 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1184 device_printf(sc->bce_dev,
1185 "Unable to write CTX memory: "
1186 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1187 cid_addr, ctx_offset);
1190 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1191 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1196 /****************************************************************************/
1197 /* PHY register read. */
1199 /* Implements register reads on the MII bus. */
1202 /* The value of the register. */
1203 /****************************************************************************/
1205 bce_miibus_read_reg(device_t dev, int phy, int reg)
1207 struct bce_softc *sc = device_get_softc(dev);
1211 /* Make sure we are accessing the correct PHY address. */
1212 if (phy != sc->bce_phy_addr) {
1213 DBPRINT(sc, BCE_VERBOSE,
1214 "Invalid PHY address %d for PHY read!\n", phy);
1218 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1219 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1220 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1222 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1223 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1228 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1229 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1230 BCE_EMAC_MDIO_COMM_START_BUSY;
1231 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1233 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1236 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1237 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1240 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1241 val &= BCE_EMAC_MDIO_COMM_DATA;
1246 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1247 if_printf(&sc->arpcom.ac_if,
1248 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1252 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1255 DBPRINT(sc, BCE_EXCESSIVE,
1256 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1257 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1259 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1260 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1261 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1263 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1264 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1268 return (val & 0xffff);
1272 /****************************************************************************/
1273 /* PHY register write. */
1275 /* Implements register writes on the MII bus. */
1278 /* The value of the register. */
1279 /****************************************************************************/
1281 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1283 struct bce_softc *sc = device_get_softc(dev);
1287 /* Make sure we are accessing the correct PHY address. */
1288 if (phy != sc->bce_phy_addr) {
1289 DBPRINT(sc, BCE_WARN,
1290 "Invalid PHY address %d for PHY write!\n", phy);
1294 DBPRINT(sc, BCE_EXCESSIVE,
1295 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1296 __func__, phy, (uint16_t)(reg & 0xffff),
1297 (uint16_t)(val & 0xffff));
1299 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1300 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1301 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1303 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1304 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1309 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1310 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1311 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1312 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1314 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1317 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1318 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1324 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1325 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1327 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1328 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1329 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1331 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1332 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1340 /****************************************************************************/
1341 /* MII bus status change. */
1343 /* Called by the MII bus driver when the PHY establishes link to set the */
1344 /* MAC interface registers. */
1348 /****************************************************************************/
1350 bce_miibus_statchg(device_t dev)
1352 struct bce_softc *sc = device_get_softc(dev);
1353 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1355 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1356 mii->mii_media_active);
1359 /* Decode the interface media flags. */
1360 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1361 switch(IFM_TYPE(mii->mii_media_active)) {
1363 kprintf("Ethernet )");
1366 kprintf("Unknown )");
1370 kprintf(" Media Options: ( ");
1371 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1373 kprintf("Autoselect )");
1376 kprintf("Manual )");
1382 kprintf("10Base-T )");
1385 kprintf("100Base-TX )");
1388 kprintf("1000Base-SX )");
1391 kprintf("1000Base-T )");
1398 kprintf(" Global Options: (");
1399 if (mii->mii_media_active & IFM_FDX)
1400 kprintf(" FullDuplex");
1401 if (mii->mii_media_active & IFM_HDX)
1402 kprintf(" HalfDuplex");
1403 if (mii->mii_media_active & IFM_LOOP)
1404 kprintf(" Loopback");
1405 if (mii->mii_media_active & IFM_FLAG0)
1407 if (mii->mii_media_active & IFM_FLAG1)
1409 if (mii->mii_media_active & IFM_FLAG2)
1414 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1417 * Set MII or GMII interface based on the speed negotiated
1420 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1421 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1422 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1423 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1425 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1426 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1430 * Set half or full duplex based on the duplicity negotiated
1433 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1434 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1435 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1437 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1438 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1443 /****************************************************************************/
1444 /* Acquire NVRAM lock. */
1446 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1447 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1448 /* for use by the driver. */
1451 /* 0 on success, positive value on failure. */
1452 /****************************************************************************/
1454 bce_acquire_nvram_lock(struct bce_softc *sc)
1459 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1461 /* Request access to the flash interface. */
1462 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1463 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1464 val = REG_RD(sc, BCE_NVM_SW_ARB);
1465 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1471 if (j >= NVRAM_TIMEOUT_COUNT) {
1472 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1479 /****************************************************************************/
1480 /* Release NVRAM lock. */
1482 /* When the caller is finished accessing NVRAM the lock must be released. */
1483 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1484 /* for use by the driver. */
1487 /* 0 on success, positive value on failure. */
1488 /****************************************************************************/
1490 bce_release_nvram_lock(struct bce_softc *sc)
1495 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1498 * Relinquish nvram interface.
1500 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1502 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1503 val = REG_RD(sc, BCE_NVM_SW_ARB);
1504 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1510 if (j >= NVRAM_TIMEOUT_COUNT) {
1511 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1518 /****************************************************************************/
1519 /* Enable NVRAM access. */
1521 /* Before accessing NVRAM for read or write operations the caller must */
1522 /* enabled NVRAM access. */
1526 /****************************************************************************/
1528 bce_enable_nvram_access(struct bce_softc *sc)
1532 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1534 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1535 /* Enable both bits, even on read. */
1536 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1537 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1541 /****************************************************************************/
1542 /* Disable NVRAM access. */
1544 /* When the caller is finished accessing NVRAM access must be disabled. */
1548 /****************************************************************************/
1550 bce_disable_nvram_access(struct bce_softc *sc)
1554 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1556 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1558 /* Disable both bits, even after read. */
1559 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1560 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1564 /****************************************************************************/
1565 /* Read a dword (32 bits) from NVRAM. */
1567 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1568 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1571 /* 0 on success and the 32 bit value read, positive value on failure. */
1572 /****************************************************************************/
1574 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1580 /* Build the command word. */
1581 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1583 /* Calculate the offset for buffered flash. */
1584 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1585 offset = ((offset / sc->bce_flash_info->page_size) <<
1586 sc->bce_flash_info->page_bits) +
1587 (offset % sc->bce_flash_info->page_size);
1591 * Clear the DONE bit separately, set the address to read,
1592 * and issue the read.
1594 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1595 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1596 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1598 /* Wait for completion. */
1599 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1604 val = REG_RD(sc, BCE_NVM_COMMAND);
1605 if (val & BCE_NVM_COMMAND_DONE) {
1606 val = REG_RD(sc, BCE_NVM_READ);
1609 memcpy(ret_val, &val, 4);
1614 /* Check for errors. */
1615 if (i >= NVRAM_TIMEOUT_COUNT) {
1616 if_printf(&sc->arpcom.ac_if,
1617 "Timeout error reading NVRAM at offset 0x%08X!\n",
1625 /****************************************************************************/
1626 /* Initialize NVRAM access. */
1628 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
1629 /* access that device. */
1632 /* 0 on success, positive value on failure. */
1633 /****************************************************************************/
1635 bce_init_nvram(struct bce_softc *sc)
1638 int j, entry_count, rc = 0;
1639 const struct flash_spec *flash;
1641 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1643 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1644 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1645 sc->bce_flash_info = &flash_5709;
1646 goto bce_init_nvram_get_flash_size;
1649 /* Determine the selected interface. */
1650 val = REG_RD(sc, BCE_NVM_CFG1);
1652 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1655 * Flash reconfiguration is required to support additional
1656 * NVRAM devices not directly supported in hardware.
1657 * Check if the flash interface was reconfigured
1661 if (val & 0x40000000) {
1662 /* Flash interface reconfigured by bootcode. */
1664 DBPRINT(sc, BCE_INFO_LOAD,
1665 "%s(): Flash WAS reconfigured.\n", __func__);
1667 for (j = 0, flash = flash_table; j < entry_count;
1669 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1670 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1671 sc->bce_flash_info = flash;
1676 /* Flash interface not yet reconfigured. */
1679 DBPRINT(sc, BCE_INFO_LOAD,
1680 "%s(): Flash was NOT reconfigured.\n", __func__);
1682 if (val & (1 << 23))
1683 mask = FLASH_BACKUP_STRAP_MASK;
1685 mask = FLASH_STRAP_MASK;
1687 /* Look for the matching NVRAM device configuration data. */
1688 for (j = 0, flash = flash_table; j < entry_count;
1690 /* Check if the device matches any of the known devices. */
1691 if ((val & mask) == (flash->strapping & mask)) {
1692 /* Found a device match. */
1693 sc->bce_flash_info = flash;
1695 /* Request access to the flash interface. */
1696 rc = bce_acquire_nvram_lock(sc);
1700 /* Reconfigure the flash interface. */
1701 bce_enable_nvram_access(sc);
1702 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1703 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1704 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1705 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1706 bce_disable_nvram_access(sc);
1707 bce_release_nvram_lock(sc);
1713 /* Check if a matching device was found. */
1714 if (j == entry_count) {
1715 sc->bce_flash_info = NULL;
1716 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1720 bce_init_nvram_get_flash_size:
1721 /* Write the flash config data to the shared memory interface. */
1722 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1723 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1725 sc->bce_flash_size = val;
1727 sc->bce_flash_size = sc->bce_flash_info->total_size;
1729 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1730 __func__, sc->bce_flash_info->total_size);
1732 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1738 /****************************************************************************/
1739 /* Read an arbitrary range of data from NVRAM. */
1741 /* Prepares the NVRAM interface for access and reads the requested data */
1742 /* into the supplied buffer. */
1745 /* 0 on success and the data read, positive value on failure. */
1746 /****************************************************************************/
1748 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1751 uint32_t cmd_flags, offset32, len32, extra;
1757 /* Request access to the flash interface. */
1758 rc = bce_acquire_nvram_lock(sc);
1762 /* Enable access to flash interface */
1763 bce_enable_nvram_access(sc);
1771 /* XXX should we release nvram lock if read_dword() fails? */
1777 pre_len = 4 - (offset & 3);
1779 if (pre_len >= len32) {
1781 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1783 cmd_flags = BCE_NVM_COMMAND_FIRST;
1786 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1790 memcpy(ret_buf, buf + (offset & 3), pre_len);
1798 extra = 4 - (len32 & 3);
1799 len32 = (len32 + 4) & ~3;
1806 cmd_flags = BCE_NVM_COMMAND_LAST;
1808 cmd_flags = BCE_NVM_COMMAND_FIRST |
1809 BCE_NVM_COMMAND_LAST;
1811 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1813 memcpy(ret_buf, buf, 4 - extra);
1814 } else if (len32 > 0) {
1817 /* Read the first word. */
1821 cmd_flags = BCE_NVM_COMMAND_FIRST;
1823 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1825 /* Advance to the next dword. */
1830 while (len32 > 4 && rc == 0) {
1831 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1833 /* Advance to the next dword. */
1840 goto bce_nvram_read_locked_exit;
1842 cmd_flags = BCE_NVM_COMMAND_LAST;
1843 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1845 memcpy(ret_buf, buf, 4 - extra);
1848 bce_nvram_read_locked_exit:
1849 /* Disable access to flash interface and release the lock. */
1850 bce_disable_nvram_access(sc);
1851 bce_release_nvram_lock(sc);
1857 /****************************************************************************/
1858 /* Verifies that NVRAM is accessible and contains valid data. */
1860 /* Reads the configuration data from NVRAM and verifies that the CRC is */
1864 /* 0 on success, positive value on failure. */
1865 /****************************************************************************/
1867 bce_nvram_test(struct bce_softc *sc)
1869 uint32_t buf[BCE_NVRAM_SIZE / 4];
1870 uint32_t magic, csum;
1871 uint8_t *data = (uint8_t *)buf;
1875 * Check that the device NVRAM is valid by reading
1876 * the magic value at offset 0.
1878 rc = bce_nvram_read(sc, 0, data, 4);
1882 magic = be32toh(buf[0]);
1883 if (magic != BCE_NVRAM_MAGIC) {
1884 if_printf(&sc->arpcom.ac_if,
1885 "Invalid NVRAM magic value! Expected: 0x%08X, "
1886 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1891 * Verify that the device NVRAM includes valid
1892 * configuration data.
1894 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1898 csum = ether_crc32_le(data, 0x100);
1899 if (csum != BCE_CRC32_RESIDUAL) {
1900 if_printf(&sc->arpcom.ac_if,
1901 "Invalid Manufacturing Information NVRAM CRC! "
1902 "Expected: 0x%08X, Found: 0x%08X\n",
1903 BCE_CRC32_RESIDUAL, csum);
1907 csum = ether_crc32_le(data + 0x100, 0x100);
1908 if (csum != BCE_CRC32_RESIDUAL) {
1909 if_printf(&sc->arpcom.ac_if,
1910 "Invalid Feature Configuration Information "
1911 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1912 BCE_CRC32_RESIDUAL, csum);
1919 /****************************************************************************/
1920 /* Identifies the current media type of the controller and sets the PHY */
1925 /****************************************************************************/
1927 bce_get_media(struct bce_softc *sc)
1931 sc->bce_phy_addr = 1;
1933 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1934 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1935 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1936 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1940 * The BCM5709S is software configurable
1941 * for Copper or SerDes operation.
1943 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1945 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1946 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1950 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1951 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1954 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1957 if (pci_get_function(sc->bce_dev) == 0) {
1962 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1970 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1974 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1975 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1978 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1979 sc->bce_flags |= BCE_NO_WOL_FLAG;
1980 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1981 sc->bce_phy_addr = 2;
1982 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1983 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1984 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1986 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1987 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1988 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1993 /****************************************************************************/
1994 /* Free any DMA memory owned by the driver. */
1996 /* Scans through each data structre that requires DMA memory and frees */
1997 /* the memory if allocated. */
2001 /****************************************************************************/
2003 bce_dma_free(struct bce_softc *sc)
2007 /* Destroy the status block. */
2008 if (sc->status_tag != NULL) {
2009 if (sc->status_block != NULL) {
2010 bus_dmamap_unload(sc->status_tag, sc->status_map);
2011 bus_dmamem_free(sc->status_tag, sc->status_block,
2014 bus_dma_tag_destroy(sc->status_tag);
2018 /* Destroy the statistics block. */
2019 if (sc->stats_tag != NULL) {
2020 if (sc->stats_block != NULL) {
2021 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2022 bus_dmamem_free(sc->stats_tag, sc->stats_block,
2025 bus_dma_tag_destroy(sc->stats_tag);
2028 /* Destroy the CTX DMA stuffs. */
2029 if (sc->ctx_tag != NULL) {
2030 for (i = 0; i < sc->ctx_pages; i++) {
2031 if (sc->ctx_block[i] != NULL) {
2032 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2033 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2037 bus_dma_tag_destroy(sc->ctx_tag);
2040 /* Destroy the TX buffer descriptor DMA stuffs. */
2041 if (sc->tx_bd_chain_tag != NULL) {
2042 for (i = 0; i < TX_PAGES; i++) {
2043 if (sc->tx_bd_chain[i] != NULL) {
2044 bus_dmamap_unload(sc->tx_bd_chain_tag,
2045 sc->tx_bd_chain_map[i]);
2046 bus_dmamem_free(sc->tx_bd_chain_tag,
2048 sc->tx_bd_chain_map[i]);
2051 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2054 /* Destroy the RX buffer descriptor DMA stuffs. */
2055 if (sc->rx_bd_chain_tag != NULL) {
2056 for (i = 0; i < RX_PAGES; i++) {
2057 if (sc->rx_bd_chain[i] != NULL) {
2058 bus_dmamap_unload(sc->rx_bd_chain_tag,
2059 sc->rx_bd_chain_map[i]);
2060 bus_dmamem_free(sc->rx_bd_chain_tag,
2062 sc->rx_bd_chain_map[i]);
2065 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2068 /* Destroy the TX mbuf DMA stuffs. */
2069 if (sc->tx_mbuf_tag != NULL) {
2070 for (i = 0; i < TOTAL_TX_BD; i++) {
2071 /* Must have been unloaded in bce_stop() */
2072 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2073 bus_dmamap_destroy(sc->tx_mbuf_tag,
2074 sc->tx_mbuf_map[i]);
2076 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2079 /* Destroy the RX mbuf DMA stuffs. */
2080 if (sc->rx_mbuf_tag != NULL) {
2081 for (i = 0; i < TOTAL_RX_BD; i++) {
2082 /* Must have been unloaded in bce_stop() */
2083 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2084 bus_dmamap_destroy(sc->rx_mbuf_tag,
2085 sc->rx_mbuf_map[i]);
2087 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2088 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2091 /* Destroy the parent tag */
2092 if (sc->parent_tag != NULL)
2093 bus_dma_tag_destroy(sc->parent_tag);
2097 /****************************************************************************/
2098 /* Get DMA memory from the OS. */
2100 /* Validates that the OS has provided DMA buffers in response to a */
2101 /* bus_dmamap_load() call and saves the physical address of those buffers. */
2102 /* When the callback is used the OS will return 0 for the mapping function */
2103 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2104 /* failures back to the caller. */
2108 /****************************************************************************/
2110 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2112 bus_addr_t *busaddr = arg;
2115 * Simulate a mapping failure.
2118 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2119 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2120 __FILE__, __LINE__);
2123 /* Check for an error and signal the caller that an error occurred. */
2127 KASSERT(nseg == 1, ("only one segment is allowed\n"));
2128 *busaddr = segs->ds_addr;
2132 /****************************************************************************/
2133 /* Allocate any DMA memory needed by the driver. */
2135 /* Allocates DMA memory needed for the various global structures needed by */
2138 /* Memory alignment requirements: */
2139 /* -----------------+----------+----------+----------+----------+ */
2140 /* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2141 /* -----------------+----------+----------+----------+----------+ */
2142 /* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2143 /* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2144 /* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2145 /* PG Buffers | none | none | none | none | */
2146 /* TX Buffers | none | none | none | none | */
2147 /* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2148 /* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2149 /* -----------------+----------+----------+----------+----------+ */
2151 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2154 /* 0 for success, positive value for failure. */
2155 /****************************************************************************/
2157 bce_dma_alloc(struct bce_softc *sc)
2159 struct ifnet *ifp = &sc->arpcom.ac_if;
2161 bus_addr_t busaddr, max_busaddr;
2162 bus_size_t status_align, stats_align;
2165 * The embedded PCIe to PCI-X bridge (EPB)
2166 * in the 5708 cannot address memory above
2167 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2169 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2170 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2172 max_busaddr = BUS_SPACE_MAXADDR;
2175 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2177 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2178 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2179 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2180 if (sc->ctx_pages == 0)
2182 if (sc->ctx_pages > BCE_CTX_PAGES) {
2183 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2195 * Allocate the parent bus DMA tag appropriate for PCI.
2197 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2198 max_busaddr, BUS_SPACE_MAXADDR,
2200 BUS_SPACE_MAXSIZE_32BIT, 0,
2201 BUS_SPACE_MAXSIZE_32BIT,
2202 0, &sc->parent_tag);
2204 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2209 * Allocate status block.
2211 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2212 status_align, BCE_STATUS_BLK_SZ,
2213 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2214 &sc->status_tag, &sc->status_map,
2215 &sc->status_block_paddr);
2216 if (sc->status_block == NULL) {
2217 if_printf(ifp, "Could not allocate status block!\n");
2222 * Allocate statistics block.
2224 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2225 stats_align, BCE_STATS_BLK_SZ,
2226 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2227 &sc->stats_tag, &sc->stats_map,
2228 &sc->stats_block_paddr);
2229 if (sc->stats_block == NULL) {
2230 if_printf(ifp, "Could not allocate statistics block!\n");
2235 * Allocate context block, if needed
2237 if (sc->ctx_pages != 0) {
2238 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2239 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2241 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2244 if_printf(ifp, "Could not allocate "
2245 "context block DMA tag!\n");
2249 for (i = 0; i < sc->ctx_pages; i++) {
2250 rc = bus_dmamem_alloc(sc->ctx_tag,
2251 (void **)&sc->ctx_block[i],
2252 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2256 if_printf(ifp, "Could not allocate %dth context "
2257 "DMA memory!\n", i);
2261 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2262 sc->ctx_block[i], BCM_PAGE_SIZE,
2263 bce_dma_map_addr, &busaddr,
2266 if (rc == EINPROGRESS) {
2267 panic("%s coherent memory loading "
2268 "is still in progress!", ifp->if_xname);
2270 if_printf(ifp, "Could not map %dth context "
2271 "DMA memory!\n", i);
2272 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2274 sc->ctx_block[i] = NULL;
2277 sc->ctx_paddr[i] = busaddr;
2282 * Create a DMA tag for the TX buffer descriptor chain,
2283 * allocate and clear the memory, and fetch the
2284 * physical address of the block.
2286 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2287 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2289 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2290 0, &sc->tx_bd_chain_tag);
2292 if_printf(ifp, "Could not allocate "
2293 "TX descriptor chain DMA tag!\n");
2297 for (i = 0; i < TX_PAGES; i++) {
2298 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2299 (void **)&sc->tx_bd_chain[i],
2300 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2302 &sc->tx_bd_chain_map[i]);
2304 if_printf(ifp, "Could not allocate %dth TX descriptor "
2305 "chain DMA memory!\n", i);
2309 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2310 sc->tx_bd_chain_map[i],
2311 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2312 bce_dma_map_addr, &busaddr,
2315 if (rc == EINPROGRESS) {
2316 panic("%s coherent memory loading "
2317 "is still in progress!", ifp->if_xname);
2319 if_printf(ifp, "Could not map %dth TX descriptor "
2320 "chain DMA memory!\n", i);
2321 bus_dmamem_free(sc->tx_bd_chain_tag,
2323 sc->tx_bd_chain_map[i]);
2324 sc->tx_bd_chain[i] = NULL;
2328 sc->tx_bd_chain_paddr[i] = busaddr;
2329 /* DRC - Fix for 64 bit systems. */
2330 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2331 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2334 /* Create a DMA tag for TX mbufs. */
2335 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2336 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2338 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2339 BCE_MAX_SEGMENTS, MCLBYTES,
2340 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2344 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2348 /* Create DMA maps for the TX mbufs clusters. */
2349 for (i = 0; i < TOTAL_TX_BD; i++) {
2350 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2351 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2352 &sc->tx_mbuf_map[i]);
2354 for (j = 0; j < i; ++j) {
2355 bus_dmamap_destroy(sc->tx_mbuf_tag,
2356 sc->tx_mbuf_map[i]);
2358 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2359 sc->tx_mbuf_tag = NULL;
2361 if_printf(ifp, "Unable to create "
2362 "%dth TX mbuf DMA map!\n", i);
2368 * Create a DMA tag for the RX buffer descriptor chain,
2369 * allocate and clear the memory, and fetch the physical
2370 * address of the blocks.
2372 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2373 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2375 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2376 0, &sc->rx_bd_chain_tag);
2378 if_printf(ifp, "Could not allocate "
2379 "RX descriptor chain DMA tag!\n");
2383 for (i = 0; i < RX_PAGES; i++) {
2384 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2385 (void **)&sc->rx_bd_chain[i],
2386 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2388 &sc->rx_bd_chain_map[i]);
2390 if_printf(ifp, "Could not allocate %dth RX descriptor "
2391 "chain DMA memory!\n", i);
2395 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2396 sc->rx_bd_chain_map[i],
2397 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2398 bce_dma_map_addr, &busaddr,
2401 if (rc == EINPROGRESS) {
2402 panic("%s coherent memory loading "
2403 "is still in progress!", ifp->if_xname);
2405 if_printf(ifp, "Could not map %dth RX descriptor "
2406 "chain DMA memory!\n", i);
2407 bus_dmamem_free(sc->rx_bd_chain_tag,
2409 sc->rx_bd_chain_map[i]);
2410 sc->rx_bd_chain[i] = NULL;
2414 sc->rx_bd_chain_paddr[i] = busaddr;
2415 /* DRC - Fix for 64 bit systems. */
2416 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2417 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2420 /* Create a DMA tag for RX mbufs. */
2421 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2422 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2424 MCLBYTES, 1, MCLBYTES,
2425 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2429 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2433 /* Create tmp DMA map for RX mbuf clusters. */
2434 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2435 &sc->rx_mbuf_tmpmap);
2437 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2438 sc->rx_mbuf_tag = NULL;
2440 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2444 /* Create DMA maps for the RX mbuf clusters. */
2445 for (i = 0; i < TOTAL_RX_BD; i++) {
2446 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2447 &sc->rx_mbuf_map[i]);
2449 for (j = 0; j < i; ++j) {
2450 bus_dmamap_destroy(sc->rx_mbuf_tag,
2451 sc->rx_mbuf_map[j]);
2453 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2454 sc->rx_mbuf_tag = NULL;
2456 if_printf(ifp, "Unable to create "
2457 "%dth RX mbuf DMA map!\n", i);
2465 /****************************************************************************/
2466 /* Firmware synchronization. */
2468 /* Before performing certain events such as a chip reset, synchronize with */
2469 /* the firmware first. */
2472 /* 0 for success, positive value for failure. */
2473 /****************************************************************************/
2475 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2480 /* Don't waste any time if we've timed out before. */
2481 if (sc->bce_fw_timed_out)
2484 /* Increment the message sequence number. */
2485 sc->bce_fw_wr_seq++;
2486 msg_data |= sc->bce_fw_wr_seq;
2488 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2490 /* Send the message to the bootcode driver mailbox. */
2491 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2493 /* Wait for the bootcode to acknowledge the message. */
2494 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2495 /* Check for a response in the bootcode firmware mailbox. */
2496 val = bce_shmem_rd(sc, BCE_FW_MB);
2497 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2502 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2503 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2504 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2505 if_printf(&sc->arpcom.ac_if,
2506 "Firmware synchronization timeout! "
2507 "msg_data = 0x%08X\n", msg_data);
2509 msg_data &= ~BCE_DRV_MSG_CODE;
2510 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2512 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2514 sc->bce_fw_timed_out = 1;
2521 /****************************************************************************/
2522 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2526 /****************************************************************************/
2528 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2529 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2534 for (i = 0; i < rv2p_code_len; i += 8) {
2535 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2537 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2540 if (rv2p_proc == RV2P_PROC1) {
2541 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2542 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2544 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2545 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2549 /* Reset the processor, un-stall is done later. */
2550 if (rv2p_proc == RV2P_PROC1)
2551 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2553 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2557 /****************************************************************************/
2558 /* Load RISC processor firmware. */
2560 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2561 /* associated with a particular processor. */
2565 /****************************************************************************/
2567 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2573 bce_halt_cpu(sc, cpu_reg);
2575 /* Load the Text area. */
2576 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2578 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2579 REG_WR_IND(sc, offset, fw->text[j]);
2582 /* Load the Data area. */
2583 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2585 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2586 REG_WR_IND(sc, offset, fw->data[j]);
2589 /* Load the SBSS area. */
2590 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2592 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2593 REG_WR_IND(sc, offset, fw->sbss[j]);
2596 /* Load the BSS area. */
2597 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2599 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2600 REG_WR_IND(sc, offset, fw->bss[j]);
2603 /* Load the Read-Only area. */
2604 offset = cpu_reg->spad_base +
2605 (fw->rodata_addr - cpu_reg->mips_view_base);
2607 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2608 REG_WR_IND(sc, offset, fw->rodata[j]);
2611 /* Clear the pre-fetch instruction and set the FW start address. */
2612 REG_WR_IND(sc, cpu_reg->inst, 0);
2613 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2617 /****************************************************************************/
2618 /* Starts the RISC processor. */
2620 /* Assumes the CPU starting address has already been set. */
2624 /****************************************************************************/
2626 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2630 /* Start the CPU. */
2631 val = REG_RD_IND(sc, cpu_reg->mode);
2632 val &= ~cpu_reg->mode_value_halt;
2633 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2634 REG_WR_IND(sc, cpu_reg->mode, val);
2638 /****************************************************************************/
2639 /* Halts the RISC processor. */
2643 /****************************************************************************/
2645 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2650 val = REG_RD_IND(sc, cpu_reg->mode);
2651 val |= cpu_reg->mode_value_halt;
2652 REG_WR_IND(sc, cpu_reg->mode, val);
2653 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2657 /****************************************************************************/
2658 /* Start the RX CPU. */
2662 /****************************************************************************/
2664 bce_start_rxp_cpu(struct bce_softc *sc)
2666 struct cpu_reg cpu_reg;
2668 cpu_reg.mode = BCE_RXP_CPU_MODE;
2669 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2670 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2671 cpu_reg.state = BCE_RXP_CPU_STATE;
2672 cpu_reg.state_value_clear = 0xffffff;
2673 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2674 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2675 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2676 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2677 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2678 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2679 cpu_reg.mips_view_base = 0x8000000;
2681 bce_start_cpu(sc, &cpu_reg);
2685 /****************************************************************************/
2686 /* Initialize the RX CPU. */
2690 /****************************************************************************/
2692 bce_init_rxp_cpu(struct bce_softc *sc)
2694 struct cpu_reg cpu_reg;
2697 cpu_reg.mode = BCE_RXP_CPU_MODE;
2698 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2699 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2700 cpu_reg.state = BCE_RXP_CPU_STATE;
2701 cpu_reg.state_value_clear = 0xffffff;
2702 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2703 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2704 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2705 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2706 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2707 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2708 cpu_reg.mips_view_base = 0x8000000;
2710 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2711 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2712 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2713 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2714 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2715 fw.start_addr = bce_RXP_b09FwStartAddr;
2717 fw.text_addr = bce_RXP_b09FwTextAddr;
2718 fw.text_len = bce_RXP_b09FwTextLen;
2720 fw.text = bce_RXP_b09FwText;
2722 fw.data_addr = bce_RXP_b09FwDataAddr;
2723 fw.data_len = bce_RXP_b09FwDataLen;
2725 fw.data = bce_RXP_b09FwData;
2727 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2728 fw.sbss_len = bce_RXP_b09FwSbssLen;
2730 fw.sbss = bce_RXP_b09FwSbss;
2732 fw.bss_addr = bce_RXP_b09FwBssAddr;
2733 fw.bss_len = bce_RXP_b09FwBssLen;
2735 fw.bss = bce_RXP_b09FwBss;
2737 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2738 fw.rodata_len = bce_RXP_b09FwRodataLen;
2739 fw.rodata_index = 0;
2740 fw.rodata = bce_RXP_b09FwRodata;
2742 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2743 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2744 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2745 fw.start_addr = bce_RXP_b06FwStartAddr;
2747 fw.text_addr = bce_RXP_b06FwTextAddr;
2748 fw.text_len = bce_RXP_b06FwTextLen;
2750 fw.text = bce_RXP_b06FwText;
2752 fw.data_addr = bce_RXP_b06FwDataAddr;
2753 fw.data_len = bce_RXP_b06FwDataLen;
2755 fw.data = bce_RXP_b06FwData;
2757 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2758 fw.sbss_len = bce_RXP_b06FwSbssLen;
2760 fw.sbss = bce_RXP_b06FwSbss;
2762 fw.bss_addr = bce_RXP_b06FwBssAddr;
2763 fw.bss_len = bce_RXP_b06FwBssLen;
2765 fw.bss = bce_RXP_b06FwBss;
2767 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2768 fw.rodata_len = bce_RXP_b06FwRodataLen;
2769 fw.rodata_index = 0;
2770 fw.rodata = bce_RXP_b06FwRodata;
2773 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2774 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2775 /* Delay RXP start until initialization is complete. */
2779 /****************************************************************************/
2780 /* Initialize the TX CPU. */
2784 /****************************************************************************/
2786 bce_init_txp_cpu(struct bce_softc *sc)
2788 struct cpu_reg cpu_reg;
2791 cpu_reg.mode = BCE_TXP_CPU_MODE;
2792 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2793 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2794 cpu_reg.state = BCE_TXP_CPU_STATE;
2795 cpu_reg.state_value_clear = 0xffffff;
2796 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2797 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2798 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2799 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2800 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2801 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2802 cpu_reg.mips_view_base = 0x8000000;
2804 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2805 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2806 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2807 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2808 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2809 fw.start_addr = bce_TXP_b09FwStartAddr;
2811 fw.text_addr = bce_TXP_b09FwTextAddr;
2812 fw.text_len = bce_TXP_b09FwTextLen;
2814 fw.text = bce_TXP_b09FwText;
2816 fw.data_addr = bce_TXP_b09FwDataAddr;
2817 fw.data_len = bce_TXP_b09FwDataLen;
2819 fw.data = bce_TXP_b09FwData;
2821 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2822 fw.sbss_len = bce_TXP_b09FwSbssLen;
2824 fw.sbss = bce_TXP_b09FwSbss;
2826 fw.bss_addr = bce_TXP_b09FwBssAddr;
2827 fw.bss_len = bce_TXP_b09FwBssLen;
2829 fw.bss = bce_TXP_b09FwBss;
2831 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2832 fw.rodata_len = bce_TXP_b09FwRodataLen;
2833 fw.rodata_index = 0;
2834 fw.rodata = bce_TXP_b09FwRodata;
2836 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2837 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2838 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2839 fw.start_addr = bce_TXP_b06FwStartAddr;
2841 fw.text_addr = bce_TXP_b06FwTextAddr;
2842 fw.text_len = bce_TXP_b06FwTextLen;
2844 fw.text = bce_TXP_b06FwText;
2846 fw.data_addr = bce_TXP_b06FwDataAddr;
2847 fw.data_len = bce_TXP_b06FwDataLen;
2849 fw.data = bce_TXP_b06FwData;
2851 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2852 fw.sbss_len = bce_TXP_b06FwSbssLen;
2854 fw.sbss = bce_TXP_b06FwSbss;
2856 fw.bss_addr = bce_TXP_b06FwBssAddr;
2857 fw.bss_len = bce_TXP_b06FwBssLen;
2859 fw.bss = bce_TXP_b06FwBss;
2861 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2862 fw.rodata_len = bce_TXP_b06FwRodataLen;
2863 fw.rodata_index = 0;
2864 fw.rodata = bce_TXP_b06FwRodata;
2867 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2868 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2869 bce_start_cpu(sc, &cpu_reg);
2873 /****************************************************************************/
2874 /* Initialize the TPAT CPU. */
2878 /****************************************************************************/
2880 bce_init_tpat_cpu(struct bce_softc *sc)
2882 struct cpu_reg cpu_reg;
2885 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2886 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2887 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2888 cpu_reg.state = BCE_TPAT_CPU_STATE;
2889 cpu_reg.state_value_clear = 0xffffff;
2890 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2891 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2892 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2893 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2894 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2895 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2896 cpu_reg.mips_view_base = 0x8000000;
2898 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2899 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2900 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2901 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2902 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2903 fw.start_addr = bce_TPAT_b09FwStartAddr;
2905 fw.text_addr = bce_TPAT_b09FwTextAddr;
2906 fw.text_len = bce_TPAT_b09FwTextLen;
2908 fw.text = bce_TPAT_b09FwText;
2910 fw.data_addr = bce_TPAT_b09FwDataAddr;
2911 fw.data_len = bce_TPAT_b09FwDataLen;
2913 fw.data = bce_TPAT_b09FwData;
2915 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2916 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2918 fw.sbss = bce_TPAT_b09FwSbss;
2920 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2921 fw.bss_len = bce_TPAT_b09FwBssLen;
2923 fw.bss = bce_TPAT_b09FwBss;
2925 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2926 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2927 fw.rodata_index = 0;
2928 fw.rodata = bce_TPAT_b09FwRodata;
2930 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2931 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2932 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2933 fw.start_addr = bce_TPAT_b06FwStartAddr;
2935 fw.text_addr = bce_TPAT_b06FwTextAddr;
2936 fw.text_len = bce_TPAT_b06FwTextLen;
2938 fw.text = bce_TPAT_b06FwText;
2940 fw.data_addr = bce_TPAT_b06FwDataAddr;
2941 fw.data_len = bce_TPAT_b06FwDataLen;
2943 fw.data = bce_TPAT_b06FwData;
2945 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2946 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2948 fw.sbss = bce_TPAT_b06FwSbss;
2950 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2951 fw.bss_len = bce_TPAT_b06FwBssLen;
2953 fw.bss = bce_TPAT_b06FwBss;
2955 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2956 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2957 fw.rodata_index = 0;
2958 fw.rodata = bce_TPAT_b06FwRodata;
2961 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2962 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2963 bce_start_cpu(sc, &cpu_reg);
2967 /****************************************************************************/
2968 /* Initialize the CP CPU. */
2972 /****************************************************************************/
2974 bce_init_cp_cpu(struct bce_softc *sc)
2976 struct cpu_reg cpu_reg;
2979 cpu_reg.mode = BCE_CP_CPU_MODE;
2980 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2981 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2982 cpu_reg.state = BCE_CP_CPU_STATE;
2983 cpu_reg.state_value_clear = 0xffffff;
2984 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
2985 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
2986 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
2987 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
2988 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
2989 cpu_reg.spad_base = BCE_CP_SCRATCH;
2990 cpu_reg.mips_view_base = 0x8000000;
2992 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2993 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2994 fw.ver_major = bce_CP_b09FwReleaseMajor;
2995 fw.ver_minor = bce_CP_b09FwReleaseMinor;
2996 fw.ver_fix = bce_CP_b09FwReleaseFix;
2997 fw.start_addr = bce_CP_b09FwStartAddr;
2999 fw.text_addr = bce_CP_b09FwTextAddr;
3000 fw.text_len = bce_CP_b09FwTextLen;
3002 fw.text = bce_CP_b09FwText;
3004 fw.data_addr = bce_CP_b09FwDataAddr;
3005 fw.data_len = bce_CP_b09FwDataLen;
3007 fw.data = bce_CP_b09FwData;
3009 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3010 fw.sbss_len = bce_CP_b09FwSbssLen;
3012 fw.sbss = bce_CP_b09FwSbss;
3014 fw.bss_addr = bce_CP_b09FwBssAddr;
3015 fw.bss_len = bce_CP_b09FwBssLen;
3017 fw.bss = bce_CP_b09FwBss;
3019 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3020 fw.rodata_len = bce_CP_b09FwRodataLen;
3021 fw.rodata_index = 0;
3022 fw.rodata = bce_CP_b09FwRodata;
3024 fw.ver_major = bce_CP_b06FwReleaseMajor;
3025 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3026 fw.ver_fix = bce_CP_b06FwReleaseFix;
3027 fw.start_addr = bce_CP_b06FwStartAddr;
3029 fw.text_addr = bce_CP_b06FwTextAddr;
3030 fw.text_len = bce_CP_b06FwTextLen;
3032 fw.text = bce_CP_b06FwText;
3034 fw.data_addr = bce_CP_b06FwDataAddr;
3035 fw.data_len = bce_CP_b06FwDataLen;
3037 fw.data = bce_CP_b06FwData;
3039 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3040 fw.sbss_len = bce_CP_b06FwSbssLen;
3042 fw.sbss = bce_CP_b06FwSbss;
3044 fw.bss_addr = bce_CP_b06FwBssAddr;
3045 fw.bss_len = bce_CP_b06FwBssLen;
3047 fw.bss = bce_CP_b06FwBss;
3049 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3050 fw.rodata_len = bce_CP_b06FwRodataLen;
3051 fw.rodata_index = 0;
3052 fw.rodata = bce_CP_b06FwRodata;
3055 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3056 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3057 bce_start_cpu(sc, &cpu_reg);
3061 /****************************************************************************/
3062 /* Initialize the COM CPU. */
3066 /****************************************************************************/
3068 bce_init_com_cpu(struct bce_softc *sc)
3070 struct cpu_reg cpu_reg;
3073 cpu_reg.mode = BCE_COM_CPU_MODE;
3074 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3075 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3076 cpu_reg.state = BCE_COM_CPU_STATE;
3077 cpu_reg.state_value_clear = 0xffffff;
3078 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3079 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3080 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3081 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3082 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3083 cpu_reg.spad_base = BCE_COM_SCRATCH;
3084 cpu_reg.mips_view_base = 0x8000000;
3086 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3087 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3088 fw.ver_major = bce_COM_b09FwReleaseMajor;
3089 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3090 fw.ver_fix = bce_COM_b09FwReleaseFix;
3091 fw.start_addr = bce_COM_b09FwStartAddr;
3093 fw.text_addr = bce_COM_b09FwTextAddr;
3094 fw.text_len = bce_COM_b09FwTextLen;
3096 fw.text = bce_COM_b09FwText;
3098 fw.data_addr = bce_COM_b09FwDataAddr;
3099 fw.data_len = bce_COM_b09FwDataLen;
3101 fw.data = bce_COM_b09FwData;
3103 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3104 fw.sbss_len = bce_COM_b09FwSbssLen;
3106 fw.sbss = bce_COM_b09FwSbss;
3108 fw.bss_addr = bce_COM_b09FwBssAddr;
3109 fw.bss_len = bce_COM_b09FwBssLen;
3111 fw.bss = bce_COM_b09FwBss;
3113 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3114 fw.rodata_len = bce_COM_b09FwRodataLen;
3115 fw.rodata_index = 0;
3116 fw.rodata = bce_COM_b09FwRodata;
3118 fw.ver_major = bce_COM_b06FwReleaseMajor;
3119 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3120 fw.ver_fix = bce_COM_b06FwReleaseFix;
3121 fw.start_addr = bce_COM_b06FwStartAddr;
3123 fw.text_addr = bce_COM_b06FwTextAddr;
3124 fw.text_len = bce_COM_b06FwTextLen;
3126 fw.text = bce_COM_b06FwText;
3128 fw.data_addr = bce_COM_b06FwDataAddr;
3129 fw.data_len = bce_COM_b06FwDataLen;
3131 fw.data = bce_COM_b06FwData;
3133 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3134 fw.sbss_len = bce_COM_b06FwSbssLen;
3136 fw.sbss = bce_COM_b06FwSbss;
3138 fw.bss_addr = bce_COM_b06FwBssAddr;
3139 fw.bss_len = bce_COM_b06FwBssLen;
3141 fw.bss = bce_COM_b06FwBss;
3143 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3144 fw.rodata_len = bce_COM_b06FwRodataLen;
3145 fw.rodata_index = 0;
3146 fw.rodata = bce_COM_b06FwRodata;
3149 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3150 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3151 bce_start_cpu(sc, &cpu_reg);
3155 /****************************************************************************/
3156 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3158 /* Loads the firmware for each CPU and starts the CPU. */
3162 /****************************************************************************/
3164 bce_init_cpus(struct bce_softc *sc)
3166 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3167 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3168 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3169 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3170 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3171 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3172 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3174 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3175 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3176 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3177 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3180 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3181 sizeof(bce_rv2p_proc1), RV2P_PROC1);
3182 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3183 sizeof(bce_rv2p_proc2), RV2P_PROC2);
3186 bce_init_rxp_cpu(sc);
3187 bce_init_txp_cpu(sc);
3188 bce_init_tpat_cpu(sc);
3189 bce_init_com_cpu(sc);
3190 bce_init_cp_cpu(sc);
3194 /****************************************************************************/
3195 /* Initialize context memory. */
3197 /* Clears the memory associated with each Context ID (CID). */
3201 /****************************************************************************/
3203 bce_init_ctx(struct bce_softc *sc)
3205 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3206 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3207 /* DRC: Replace this constant value with a #define. */
3208 int i, retry_cnt = 10;
3212 * BCM5709 context memory may be cached
3213 * in host memory so prepare the host memory
3216 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3218 val |= (BCM_PAGE_BITS - 8) << 16;
3219 REG_WR(sc, BCE_CTX_COMMAND, val);
3221 /* Wait for mem init command to complete. */
3222 for (i = 0; i < retry_cnt; i++) {
3223 val = REG_RD(sc, BCE_CTX_COMMAND);
3224 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3228 if (i == retry_cnt) {
3229 device_printf(sc->bce_dev,
3230 "Context memory initialization failed!\n");
3234 for (i = 0; i < sc->ctx_pages; i++) {
3238 * Set the physical address of the context
3241 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3242 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3243 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3244 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3245 BCE_ADDR_HI(sc->ctx_paddr[i]));
3246 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3247 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3250 * Verify that the context memory write was successful.
3252 for (j = 0; j < retry_cnt; j++) {
3253 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3255 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3259 if (j == retry_cnt) {
3260 device_printf(sc->bce_dev,
3261 "Failed to initialize context page!\n");
3266 uint32_t vcid_addr, offset;
3269 * For the 5706/5708, context memory is local to
3270 * the controller, so initialize the controller
3274 vcid_addr = GET_CID_ADDR(96);
3276 vcid_addr -= PHY_CTX_SIZE;
3278 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3279 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3281 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3282 CTX_WR(sc, 0x00, offset, 0);
3284 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3285 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3292 /****************************************************************************/
3293 /* Fetch the permanent MAC address of the controller. */
3297 /****************************************************************************/
3299 bce_get_mac_addr(struct bce_softc *sc)
3301 uint32_t mac_lo = 0, mac_hi = 0;
3304 * The NetXtreme II bootcode populates various NIC
3305 * power-on and runtime configuration items in a
3306 * shared memory area. The factory configured MAC
3307 * address is available from both NVRAM and the
3308 * shared memory area so we'll read the value from
3309 * shared memory for speed.
3312 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
3313 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3315 if (mac_lo == 0 && mac_hi == 0) {
3316 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3318 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3319 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3320 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3321 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3322 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3323 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3326 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3330 /****************************************************************************/
3331 /* Program the MAC address. */
3335 /****************************************************************************/
3337 bce_set_mac_addr(struct bce_softc *sc)
3339 const uint8_t *mac_addr = sc->eaddr;
3342 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3345 val = (mac_addr[0] << 8) | mac_addr[1];
3346 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3348 val = (mac_addr[2] << 24) |
3349 (mac_addr[3] << 16) |
3350 (mac_addr[4] << 8) |
3352 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3356 /****************************************************************************/
3357 /* Stop the controller. */
3361 /****************************************************************************/
3363 bce_stop(struct bce_softc *sc)
3365 struct ifnet *ifp = &sc->arpcom.ac_if;
3367 ASSERT_SERIALIZED(ifp->if_serializer);
3369 callout_stop(&sc->bce_tick_callout);
3371 /* Disable the transmit/receive blocks. */
3372 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3373 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3376 bce_disable_intr(sc);
3378 /* Free the RX lists. */
3379 bce_free_rx_chain(sc);
3381 /* Free TX buffers. */
3382 bce_free_tx_chain(sc);
3385 sc->bce_coalchg_mask = 0;
3387 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3393 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3398 /* Wait for pending PCI transactions to complete. */
3399 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3400 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3401 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3402 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3403 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3404 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3408 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3409 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3410 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3411 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3412 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3415 /* Assume bootcode is running. */
3416 sc->bce_fw_timed_out = 0;
3417 sc->bce_drv_cardiac_arrest = 0;
3419 /* Give the firmware a chance to prepare for the reset. */
3420 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3422 if_printf(&sc->arpcom.ac_if,
3423 "Firmware is not ready for reset\n");
3427 /* Set a firmware reminder that this is a soft reset. */
3428 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3429 BCE_DRV_RESET_SIGNATURE_MAGIC);
3431 /* Dummy read to force the chip to complete all current transactions. */
3432 val = REG_RD(sc, BCE_MISC_ID);
3435 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3436 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3437 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3438 REG_RD(sc, BCE_MISC_COMMAND);
3441 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3442 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3444 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3446 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3447 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3448 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3449 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3451 /* Allow up to 30us for reset to complete. */
3452 for (i = 0; i < 10; i++) {
3453 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3454 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3455 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3460 /* Check that reset completed successfully. */
3461 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3462 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3463 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3468 /* Make sure byte swapping is properly configured. */
3469 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3470 if (val != 0x01020304) {
3471 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3475 /* Just completed a reset, assume that firmware is running again. */
3476 sc->bce_fw_timed_out = 0;
3477 sc->bce_drv_cardiac_arrest = 0;
3479 /* Wait for the firmware to finish its initialization. */
3480 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3482 if_printf(&sc->arpcom.ac_if,
3483 "Firmware did not complete initialization!\n");
3490 bce_chipinit(struct bce_softc *sc)
3495 /* Make sure the interrupt is not active. */
3496 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3497 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3500 * Initialize DMA byte/word swapping, configure the number of DMA
3501 * channels and PCI clock compensation delay.
3503 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3504 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3505 #if BYTE_ORDER == BIG_ENDIAN
3506 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3508 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3509 DMA_READ_CHANS << 12 |
3510 DMA_WRITE_CHANS << 16;
3512 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3514 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3515 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3518 * This setting resolves a problem observed on certain Intel PCI
3519 * chipsets that cannot handle multiple outstanding DMA operations.
3520 * See errata E9_5706A1_65.
3522 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3523 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3524 !(sc->bce_flags & BCE_PCIX_FLAG))
3525 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3527 REG_WR(sc, BCE_DMA_CONFIG, val);
3529 /* Enable the RX_V2P and Context state machines before access. */
3530 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3531 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3532 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3533 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3535 /* Initialize context mapping and zero out the quick contexts. */
3536 rc = bce_init_ctx(sc);
3540 /* Initialize the on-boards CPUs */
3543 /* Enable management frames (NC-SI) to flow to the MCP. */
3544 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3545 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3546 BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3547 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3550 /* Prepare NVRAM for access. */
3551 rc = bce_init_nvram(sc);
3555 /* Set the kernel bypass block size */
3556 val = REG_RD(sc, BCE_MQ_CONFIG);
3557 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3558 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3560 /* Enable bins used on the 5709/5716. */
3561 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3562 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3563 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3564 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3565 val |= BCE_MQ_CONFIG_HALT_DIS;
3568 REG_WR(sc, BCE_MQ_CONFIG, val);
3570 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3571 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3572 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3574 /* Set the page size and clear the RV2P processor stall bits. */
3575 val = (BCM_PAGE_BITS - 8) << 24;
3576 REG_WR(sc, BCE_RV2P_CONFIG, val);
3578 /* Configure page size. */
3579 val = REG_RD(sc, BCE_TBDR_CONFIG);
3580 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3581 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3582 REG_WR(sc, BCE_TBDR_CONFIG, val);
3584 /* Set the perfect match control register to default. */
3585 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3591 /****************************************************************************/
3592 /* Initialize the controller in preparation to send/receive traffic. */
3595 /* 0 for success, positive value for failure. */
3596 /****************************************************************************/
3598 bce_blockinit(struct bce_softc *sc)
3603 /* Load the hardware default MAC address. */
3604 bce_set_mac_addr(sc);
3606 /* Set the Ethernet backoff seed value */
3607 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3608 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3609 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3611 sc->last_status_idx = 0;
3612 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3614 /* Set up link change interrupt generation. */
3615 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3617 /* Program the physical address of the status block. */
3618 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3619 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3621 /* Program the physical address of the statistics block. */
3622 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3623 BCE_ADDR_LO(sc->stats_block_paddr));
3624 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3625 BCE_ADDR_HI(sc->stats_block_paddr));
3627 /* Program various host coalescing parameters. */
3628 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3629 (sc->bce_tx_quick_cons_trip_int << 16) |
3630 sc->bce_tx_quick_cons_trip);
3631 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3632 (sc->bce_rx_quick_cons_trip_int << 16) |
3633 sc->bce_rx_quick_cons_trip);
3634 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3635 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3636 REG_WR(sc, BCE_HC_TX_TICKS,
3637 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3638 REG_WR(sc, BCE_HC_RX_TICKS,
3639 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3640 REG_WR(sc, BCE_HC_COM_TICKS,
3641 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3642 REG_WR(sc, BCE_HC_CMD_TICKS,
3643 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3644 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3645 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3646 REG_WR(sc, BCE_HC_CONFIG,
3647 BCE_HC_CONFIG_TX_TMR_MODE |
3648 BCE_HC_CONFIG_COLLECT_STATS);
3650 /* Clear the internal statistics counters. */
3651 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3653 /* Verify that bootcode is running. */
3654 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3656 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3657 if_printf(&sc->arpcom.ac_if,
3658 "%s(%d): Simulating bootcode failure.\n",
3659 __FILE__, __LINE__);
3662 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3663 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3664 if_printf(&sc->arpcom.ac_if,
3665 "Bootcode not running! Found: 0x%08X, "
3666 "Expected: 08%08X\n",
3667 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3668 BCE_DEV_INFO_SIGNATURE_MAGIC);
3673 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3674 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3675 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3676 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3677 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3680 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3681 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3683 /* Enable link state change interrupt generation. */
3684 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3686 /* Enable the RXP. */
3687 bce_start_rxp_cpu(sc);
3689 /* Disable management frames (NC-SI) from flowing to the MCP. */
3690 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3691 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3692 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3693 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3696 /* Enable all remaining blocks in the MAC. */
3697 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3698 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3699 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3700 BCE_MISC_ENABLE_DEFAULT_XI);
3702 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3704 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3707 /* Save the current host coalescing block settings. */
3708 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3714 /****************************************************************************/
3715 /* Encapsulate an mbuf cluster into the rx_bd chain. */
3717 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3718 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3722 /* 0 for success, positive value for failure. */
3723 /****************************************************************************/
3725 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3726 uint32_t *prod_bseq, int init)
3729 bus_dma_segment_t seg;
3733 uint16_t debug_chain_prod = *chain_prod;
3736 /* Make sure the inputs are valid. */
3737 DBRUNIF((*chain_prod > MAX_RX_BD),
3738 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3739 "RX producer out of range: 0x%04X > 0x%04X\n",
3741 *chain_prod, (uint16_t)MAX_RX_BD));
3743 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3744 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3746 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3747 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3748 "Simulating mbuf allocation failure.\n",
3749 __FILE__, __LINE__);
3750 sc->mbuf_alloc_failed++;
3753 /* This is a new mbuf allocation. */
3754 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3757 DBRUNIF(1, sc->rx_mbuf_alloc++);
3759 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3761 /* Map the mbuf cluster into device memory. */
3762 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3763 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3768 if_printf(&sc->arpcom.ac_if,
3769 "Error mapping mbuf into RX chain!\n");
3771 DBRUNIF(1, sc->rx_mbuf_alloc--);
3775 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3776 bus_dmamap_unload(sc->rx_mbuf_tag,
3777 sc->rx_mbuf_map[*chain_prod]);
3780 map = sc->rx_mbuf_map[*chain_prod];
3781 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3782 sc->rx_mbuf_tmpmap = map;
3784 /* Watch for overflow. */
3785 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3786 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3787 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3788 __FILE__, __LINE__, sc->free_rx_bd,
3789 (uint16_t)USABLE_RX_BD));
3791 /* Update some debug statistic counters */
3792 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3793 sc->rx_low_watermark = sc->free_rx_bd);
3794 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3796 /* Save the mbuf and update our counter. */
3797 sc->rx_mbuf_ptr[*chain_prod] = m_new;
3798 sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3801 bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3803 DBRUN(BCE_VERBOSE_RECV,
3804 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3806 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3807 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3814 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3820 paddr = sc->rx_mbuf_paddr[chain_prod];
3821 len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3823 /* Setup the rx_bd for the first segment. */
3824 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3826 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3827 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3828 rxbd->rx_bd_len = htole32(len);
3829 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3832 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3836 /****************************************************************************/
3837 /* Initialize the TX context memory. */
3841 /****************************************************************************/
3843 bce_init_tx_context(struct bce_softc *sc)
3847 /* Initialize the context ID for an L2 TX chain. */
3848 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3849 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3850 /* Set the CID type to support an L2 connection. */
3851 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3852 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3853 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3854 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3856 /* Point the hardware to the first page in the chain. */
3857 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3858 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3859 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3860 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3861 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3862 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3864 /* Set the CID type to support an L2 connection. */
3865 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3866 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3867 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3868 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3870 /* Point the hardware to the first page in the chain. */
3871 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3872 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3873 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3874 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3875 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3876 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3881 /****************************************************************************/
3882 /* Allocate memory and initialize the TX data structures. */
3885 /* 0 for success, positive value for failure. */
3886 /****************************************************************************/
3888 bce_init_tx_chain(struct bce_softc *sc)
3893 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3895 /* Set the initial TX producer/consumer indices. */
3898 sc->tx_prod_bseq = 0;
3900 sc->max_tx_bd = USABLE_TX_BD;
3901 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3902 DBRUNIF(1, sc->tx_full_count = 0);
3905 * The NetXtreme II supports a linked-list structre called
3906 * a Buffer Descriptor Chain (or BD chain). A BD chain
3907 * consists of a series of 1 or more chain pages, each of which
3908 * consists of a fixed number of BD entries.
3909 * The last BD entry on each page is a pointer to the next page
3910 * in the chain, and the last pointer in the BD chain
3911 * points back to the beginning of the chain.
3914 /* Set the TX next pointer chain entries. */
3915 for (i = 0; i < TX_PAGES; i++) {
3918 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3920 /* Check if we've reached the last page. */
3921 if (i == (TX_PAGES - 1))
3926 txbd->tx_bd_haddr_hi =
3927 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3928 txbd->tx_bd_haddr_lo =
3929 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3931 bce_init_tx_context(sc);
3937 /****************************************************************************/
3938 /* Free memory and clear the TX data structures. */
3942 /****************************************************************************/
3944 bce_free_tx_chain(struct bce_softc *sc)
3948 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3950 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3951 for (i = 0; i < TOTAL_TX_BD; i++) {
3952 if (sc->tx_mbuf_ptr[i] != NULL) {
3953 bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3954 m_freem(sc->tx_mbuf_ptr[i]);
3955 sc->tx_mbuf_ptr[i] = NULL;
3956 DBRUNIF(1, sc->tx_mbuf_alloc--);
3960 /* Clear each TX chain page. */
3961 for (i = 0; i < TX_PAGES; i++)
3962 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3965 /* Check if we lost any mbufs in the process. */
3966 DBRUNIF((sc->tx_mbuf_alloc),
3967 if_printf(&sc->arpcom.ac_if,
3968 "%s(%d): Memory leak! "
3969 "Lost %d mbufs from tx chain!\n",
3970 __FILE__, __LINE__, sc->tx_mbuf_alloc));
3972 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3976 /****************************************************************************/
3977 /* Initialize the RX context memory. */
3981 /****************************************************************************/
3983 bce_init_rx_context(struct bce_softc *sc)
3987 /* Initialize the context ID for an L2 RX chain. */
3988 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3989 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3992 * Set the level for generating pause frames
3993 * when the number of available rx_bd's gets
3994 * too low (the low watermark) and the level
3995 * when pause frames can be stopped (the high
3998 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3999 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4000 uint32_t lo_water, hi_water;
4002 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4003 hi_water = USABLE_RX_BD / 4;
4005 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4006 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4010 else if (hi_water == 0)
4013 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4016 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4018 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4019 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4020 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4021 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4022 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4025 /* Point the hardware to the first page in the chain. */
4026 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4027 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4028 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4029 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4033 /****************************************************************************/
4034 /* Allocate memory and initialize the RX data structures. */
4037 /* 0 for success, positive value for failure. */
4038 /****************************************************************************/
4040 bce_init_rx_chain(struct bce_softc *sc)
4044 uint16_t prod, chain_prod;
4047 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4049 /* Initialize the RX producer and consumer indices. */
4052 sc->rx_prod_bseq = 0;
4053 sc->free_rx_bd = USABLE_RX_BD;
4054 sc->max_rx_bd = USABLE_RX_BD;
4055 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
4056 DBRUNIF(1, sc->rx_empty_count = 0);
4058 /* Initialize the RX next pointer chain entries. */
4059 for (i = 0; i < RX_PAGES; i++) {
4062 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4064 /* Check if we've reached the last page. */
4065 if (i == (RX_PAGES - 1))
4070 /* Setup the chain page pointers. */
4071 rxbd->rx_bd_haddr_hi =
4072 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4073 rxbd->rx_bd_haddr_lo =
4074 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4077 /* Allocate mbuf clusters for the rx_bd chain. */
4078 prod = prod_bseq = 0;
4079 while (prod < TOTAL_RX_BD) {
4080 chain_prod = RX_CHAIN_IDX(prod);
4081 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4082 if_printf(&sc->arpcom.ac_if,
4083 "Error filling RX chain: rx_bd[0x%04X]!\n",
4088 prod = NEXT_RX_BD(prod);
4091 /* Save the RX chain producer index. */
4093 sc->rx_prod_bseq = prod_bseq;
4095 /* Tell the chip about the waiting rx_bd's. */
4096 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4098 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4101 bce_init_rx_context(sc);
4107 /****************************************************************************/
4108 /* Free memory and clear the RX data structures. */
4112 /****************************************************************************/
4114 bce_free_rx_chain(struct bce_softc *sc)
4118 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4120 /* Free any mbufs still in the RX mbuf chain. */
4121 for (i = 0; i < TOTAL_RX_BD; i++) {
4122 if (sc->rx_mbuf_ptr[i] != NULL) {
4123 bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4124 m_freem(sc->rx_mbuf_ptr[i]);
4125 sc->rx_mbuf_ptr[i] = NULL;
4126 DBRUNIF(1, sc->rx_mbuf_alloc--);
4130 /* Clear each RX chain page. */
4131 for (i = 0; i < RX_PAGES; i++)
4132 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4134 /* Check if we lost any mbufs in the process. */
4135 DBRUNIF((sc->rx_mbuf_alloc),
4136 if_printf(&sc->arpcom.ac_if,
4137 "%s(%d): Memory leak! "
4138 "Lost %d mbufs from rx chain!\n",
4139 __FILE__, __LINE__, sc->rx_mbuf_alloc));
4141 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4145 /****************************************************************************/
4146 /* Set media options. */
4149 /* 0 for success, positive value for failure. */
4150 /****************************************************************************/
4152 bce_ifmedia_upd(struct ifnet *ifp)
4154 struct bce_softc *sc = ifp->if_softc;
4155 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4159 * 'mii' will be NULL, when this function is called on following
4160 * code path: bce_attach() -> bce_mgmt_init()
4163 /* Make sure the MII bus has been enumerated. */
4165 if (mii->mii_instance) {
4166 struct mii_softc *miisc;
4168 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4169 mii_phy_reset(miisc);
4171 error = mii_mediachg(mii);
4177 /****************************************************************************/
4178 /* Reports current media status. */
4182 /****************************************************************************/
4184 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4186 struct bce_softc *sc = ifp->if_softc;
4187 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4190 ifmr->ifm_active = mii->mii_media_active;
4191 ifmr->ifm_status = mii->mii_media_status;
4195 /****************************************************************************/
4196 /* Handles PHY generated interrupt events. */
4200 /****************************************************************************/
4202 bce_phy_intr(struct bce_softc *sc)
4204 uint32_t new_link_state, old_link_state;
4205 struct ifnet *ifp = &sc->arpcom.ac_if;
4207 ASSERT_SERIALIZED(ifp->if_serializer);
4209 new_link_state = sc->status_block->status_attn_bits &
4210 STATUS_ATTN_BITS_LINK_STATE;
4211 old_link_state = sc->status_block->status_attn_bits_ack &
4212 STATUS_ATTN_BITS_LINK_STATE;
4214 /* Handle any changes if the link state has changed. */
4215 if (new_link_state != old_link_state) { /* XXX redundant? */
4216 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4218 /* Update the status_attn_bits_ack field in the status block. */
4219 if (new_link_state) {
4220 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4221 STATUS_ATTN_BITS_LINK_STATE);
4223 if_printf(ifp, "Link is now UP.\n");
4225 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4226 STATUS_ATTN_BITS_LINK_STATE);
4228 if_printf(ifp, "Link is now DOWN.\n");
4232 * Assume link is down and allow tick routine to
4233 * update the state based on the actual media state.
4236 callout_stop(&sc->bce_tick_callout);
4237 bce_tick_serialized(sc);
4240 /* Acknowledge the link change interrupt. */
4241 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4245 /****************************************************************************/
4246 /* Reads the receive consumer value from the status block (skipping over */
4247 /* chain page pointer if necessary). */
4251 /****************************************************************************/
4252 static __inline uint16_t
4253 bce_get_hw_rx_cons(struct bce_softc *sc)
4255 uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4257 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4263 /****************************************************************************/
4264 /* Handles received frame interrupt events. */
4268 /****************************************************************************/
4270 bce_rx_intr(struct bce_softc *sc, int count)
4272 struct ifnet *ifp = &sc->arpcom.ac_if;
4273 uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4274 uint32_t sw_prod_bseq;
4275 struct mbuf_chain chain[MAXCPU];
4277 ASSERT_SERIALIZED(ifp->if_serializer);
4279 ether_input_chain_init(chain);
4281 DBRUNIF(1, sc->rx_interrupts++);
4283 /* Get the hardware's view of the RX consumer index. */
4284 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4286 /* Get working copies of the driver's view of the RX indices. */
4287 sw_cons = sc->rx_cons;
4288 sw_prod = sc->rx_prod;
4289 sw_prod_bseq = sc->rx_prod_bseq;
4291 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4292 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4293 __func__, sw_prod, sw_cons, sw_prod_bseq);
4295 /* Prevent speculative reads from getting ahead of the status block. */
4296 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4297 BUS_SPACE_BARRIER_READ);
4299 /* Update some debug statistics counters */
4300 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4301 sc->rx_low_watermark = sc->free_rx_bd);
4302 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4304 /* Scan through the receive chain as long as there is work to do. */
4305 while (sw_cons != hw_cons) {
4306 struct mbuf *m = NULL;
4307 struct l2_fhdr *l2fhdr = NULL;
4310 uint32_t status = 0;
4312 #ifdef DEVICE_POLLING
4313 if (count >= 0 && count-- == 0) {
4314 sc->hw_rx_cons = sw_cons;
4320 * Convert the producer/consumer indices
4321 * to an actual rx_bd index.
4323 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
4324 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
4326 /* Get the used rx_bd. */
4327 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4328 [RX_IDX(sw_chain_cons)];
4331 DBRUN(BCE_VERBOSE_RECV,
4332 if_printf(ifp, "%s(): ", __func__);
4333 bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4335 /* The mbuf is stored with the last rx_bd entry of a packet. */
4336 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4337 /* Validate that this is the last rx_bd. */
4338 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4339 if_printf(ifp, "%s(%d): "
4340 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4341 __FILE__, __LINE__, sw_chain_cons);
4342 bce_breakpoint(sc));
4344 if (sw_chain_cons != sw_chain_prod) {
4345 if_printf(ifp, "RX cons(%d) != prod(%d), "
4346 "drop!\n", sw_chain_cons,
4350 bce_setup_rxdesc_std(sc, sw_chain_cons,
4353 goto bce_rx_int_next_rx;
4356 /* Unmap the mbuf from DMA space. */
4357 bus_dmamap_sync(sc->rx_mbuf_tag,
4358 sc->rx_mbuf_map[sw_chain_cons],
4359 BUS_DMASYNC_POSTREAD);
4361 /* Save the mbuf from the driver's chain. */
4362 m = sc->rx_mbuf_ptr[sw_chain_cons];
4365 * Frames received on the NetXteme II are prepended
4366 * with an l2_fhdr structure which provides status
4367 * information about the received frame (including
4368 * VLAN tags and checksum info). The frames are also
4369 * automatically adjusted to align the IP header
4370 * (i.e. two null bytes are inserted before the
4371 * Ethernet header). As a result the data DMA'd by
4372 * the controller into the mbuf is as follows:
4374 * +---------+-----+---------------------+-----+
4375 * | l2_fhdr | pad | packet data | FCS |
4376 * +---------+-----+---------------------+-----+
4378 * The l2_fhdr needs to be checked and skipped and the
4379 * FCS needs to be stripped before sending the packet
4382 l2fhdr = mtod(m, struct l2_fhdr *);
4384 len = l2fhdr->l2_fhdr_pkt_len;
4385 status = l2fhdr->l2_fhdr_status;
4387 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4389 "Simulating l2_fhdr status error.\n");
4390 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4392 /* Watch for unusual sized frames. */
4393 DBRUNIF((len < BCE_MIN_MTU ||
4394 len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4396 "%s(%d): Unusual frame size found. "
4397 "Min(%d), Actual(%d), Max(%d)\n",
4399 (int)BCE_MIN_MTU, len,
4400 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4401 bce_dump_mbuf(sc, m);
4402 bce_breakpoint(sc));
4404 len -= ETHER_CRC_LEN;
4406 /* Check the received frame for errors. */
4407 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4408 L2_FHDR_ERRORS_PHY_DECODE |
4409 L2_FHDR_ERRORS_ALIGNMENT |
4410 L2_FHDR_ERRORS_TOO_SHORT |
4411 L2_FHDR_ERRORS_GIANT_FRAME)) {
4413 DBRUNIF(1, sc->l2fhdr_status_errors++);
4415 /* Reuse the mbuf for a new frame. */
4416 bce_setup_rxdesc_std(sc, sw_chain_prod,
4419 goto bce_rx_int_next_rx;
4423 * Get a new mbuf for the rx_bd. If no new
4424 * mbufs are available then reuse the current mbuf,
4425 * log an ierror on the interface, and generate
4426 * an error in the system log.
4428 if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4429 &sw_prod_bseq, 0)) {
4432 "%s(%d): Failed to allocate new mbuf, "
4433 "incoming frame dropped!\n",
4434 __FILE__, __LINE__));
4438 /* Try and reuse the exisitng mbuf. */
4439 bce_setup_rxdesc_std(sc, sw_chain_prod,
4442 goto bce_rx_int_next_rx;
4446 * Skip over the l2_fhdr when passing
4447 * the data up the stack.
4449 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4451 m->m_pkthdr.len = m->m_len = len;
4452 m->m_pkthdr.rcvif = ifp;
4454 DBRUN(BCE_VERBOSE_RECV,
4455 struct ether_header *eh;
4456 eh = mtod(m, struct ether_header *);
4457 if_printf(ifp, "%s(): to: %6D, from: %6D, "
4458 "type: 0x%04X\n", __func__,
4459 eh->ether_dhost, ":",
4460 eh->ether_shost, ":",
4461 htons(eh->ether_type)));
4463 /* Validate the checksum if offload enabled. */
4464 if (ifp->if_capenable & IFCAP_RXCSUM) {
4465 /* Check for an IP datagram. */
4466 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4467 m->m_pkthdr.csum_flags |=
4470 /* Check if the IP checksum is valid. */
4471 if ((l2fhdr->l2_fhdr_ip_xsum ^
4473 m->m_pkthdr.csum_flags |=
4476 DBPRINT(sc, BCE_WARN_RECV,
4477 "%s(): Invalid IP checksum = 0x%04X!\n",
4478 __func__, l2fhdr->l2_fhdr_ip_xsum);
4482 /* Check for a valid TCP/UDP frame. */
4483 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4484 L2_FHDR_STATUS_UDP_DATAGRAM)) {
4486 /* Check for a good TCP/UDP checksum. */
4488 (L2_FHDR_ERRORS_TCP_XSUM |
4489 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4490 m->m_pkthdr.csum_data =
4491 l2fhdr->l2_fhdr_tcp_udp_xsum;
4492 m->m_pkthdr.csum_flags |=
4496 DBPRINT(sc, BCE_WARN_RECV,
4497 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4498 __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4505 sw_prod = NEXT_RX_BD(sw_prod);
4508 sw_cons = NEXT_RX_BD(sw_cons);
4510 /* If we have a packet, pass it up the stack */
4512 DBPRINT(sc, BCE_VERBOSE_RECV,
4513 "%s(): Passing received frame up.\n", __func__);
4515 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4516 m->m_flags |= M_VLANTAG;
4517 m->m_pkthdr.ether_vlantag =
4518 l2fhdr->l2_fhdr_vlan_tag;
4520 ether_input_chain(ifp, m, NULL, chain);
4522 DBRUNIF(1, sc->rx_mbuf_alloc--);
4526 * If polling(4) is not enabled, refresh hw_cons to see
4527 * whether there's new work.
4529 * If polling(4) is enabled, i.e count >= 0, refreshing
4530 * should not be performed, so that we would not spend
4531 * too much time in RX processing.
4533 if (count < 0 && sw_cons == hw_cons)
4534 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4537 * Prevent speculative reads from getting ahead
4538 * of the status block.
4540 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4541 BUS_SPACE_BARRIER_READ);
4544 ether_input_dispatch(chain);
4546 sc->rx_cons = sw_cons;
4547 sc->rx_prod = sw_prod;
4548 sc->rx_prod_bseq = sw_prod_bseq;
4550 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4552 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4555 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4556 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4557 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4561 /****************************************************************************/
4562 /* Reads the transmit consumer value from the status block (skipping over */
4563 /* chain page pointer if necessary). */
4567 /****************************************************************************/
4568 static __inline uint16_t
4569 bce_get_hw_tx_cons(struct bce_softc *sc)
4571 uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4573 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4579 /****************************************************************************/
4580 /* Handles transmit completion interrupt events. */
4584 /****************************************************************************/
4586 bce_tx_intr(struct bce_softc *sc)
4588 struct ifnet *ifp = &sc->arpcom.ac_if;
4589 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4591 ASSERT_SERIALIZED(ifp->if_serializer);
4593 DBRUNIF(1, sc->tx_interrupts++);
4595 /* Get the hardware's view of the TX consumer index. */
4596 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4597 sw_tx_cons = sc->tx_cons;
4599 /* Prevent speculative reads from getting ahead of the status block. */
4600 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4601 BUS_SPACE_BARRIER_READ);
4603 /* Cycle through any completed TX chain page entries. */
4604 while (sw_tx_cons != hw_tx_cons) {
4606 struct tx_bd *txbd = NULL;
4608 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4610 DBPRINT(sc, BCE_INFO_SEND,
4611 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4612 "sw_tx_chain_cons = 0x%04X\n",
4613 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4615 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4616 if_printf(ifp, "%s(%d): "
4617 "TX chain consumer out of range! "
4618 " 0x%04X > 0x%04X\n",
4619 __FILE__, __LINE__, sw_tx_chain_cons,
4621 bce_breakpoint(sc));
4623 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4624 [TX_IDX(sw_tx_chain_cons)]);
4626 DBRUNIF((txbd == NULL),
4627 if_printf(ifp, "%s(%d): "
4628 "Unexpected NULL tx_bd[0x%04X]!\n",
4629 __FILE__, __LINE__, sw_tx_chain_cons);
4630 bce_breakpoint(sc));
4632 DBRUN(BCE_INFO_SEND,
4633 if_printf(ifp, "%s(): ", __func__);
4634 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4637 * Free the associated mbuf. Remember
4638 * that only the last tx_bd of a packet
4639 * has an mbuf pointer and DMA map.
4641 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4642 /* Validate that this is the last tx_bd. */
4643 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4644 if_printf(ifp, "%s(%d): "
4645 "tx_bd END flag not set but "
4646 "txmbuf == NULL!\n", __FILE__, __LINE__);
4647 bce_breakpoint(sc));
4649 DBRUN(BCE_INFO_SEND,
4650 if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4651 "from tx_bd[0x%04X]\n", __func__,
4654 /* Unmap the mbuf. */
4655 bus_dmamap_unload(sc->tx_mbuf_tag,
4656 sc->tx_mbuf_map[sw_tx_chain_cons]);
4658 /* Free the mbuf. */
4659 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4660 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4661 DBRUNIF(1, sc->tx_mbuf_alloc--);
4667 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4669 if (sw_tx_cons == hw_tx_cons) {
4670 /* Refresh hw_cons to see if there's new work. */
4671 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4675 * Prevent speculative reads from getting
4676 * ahead of the status block.
4678 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4679 BUS_SPACE_BARRIER_READ);
4682 if (sc->used_tx_bd == 0) {
4683 /* Clear the TX timeout timer. */
4687 /* Clear the tx hardware queue full flag. */
4688 if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4689 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4690 DBPRINT(sc, BCE_WARN_SEND,
4691 "%s(): Open TX chain! %d/%d (used/total)\n",
4692 __func__, sc->used_tx_bd, sc->max_tx_bd));
4693 ifp->if_flags &= ~IFF_OACTIVE;
4695 sc->tx_cons = sw_tx_cons;
4699 /****************************************************************************/
4700 /* Disables interrupt generation. */
4704 /****************************************************************************/
4706 bce_disable_intr(struct bce_softc *sc)
4708 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4709 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4710 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4714 /****************************************************************************/
4715 /* Enables interrupt generation. */
4719 /****************************************************************************/
4721 bce_enable_intr(struct bce_softc *sc, int coal_now)
4723 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4725 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4726 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4727 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4729 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4730 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4733 REG_WR(sc, BCE_HC_COMMAND,
4734 sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4739 /****************************************************************************/
4740 /* Handles controller initialization. */
4744 /****************************************************************************/
4748 struct bce_softc *sc = xsc;
4749 struct ifnet *ifp = &sc->arpcom.ac_if;
4753 ASSERT_SERIALIZED(ifp->if_serializer);
4755 /* Check if the driver is still running and bail out if it is. */
4756 if (ifp->if_flags & IFF_RUNNING)
4761 error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4763 if_printf(ifp, "Controller reset failed!\n");
4767 error = bce_chipinit(sc);
4769 if_printf(ifp, "Controller initialization failed!\n");
4773 error = bce_blockinit(sc);
4775 if_printf(ifp, "Block initialization failed!\n");
4779 /* Load our MAC address. */
4780 bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4781 bce_set_mac_addr(sc);
4783 /* Calculate and program the Ethernet MTU size. */
4784 ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4786 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4789 * Program the mtu, enabling jumbo frame
4790 * support if necessary. Also set the mbuf
4791 * allocation count for RX frames.
4793 if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4795 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4796 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4797 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4798 sc->mbuf_alloc_size = MJUM9BYTES;
4800 panic("jumbo buffer is not supported yet\n");
4803 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4804 sc->mbuf_alloc_size = MCLBYTES;
4807 /* Calculate the RX Ethernet frame size for rx_bd's. */
4808 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4810 DBPRINT(sc, BCE_INFO,
4811 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4812 "max_frame_size = %d\n",
4813 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4814 sc->max_frame_size);
4816 /* Program appropriate promiscuous/multicast filtering. */
4817 bce_set_rx_mode(sc);
4819 /* Init RX buffer descriptor chain. */
4820 bce_init_rx_chain(sc); /* XXX return value */
4822 /* Init TX buffer descriptor chain. */
4823 bce_init_tx_chain(sc); /* XXX return value */
4825 #ifdef DEVICE_POLLING
4826 /* Disable interrupts if we are polling. */
4827 if (ifp->if_flags & IFF_POLLING) {
4828 bce_disable_intr(sc);
4830 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4831 (1 << 16) | sc->bce_rx_quick_cons_trip);
4832 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4833 (1 << 16) | sc->bce_tx_quick_cons_trip);
4836 /* Enable host interrupts. */
4837 bce_enable_intr(sc, 1);
4839 bce_ifmedia_upd(ifp);
4841 ifp->if_flags |= IFF_RUNNING;
4842 ifp->if_flags &= ~IFF_OACTIVE;
4844 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4851 /****************************************************************************/
4852 /* Initialize the controller just enough so that any management firmware */
4853 /* running on the device will continue to operate corectly. */
4857 /****************************************************************************/
4859 bce_mgmt_init(struct bce_softc *sc)
4861 struct ifnet *ifp = &sc->arpcom.ac_if;
4863 /* Bail out if management firmware is not running. */
4864 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4867 /* Enable all critical blocks in the MAC. */
4868 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4869 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4870 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4871 BCE_MISC_ENABLE_DEFAULT_XI);
4873 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4875 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4878 bce_ifmedia_upd(ifp);
4882 /****************************************************************************/
4883 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4884 /* memory visible to the controller. */
4887 /* 0 for success, positive value for failure. */
4888 /****************************************************************************/
4890 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4892 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4893 bus_dmamap_t map, tmp_map;
4894 struct mbuf *m0 = *m_head;
4895 struct tx_bd *txbd = NULL;
4896 uint16_t vlan_tag = 0, flags = 0;
4897 uint16_t chain_prod, chain_prod_start, prod;
4899 int i, error, maxsegs, nsegs;
4901 uint16_t debug_prod;
4904 /* Transfer any checksum offload flags to the bd. */
4905 if (m0->m_pkthdr.csum_flags) {
4906 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4907 flags |= TX_BD_FLAGS_IP_CKSUM;
4908 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4909 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4912 /* Transfer any VLAN tags to the bd. */
4913 if (m0->m_flags & M_VLANTAG) {
4914 flags |= TX_BD_FLAGS_VLAN_TAG;
4915 vlan_tag = m0->m_pkthdr.ether_vlantag;
4919 chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4921 /* Map the mbuf into DMAable memory. */
4922 map = sc->tx_mbuf_map[chain_prod_start];
4924 maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4925 KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4926 ("not enough segements %d\n", maxsegs));
4927 if (maxsegs > BCE_MAX_SEGMENTS)
4928 maxsegs = BCE_MAX_SEGMENTS;
4930 /* Map the mbuf into our DMA address space. */
4931 error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4932 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4935 bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4940 /* prod points to an empty tx_bd at this point. */
4941 prod_bseq = sc->tx_prod_bseq;
4944 debug_prod = chain_prod;
4947 DBPRINT(sc, BCE_INFO_SEND,
4948 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4949 "prod_bseq = 0x%08X\n",
4950 __func__, prod, chain_prod, prod_bseq);
4953 * Cycle through each mbuf segment that makes up
4954 * the outgoing frame, gathering the mapping info
4955 * for that segment and creating a tx_bd to for
4958 for (i = 0; i < nsegs; i++) {
4959 chain_prod = TX_CHAIN_IDX(prod);
4960 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4962 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4963 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4964 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4965 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4966 txbd->tx_bd_flags = htole16(flags);
4967 prod_bseq += segs[i].ds_len;
4969 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4970 prod = NEXT_TX_BD(prod);
4973 /* Set the END flag on the last TX buffer descriptor. */
4974 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4976 DBRUN(BCE_EXCESSIVE_SEND,
4977 bce_dump_tx_chain(sc, debug_prod, nsegs));
4979 DBPRINT(sc, BCE_INFO_SEND,
4980 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4981 "prod_bseq = 0x%08X\n",
4982 __func__, prod, chain_prod, prod_bseq);
4985 * Ensure that the mbuf pointer for this transmission
4986 * is placed at the array index of the last
4987 * descriptor in this chain. This is done
4988 * because a single map is used for all
4989 * segments of the mbuf and we don't want to
4990 * unload the map before all of the segments
4993 sc->tx_mbuf_ptr[chain_prod] = m0;
4995 tmp_map = sc->tx_mbuf_map[chain_prod];
4996 sc->tx_mbuf_map[chain_prod] = map;
4997 sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4999 sc->used_tx_bd += nsegs;
5001 /* Update some debug statistic counters */
5002 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
5003 sc->tx_hi_watermark = sc->used_tx_bd);
5004 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
5005 DBRUNIF(1, sc->tx_mbuf_alloc++);
5007 DBRUN(BCE_VERBOSE_SEND,
5008 bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
5010 /* prod points to the next free tx_bd at this point. */
5012 sc->tx_prod_bseq = prod_bseq;
5022 /****************************************************************************/
5023 /* Main transmit routine when called from another routine with a lock. */
5027 /****************************************************************************/
5029 bce_start(struct ifnet *ifp)
5031 struct bce_softc *sc = ifp->if_softc;
5034 ASSERT_SERIALIZED(ifp->if_serializer);
5036 /* If there's no link or the transmit queue is empty then just exit. */
5037 if (!sc->bce_link) {
5038 ifq_purge(&ifp->if_snd);
5042 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
5045 DBPRINT(sc, BCE_INFO_SEND,
5046 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
5047 "tx_prod_bseq = 0x%08X\n",
5049 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5052 struct mbuf *m_head;
5055 * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
5058 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
5059 ifp->if_flags |= IFF_OACTIVE;
5063 /* Check for any frames to send. */
5064 m_head = ifq_dequeue(&ifp->if_snd, NULL);
5069 * Pack the data into the transmit ring. If we
5070 * don't have room, place the mbuf back at the
5071 * head of the queue and set the OACTIVE flag
5072 * to wait for the NIC to drain the chain.
5074 if (bce_encap(sc, &m_head)) {
5076 if (sc->used_tx_bd == 0) {
5079 ifp->if_flags |= IFF_OACTIVE;
5086 /* Send a copy of the frame to any BPF listeners. */
5087 ETHER_BPF_MTAP(ifp, m_head);
5091 /* no packets were dequeued */
5092 DBPRINT(sc, BCE_VERBOSE_SEND,
5093 "%s(): No packets were dequeued\n", __func__);
5097 DBPRINT(sc, BCE_INFO_SEND,
5098 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
5099 "tx_prod_bseq = 0x%08X\n",
5101 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5103 REG_WR(sc, BCE_MQ_COMMAND,
5104 REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5106 /* Start the transmit. */
5107 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5108 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5110 /* Set the tx timeout. */
5111 ifp->if_timer = BCE_TX_TIMEOUT;
5115 /****************************************************************************/
5116 /* Handles any IOCTL calls from the operating system. */
5119 /* 0 for success, positive value for failure. */
5120 /****************************************************************************/
5122 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5124 struct bce_softc *sc = ifp->if_softc;
5125 struct ifreq *ifr = (struct ifreq *)data;
5126 struct mii_data *mii;
5127 int mask, error = 0;
5129 ASSERT_SERIALIZED(ifp->if_serializer);
5133 /* Check that the MTU setting is supported. */
5134 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5136 ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5138 ifr->ifr_mtu > ETHERMTU
5145 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5147 ifp->if_mtu = ifr->ifr_mtu;
5148 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5153 if (ifp->if_flags & IFF_UP) {
5154 if (ifp->if_flags & IFF_RUNNING) {
5155 mask = ifp->if_flags ^ sc->bce_if_flags;
5157 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5158 bce_set_rx_mode(sc);
5162 } else if (ifp->if_flags & IFF_RUNNING) {
5165 /* If MFW is running, restart the controller a bit. */
5166 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5167 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5172 sc->bce_if_flags = ifp->if_flags;
5177 if (ifp->if_flags & IFF_RUNNING)
5178 bce_set_rx_mode(sc);
5183 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5185 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5187 mii = device_get_softc(sc->bce_miibus);
5188 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5192 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5193 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5196 if (mask & IFCAP_HWCSUM) {
5197 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5198 if (IFCAP_HWCSUM & ifp->if_capenable)
5199 ifp->if_hwassist = BCE_IF_HWASSIST;
5201 ifp->if_hwassist = 0;
5206 error = ether_ioctl(ifp, command, data);
5213 /****************************************************************************/
5214 /* Transmit timeout handler. */
5218 /****************************************************************************/
5220 bce_watchdog(struct ifnet *ifp)
5222 struct bce_softc *sc = ifp->if_softc;
5224 ASSERT_SERIALIZED(ifp->if_serializer);
5226 DBRUN(BCE_VERBOSE_SEND,
5227 bce_dump_driver_state(sc);
5228 bce_dump_status_block(sc));
5231 * If we are in this routine because of pause frames, then
5232 * don't reset the hardware.
5234 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5237 if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5239 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5241 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5246 if (!ifq_is_empty(&ifp->if_snd))
5251 #ifdef DEVICE_POLLING
5254 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5256 struct bce_softc *sc = ifp->if_softc;
5257 struct status_block *sblk = sc->status_block;
5258 uint16_t hw_tx_cons, hw_rx_cons;
5260 ASSERT_SERIALIZED(ifp->if_serializer);
5264 bce_disable_intr(sc);
5266 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5267 (1 << 16) | sc->bce_rx_quick_cons_trip);
5268 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5269 (1 << 16) | sc->bce_tx_quick_cons_trip);
5271 case POLL_DEREGISTER:
5272 bce_enable_intr(sc, 1);
5274 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5275 (sc->bce_tx_quick_cons_trip_int << 16) |
5276 sc->bce_tx_quick_cons_trip);
5277 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5278 (sc->bce_rx_quick_cons_trip_int << 16) |
5279 sc->bce_rx_quick_cons_trip);
5285 if (cmd == POLL_AND_CHECK_STATUS) {
5286 uint32_t status_attn_bits;
5288 status_attn_bits = sblk->status_attn_bits;
5290 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5292 "Simulating unexpected status attention bit set.");
5293 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5295 /* Was it a link change interrupt? */
5296 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5297 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5300 /* Clear any transient status updates during link state change. */
5301 REG_WR(sc, BCE_HC_COMMAND,
5302 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5303 REG_RD(sc, BCE_HC_COMMAND);
5306 * If any other attention is asserted then
5307 * the chip is toast.
5309 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5310 (sblk->status_attn_bits_ack &
5311 ~STATUS_ATTN_BITS_LINK_STATE)) {
5312 DBRUN(1, sc->unexpected_attentions++);
5314 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5315 sblk->status_attn_bits);
5318 if (bce_debug_unexpected_attention == 0)
5319 bce_breakpoint(sc));
5326 hw_rx_cons = bce_get_hw_rx_cons(sc);
5327 hw_tx_cons = bce_get_hw_tx_cons(sc);
5329 /* Check for any completed RX frames. */
5330 if (hw_rx_cons != sc->hw_rx_cons)
5331 bce_rx_intr(sc, count);
5333 /* Check for any completed TX frames. */
5334 if (hw_tx_cons != sc->hw_tx_cons)
5337 /* Check for new frames to transmit. */
5338 if (!ifq_is_empty(&ifp->if_snd))
5342 #endif /* DEVICE_POLLING */
5346 * Interrupt handler.
5348 /****************************************************************************/
5349 /* Main interrupt entry point. Verifies that the controller generated the */
5350 /* interrupt and then calls a separate routine for handle the various */
5351 /* interrupt causes (PHY, TX, RX). */
5354 /* 0 for success, positive value for failure. */
5355 /****************************************************************************/
5359 struct bce_softc *sc = xsc;
5360 struct ifnet *ifp = &sc->arpcom.ac_if;
5361 struct status_block *sblk;
5362 uint16_t hw_rx_cons, hw_tx_cons;
5364 ASSERT_SERIALIZED(ifp->if_serializer);
5366 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5367 DBRUNIF(1, sc->interrupts_generated++);
5369 sblk = sc->status_block;
5372 * If the hardware status block index matches the last value
5373 * read by the driver and we haven't asserted our interrupt
5374 * then there's nothing to do.
5376 if (sblk->status_idx == sc->last_status_idx &&
5377 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5378 BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5381 /* Ack the interrupt and stop others from occuring. */
5382 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5383 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5384 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5387 * Read back to deassert IRQ immediately to avoid too
5388 * many spurious interrupts.
5390 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5392 /* Check if the hardware has finished any work. */
5393 hw_rx_cons = bce_get_hw_rx_cons(sc);
5394 hw_tx_cons = bce_get_hw_tx_cons(sc);
5396 /* Keep processing data as long as there is work to do. */
5398 uint32_t status_attn_bits;
5400 status_attn_bits = sblk->status_attn_bits;
5402 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5404 "Simulating unexpected status attention bit set.");
5405 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5407 /* Was it a link change interrupt? */
5408 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5409 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5413 * Clear any transient status updates during link state
5416 REG_WR(sc, BCE_HC_COMMAND,
5417 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5418 REG_RD(sc, BCE_HC_COMMAND);
5422 * If any other attention is asserted then
5423 * the chip is toast.
5425 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5426 (sblk->status_attn_bits_ack &
5427 ~STATUS_ATTN_BITS_LINK_STATE)) {
5428 DBRUN(1, sc->unexpected_attentions++);
5430 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5431 sblk->status_attn_bits);
5434 if (bce_debug_unexpected_attention == 0)
5435 bce_breakpoint(sc));
5441 /* Check for any completed RX frames. */
5442 if (hw_rx_cons != sc->hw_rx_cons)
5443 bce_rx_intr(sc, -1);
5445 /* Check for any completed TX frames. */
5446 if (hw_tx_cons != sc->hw_tx_cons)
5450 * Save the status block index value
5451 * for use during the next interrupt.
5453 sc->last_status_idx = sblk->status_idx;
5456 * Prevent speculative reads from getting
5457 * ahead of the status block.
5459 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5460 BUS_SPACE_BARRIER_READ);
5463 * If there's no work left then exit the
5464 * interrupt service routine.
5466 hw_rx_cons = bce_get_hw_rx_cons(sc);
5467 hw_tx_cons = bce_get_hw_tx_cons(sc);
5468 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5472 /* Re-enable interrupts. */
5473 bce_enable_intr(sc, 0);
5475 if (sc->bce_coalchg_mask)
5476 bce_coal_change(sc);
5478 /* Handle any frames that arrived while handling the interrupt. */
5479 if (!ifq_is_empty(&ifp->if_snd))
5484 /****************************************************************************/
5485 /* Programs the various packet receive modes (broadcast and multicast). */
5489 /****************************************************************************/
5491 bce_set_rx_mode(struct bce_softc *sc)
5493 struct ifnet *ifp = &sc->arpcom.ac_if;
5494 struct ifmultiaddr *ifma;
5495 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5496 uint32_t rx_mode, sort_mode;
5499 ASSERT_SERIALIZED(ifp->if_serializer);
5501 /* Initialize receive mode default settings. */
5502 rx_mode = sc->rx_mode &
5503 ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5504 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5505 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5508 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5511 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5512 !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5513 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5516 * Check for promiscuous, all multicast, or selected
5517 * multicast address filtering.
5519 if (ifp->if_flags & IFF_PROMISC) {
5520 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5522 /* Enable promiscuous mode. */
5523 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5524 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5525 } else if (ifp->if_flags & IFF_ALLMULTI) {
5526 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5528 /* Enable all multicast addresses. */
5529 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5530 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5533 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5535 /* Accept one or more multicast(s). */
5536 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5538 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5539 if (ifma->ifma_addr->sa_family != AF_LINK)
5542 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5543 ETHER_ADDR_LEN) & 0xFF;
5544 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5547 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5548 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5551 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5554 /* Only make changes if the recive mode has actually changed. */
5555 if (rx_mode != sc->rx_mode) {
5556 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5559 sc->rx_mode = rx_mode;
5560 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5563 /* Disable and clear the exisitng sort before enabling a new sort. */
5564 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5565 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5566 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5570 /****************************************************************************/
5571 /* Called periodically to updates statistics from the controllers */
5572 /* statistics block. */
5576 /****************************************************************************/
5578 bce_stats_update(struct bce_softc *sc)
5580 struct ifnet *ifp = &sc->arpcom.ac_if;
5581 struct statistics_block *stats = sc->stats_block;
5583 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5585 ASSERT_SERIALIZED(ifp->if_serializer);
5588 * Certain controllers don't report carrier sense errors correctly.
5589 * See errata E11_5708CA0_1165.
5591 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5592 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5594 (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5598 * Update the sysctl statistics from the hardware statistics.
5600 sc->stat_IfHCInOctets =
5601 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5602 (uint64_t)stats->stat_IfHCInOctets_lo;
5604 sc->stat_IfHCInBadOctets =
5605 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5606 (uint64_t)stats->stat_IfHCInBadOctets_lo;
5608 sc->stat_IfHCOutOctets =
5609 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5610 (uint64_t)stats->stat_IfHCOutOctets_lo;
5612 sc->stat_IfHCOutBadOctets =
5613 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5614 (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5616 sc->stat_IfHCInUcastPkts =
5617 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5618 (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5620 sc->stat_IfHCInMulticastPkts =
5621 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5622 (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5624 sc->stat_IfHCInBroadcastPkts =
5625 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5626 (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5628 sc->stat_IfHCOutUcastPkts =
5629 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5630 (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5632 sc->stat_IfHCOutMulticastPkts =
5633 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5634 (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5636 sc->stat_IfHCOutBroadcastPkts =
5637 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5638 (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5640 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5641 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5643 sc->stat_Dot3StatsCarrierSenseErrors =
5644 stats->stat_Dot3StatsCarrierSenseErrors;
5646 sc->stat_Dot3StatsFCSErrors =
5647 stats->stat_Dot3StatsFCSErrors;
5649 sc->stat_Dot3StatsAlignmentErrors =
5650 stats->stat_Dot3StatsAlignmentErrors;
5652 sc->stat_Dot3StatsSingleCollisionFrames =
5653 stats->stat_Dot3StatsSingleCollisionFrames;
5655 sc->stat_Dot3StatsMultipleCollisionFrames =
5656 stats->stat_Dot3StatsMultipleCollisionFrames;
5658 sc->stat_Dot3StatsDeferredTransmissions =
5659 stats->stat_Dot3StatsDeferredTransmissions;
5661 sc->stat_Dot3StatsExcessiveCollisions =
5662 stats->stat_Dot3StatsExcessiveCollisions;
5664 sc->stat_Dot3StatsLateCollisions =
5665 stats->stat_Dot3StatsLateCollisions;
5667 sc->stat_EtherStatsCollisions =
5668 stats->stat_EtherStatsCollisions;
5670 sc->stat_EtherStatsFragments =
5671 stats->stat_EtherStatsFragments;
5673 sc->stat_EtherStatsJabbers =
5674 stats->stat_EtherStatsJabbers;
5676 sc->stat_EtherStatsUndersizePkts =
5677 stats->stat_EtherStatsUndersizePkts;
5679 sc->stat_EtherStatsOverrsizePkts =
5680 stats->stat_EtherStatsOverrsizePkts;
5682 sc->stat_EtherStatsPktsRx64Octets =
5683 stats->stat_EtherStatsPktsRx64Octets;
5685 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5686 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5688 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5689 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5691 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5692 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5694 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5695 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5697 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5698 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5700 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5701 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5703 sc->stat_EtherStatsPktsTx64Octets =
5704 stats->stat_EtherStatsPktsTx64Octets;
5706 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5707 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5709 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5710 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5712 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5713 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5715 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5716 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5718 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5719 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5721 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5722 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5724 sc->stat_XonPauseFramesReceived =
5725 stats->stat_XonPauseFramesReceived;
5727 sc->stat_XoffPauseFramesReceived =
5728 stats->stat_XoffPauseFramesReceived;
5730 sc->stat_OutXonSent =
5731 stats->stat_OutXonSent;
5733 sc->stat_OutXoffSent =
5734 stats->stat_OutXoffSent;
5736 sc->stat_FlowControlDone =
5737 stats->stat_FlowControlDone;
5739 sc->stat_MacControlFramesReceived =
5740 stats->stat_MacControlFramesReceived;
5742 sc->stat_XoffStateEntered =
5743 stats->stat_XoffStateEntered;
5745 sc->stat_IfInFramesL2FilterDiscards =
5746 stats->stat_IfInFramesL2FilterDiscards;
5748 sc->stat_IfInRuleCheckerDiscards =
5749 stats->stat_IfInRuleCheckerDiscards;
5751 sc->stat_IfInFTQDiscards =
5752 stats->stat_IfInFTQDiscards;
5754 sc->stat_IfInMBUFDiscards =
5755 stats->stat_IfInMBUFDiscards;
5757 sc->stat_IfInRuleCheckerP4Hit =
5758 stats->stat_IfInRuleCheckerP4Hit;
5760 sc->stat_CatchupInRuleCheckerDiscards =
5761 stats->stat_CatchupInRuleCheckerDiscards;
5763 sc->stat_CatchupInFTQDiscards =
5764 stats->stat_CatchupInFTQDiscards;
5766 sc->stat_CatchupInMBUFDiscards =
5767 stats->stat_CatchupInMBUFDiscards;
5769 sc->stat_CatchupInRuleCheckerP4Hit =
5770 stats->stat_CatchupInRuleCheckerP4Hit;
5772 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5775 * Update the interface statistics from the
5776 * hardware statistics.
5778 ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5780 ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5781 (u_long)sc->stat_EtherStatsOverrsizePkts +
5782 (u_long)sc->stat_IfInMBUFDiscards +
5783 (u_long)sc->stat_Dot3StatsAlignmentErrors +
5784 (u_long)sc->stat_Dot3StatsFCSErrors +
5785 (u_long)sc->stat_IfInRuleCheckerDiscards +
5786 (u_long)sc->stat_IfInFTQDiscards +
5787 (u_long)sc->com_no_buffers;
5790 (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5791 (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5792 (u_long)sc->stat_Dot3StatsLateCollisions;
5794 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5798 /****************************************************************************/
5799 /* Periodic function to notify the bootcode that the driver is still */
5804 /****************************************************************************/
5806 bce_pulse(void *xsc)
5808 struct bce_softc *sc = xsc;
5809 struct ifnet *ifp = &sc->arpcom.ac_if;
5812 lwkt_serialize_enter(ifp->if_serializer);
5814 /* Tell the firmware that the driver is still running. */
5815 msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5816 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5818 /* Update the bootcode condition. */
5819 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5821 /* Report whether the bootcode still knows the driver is running. */
5822 if (!sc->bce_drv_cardiac_arrest) {
5823 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5824 sc->bce_drv_cardiac_arrest = 1;
5825 if_printf(ifp, "Bootcode lost the driver pulse! "
5826 "(bc_state = 0x%08X)\n", sc->bc_state);
5830 * Not supported by all bootcode versions.
5831 * (v5.0.11+ and v5.2.1+) Older bootcode
5832 * will require the driver to reset the
5833 * controller to clear this condition.
5835 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5836 sc->bce_drv_cardiac_arrest = 0;
5837 if_printf(ifp, "Bootcode found the driver pulse! "
5838 "(bc_state = 0x%08X)\n", sc->bc_state);
5842 /* Schedule the next pulse. */
5843 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5845 lwkt_serialize_exit(ifp->if_serializer);
5849 /****************************************************************************/
5850 /* Periodic function to perform maintenance tasks. */
5854 /****************************************************************************/
5856 bce_tick_serialized(struct bce_softc *sc)
5858 struct ifnet *ifp = &sc->arpcom.ac_if;
5859 struct mii_data *mii;
5861 ASSERT_SERIALIZED(ifp->if_serializer);
5863 /* Update the statistics from the hardware statistics block. */
5864 bce_stats_update(sc);
5866 /* Schedule the next tick. */
5867 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5869 /* If link is up already up then we're done. */
5873 mii = device_get_softc(sc->bce_miibus);
5876 /* Check if the link has come up. */
5877 if ((mii->mii_media_status & IFM_ACTIVE) &&
5878 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5880 /* Now that link is up, handle any outstanding TX traffic. */
5881 if (!ifq_is_empty(&ifp->if_snd))
5890 struct bce_softc *sc = xsc;
5891 struct ifnet *ifp = &sc->arpcom.ac_if;
5893 lwkt_serialize_enter(ifp->if_serializer);
5894 bce_tick_serialized(sc);
5895 lwkt_serialize_exit(ifp->if_serializer);
5900 /****************************************************************************/
5901 /* Allows the driver state to be dumped through the sysctl interface. */
5904 /* 0 for success, positive value for failure. */
5905 /****************************************************************************/
5907 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5911 struct bce_softc *sc;
5914 error = sysctl_handle_int(oidp, &result, 0, req);
5916 if (error || !req->newptr)
5920 sc = (struct bce_softc *)arg1;
5921 bce_dump_driver_state(sc);
5928 /****************************************************************************/
5929 /* Allows the hardware state to be dumped through the sysctl interface. */
5932 /* 0 for success, positive value for failure. */
5933 /****************************************************************************/
5935 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5939 struct bce_softc *sc;
5942 error = sysctl_handle_int(oidp, &result, 0, req);
5944 if (error || !req->newptr)
5948 sc = (struct bce_softc *)arg1;
5949 bce_dump_hw_state(sc);
5956 /****************************************************************************/
5957 /* Provides a sysctl interface to allows dumping the RX chain. */
5960 /* 0 for success, positive value for failure. */
5961 /****************************************************************************/
5963 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5967 struct bce_softc *sc;
5970 error = sysctl_handle_int(oidp, &result, 0, req);
5972 if (error || !req->newptr)
5976 sc = (struct bce_softc *)arg1;
5977 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5984 /****************************************************************************/
5985 /* Provides a sysctl interface to allows dumping the TX chain. */
5988 /* 0 for success, positive value for failure. */
5989 /****************************************************************************/
5991 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5995 struct bce_softc *sc;
5998 error = sysctl_handle_int(oidp, &result, 0, req);
6000 if (error || !req->newptr)
6004 sc = (struct bce_softc *)arg1;
6005 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
6012 /****************************************************************************/
6013 /* Provides a sysctl interface to allow reading arbitrary registers in the */
6014 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6017 /* 0 for success, positive value for failure. */
6018 /****************************************************************************/
6020 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6022 struct bce_softc *sc;
6024 uint32_t val, result;
6027 error = sysctl_handle_int(oidp, &result, 0, req);
6028 if (error || (req->newptr == NULL))
6031 /* Make sure the register is accessible. */
6032 if (result < 0x8000) {
6033 sc = (struct bce_softc *)arg1;
6034 val = REG_RD(sc, result);
6035 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6037 } else if (result < 0x0280000) {
6038 sc = (struct bce_softc *)arg1;
6039 val = REG_RD_IND(sc, result);
6040 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6047 /****************************************************************************/
6048 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
6049 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6052 /* 0 for success, positive value for failure. */
6053 /****************************************************************************/
6055 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6057 struct bce_softc *sc;
6063 error = sysctl_handle_int(oidp, &result, 0, req);
6064 if (error || (req->newptr == NULL))
6067 /* Make sure the register is accessible. */
6068 if (result < 0x20) {
6069 sc = (struct bce_softc *)arg1;
6071 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6072 if_printf(&sc->arpcom.ac_if,
6073 "phy 0x%02X = 0x%04X\n", result, val);
6079 /****************************************************************************/
6080 /* Provides a sysctl interface to forcing the driver to dump state and */
6081 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6084 /* 0 for success, positive value for failure. */
6085 /****************************************************************************/
6087 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6091 struct bce_softc *sc;
6094 error = sysctl_handle_int(oidp, &result, 0, req);
6096 if (error || !req->newptr)
6100 sc = (struct bce_softc *)arg1;
6109 /****************************************************************************/
6110 /* Adds any sysctl parameters for tuning or debugging purposes. */
6113 /* 0 for success, positive value for failure. */
6114 /****************************************************************************/
6116 bce_add_sysctls(struct bce_softc *sc)
6118 struct sysctl_ctx_list *ctx;
6119 struct sysctl_oid_list *children;
6121 sysctl_ctx_init(&sc->bce_sysctl_ctx);
6122 sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6123 SYSCTL_STATIC_CHILDREN(_hw),
6125 device_get_nameunit(sc->bce_dev),
6127 if (sc->bce_sysctl_tree == NULL) {
6128 device_printf(sc->bce_dev, "can't add sysctl node\n");
6132 ctx = &sc->bce_sysctl_ctx;
6133 children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6135 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6136 CTLTYPE_INT | CTLFLAG_RW,
6137 sc, 0, bce_sysctl_tx_bds_int, "I",
6138 "Send max coalesced BD count during interrupt");
6139 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6140 CTLTYPE_INT | CTLFLAG_RW,
6141 sc, 0, bce_sysctl_tx_bds, "I",
6142 "Send max coalesced BD count");
6143 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6144 CTLTYPE_INT | CTLFLAG_RW,
6145 sc, 0, bce_sysctl_tx_ticks_int, "I",
6146 "Send coalescing ticks during interrupt");
6147 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6148 CTLTYPE_INT | CTLFLAG_RW,
6149 sc, 0, bce_sysctl_tx_ticks, "I",
6150 "Send coalescing ticks");
6152 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6153 CTLTYPE_INT | CTLFLAG_RW,
6154 sc, 0, bce_sysctl_rx_bds_int, "I",
6155 "Receive max coalesced BD count during interrupt");
6156 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6157 CTLTYPE_INT | CTLFLAG_RW,
6158 sc, 0, bce_sysctl_rx_bds, "I",
6159 "Receive max coalesced BD count");
6160 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6161 CTLTYPE_INT | CTLFLAG_RW,
6162 sc, 0, bce_sysctl_rx_ticks_int, "I",
6163 "Receive coalescing ticks during interrupt");
6164 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6165 CTLTYPE_INT | CTLFLAG_RW,
6166 sc, 0, bce_sysctl_rx_ticks, "I",
6167 "Receive coalescing ticks");
6170 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6172 CTLFLAG_RD, &sc->rx_low_watermark,
6173 0, "Lowest level of free rx_bd's");
6175 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6177 CTLFLAG_RD, &sc->rx_empty_count,
6178 0, "Number of times the RX chain was empty");
6180 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6182 CTLFLAG_RD, &sc->tx_hi_watermark,
6183 0, "Highest level of used tx_bd's");
6185 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6187 CTLFLAG_RD, &sc->tx_full_count,
6188 0, "Number of times the TX chain was full");
6190 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6191 "l2fhdr_status_errors",
6192 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6193 0, "l2_fhdr status errors");
6195 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6196 "unexpected_attentions",
6197 CTLFLAG_RD, &sc->unexpected_attentions,
6198 0, "unexpected attentions");
6200 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6201 "lost_status_block_updates",
6202 CTLFLAG_RD, &sc->lost_status_block_updates,
6203 0, "lost status block updates");
6205 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6206 "mbuf_alloc_failed",
6207 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6208 0, "mbuf cluster allocation failures");
6211 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6212 "stat_IfHCInOctets",
6213 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6216 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6217 "stat_IfHCInBadOctets",
6218 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6219 "Bad bytes received");
6221 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6222 "stat_IfHCOutOctets",
6223 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6226 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6227 "stat_IfHCOutBadOctets",
6228 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6231 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6232 "stat_IfHCInUcastPkts",
6233 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6234 "Unicast packets received");
6236 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6237 "stat_IfHCInMulticastPkts",
6238 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6239 "Multicast packets received");
6241 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6242 "stat_IfHCInBroadcastPkts",
6243 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6244 "Broadcast packets received");
6246 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6247 "stat_IfHCOutUcastPkts",
6248 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6249 "Unicast packets sent");
6251 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6252 "stat_IfHCOutMulticastPkts",
6253 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6254 "Multicast packets sent");
6256 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6257 "stat_IfHCOutBroadcastPkts",
6258 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6259 "Broadcast packets sent");
6261 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6262 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6263 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6264 0, "Internal MAC transmit errors");
6266 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6267 "stat_Dot3StatsCarrierSenseErrors",
6268 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6269 0, "Carrier sense errors");
6271 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6272 "stat_Dot3StatsFCSErrors",
6273 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6274 0, "Frame check sequence errors");
6276 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6277 "stat_Dot3StatsAlignmentErrors",
6278 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6279 0, "Alignment errors");
6281 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6282 "stat_Dot3StatsSingleCollisionFrames",
6283 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6284 0, "Single Collision Frames");
6286 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6287 "stat_Dot3StatsMultipleCollisionFrames",
6288 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6289 0, "Multiple Collision Frames");
6291 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6292 "stat_Dot3StatsDeferredTransmissions",
6293 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6294 0, "Deferred Transmissions");
6296 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6297 "stat_Dot3StatsExcessiveCollisions",
6298 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6299 0, "Excessive Collisions");
6301 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6302 "stat_Dot3StatsLateCollisions",
6303 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6304 0, "Late Collisions");
6306 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6307 "stat_EtherStatsCollisions",
6308 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6311 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6312 "stat_EtherStatsFragments",
6313 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6316 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6317 "stat_EtherStatsJabbers",
6318 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6321 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6322 "stat_EtherStatsUndersizePkts",
6323 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6324 0, "Undersize packets");
6326 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6327 "stat_EtherStatsOverrsizePkts",
6328 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6329 0, "stat_EtherStatsOverrsizePkts");
6331 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6332 "stat_EtherStatsPktsRx64Octets",
6333 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6334 0, "Bytes received in 64 byte packets");
6336 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6337 "stat_EtherStatsPktsRx65Octetsto127Octets",
6338 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6339 0, "Bytes received in 65 to 127 byte packets");
6341 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6342 "stat_EtherStatsPktsRx128Octetsto255Octets",
6343 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6344 0, "Bytes received in 128 to 255 byte packets");
6346 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6347 "stat_EtherStatsPktsRx256Octetsto511Octets",
6348 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6349 0, "Bytes received in 256 to 511 byte packets");
6351 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6352 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6353 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6354 0, "Bytes received in 512 to 1023 byte packets");
6356 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6357 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6358 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6359 0, "Bytes received in 1024 t0 1522 byte packets");
6361 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6362 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6363 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6364 0, "Bytes received in 1523 to 9022 byte packets");
6366 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6367 "stat_EtherStatsPktsTx64Octets",
6368 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6369 0, "Bytes sent in 64 byte packets");
6371 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6372 "stat_EtherStatsPktsTx65Octetsto127Octets",
6373 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6374 0, "Bytes sent in 65 to 127 byte packets");
6376 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6377 "stat_EtherStatsPktsTx128Octetsto255Octets",
6378 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6379 0, "Bytes sent in 128 to 255 byte packets");
6381 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6382 "stat_EtherStatsPktsTx256Octetsto511Octets",
6383 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6384 0, "Bytes sent in 256 to 511 byte packets");
6386 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6387 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6388 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6389 0, "Bytes sent in 512 to 1023 byte packets");
6391 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6392 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6393 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6394 0, "Bytes sent in 1024 to 1522 byte packets");
6396 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6397 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6398 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6399 0, "Bytes sent in 1523 to 9022 byte packets");
6401 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6402 "stat_XonPauseFramesReceived",
6403 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6404 0, "XON pause frames receved");
6406 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6407 "stat_XoffPauseFramesReceived",
6408 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6409 0, "XOFF pause frames received");
6411 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6413 CTLFLAG_RD, &sc->stat_OutXonSent,
6414 0, "XON pause frames sent");
6416 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6418 CTLFLAG_RD, &sc->stat_OutXoffSent,
6419 0, "XOFF pause frames sent");
6421 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6422 "stat_FlowControlDone",
6423 CTLFLAG_RD, &sc->stat_FlowControlDone,
6424 0, "Flow control done");
6426 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6427 "stat_MacControlFramesReceived",
6428 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6429 0, "MAC control frames received");
6431 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6432 "stat_XoffStateEntered",
6433 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6434 0, "XOFF state entered");
6436 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6437 "stat_IfInFramesL2FilterDiscards",
6438 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6439 0, "Received L2 packets discarded");
6441 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6442 "stat_IfInRuleCheckerDiscards",
6443 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6444 0, "Received packets discarded by rule");
6446 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6447 "stat_IfInFTQDiscards",
6448 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6449 0, "Received packet FTQ discards");
6451 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6452 "stat_IfInMBUFDiscards",
6453 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6454 0, "Received packets discarded due to lack of controller buffer memory");
6456 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6457 "stat_IfInRuleCheckerP4Hit",
6458 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6459 0, "Received packets rule checker hits");
6461 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6462 "stat_CatchupInRuleCheckerDiscards",
6463 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6464 0, "Received packets discarded in Catchup path");
6466 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6467 "stat_CatchupInFTQDiscards",
6468 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6469 0, "Received packets discarded in FTQ in Catchup path");
6471 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6472 "stat_CatchupInMBUFDiscards",
6473 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6474 0, "Received packets discarded in controller buffer memory in Catchup path");
6476 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6477 "stat_CatchupInRuleCheckerP4Hit",
6478 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6479 0, "Received packets rule checker hits in Catchup path");
6481 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6483 CTLFLAG_RD, &sc->com_no_buffers,
6484 0, "Valid packets received but no RX buffers available");
6487 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6488 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6490 bce_sysctl_driver_state, "I", "Drive state information");
6492 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6493 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6495 bce_sysctl_hw_state, "I", "Hardware state information");
6497 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6498 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6500 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6502 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6503 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6505 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6507 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6508 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6510 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6512 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6513 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6515 bce_sysctl_reg_read, "I", "Register read");
6517 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6518 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6520 bce_sysctl_phy_read, "I", "PHY register read");
6527 /****************************************************************************/
6528 /* BCE Debug Routines */
6529 /****************************************************************************/
6532 /****************************************************************************/
6533 /* Freezes the controller to allow for a cohesive state dump. */
6537 /****************************************************************************/
6539 bce_freeze_controller(struct bce_softc *sc)
6543 val = REG_RD(sc, BCE_MISC_COMMAND);
6544 val |= BCE_MISC_COMMAND_DISABLE_ALL;
6545 REG_WR(sc, BCE_MISC_COMMAND, val);
6549 /****************************************************************************/
6550 /* Unfreezes the controller after a freeze operation. This may not always */
6551 /* work and the controller will require a reset! */
6555 /****************************************************************************/
6557 bce_unfreeze_controller(struct bce_softc *sc)
6561 val = REG_RD(sc, BCE_MISC_COMMAND);
6562 val |= BCE_MISC_COMMAND_ENABLE_ALL;
6563 REG_WR(sc, BCE_MISC_COMMAND, val);
6567 /****************************************************************************/
6568 /* Prints out information about an mbuf. */
6572 /****************************************************************************/
6574 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6576 struct ifnet *ifp = &sc->arpcom.ac_if;
6577 uint32_t val_hi, val_lo;
6578 struct mbuf *mp = m;
6581 /* Index out of range. */
6582 if_printf(ifp, "mbuf: null pointer\n");
6587 val_hi = BCE_ADDR_HI(mp);
6588 val_lo = BCE_ADDR_LO(mp);
6589 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6590 "m_flags = ( ", val_hi, val_lo, mp->m_len);
6592 if (mp->m_flags & M_EXT)
6594 if (mp->m_flags & M_PKTHDR)
6595 kprintf("M_PKTHDR ");
6596 if (mp->m_flags & M_EOR)
6599 if (mp->m_flags & M_RDONLY)
6600 kprintf("M_RDONLY ");
6603 val_hi = BCE_ADDR_HI(mp->m_data);
6604 val_lo = BCE_ADDR_LO(mp->m_data);
6605 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6607 if (mp->m_flags & M_PKTHDR) {
6608 if_printf(ifp, "- m_pkthdr: flags = ( ");
6609 if (mp->m_flags & M_BCAST)
6610 kprintf("M_BCAST ");
6611 if (mp->m_flags & M_MCAST)
6612 kprintf("M_MCAST ");
6613 if (mp->m_flags & M_FRAG)
6615 if (mp->m_flags & M_FIRSTFRAG)
6616 kprintf("M_FIRSTFRAG ");
6617 if (mp->m_flags & M_LASTFRAG)
6618 kprintf("M_LASTFRAG ");
6620 if (mp->m_flags & M_VLANTAG)
6621 kprintf("M_VLANTAG ");
6624 if (mp->m_flags & M_PROMISC)
6625 kprintf("M_PROMISC ");
6627 kprintf(") csum_flags = ( ");
6628 if (mp->m_pkthdr.csum_flags & CSUM_IP)
6629 kprintf("CSUM_IP ");
6630 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6631 kprintf("CSUM_TCP ");
6632 if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6633 kprintf("CSUM_UDP ");
6634 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6635 kprintf("CSUM_IP_FRAGS ");
6636 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6637 kprintf("CSUM_FRAGMENT ");
6639 if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6640 kprintf("CSUM_TSO ");
6642 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6643 kprintf("CSUM_IP_CHECKED ");
6644 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6645 kprintf("CSUM_IP_VALID ");
6646 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6647 kprintf("CSUM_DATA_VALID ");
6651 if (mp->m_flags & M_EXT) {
6652 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6653 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6654 if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6656 val_hi, val_lo, mp->m_ext.ext_size);
6663 /****************************************************************************/
6664 /* Prints out the mbufs in the TX mbuf chain. */
6668 /****************************************************************************/
6670 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6672 struct ifnet *ifp = &sc->arpcom.ac_if;
6676 "----------------------------"
6678 "----------------------------\n");
6680 for (i = 0; i < count; i++) {
6681 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6682 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6683 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6687 "----------------------------"
6689 "----------------------------\n");
6693 /****************************************************************************/
6694 /* Prints out the mbufs in the RX mbuf chain. */
6698 /****************************************************************************/
6700 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6702 struct ifnet *ifp = &sc->arpcom.ac_if;
6706 "----------------------------"
6708 "----------------------------\n");
6710 for (i = 0; i < count; i++) {
6711 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6712 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6713 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6717 "----------------------------"
6719 "----------------------------\n");
6723 /****************************************************************************/
6724 /* Prints out a tx_bd structure. */
6728 /****************************************************************************/
6730 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6732 struct ifnet *ifp = &sc->arpcom.ac_if;
6734 if (idx > MAX_TX_BD) {
6735 /* Index out of range. */
6736 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6737 } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6738 /* TX Chain page pointer. */
6739 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6740 "chain page pointer\n",
6741 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6743 /* Normal tx_bd entry. */
6744 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6746 "vlan tag= 0x%04X, flags = 0x%04X (",
6747 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6748 txbd->tx_bd_mss_nbytes,
6749 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6751 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6752 kprintf(" CONN_FAULT");
6754 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6755 kprintf(" TCP_UDP_CKSUM");
6757 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6758 kprintf(" IP_CKSUM");
6760 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6763 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6764 kprintf(" COAL_NOW");
6766 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6767 kprintf(" DONT_GEN_CRC");
6769 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6772 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6775 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6778 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6779 kprintf(" OPTION_WORD");
6781 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6784 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6792 /****************************************************************************/
6793 /* Prints out a rx_bd structure. */
6797 /****************************************************************************/
6799 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6801 struct ifnet *ifp = &sc->arpcom.ac_if;
6803 if (idx > MAX_RX_BD) {
6804 /* Index out of range. */
6805 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6806 } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6807 /* TX Chain page pointer. */
6808 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6809 "chain page pointer\n",
6810 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6812 /* Normal tx_bd entry. */
6813 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6814 "nbytes = 0x%08X, flags = 0x%08X\n",
6815 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6816 rxbd->rx_bd_len, rxbd->rx_bd_flags);
6821 /****************************************************************************/
6822 /* Prints out a l2_fhdr structure. */
6826 /****************************************************************************/
6828 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6830 if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6831 "pkt_len = 0x%04X, vlan = 0x%04x, "
6832 "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6833 idx, l2fhdr->l2_fhdr_status,
6834 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6835 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6839 /****************************************************************************/
6840 /* Prints out the tx chain. */
6844 /****************************************************************************/
6846 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6848 struct ifnet *ifp = &sc->arpcom.ac_if;
6851 /* First some info about the tx_bd chain structure. */
6853 "----------------------------"
6855 "----------------------------\n");
6857 if_printf(ifp, "page size = 0x%08X, "
6858 "tx chain pages = 0x%08X\n",
6859 (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6861 if_printf(ifp, "tx_bd per page = 0x%08X, "
6862 "usable tx_bd per page = 0x%08X\n",
6863 (uint32_t)TOTAL_TX_BD_PER_PAGE,
6864 (uint32_t)USABLE_TX_BD_PER_PAGE);
6866 if_printf(ifp, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6869 "----------------------------"
6871 "----------------------------\n");
6873 /* Now print out the tx_bd's themselves. */
6874 for (i = 0; i < count; i++) {
6877 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6878 bce_dump_txbd(sc, tx_prod, txbd);
6879 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6883 "----------------------------"
6885 "----------------------------\n");
6889 /****************************************************************************/
6890 /* Prints out the rx chain. */
6894 /****************************************************************************/
6896 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6898 struct ifnet *ifp = &sc->arpcom.ac_if;
6901 /* First some info about the tx_bd chain structure. */
6903 "----------------------------"
6905 "----------------------------\n");
6907 if_printf(ifp, "page size = 0x%08X, "
6908 "rx chain pages = 0x%08X\n",
6909 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6911 if_printf(ifp, "rx_bd per page = 0x%08X, "
6912 "usable rx_bd per page = 0x%08X\n",
6913 (uint32_t)TOTAL_RX_BD_PER_PAGE,
6914 (uint32_t)USABLE_RX_BD_PER_PAGE);
6916 if_printf(ifp, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6919 "----------------------------"
6921 "----------------------------\n");
6923 /* Now print out the rx_bd's themselves. */
6924 for (i = 0; i < count; i++) {
6927 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6928 bce_dump_rxbd(sc, rx_prod, rxbd);
6929 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6933 "----------------------------"
6935 "----------------------------\n");
6939 /****************************************************************************/
6940 /* Prints out the status block from host memory. */
6944 /****************************************************************************/
6946 bce_dump_status_block(struct bce_softc *sc)
6948 struct status_block *sblk = sc->status_block;
6949 struct ifnet *ifp = &sc->arpcom.ac_if;
6952 "----------------------------"
6954 "----------------------------\n");
6956 if_printf(ifp, " 0x%08X - attn_bits\n", sblk->status_attn_bits);
6958 if_printf(ifp, " 0x%08X - attn_bits_ack\n",
6959 sblk->status_attn_bits_ack);
6961 if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6962 sblk->status_rx_quick_consumer_index0,
6963 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6965 if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6966 sblk->status_tx_quick_consumer_index0,
6967 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6969 if_printf(ifp, " 0x%04X - status_idx\n", sblk->status_idx);
6971 /* Theses indices are not used for normal L2 drivers. */
6972 if (sblk->status_rx_quick_consumer_index1) {
6973 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6974 sblk->status_rx_quick_consumer_index1,
6975 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6978 if (sblk->status_tx_quick_consumer_index1) {
6979 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6980 sblk->status_tx_quick_consumer_index1,
6981 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6984 if (sblk->status_rx_quick_consumer_index2) {
6985 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6986 sblk->status_rx_quick_consumer_index2,
6987 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6990 if (sblk->status_tx_quick_consumer_index2) {
6991 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6992 sblk->status_tx_quick_consumer_index2,
6993 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6996 if (sblk->status_rx_quick_consumer_index3) {
6997 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6998 sblk->status_rx_quick_consumer_index3,
6999 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
7002 if (sblk->status_tx_quick_consumer_index3) {
7003 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
7004 sblk->status_tx_quick_consumer_index3,
7005 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
7008 if (sblk->status_rx_quick_consumer_index4 ||
7009 sblk->status_rx_quick_consumer_index5) {
7010 if_printf(ifp, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
7011 sblk->status_rx_quick_consumer_index4,
7012 sblk->status_rx_quick_consumer_index5);
7015 if (sblk->status_rx_quick_consumer_index6 ||
7016 sblk->status_rx_quick_consumer_index7) {
7017 if_printf(ifp, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
7018 sblk->status_rx_quick_consumer_index6,
7019 sblk->status_rx_quick_consumer_index7);
7022 if (sblk->status_rx_quick_consumer_index8 ||
7023 sblk->status_rx_quick_consumer_index9) {
7024 if_printf(ifp, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
7025 sblk->status_rx_quick_consumer_index8,
7026 sblk->status_rx_quick_consumer_index9);
7029 if (sblk->status_rx_quick_consumer_index10 ||
7030 sblk->status_rx_quick_consumer_index11) {
7031 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
7032 sblk->status_rx_quick_consumer_index10,
7033 sblk->status_rx_quick_consumer_index11);
7036 if (sblk->status_rx_quick_consumer_index12 ||
7037 sblk->status_rx_quick_consumer_index13) {
7038 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
7039 sblk->status_rx_quick_consumer_index12,
7040 sblk->status_rx_quick_consumer_index13);
7043 if (sblk->status_rx_quick_consumer_index14 ||
7044 sblk->status_rx_quick_consumer_index15) {
7045 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
7046 sblk->status_rx_quick_consumer_index14,
7047 sblk->status_rx_quick_consumer_index15);
7050 if (sblk->status_completion_producer_index ||
7051 sblk->status_cmd_consumer_index) {
7052 if_printf(ifp, "com_prod = 0x%08X, cmd_cons = 0x%08X\n",
7053 sblk->status_completion_producer_index,
7054 sblk->status_cmd_consumer_index);
7058 "----------------------------"
7060 "----------------------------\n");
7064 /****************************************************************************/
7065 /* Prints out the statistics block. */
7069 /****************************************************************************/
7071 bce_dump_stats_block(struct bce_softc *sc)
7073 struct statistics_block *sblk = sc->stats_block;
7074 struct ifnet *ifp = &sc->arpcom.ac_if;
7078 " Stats Block (All Stats Not Shown Are 0) "
7079 "---------------\n");
7081 if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7082 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7083 sblk->stat_IfHCInOctets_hi,
7084 sblk->stat_IfHCInOctets_lo);
7087 if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7088 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7089 sblk->stat_IfHCInBadOctets_hi,
7090 sblk->stat_IfHCInBadOctets_lo);
7093 if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7094 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7095 sblk->stat_IfHCOutOctets_hi,
7096 sblk->stat_IfHCOutOctets_lo);
7099 if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7100 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7101 sblk->stat_IfHCOutBadOctets_hi,
7102 sblk->stat_IfHCOutBadOctets_lo);
7105 if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7106 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7107 sblk->stat_IfHCInUcastPkts_hi,
7108 sblk->stat_IfHCInUcastPkts_lo);
7111 if (sblk->stat_IfHCInBroadcastPkts_hi ||
7112 sblk->stat_IfHCInBroadcastPkts_lo) {
7113 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7114 sblk->stat_IfHCInBroadcastPkts_hi,
7115 sblk->stat_IfHCInBroadcastPkts_lo);
7118 if (sblk->stat_IfHCInMulticastPkts_hi ||
7119 sblk->stat_IfHCInMulticastPkts_lo) {
7120 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7121 sblk->stat_IfHCInMulticastPkts_hi,
7122 sblk->stat_IfHCInMulticastPkts_lo);
7125 if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7126 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7127 sblk->stat_IfHCOutUcastPkts_hi,
7128 sblk->stat_IfHCOutUcastPkts_lo);
7131 if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7132 sblk->stat_IfHCOutBroadcastPkts_lo) {
7133 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7134 sblk->stat_IfHCOutBroadcastPkts_hi,
7135 sblk->stat_IfHCOutBroadcastPkts_lo);
7138 if (sblk->stat_IfHCOutMulticastPkts_hi ||
7139 sblk->stat_IfHCOutMulticastPkts_lo) {
7140 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7141 sblk->stat_IfHCOutMulticastPkts_hi,
7142 sblk->stat_IfHCOutMulticastPkts_lo);
7145 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7146 if_printf(ifp, " 0x%08X : "
7147 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7148 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7151 if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7152 if_printf(ifp, " 0x%08X : "
7153 "Dot3StatsCarrierSenseErrors\n",
7154 sblk->stat_Dot3StatsCarrierSenseErrors);
7157 if (sblk->stat_Dot3StatsFCSErrors) {
7158 if_printf(ifp, " 0x%08X : Dot3StatsFCSErrors\n",
7159 sblk->stat_Dot3StatsFCSErrors);
7162 if (sblk->stat_Dot3StatsAlignmentErrors) {
7163 if_printf(ifp, " 0x%08X : Dot3StatsAlignmentErrors\n",
7164 sblk->stat_Dot3StatsAlignmentErrors);
7167 if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7168 if_printf(ifp, " 0x%08X : "
7169 "Dot3StatsSingleCollisionFrames\n",
7170 sblk->stat_Dot3StatsSingleCollisionFrames);
7173 if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7174 if_printf(ifp, " 0x%08X : "
7175 "Dot3StatsMultipleCollisionFrames\n",
7176 sblk->stat_Dot3StatsMultipleCollisionFrames);
7179 if (sblk->stat_Dot3StatsDeferredTransmissions) {
7180 if_printf(ifp, " 0x%08X : "
7181 "Dot3StatsDeferredTransmissions\n",
7182 sblk->stat_Dot3StatsDeferredTransmissions);
7185 if (sblk->stat_Dot3StatsExcessiveCollisions) {
7186 if_printf(ifp, " 0x%08X : "
7187 "Dot3StatsExcessiveCollisions\n",
7188 sblk->stat_Dot3StatsExcessiveCollisions);
7191 if (sblk->stat_Dot3StatsLateCollisions) {
7192 if_printf(ifp, " 0x%08X : Dot3StatsLateCollisions\n",
7193 sblk->stat_Dot3StatsLateCollisions);
7196 if (sblk->stat_EtherStatsCollisions) {
7197 if_printf(ifp, " 0x%08X : EtherStatsCollisions\n",
7198 sblk->stat_EtherStatsCollisions);
7201 if (sblk->stat_EtherStatsFragments) {
7202 if_printf(ifp, " 0x%08X : EtherStatsFragments\n",
7203 sblk->stat_EtherStatsFragments);
7206 if (sblk->stat_EtherStatsJabbers) {
7207 if_printf(ifp, " 0x%08X : EtherStatsJabbers\n",
7208 sblk->stat_EtherStatsJabbers);
7211 if (sblk->stat_EtherStatsUndersizePkts) {
7212 if_printf(ifp, " 0x%08X : EtherStatsUndersizePkts\n",
7213 sblk->stat_EtherStatsUndersizePkts);
7216 if (sblk->stat_EtherStatsOverrsizePkts) {
7217 if_printf(ifp, " 0x%08X : EtherStatsOverrsizePkts\n",
7218 sblk->stat_EtherStatsOverrsizePkts);
7221 if (sblk->stat_EtherStatsPktsRx64Octets) {
7222 if_printf(ifp, " 0x%08X : EtherStatsPktsRx64Octets\n",
7223 sblk->stat_EtherStatsPktsRx64Octets);
7226 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7227 if_printf(ifp, " 0x%08X : "
7228 "EtherStatsPktsRx65Octetsto127Octets\n",
7229 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7232 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7233 if_printf(ifp, " 0x%08X : "
7234 "EtherStatsPktsRx128Octetsto255Octets\n",
7235 sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7238 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7239 if_printf(ifp, " 0x%08X : "
7240 "EtherStatsPktsRx256Octetsto511Octets\n",
7241 sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7244 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7245 if_printf(ifp, " 0x%08X : "
7246 "EtherStatsPktsRx512Octetsto1023Octets\n",
7247 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7250 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7251 if_printf(ifp, " 0x%08X : "
7252 "EtherStatsPktsRx1024Octetsto1522Octets\n",
7253 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7256 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7257 if_printf(ifp, " 0x%08X : "
7258 "EtherStatsPktsRx1523Octetsto9022Octets\n",
7259 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7262 if (sblk->stat_EtherStatsPktsTx64Octets) {
7263 if_printf(ifp, " 0x%08X : EtherStatsPktsTx64Octets\n",
7264 sblk->stat_EtherStatsPktsTx64Octets);
7267 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7268 if_printf(ifp, " 0x%08X : "
7269 "EtherStatsPktsTx65Octetsto127Octets\n",
7270 sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7273 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7274 if_printf(ifp, " 0x%08X : "
7275 "EtherStatsPktsTx128Octetsto255Octets\n",
7276 sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7279 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7280 if_printf(ifp, " 0x%08X : "
7281 "EtherStatsPktsTx256Octetsto511Octets\n",
7282 sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7285 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7286 if_printf(ifp, " 0x%08X : "
7287 "EtherStatsPktsTx512Octetsto1023Octets\n",
7288 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7291 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7292 if_printf(ifp, " 0x%08X : "
7293 "EtherStatsPktsTx1024Octetsto1522Octets\n",
7294 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7297 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7298 if_printf(ifp, " 0x%08X : "
7299 "EtherStatsPktsTx1523Octetsto9022Octets\n",
7300 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7303 if (sblk->stat_XonPauseFramesReceived) {
7304 if_printf(ifp, " 0x%08X : XonPauseFramesReceived\n",
7305 sblk->stat_XonPauseFramesReceived);
7308 if (sblk->stat_XoffPauseFramesReceived) {
7309 if_printf(ifp, " 0x%08X : XoffPauseFramesReceived\n",
7310 sblk->stat_XoffPauseFramesReceived);
7313 if (sblk->stat_OutXonSent) {
7314 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7315 sblk->stat_OutXonSent);
7318 if (sblk->stat_OutXoffSent) {
7319 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7320 sblk->stat_OutXoffSent);
7323 if (sblk->stat_FlowControlDone) {
7324 if_printf(ifp, " 0x%08X : FlowControlDone\n",
7325 sblk->stat_FlowControlDone);
7328 if (sblk->stat_MacControlFramesReceived) {
7329 if_printf(ifp, " 0x%08X : MacControlFramesReceived\n",
7330 sblk->stat_MacControlFramesReceived);
7333 if (sblk->stat_XoffStateEntered) {
7334 if_printf(ifp, " 0x%08X : XoffStateEntered\n",
7335 sblk->stat_XoffStateEntered);
7338 if (sblk->stat_IfInFramesL2FilterDiscards) {
7339 if_printf(ifp, " 0x%08X : IfInFramesL2FilterDiscards\n", sblk->stat_IfInFramesL2FilterDiscards);
7342 if (sblk->stat_IfInRuleCheckerDiscards) {
7343 if_printf(ifp, " 0x%08X : IfInRuleCheckerDiscards\n",
7344 sblk->stat_IfInRuleCheckerDiscards);
7347 if (sblk->stat_IfInFTQDiscards) {
7348 if_printf(ifp, " 0x%08X : IfInFTQDiscards\n",
7349 sblk->stat_IfInFTQDiscards);
7352 if (sblk->stat_IfInMBUFDiscards) {
7353 if_printf(ifp, " 0x%08X : IfInMBUFDiscards\n",
7354 sblk->stat_IfInMBUFDiscards);
7357 if (sblk->stat_IfInRuleCheckerP4Hit) {
7358 if_printf(ifp, " 0x%08X : IfInRuleCheckerP4Hit\n",
7359 sblk->stat_IfInRuleCheckerP4Hit);
7362 if (sblk->stat_CatchupInRuleCheckerDiscards) {
7363 if_printf(ifp, " 0x%08X : "
7364 "CatchupInRuleCheckerDiscards\n",
7365 sblk->stat_CatchupInRuleCheckerDiscards);
7368 if (sblk->stat_CatchupInFTQDiscards) {
7369 if_printf(ifp, " 0x%08X : CatchupInFTQDiscards\n",
7370 sblk->stat_CatchupInFTQDiscards);
7373 if (sblk->stat_CatchupInMBUFDiscards) {
7374 if_printf(ifp, " 0x%08X : CatchupInMBUFDiscards\n",
7375 sblk->stat_CatchupInMBUFDiscards);
7378 if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7379 if_printf(ifp, " 0x%08X : CatchupInRuleCheckerP4Hit\n",
7380 sblk->stat_CatchupInRuleCheckerP4Hit);
7384 "----------------------------"
7386 "----------------------------\n");
7390 /****************************************************************************/
7391 /* Prints out a summary of the driver state. */
7395 /****************************************************************************/
7397 bce_dump_driver_state(struct bce_softc *sc)
7399 struct ifnet *ifp = &sc->arpcom.ac_if;
7400 uint32_t val_hi, val_lo;
7403 "-----------------------------"
7405 "-----------------------------\n");
7407 val_hi = BCE_ADDR_HI(sc);
7408 val_lo = BCE_ADDR_LO(sc);
7409 if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7410 "virtual address\n", val_hi, val_lo);
7412 val_hi = BCE_ADDR_HI(sc->status_block);
7413 val_lo = BCE_ADDR_LO(sc->status_block);
7414 if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7415 "virtual address\n", val_hi, val_lo);
7417 val_hi = BCE_ADDR_HI(sc->stats_block);
7418 val_lo = BCE_ADDR_LO(sc->stats_block);
7419 if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7420 "virtual address\n", val_hi, val_lo);
7422 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7423 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7424 if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7425 "virtual adddress\n", val_hi, val_lo);
7427 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7428 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7429 if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7430 "virtual address\n", val_hi, val_lo);
7432 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7433 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7434 if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7435 "virtual address\n", val_hi, val_lo);
7437 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7438 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7439 if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7440 "virtual address\n", val_hi, val_lo);
7442 if_printf(ifp, " 0x%08X - (sc->interrupts_generated) "
7443 "h/w intrs\n", sc->interrupts_generated);
7445 if_printf(ifp, " 0x%08X - (sc->rx_interrupts) "
7446 "rx interrupts handled\n", sc->rx_interrupts);
7448 if_printf(ifp, " 0x%08X - (sc->tx_interrupts) "
7449 "tx interrupts handled\n", sc->tx_interrupts);
7451 if_printf(ifp, " 0x%08X - (sc->last_status_idx) "
7452 "status block index\n", sc->last_status_idx);
7454 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_prod) "
7455 "tx producer index\n",
7456 sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
7458 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_cons) "
7459 "tx consumer index\n",
7460 sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
7462 if_printf(ifp, " 0x%08X - (sc->tx_prod_bseq) "
7463 "tx producer bseq index\n", sc->tx_prod_bseq);
7465 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_prod) "
7466 "rx producer index\n",
7467 sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
7469 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_cons) "
7470 "rx consumer index\n",
7471 sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
7473 if_printf(ifp, " 0x%08X - (sc->rx_prod_bseq) "
7474 "rx producer bseq index\n", sc->rx_prod_bseq);
7476 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7477 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7479 if_printf(ifp, " 0x%08X - (sc->free_rx_bd) "
7480 "free rx_bd's\n", sc->free_rx_bd);
7482 if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7483 "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7485 if_printf(ifp, " 0x%08X - (sc->txmbuf_alloc) "
7486 "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7488 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7489 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7491 if_printf(ifp, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7494 if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7495 sc->tx_hi_watermark, sc->max_tx_bd);
7497 if_printf(ifp, " 0x%08X - (sc->mbuf_alloc_failed) "
7498 "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7501 "----------------------------"
7503 "----------------------------\n");
7507 /****************************************************************************/
7508 /* Prints out the hardware state through a summary of important registers, */
7509 /* followed by a complete register dump. */
7513 /****************************************************************************/
7515 bce_dump_hw_state(struct bce_softc *sc)
7517 struct ifnet *ifp = &sc->arpcom.ac_if;
7522 "----------------------------"
7524 "----------------------------\n");
7526 if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7528 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7529 if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7530 val1, BCE_MISC_ENABLE_STATUS_BITS);
7532 val1 = REG_RD(sc, BCE_DMA_STATUS);
7533 if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7535 val1 = REG_RD(sc, BCE_CTX_STATUS);
7536 if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7538 val1 = REG_RD(sc, BCE_EMAC_STATUS);
7539 if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7540 val1, BCE_EMAC_STATUS);
7542 val1 = REG_RD(sc, BCE_RPM_STATUS);
7543 if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7545 val1 = REG_RD(sc, BCE_TBDR_STATUS);
7546 if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7547 val1, BCE_TBDR_STATUS);
7549 val1 = REG_RD(sc, BCE_TDMA_STATUS);
7550 if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7551 val1, BCE_TDMA_STATUS);
7553 val1 = REG_RD(sc, BCE_HC_STATUS);
7554 if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7556 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7557 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7558 val1, BCE_TXP_CPU_STATE);
7560 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7561 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7562 val1, BCE_TPAT_CPU_STATE);
7564 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7565 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7566 val1, BCE_RXP_CPU_STATE);
7568 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7569 if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7570 val1, BCE_COM_CPU_STATE);
7572 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7573 if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7574 val1, BCE_MCP_CPU_STATE);
7576 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7577 if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7578 val1, BCE_CP_CPU_STATE);
7581 "----------------------------"
7583 "----------------------------\n");
7586 "----------------------------"
7588 "----------------------------\n");
7590 for (i = 0x400; i < 0x8000; i += 0x10) {
7591 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7593 REG_RD(sc, i + 0x4),
7594 REG_RD(sc, i + 0x8),
7595 REG_RD(sc, i + 0xc));
7599 "----------------------------"
7601 "----------------------------\n");
7605 /****************************************************************************/
7606 /* Prints out the TXP state. */
7610 /****************************************************************************/
7612 bce_dump_txp_state(struct bce_softc *sc)
7614 struct ifnet *ifp = &sc->arpcom.ac_if;
7619 "----------------------------"
7621 "----------------------------\n");
7623 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7624 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7625 val1, BCE_TXP_CPU_MODE);
7627 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7628 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7629 val1, BCE_TXP_CPU_STATE);
7631 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7632 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7633 val1, BCE_TXP_CPU_EVENT_MASK);
7636 "----------------------------"
7638 "----------------------------\n");
7640 for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7641 /* Skip the big blank spaces */
7642 if (i < 0x454000 && i > 0x5ffff) {
7643 if_printf(ifp, "0x%04X: "
7644 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7646 REG_RD_IND(sc, i + 0x4),
7647 REG_RD_IND(sc, i + 0x8),
7648 REG_RD_IND(sc, i + 0xc));
7653 "----------------------------"
7655 "----------------------------\n");
7659 /****************************************************************************/
7660 /* Prints out the RXP state. */
7664 /****************************************************************************/
7666 bce_dump_rxp_state(struct bce_softc *sc)
7668 struct ifnet *ifp = &sc->arpcom.ac_if;
7673 "----------------------------"
7675 "----------------------------\n");
7677 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7678 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7679 val1, BCE_RXP_CPU_MODE);
7681 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7682 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7683 val1, BCE_RXP_CPU_STATE);
7685 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7686 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7687 val1, BCE_RXP_CPU_EVENT_MASK);
7690 "----------------------------"
7692 "----------------------------\n");
7694 for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7695 /* Skip the big blank sapces */
7696 if (i < 0xc5400 && i > 0xdffff) {
7697 if_printf(ifp, "0x%04X: "
7698 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7700 REG_RD_IND(sc, i + 0x4),
7701 REG_RD_IND(sc, i + 0x8),
7702 REG_RD_IND(sc, i + 0xc));
7707 "----------------------------"
7709 "----------------------------\n");
7713 /****************************************************************************/
7714 /* Prints out the TPAT state. */
7718 /****************************************************************************/
7720 bce_dump_tpat_state(struct bce_softc *sc)
7722 struct ifnet *ifp = &sc->arpcom.ac_if;
7727 "----------------------------"
7729 "----------------------------\n");
7731 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7732 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7733 val1, BCE_TPAT_CPU_MODE);
7735 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7736 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7737 val1, BCE_TPAT_CPU_STATE);
7739 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7740 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7741 val1, BCE_TPAT_CPU_EVENT_MASK);
7744 "----------------------------"
7746 "----------------------------\n");
7748 for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7749 /* Skip the big blank spaces */
7750 if (i < 0x854000 && i > 0x9ffff) {
7751 if_printf(ifp, "0x%04X: "
7752 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7754 REG_RD_IND(sc, i + 0x4),
7755 REG_RD_IND(sc, i + 0x8),
7756 REG_RD_IND(sc, i + 0xc));
7761 "----------------------------"
7763 "----------------------------\n");
7767 /****************************************************************************/
7768 /* Prints out the driver state and then enters the debugger. */
7772 /****************************************************************************/
7774 bce_breakpoint(struct bce_softc *sc)
7777 bce_freeze_controller(sc);
7780 bce_dump_driver_state(sc);
7781 bce_dump_status_block(sc);
7782 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7783 bce_dump_hw_state(sc);
7784 bce_dump_txp_state(sc);
7787 bce_unfreeze_controller(sc);
7790 /* Call the debugger. */
7794 #endif /* BCE_DEBUG */
7797 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7799 struct bce_softc *sc = arg1;
7801 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7802 &sc->bce_tx_quick_cons_trip_int,
7803 BCE_COALMASK_TX_BDS_INT);
7807 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7809 struct bce_softc *sc = arg1;
7811 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7812 &sc->bce_tx_quick_cons_trip,
7813 BCE_COALMASK_TX_BDS);
7817 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7819 struct bce_softc *sc = arg1;
7821 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7822 &sc->bce_tx_ticks_int,
7823 BCE_COALMASK_TX_TICKS_INT);
7827 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7829 struct bce_softc *sc = arg1;
7831 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7833 BCE_COALMASK_TX_TICKS);
7837 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7839 struct bce_softc *sc = arg1;
7841 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7842 &sc->bce_rx_quick_cons_trip_int,
7843 BCE_COALMASK_RX_BDS_INT);
7847 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7849 struct bce_softc *sc = arg1;
7851 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7852 &sc->bce_rx_quick_cons_trip,
7853 BCE_COALMASK_RX_BDS);
7857 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7859 struct bce_softc *sc = arg1;
7861 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7862 &sc->bce_rx_ticks_int,
7863 BCE_COALMASK_RX_TICKS_INT);
7867 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7869 struct bce_softc *sc = arg1;
7871 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7873 BCE_COALMASK_RX_TICKS);
7877 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7878 uint32_t coalchg_mask)
7880 struct bce_softc *sc = arg1;
7881 struct ifnet *ifp = &sc->arpcom.ac_if;
7884 lwkt_serialize_enter(ifp->if_serializer);
7887 error = sysctl_handle_int(oidp, &v, 0, req);
7888 if (!error && req->newptr != NULL) {
7893 sc->bce_coalchg_mask |= coalchg_mask;
7897 lwkt_serialize_exit(ifp->if_serializer);
7902 bce_coal_change(struct bce_softc *sc)
7904 struct ifnet *ifp = &sc->arpcom.ac_if;
7906 ASSERT_SERIALIZED(ifp->if_serializer);
7908 if ((ifp->if_flags & IFF_RUNNING) == 0) {
7909 sc->bce_coalchg_mask = 0;
7913 if (sc->bce_coalchg_mask &
7914 (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7915 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7916 (sc->bce_tx_quick_cons_trip_int << 16) |
7917 sc->bce_tx_quick_cons_trip);
7919 if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7920 sc->bce_tx_quick_cons_trip,
7921 sc->bce_tx_quick_cons_trip_int);
7925 if (sc->bce_coalchg_mask &
7926 (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7927 REG_WR(sc, BCE_HC_TX_TICKS,
7928 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7930 if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7931 sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7935 if (sc->bce_coalchg_mask &
7936 (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7937 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7938 (sc->bce_rx_quick_cons_trip_int << 16) |
7939 sc->bce_rx_quick_cons_trip);
7941 if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7942 sc->bce_rx_quick_cons_trip,
7943 sc->bce_rx_quick_cons_trip_int);
7947 if (sc->bce_coalchg_mask &
7948 (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7949 REG_WR(sc, BCE_HC_RX_TICKS,
7950 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7952 if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7953 sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7957 sc->bce_coalchg_mask = 0;