2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $
41 * Tigon general information block. This resides in host memory
42 * and contains the status counters, ring control blocks and
47 struct bge_stats bnx_stats;
48 struct bge_rcb bnx_tx_rcb[16];
49 struct bge_rcb bnx_std_rx_rcb;
50 struct bge_rcb bnx_jumbo_rx_rcb;
51 struct bge_rcb bnx_mini_rx_rcb;
52 struct bge_rcb bnx_return_rcb;
55 #define BNX_MIN_FRAMELEN 60
56 #define BNX_MAX_FRAMELEN 1536
57 #define BNX_JUMBO_FRAMELEN 9018
58 #define BNX_JUMBO_MTU (BNX_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
60 #define BNX_TIMEOUT 5000
61 #define BNX_FIRMWARE_TIMEOUT 100000
62 #define BNX_TXCONS_UNSET 0xFFFF /* impossible value */
65 * Other utility macros.
67 #define BNX_INC(x, y) (x) = ((x) + 1) % (y)
70 * BAR0 MAC register access macros. The Tigon always uses memory mapped
71 * register accesses and all registers must be accessed with 32 bit
75 #define CSR_WRITE_4(sc, reg, val) \
76 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
78 #define CSR_READ_4(sc, reg) \
79 bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
81 #define BNX_SETBIT(sc, reg, x) \
82 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
84 #define BNX_CLRBIT(sc, reg, x) \
85 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
87 /* BAR2 APE register access macros. */
88 #define APE_WRITE_4(sc, reg, val) \
89 bus_write_4(sc->bnx_res2, reg, val)
91 #define APE_READ_4(sc, reg) \
92 bus_read_4(sc->bnx_res2, reg)
94 #define APE_SETBIT(sc, reg, x) \
95 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x)))
96 #define APE_CLRBIT(sc, reg, x) \
97 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x)))
99 #define BNX_MEMWIN_READ(sc, x, val) \
101 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \
102 (0xFFFF0000 & x), 4); \
103 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
106 #define BNX_MEMWIN_WRITE(sc, x, val) \
108 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \
109 (0xFFFF0000 & x), 4); \
110 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
113 #define RCB_WRITE_4(sc, rcb, offset, val) \
114 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, \
115 rcb + offsetof(struct bge_rcb, offset), val)
118 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
119 * values are tuneable. They control the actual amount of buffers
120 * allocated for the standard, mini and jumbo receive rings.
123 #define BNX_SSLOTS 256
124 #define BNX_MSLOTS 256
125 #define BNX_JSLOTS 384
127 #define BNX_JRAWLEN (BNX_JUMBO_FRAMELEN + ETHER_ALIGN)
128 #define BNX_JLEN (BNX_JRAWLEN + \
129 (sizeof(uint64_t) - BNX_JRAWLEN % sizeof(uint64_t)))
130 #define BNX_JPAGESZ PAGE_SIZE
131 #define BNX_RESID (BNX_JPAGESZ - (BNX_JLEN * BNX_JSLOTS) % BNX_JPAGESZ)
132 #define BNX_JMEM ((BNX_JLEN * BNX_JSLOTS) + BNX_RESID)
138 struct bnx_softc *bnx_sc;
140 bus_addr_t bnx_paddr;
143 SLIST_ENTRY(bnx_jslot) jslot_link;
147 * Ring structures. Most of these reside in host memory and we tell
148 * the NIC where they are via the ring control blocks. The exceptions
149 * are the tx and command rings, which live in NIC memory and which
150 * we access via the shared memory window.
152 struct bnx_ring_data {
153 struct bge_rx_bd *bnx_rx_jumbo_ring;
154 bus_addr_t bnx_rx_jumbo_ring_paddr;
156 struct bnx_gib bnx_info;
160 bus_dmamap_t bnx_rx_dmamap;
161 struct mbuf *bnx_rx_mbuf;
162 bus_addr_t bnx_rx_paddr;
167 struct bnx_rx_std_ring {
168 struct lwkt_serialize bnx_rx_std_serialize;
169 struct bnx_softc *bnx_sc;
171 uint16_t bnx_rx_std_stop;
172 uint16_t bnx_rx_std; /* current prod ring head */
173 struct bge_rx_bd *bnx_rx_std_ring;
175 int bnx_rx_std_refill __cachealign;
177 u_int bnx_rx_std_running;
178 struct thread bnx_rx_std_ithread;
180 struct bnx_rx_buf bnx_rx_std_buf[BGE_STD_RX_RING_CNT];
182 bus_dma_tag_t bnx_rx_mtag; /* RX mbuf DMA tag */
184 bus_dma_tag_t bnx_rx_std_ring_tag;
185 bus_dmamap_t bnx_rx_std_ring_map;
186 bus_addr_t bnx_rx_std_ring_paddr;
189 struct bnx_rx_ret_ring {
190 struct lwkt_serialize bnx_rx_ret_serialize;
192 uint32_t bnx_saved_status_tag;
193 volatile uint32_t *bnx_hw_status_tag;
195 struct bnx_softc *bnx_sc;
196 struct bnx_rx_std_ring *bnx_std;
197 struct bnx_tx_ring *bnx_txr;
199 /* Shadow of bnx_rx_std_ring's bnx_rx_mtag */
200 bus_dma_tag_t bnx_rx_mtag;
202 volatile uint16_t *bnx_rx_considx;
203 uint16_t bnx_rx_saved_considx;
205 uint16_t bnx_rx_cntmax;
206 uint16_t bnx_rx_mask;
207 struct bge_rx_bd *bnx_rx_ret_ring;
208 bus_dmamap_t bnx_rx_tmpmap;
210 bus_dma_tag_t bnx_rx_ret_ring_tag;
211 bus_dmamap_t bnx_rx_ret_ring_map;
212 bus_addr_t bnx_rx_ret_ring_paddr;
215 u_long bnx_rx_force_sched;
219 * Mbuf pointers. We need these to keep track of the virtual addresses
220 * of our mbuf chains since we can only convert from physical to virtual,
221 * not the other way around.
223 struct bnx_chain_data {
224 bus_dma_tag_t bnx_parent_tag;
225 bus_dma_tag_t bnx_rx_jumbo_ring_tag;
226 bus_dma_tag_t bnx_jumbo_tag;
227 bus_dmamap_t bnx_rx_jumbo_ring_map;
228 bus_dmamap_t bnx_jumbo_map;
229 struct bnx_rx_buf bnx_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
230 /* Stick the jumbo mem management stuff here too. */
231 struct bnx_jslot bnx_jslots[BNX_JSLOTS];
235 bus_dmamap_t bnx_tx_dmamap;
236 struct mbuf *bnx_tx_mbuf;
240 struct lwkt_serialize bnx_tx_serialize;
241 volatile uint32_t *bnx_hw_status_tag;
242 uint32_t bnx_saved_status_tag;
243 struct bnx_softc *bnx_sc;
244 struct ifaltq_subque *bnx_ifsq;
245 volatile uint16_t *bnx_tx_considx;
246 uint16_t bnx_tx_flags;
247 #define BNX_TX_FLAG_SHORTDMA 0x0001
248 #define BNX_TX_FLAG_FORCE_DEFRAG 0x0002
249 uint16_t bnx_tx_saved_considx;
251 uint32_t bnx_tx_prodidx;
254 struct ifsubq_watchdog bnx_tx_watchdog;
256 struct bge_tx_bd *bnx_tx_ring;
258 bus_dma_tag_t bnx_tx_mtag; /* TX mbuf DMA tag */
259 struct bnx_tx_buf bnx_tx_buf[BGE_TX_RING_CNT];
261 bus_dma_tag_t bnx_tx_ring_tag;
262 bus_dmamap_t bnx_tx_ring_map;
263 bus_addr_t bnx_tx_ring_paddr;
269 struct bnx_intr_data {
270 struct bnx_softc *bnx_sc;
271 struct bnx_rx_ret_ring *bnx_ret;
272 struct bnx_tx_ring *bnx_txr;
275 struct lwkt_serialize *bnx_intr_serialize;
276 struct callout bnx_intr_timer;
277 void (*bnx_intr_check)(void *);
278 uint16_t bnx_rx_check_considx;
279 uint16_t bnx_tx_check_considx;
280 boolean_t bnx_intr_maylose;
283 driver_intr_t *bnx_intr_func;
285 struct resource *bnx_intr_res;
288 const uint32_t *bnx_saved_status_tag;
290 const char *bnx_intr_desc;
291 char bnx_intr_desc0[64];
293 bus_dma_tag_t bnx_status_tag;
294 bus_dmamap_t bnx_status_map;
295 struct bge_status_block *bnx_status_block;
296 bus_addr_t bnx_status_block_paddr;
299 #define BNX_RX_RING_MAX 4
300 #define BNX_TX_RING_MAX 4
301 #define BNX_INTR_MAX 5
304 struct arpcom arpcom; /* interface info */
307 bus_space_handle_t bnx_bhandle;
308 bus_space_tag_t bnx_btag;
309 struct resource *bnx_res; /* MAC mapped I/O */
310 struct resource *bnx_res2; /* APE mapped I/O */
311 struct ifmedia bnx_ifmedia; /* TBI media info */
313 uint32_t bnx_flags; /* BNX_FLAG_ */
314 #define BNX_FLAG_TBI 0x00000001
315 #define BNX_FLAG_JUMBO 0x00000002
316 #define BNX_FLAG_APE 0x00000004
317 #define BNX_FLAG_5717_PLUS 0x00000008
318 #define BNX_FLAG_MII_SERDES 0x00000010
319 #define BNX_FLAG_CPMU 0x00000020
320 #define BNX_FLAG_57765_PLUS 0x00000040
321 #define BNX_FLAG_57765_FAMILY 0x00000080
322 #define BNX_FLAG_STATUSTAG_BUG 0x00000100
323 #define BNX_FLAG_TSO 0x00000200
324 #define BNX_FLAG_NO_EEPROM 0x10000000
325 #define BNX_FLAG_RXTX_BUNDLE 0x20000000
326 #define BNX_FLAG_STD_THREAD 0x40000000
327 #define BNX_FLAG_STATUS_HASTAG 0x80000000
329 uint32_t bnx_mfw_flags; /* Management F/W flags */
330 #define BNX_MFW_ON_RXCPU 0x00000001
331 #define BNX_MFW_ON_APE 0x00000002
332 #define BNX_MFW_TYPE_NCSI 0x00000004
333 #define BNX_MFW_TYPE_DASH 0x00000008
334 int bnx_phy_ape_lock;
338 uint32_t bnx_asicrev;
339 uint32_t bnx_chiprev;
340 struct bnx_ring_data bnx_ldata; /* rings */
341 struct bnx_chain_data bnx_cdata; /* mbufs */
343 struct lwkt_serialize bnx_main_serialize;
344 volatile uint32_t *bnx_hw_status;
345 volatile uint32_t *bnx_hw_status_tag;
346 uint32_t bnx_saved_status_tag;
351 int bnx_serialize_cnt;
352 struct lwkt_serialize **bnx_serialize;
355 struct bnx_tx_ring *bnx_tx_ring;
357 struct bnx_rx_ret_ring *bnx_rx_ret_ring;
358 struct bnx_rx_std_ring bnx_rx_std_ring;
360 uint16_t bnx_jumbo; /* current jumo ring head */
361 SLIST_HEAD(__bnx_jfreehead, bnx_jslot) bnx_jfree_listhead;
362 struct lwkt_serialize bnx_jslot_serializer;
363 uint32_t bnx_rx_coal_ticks;
364 uint32_t bnx_tx_coal_ticks;
365 uint32_t bnx_rx_coal_bds;
366 uint32_t bnx_rx_coal_bds_poll;
367 uint32_t bnx_tx_coal_bds;
368 uint32_t bnx_tx_coal_bds_poll;
369 uint32_t bnx_rx_coal_bds_int;
370 uint32_t bnx_tx_coal_bds_int;
371 uint32_t bnx_mi_mode;
375 struct callout bnx_tick_timer;
380 int bnx_msix_mem_rid;
381 struct resource *bnx_msix_mem_res;
384 struct bnx_intr_data bnx_intr_data[BNX_INTR_MAX];
386 struct sysctl_ctx_list bnx_sysctl_ctx;
387 struct sysctl_oid *bnx_sysctl_tree;
390 uint32_t bnx_coal_chg;
391 #define BNX_RX_COAL_TICKS_CHG 0x01
392 #define BNX_TX_COAL_TICKS_CHG 0x02
393 #define BNX_RX_COAL_BDS_CHG 0x04
394 #define BNX_TX_COAL_BDS_CHG 0x08
395 #define BNX_RX_COAL_BDS_INT_CHG 0x40
396 #define BNX_TX_COAL_BDS_INT_CHG 0x80
398 void (*bnx_link_upd)(struct bnx_softc *, uint32_t);
399 uint32_t bnx_link_chg;
402 #define BNX_TSO_NSTATS 45
403 u_long bnx_tsosegs[BNX_TSO_NSTATS];
406 #define BNX_NSEG_NEW 40
407 #define BNX_NSEG_SPARE 33 /* enough for 64K TSO segment */
408 #define BNX_NSEG_RSVD 4
410 /* RX coalesce ticks, unit: us */
411 #define BNX_RX_COAL_TICKS_MIN 0
412 #define BNX_RX_COAL_TICKS_DEF 160
413 #define BNX_RX_COAL_TICKS_MAX 1023
415 /* TX coalesce ticks, unit: us */
416 #define BNX_TX_COAL_TICKS_MIN 0
417 #define BNX_TX_COAL_TICKS_DEF 1023
418 #define BNX_TX_COAL_TICKS_MAX 1023
420 /* RX coalesce BDs */
421 #define BNX_RX_COAL_BDS_MIN 0
422 #define BNX_RX_COAL_BDS_DEF 0
423 #define BNX_RX_COAL_BDS_INT_DEF 80
424 #define BNX_RX_COAL_BDS_MAX 255
426 /* TX coalesce BDs */
427 #define BNX_TX_COAL_BDS_MIN 0
428 #define BNX_TX_COAL_BDS_DEF 128
429 #define BNX_TX_COAL_BDS_POLL_DEF 64
430 #define BNX_TX_COAL_BDS_INT_DEF 64
431 #define BNX_TX_COAL_BDS_MAX 255
433 /* Number of segments sent before writing to TX related registers */
434 #define BNX_TX_WREG_NSEGS 8
436 /* Return ring descriptor count */
437 #define BNX_RETURN_RING_CNT 512
439 #define BNX_TX_RING_MAX 4
441 #define BNX_RSS_ENABLED(sc) ((sc)->bnx_rx_retcnt > 1)
443 #endif /* !_IF_BNXVAR_H_ */