2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
36 * $FreeBSD: src/sys/dev/ath/if_ath.c,v 1.94.2.23 2006/07/10 01:15:24 sam Exp $
37 * $DragonFly: src/sys/dev/netif/ath/ath/if_ath.c,v 1.8 2007/09/15 21:24:59 swildner Exp $
41 * Driver for the Atheros Wireless LAN controller.
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/sysctl.h>
53 #include <sys/malloc.h>
54 #include <sys/kernel.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/errno.h>
58 #include <sys/callout.h>
60 #include <sys/endian.h>
61 #include <sys/kthread.h>
62 #include <sys/serialize.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
70 #include <net/if_arp.h>
71 #include <net/ethernet.h>
72 #include <net/if_llc.h>
73 #include <net/ifq_var.h>
75 #include <netproto/802_11/ieee80211_var.h>
83 #include <dev/netif/ath/ath/if_athvar.h>
84 #include <contrib/dev/ath/ah_desc.h>
85 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */
87 /* unaligned little endian access */
88 #define LE_READ_2(p) \
90 ((((uint8_t *)(p))[0] ) | (((uint8_t *)(p))[1] << 8)))
91 #define LE_READ_4(p) \
93 ((((uint8_t *)(p))[0] ) | (((uint8_t *)(p))[1] << 8) | \
94 (((uint8_t *)(p))[2] << 16) | (((uint8_t *)(p))[3] << 24)))
102 static void ath_init(void *);
103 static void ath_stop_no_pwchg(struct ifnet *);
104 static void ath_stop(struct ifnet *);
105 static void ath_start(struct ifnet *);
106 static int ath_reset(struct ifnet *);
107 static int ath_media_change(struct ifnet *);
108 static void ath_watchdog(struct ifnet *);
109 static int ath_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
110 static void ath_fatal_proc(struct ath_softc *);
111 static void ath_rxorn_proc(struct ath_softc *);
112 static void ath_bmiss_proc(struct ath_softc *);
113 static int ath_key_alloc(struct ieee80211com *,
114 const struct ieee80211_key *,
115 ieee80211_keyix *, ieee80211_keyix *);
116 static int ath_key_delete(struct ieee80211com *,
117 const struct ieee80211_key *);
118 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *,
119 const uint8_t mac[IEEE80211_ADDR_LEN]);
120 static void ath_key_update_begin(struct ieee80211com *);
121 static void ath_key_update_end(struct ieee80211com *);
122 static void ath_mode_init(struct ath_softc *);
123 static void ath_setslottime(struct ath_softc *);
124 static void ath_updateslot(struct ifnet *);
125 static int ath_beaconq_setup(struct ath_hal *);
126 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
127 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
128 static void ath_beacon_proc(struct ath_softc *);
129 static void ath_bstuck_proc(struct ath_softc *);
130 static void ath_beacon_free(struct ath_softc *);
131 static void ath_beacon_config(struct ath_softc *);
132 static void ath_descdma_cleanup(struct ath_softc *sc,
133 struct ath_descdma *, ath_bufhead *);
134 static int ath_desc_alloc(struct ath_softc *);
135 static void ath_desc_free(struct ath_softc *);
136 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *);
137 static void ath_node_free(struct ieee80211_node *);
138 static uint8_t ath_node_getrssi(const struct ieee80211_node *);
139 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
140 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
141 struct ieee80211_node *ni,
142 int subtype, int rssi, uint32_t rstamp);
143 static void ath_setdefantenna(struct ath_softc *, u_int);
144 static void ath_rx_proc(struct ath_softc *);
145 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
146 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
147 static int ath_tx_setup(struct ath_softc *, int, int);
148 static int ath_wme_update(struct ieee80211com *);
149 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
150 static void ath_tx_cleanup(struct ath_softc *);
151 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
152 struct ath_buf *, struct mbuf *);
153 static void ath_tx_proc_q0(struct ath_softc *);
154 static void ath_tx_proc_q0123(struct ath_softc *);
155 static void ath_tx_proc(struct ath_softc *);
156 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
157 static void ath_draintxq(struct ath_softc *);
158 static void ath_stoprecv(struct ath_softc *);
159 static int ath_startrecv(struct ath_softc *);
160 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
161 static void ath_next_scan(void *);
162 static void ath_calibrate(void *);
163 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int);
164 static void ath_setup_stationkey(struct ieee80211_node *);
165 static void ath_newassoc(struct ieee80211_node *, int);
166 static int ath_getchannels(struct ath_softc *, u_int cc,
167 HAL_BOOL outdoor, HAL_BOOL xchanmode);
168 static void ath_led_event(struct ath_softc *, int);
169 static void ath_update_txpow(struct ath_softc *);
171 static int ath_rate_setup(struct ath_softc *, u_int mode);
172 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
174 static void ath_sysctlattach(struct ath_softc *);
175 static void ath_bpfattach(struct ath_softc *);
176 static void ath_announce(struct ath_softc *);
178 static void ath_dma_map_mbuf(void *, bus_dma_segment_t *, int, bus_size_t,
181 SYSCTL_DECL(_hw_ath);
183 /* XXX validate sysctl values */
184 static int ath_dwelltime = 200; /* 5 channels/second */
185 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime,
186 0, "channel dwell time (ms) for AP/station scanning");
187 static int ath_calinterval = 30; /* calibrate every 30 secs */
188 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval,
189 0, "chip calibration interval (secs)");
190 static int ath_outdoor = AH_TRUE; /* outdoor operation */
191 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor,
192 0, "outdoor operation");
193 TUNABLE_INT("hw.ath.outdoor", &ath_outdoor);
194 static int ath_xchanmode = AH_TRUE; /* extended channel use */
195 SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode,
196 0, "extended channel mode");
197 TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode);
198 static int ath_countrycode = CTRY_DEFAULT; /* country code */
199 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode,
201 TUNABLE_INT("hw.ath.countrycode", &ath_countrycode);
202 static int ath_regdomain = 0; /* regulatory domain */
203 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain,
204 0, "regulatory domain");
206 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
207 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RD, &ath_rxbuf,
208 0, "rx buffers allocated");
209 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
210 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
211 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RD, &ath_txbuf,
212 0, "tx buffers allocated");
213 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
216 static int ath_debug = 0;
217 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
218 0, "control debugging kprintfs");
219 TUNABLE_INT("hw.ath.debug", &ath_debug);
221 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
222 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
223 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
224 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
225 ATH_DEBUG_RATE = 0x00000010, /* rate control */
226 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
227 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
228 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
229 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
230 ATH_DEBUG_INTR = 0x00001000, /* ISR */
231 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
232 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
233 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
234 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
235 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
236 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
237 ATH_DEBUG_NODE = 0x00080000, /* node management */
238 ATH_DEBUG_LED = 0x00100000, /* led management */
239 ATH_DEBUG_FF = 0x00200000, /* fast frames */
240 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */
241 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
242 ATH_DEBUG_ANY = 0xffffffff
244 #define IFF_DUMPPKTS(sc, m) \
245 ((sc->sc_debug & (m)) || \
246 (sc->sc_ic.ic_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
247 #define DPRINTF(sc, m, fmt, ...) do { \
248 if (sc->sc_debug & (m)) \
249 kprintf(fmt, __VA_ARGS__); \
251 #define KEYPRINTF(sc, ix, hk, mac) do { \
252 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
253 ath_keyprint(sc, __func__, ix, hk, mac); \
255 static void ath_printrxbuf(const struct ath_buf *bf, u_int ix, int);
256 static void ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done);
258 #define IFF_DUMPPKTS(sc, m) \
259 ((sc->sc_ic.ic_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
260 #define DPRINTF(sc, m, fmt, ...) do { \
263 #define KEYPRINTF(sc, k, ix, mac) do { \
268 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
271 ath_attach(uint16_t devid, struct ath_softc *sc)
273 struct ieee80211com *ic = &sc->sc_ic;
274 struct ifnet *ifp = &ic->ic_if;
275 struct ath_hal *ah = NULL;
279 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
281 /* set these up early for if_printf use */
282 if_initname(ifp, device_get_name(sc->sc_dev),
283 device_get_unit(sc->sc_dev));
286 * Mark device invalid so any interrupts (shared or otherwise)
287 * that arrive before the HAL is setup are discarded.
292 * Arrange interrupt line.
295 sc->sc_irq = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ,
297 RF_SHAREABLE | RF_ACTIVE);
298 if (sc->sc_irq == NULL) {
299 if_printf(ifp, "could not map interrupt\n");
303 sysctl_ctx_init(&sc->sc_sysctl_ctx);
304 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
305 SYSCTL_STATIC_CHILDREN(_hw),
307 device_get_nameunit(sc->sc_dev),
309 if (sc->sc_sysctl_tree == NULL) {
310 if_printf(ifp, "could not add sysctl node\n");
315 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
317 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
324 if (ah->ah_abi != HAL_ABI_VERSION) {
325 if_printf(ifp, "HAL ABI mismatch detected "
326 "(HAL:0x%x != driver:0x%x)\n",
327 ah->ah_abi, HAL_ABI_VERSION);
331 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
334 * Check if the MAC has multi-rate retry support.
335 * We do this by trying to setup a fake extended
336 * descriptor. MAC's that don't have support will
337 * return false w/o doing anything. MAC's that do
338 * support it will return true w/o doing anything.
340 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
343 * Check if the device has hardware counters for PHY
344 * errors. If so we need to enable the MIB interrupt
345 * so we can act on stat triggers.
347 if (ath_hal_hwphycounters(ah))
351 * Get the hardware key cache size.
353 sc->sc_keymax = ath_hal_keycachesize(ah);
354 if (sc->sc_keymax > ATH_KEYMAX) {
355 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
356 ATH_KEYMAX, sc->sc_keymax);
357 sc->sc_keymax = ATH_KEYMAX;
360 * Reset the key cache since some parts do not
361 * reset the contents on initial power up.
363 for (i = 0; i < sc->sc_keymax; i++)
364 ath_hal_keyreset(ah, i);
367 * Collect the channel list using the default country
368 * code and including outdoor channels. The 802.11 layer
369 * is resposible for filtering this list based on settings
372 error = ath_getchannels(sc, ath_countrycode,
373 ath_outdoor, ath_xchanmode);
378 * Setup rate tables for all potential media types.
380 ath_rate_setup(sc, IEEE80211_MODE_11A);
381 ath_rate_setup(sc, IEEE80211_MODE_11B);
382 ath_rate_setup(sc, IEEE80211_MODE_11G);
383 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
384 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
386 /* NB: setup here so ath_rate_update is happy */
387 ath_setcurmode(sc, IEEE80211_MODE_11A);
390 * Allocate tx+rx descriptors and populate the lists.
392 error = ath_desc_alloc(sc);
394 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
398 callout_init(&sc->sc_scan_ch);
399 callout_init(&sc->sc_cal_ch);
400 callout_init(&sc->sc_dfs_ch);
403 * Allocate hardware transmit queues: one queue for
404 * beacon frames and one data queue for each QoS
405 * priority. Note that the hal handles reseting
406 * these queues at the needed time.
410 sc->sc_bhalq = ath_beaconq_setup(ah);
411 if (sc->sc_bhalq == (u_int)-1) {
412 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
417 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
418 if (sc->sc_cabq == NULL) {
419 if_printf(ifp, "unable to setup CAB xmit queue!\n");
424 ath_txq_init(sc, &sc->sc_mcastq, -1); /* NB: s/w q, qnum not used */
426 /* NB: insure BK queue is the lowest priority h/w queue */
427 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
428 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
429 ieee80211_wme_acnames[WME_AC_BK]);
433 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
434 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
435 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
437 * Not enough hardware tx queues to properly do WME;
438 * just punt and assign them all to the same h/w queue.
439 * We could do a better job of this if, for example,
440 * we allocate queues when we switch from station to
443 if (sc->sc_ac2q[WME_AC_VI] != NULL)
444 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
445 if (sc->sc_ac2q[WME_AC_BE] != NULL)
446 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
447 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
448 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
449 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
453 * Special case certain configurations. Note the
454 * CAB queue is handled by these specially so don't
455 * include them when checking the txq setup mask.
457 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
459 sc->sc_tx_proc = ath_tx_proc_q0;
461 if_printf(ifp, "single TX queue\n");
464 sc->sc_tx_proc = ath_tx_proc_q0123;
466 if_printf(ifp, "four TX queues\n");
469 sc->sc_tx_proc = ath_tx_proc;
474 * Setup rate control. Some rate control modules
475 * call back to change the anntena state so expose
476 * the necessary entry points.
477 * XXX maybe belongs in struct ath_ratectrl?
479 sc->sc_setdefantenna = ath_setdefantenna;
480 sc->sc_rc = ath_rate_attach(sc);
481 if (sc->sc_rc == NULL) {
488 sc->sc_ledon = 0; /* low true */
489 sc->sc_ledidle = (2700 * hz) / 1000; /* 2.7sec */
490 callout_init(&sc->sc_ledtimer);
493 * Auto-enable soft led processing for IBM cards and for
494 * 5211 minipci cards. Users can also manually enable/disable
495 * support with a sysctl.
497 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
498 if (sc->sc_softled) {
499 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin);
500 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
504 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
505 ifp->if_start = ath_start;
506 ifp->if_watchdog = ath_watchdog;
507 ifp->if_ioctl = ath_ioctl;
508 ifp->if_init = ath_init;
509 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
510 ifq_set_ready(&ifp->if_snd);
512 ic->ic_reset = ath_reset;
513 ic->ic_newassoc = ath_newassoc;
514 ic->ic_updateslot = ath_updateslot;
515 ic->ic_wme.wme_update = ath_wme_update;
516 /* XXX not right but it's not used anywhere important */
517 ic->ic_phytype = IEEE80211_T_OFDM;
518 ic->ic_opmode = IEEE80211_M_STA;
520 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
521 | IEEE80211_C_HOSTAP /* hostap mode */
522 | IEEE80211_C_MONITOR /* monitor mode */
523 | IEEE80211_C_AHDEMO /* adhoc demo mode */
524 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
525 | IEEE80211_C_SHSLOT /* short slot time supported */
526 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
529 * Query the hal to figure out h/w crypto support.
531 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
532 ic->ic_caps |= IEEE80211_C_WEP;
533 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
534 ic->ic_caps |= IEEE80211_C_AES;
535 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
536 ic->ic_caps |= IEEE80211_C_AES_CCM;
537 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
538 ic->ic_caps |= IEEE80211_C_CKIP;
539 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
540 ic->ic_caps |= IEEE80211_C_TKIP;
542 * Check if h/w does the MIC and/or whether the
543 * separate key cache entries are required to
544 * handle both tx+rx MIC keys.
546 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
547 ic->ic_caps |= IEEE80211_C_TKIPMIC;
549 * If the h/w supports storing tx+rx MIC keys
550 * in one cache slot automatically enable use.
552 if (ath_hal_hastkipsplit(ah) ||
553 !ath_hal_settkipsplit(ah, AH_FALSE))
556 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
557 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
559 * Mark key cache slots associated with global keys
560 * as in use. If we knew TKIP was not to be used we
561 * could leave the +32, +64, and +32+64 slots free.
563 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
564 setbit(sc->sc_keymap, i);
565 setbit(sc->sc_keymap, i+64);
566 if (sc->sc_splitmic) {
567 setbit(sc->sc_keymap, i+32);
568 setbit(sc->sc_keymap, i+32+64);
572 * TPC support can be done either with a global cap or
573 * per-packet support. The latter is not available on
574 * all parts. We're a bit pedantic here as all parts
575 * support a global cap.
577 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
578 ic->ic_caps |= IEEE80211_C_TXPMGT;
581 * Mark WME capability only if we have sufficient
582 * hardware queues to do proper priority scheduling.
584 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
585 ic->ic_caps |= IEEE80211_C_WME;
587 * Check for misc other capabilities.
589 if (ath_hal_hasbursting(ah))
590 ic->ic_caps |= IEEE80211_C_BURST;
593 * Indicate we need the 802.11 header padded to a
594 * 32-bit boundary for 4-address and QoS frames.
596 ic->ic_flags |= IEEE80211_F_DATAPAD;
599 * Query the hal about antenna support.
601 sc->sc_defant = ath_hal_getdefantenna(ah);
604 * Not all chips have the VEOL support we want to
605 * use with IBSS beacons; check here for it.
607 sc->sc_hasveol = ath_hal_hasveol(ah);
609 /* get mac address from hardware */
610 ath_hal_getmac(ah, ic->ic_myaddr);
612 /* call MI attach routine. */
613 ieee80211_ifattach(ic);
614 sc->sc_opmode = ic->ic_opmode;
615 /* override default methods */
616 ic->ic_node_alloc = ath_node_alloc;
617 sc->sc_node_free = ic->ic_node_free;
618 ic->ic_node_free = ath_node_free;
619 ic->ic_node_getrssi = ath_node_getrssi;
620 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
621 ic->ic_recv_mgmt = ath_recv_mgmt;
622 sc->sc_newstate = ic->ic_newstate;
623 ic->ic_newstate = ath_newstate;
624 ic->ic_crypto.cs_max_keyix = sc->sc_keymax;
625 ic->ic_crypto.cs_key_alloc = ath_key_alloc;
626 ic->ic_crypto.cs_key_delete = ath_key_delete;
627 ic->ic_crypto.cs_key_set = ath_key_set;
628 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin;
629 ic->ic_crypto.cs_key_update_end = ath_key_update_end;
630 /* complete initialization */
631 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status);
635 * Setup dynamic sysctl's now that country code and
636 * regdomain are available from the hal.
638 ath_sysctlattach(sc);
640 error = bus_setup_intr(sc->sc_dev, sc->sc_irq, INTR_MPSAFE, ath_intr,
641 sc, &sc->sc_ih, ifp->if_serializer);
643 if_printf(ifp, "could not establish interrupt\n");
645 ieee80211_ifdetach(ic);
650 ieee80211_announce(ic);
660 ath_detach(struct ath_softc *sc)
662 struct ifnet *ifp = &sc->sc_ic.ic_if;
664 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
665 __func__, ifp->if_flags);
668 * NB: the order of these is important:
669 * o call the 802.11 layer before detaching the hal to
670 * insure callbacks into the driver to delete global
671 * key cache entries can be handled
672 * o reclaim the tx queue data structures after calling
673 * the 802.11 layer as we'll get called back to reclaim
674 * node state and potentially want to use them
675 * o to cleanup the tx queues the hal is called, so detach
677 * Other than that, it's straightforward...
680 if (device_is_attached(sc->sc_dev)) {
681 lwkt_serialize_enter(ifp->if_serializer);
683 ath_rate_stop(sc->sc_rc);
686 * It seems power changing in ath_stop() will freeze
687 * ath_hal_releasetxqueue(), which is called by
688 * ath_tx_cleanup() below.
691 ath_stop_no_pwchg(ifp);
695 bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih);
697 lwkt_serialize_exit(ifp->if_serializer);
700 ieee80211_ifdetach(&sc->sc_ic);
703 if (sc->sc_rc != NULL)
704 ath_rate_detach(sc->sc_rc);
711 ath_hal_detach(sc->sc_ah);
713 if (sc->sc_irq != NULL) {
714 bus_release_resource(sc->sc_dev, SYS_RES_IRQ, sc->sc_irq_rid,
718 if (sc->sc_sysctl_tree != NULL)
719 sysctl_ctx_free(&sc->sc_sysctl_ctx);
725 ath_suspend(struct ath_softc *sc)
727 struct ifnet *ifp = &sc->sc_ic.ic_if;
729 lwkt_serialize_enter(ifp->if_serializer);
731 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
732 __func__, ifp->if_flags);
735 lwkt_serialize_exit(ifp->if_serializer);
739 ath_resume(struct ath_softc *sc)
741 struct ifnet *ifp = &sc->sc_ic.ic_if;
743 lwkt_serialize_enter(ifp->if_serializer);
745 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
746 __func__, ifp->if_flags);
748 if (ifp->if_flags & IFF_UP) {
750 if (ifp->if_flags & IFF_RUNNING)
753 if (sc->sc_softled) {
754 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
755 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
758 lwkt_serialize_exit(ifp->if_serializer);
762 ath_shutdown(struct ath_softc *sc)
764 struct ifnet *ifp = &sc->sc_ic.ic_if;
766 lwkt_serialize_enter(ifp->if_serializer);
768 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
769 __func__, ifp->if_flags);
772 lwkt_serialize_exit(ifp->if_serializer);
776 * Interrupt handler. Most of the actual processing is deferred.
781 struct ath_softc *sc = arg;
782 struct ifnet *ifp = &sc->sc_ic.ic_if;
783 struct ath_hal *ah = sc->sc_ah;
786 if (sc->sc_invalid) {
788 * The hardware is not ready/present, don't touch anything.
789 * Note this can happen early on if the IRQ is shared.
791 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
794 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
796 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) !=
797 (IFF_UP | IFF_RUNNING)) {
798 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
799 __func__, ifp->if_flags);
800 ath_hal_getisr(ah, &status); /* clear ISR */
801 ath_hal_intrset(ah, 0); /* disable further intr's */
805 * Figure out the reason(s) for the interrupt. Note
806 * that the hal returns a pseudo-ISR that may include
807 * bits we haven't explicitly enabled so we mask the
808 * value to insure we only process bits we requested.
810 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
811 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
812 status &= sc->sc_imask; /* discard unasked for bits */
813 if (status & HAL_INT_FATAL) {
815 * Fatal errors are unrecoverable. Typically
816 * these are caused by DMA errors. Unfortunately
817 * the exact reason is not (presently) returned
820 sc->sc_stats.ast_hardware++;
821 ath_hal_intrset(ah, 0); /* disable intr's until reset */
823 } else if (status & HAL_INT_RXORN) {
824 sc->sc_stats.ast_rxorn++;
825 ath_hal_intrset(ah, 0); /* disable intr's until reset */
828 if (status & HAL_INT_SWBA) {
830 * Software beacon alert--time to send a beacon.
831 * Handle beacon transmission directly; deferring
832 * this is too slow to meet timing constraints
837 if (status & HAL_INT_RXEOL) {
839 * NB: the hardware should re-read the link when
840 * RXE bit is written, but it doesn't work at
841 * least on older hardware revs.
843 sc->sc_stats.ast_rxeol++;
844 sc->sc_rxlink = NULL;
846 if (status & HAL_INT_TXURN) {
847 sc->sc_stats.ast_txurn++;
848 /* bump tx trigger level */
849 ath_hal_updatetxtriglevel(ah, AH_TRUE);
851 if (status & HAL_INT_RX)
853 if (status & HAL_INT_TX)
855 if (status & HAL_INT_BMISS) {
856 sc->sc_stats.ast_bmiss++;
859 if (status & HAL_INT_MIB) {
860 sc->sc_stats.ast_mib++;
862 * Disable interrupts until we service the MIB
863 * interrupt; otherwise it will continue to fire.
865 ath_hal_intrset(ah, 0);
867 * Let the hal handle the event. We assume it will
868 * clear whatever condition caused the interrupt.
870 ath_hal_mibevent(ah, &sc->sc_halstats);
871 ath_hal_intrset(ah, sc->sc_imask);
877 ath_fatal_proc(struct ath_softc *sc)
879 struct ifnet *ifp = &sc->sc_ic.ic_if;
883 if_printf(ifp, "hardware error; resetting\n");
886 * Fatal errors are unrecoverable. Typically these
887 * are caused by DMA errors. Collect h/w state from
888 * the hal so we can diagnose what's going on.
890 if (ath_hal_getfatalstate(sc->sc_ah, &state, &len)) {
891 KASSERT(len >= (6 * sizeof(uint32_t)), ("len %u bytes", len));
892 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
893 state[0], state[1] , state[2], state[3],
901 ath_rxorn_proc(struct ath_softc *sc)
903 struct ifnet *ifp = &sc->sc_ic.ic_if;
905 if_printf(ifp, "rx FIFO overrun; resetting\n");
910 ath_bmiss_proc(struct ath_softc *sc)
912 struct ieee80211com *ic = &sc->sc_ic;
914 DPRINTF(sc, ATH_DEBUG_ANY, "%s\n", __func__);
915 KASSERT(ic->ic_opmode == IEEE80211_M_STA,
916 ("unexpect operating mode %u", ic->ic_opmode));
917 if (ic->ic_state == IEEE80211_S_RUN) {
918 uint64_t lastrx = sc->sc_lastrx;
919 uint64_t tsf = ath_hal_gettsf64(sc->sc_ah);
921 ic->ic_bmissthreshold * ic->ic_bss->ni_intval * 1024;
923 DPRINTF(sc, ATH_DEBUG_BEACON,
924 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
925 __func__, (unsigned long long) tsf,
926 (unsigned long long)(tsf - lastrx),
927 (unsigned long long) lastrx, bmisstimeout);
929 * Workaround phantom bmiss interrupts by sanity-checking
930 * the time of our last rx'd frame. If it is within the
931 * beacon miss interval then ignore the interrupt. If it's
932 * truly a bmiss we'll get another interrupt soon and that'll
933 * be dispatched up for processing.
935 if (tsf - lastrx > bmisstimeout)
936 ieee80211_beacon_miss(ic);
938 sc->sc_stats.ast_bmiss_phantom++;
943 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan)
945 #define N(a) (sizeof(a) / sizeof(a[0]))
946 static const u_int modeflags[] = {
947 0, /* IEEE80211_MODE_AUTO */
948 CHANNEL_A, /* IEEE80211_MODE_11A */
949 CHANNEL_B, /* IEEE80211_MODE_11B */
950 CHANNEL_PUREG, /* IEEE80211_MODE_11G */
951 0, /* IEEE80211_MODE_FH */
952 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */
953 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */
955 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan);
957 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode));
958 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode));
959 return modeflags[mode];
963 /* XXX error cleanup */
967 struct ath_softc *sc = arg;
968 struct ieee80211com *ic = &sc->sc_ic;
969 struct ifnet *ifp = &ic->ic_if;
970 struct ath_hal *ah = sc->sc_ah;
973 ASSERT_SERIALIZED(ifp->if_serializer);
975 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
976 __func__, ifp->if_flags);
979 * Stop anything previously setup. This is safe
980 * whether this is the first time through or not.
982 ath_stop_no_pwchg(ifp);
985 * The basic interface to setting the hardware in a good
986 * state is ``reset''. On return the hardware is known to
987 * be powered up and with interrupts disabled. This must
988 * be followed by initialization of the appropriate bits
989 * and then setup of the interrupt mask.
991 sc->sc_curchan.channel = ic->ic_curchan->ic_freq;
992 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan);
993 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE,
995 if_printf(ifp, "unable to reset hardware; hal status %u\n",
1001 * This is needed only to setup initial state
1002 * but it's best done after a reset.
1004 ath_update_txpow(sc);
1006 * Likewise this is set during reset so update
1007 * state cached in the driver.
1009 sc->sc_diversity = ath_hal_getdiversity(ah);
1010 sc->sc_calinterval = 1;
1011 sc->sc_caltries = 0;
1014 * Setup the hardware after reset: the key cache
1015 * is filled as needed and the receive engine is
1016 * set going. Frame transmit is handled entirely
1017 * in the frame output path; there's nothing to do
1018 * here except setup the interrupt mask.
1020 if (ath_startrecv(sc) != 0) {
1021 if_printf(ifp, "unable to start recv logic\n");
1026 * Enable interrupts.
1028 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1029 | HAL_INT_RXEOL | HAL_INT_RXORN
1030 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1032 * Enable MIB interrupts when there are hardware phy counters.
1033 * Note we only do this (at the moment) for station mode.
1035 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
1036 sc->sc_imask |= HAL_INT_MIB;
1037 ath_hal_intrset(ah, sc->sc_imask);
1039 ifp->if_flags |= IFF_RUNNING;
1040 ic->ic_state = IEEE80211_S_INIT;
1043 * The hardware should be ready to go now so it's safe
1044 * to kick the 802.11 state machine as it's likely to
1045 * immediately call back to us to send mgmt frames.
1047 ath_chan_change(sc, ic->ic_curchan);
1048 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1049 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1050 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1052 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1057 ath_stop_no_pwchg(struct ifnet *ifp)
1059 struct ath_softc *sc = ifp->if_softc;
1060 struct ieee80211com *ic = &sc->sc_ic;
1061 struct ath_hal *ah = sc->sc_ah;
1063 ASSERT_SERIALIZED(ifp->if_serializer);
1065 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
1066 __func__, sc->sc_invalid, ifp->if_flags);
1068 if (ifp->if_flags & IFF_RUNNING) {
1070 * Shutdown the hardware and driver:
1071 * reset 802.11 state machine
1073 * disable interrupts
1074 * turn off the radio
1075 * clear transmit machinery
1076 * clear receive machinery
1077 * drain and release tx queues
1078 * reclaim beacon resources
1079 * power down hardware
1081 * Note that some of this work is not possible if the
1082 * hardware is gone (invalid).
1084 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1085 ifp->if_flags &= ~IFF_RUNNING;
1087 if (!sc->sc_invalid) {
1088 if (sc->sc_softled) {
1089 callout_stop(&sc->sc_ledtimer);
1090 ath_hal_gpioset(ah, sc->sc_ledpin,
1092 sc->sc_blinking = 0;
1094 ath_hal_intrset(ah, 0);
1097 if (!sc->sc_invalid) {
1099 ath_hal_phydisable(ah);
1101 sc->sc_rxlink = NULL;
1103 ifq_purge(&ifp->if_snd);
1105 ath_beacon_free(sc);
1110 ath_stop(struct ifnet *ifp)
1112 struct ath_softc *sc = ifp->if_softc;
1114 ASSERT_SERIALIZED(ifp->if_serializer);
1116 ath_stop_no_pwchg(ifp);
1117 if (!sc->sc_invalid) {
1119 * Set the chip in full sleep mode. Note that we are
1120 * careful to do this only when bringing the interface
1121 * completely to a stop. When the chip is in this state
1122 * it must be carefully woken up or references to
1123 * registers in the PCI clock domain may freeze the bus
1124 * (and system). This varies by chip and is mostly an
1125 * issue with newer parts that go to sleep more quickly.
1127 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
1132 * Reset the hardware w/o losing operational state. This is
1133 * basically a more efficient way of doing ath_stop, ath_init,
1134 * followed by state transitions to the current 802.11
1135 * operational state. Used to recover from various errors and
1136 * to reset or reload hardware state.
1139 ath_reset(struct ifnet *ifp)
1141 struct ath_softc *sc = ifp->if_softc;
1142 struct ieee80211com *ic = &sc->sc_ic;
1143 struct ath_hal *ah = sc->sc_ah;
1144 struct ieee80211_channel *c;
1147 ASSERT_SERIALIZED(ifp->if_serializer);
1150 * Convert to a HAL channel description with the flags
1151 * constrained to reflect the current operating mode.
1154 sc->sc_curchan.channel = c->ic_freq;
1155 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c);
1157 ath_hal_intrset(ah, 0); /* disable interrupts */
1158 ath_draintxq(sc); /* stop xmit side */
1159 ath_stoprecv(sc); /* stop recv side */
1160 /* NB: indicate channel change so we do a full reset */
1161 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE,
1163 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1166 ath_update_txpow(sc); /* update tx power state */
1167 sc->sc_diversity = ath_hal_getdiversity(ah);
1168 sc->sc_calinterval = 1;
1169 sc->sc_caltries = 0;
1171 * We may be doing a reset in response to an ioctl
1172 * that changes the channel so update any state that
1173 * might change as a result.
1175 ath_chan_change(sc, c);
1176 if (ath_startrecv(sc) != 0) /* restart recv */
1177 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1178 if (ic->ic_state == IEEE80211_S_RUN)
1179 ath_beacon_config(sc); /* restart beacons */
1180 ath_hal_intrset(ah, sc->sc_imask);
1182 ath_start(ifp); /* restart xmit */
1187 ath_start(struct ifnet *ifp)
1189 struct ath_softc *sc = ifp->if_softc;
1190 struct ath_hal *ah = sc->sc_ah;
1191 struct ieee80211com *ic = &sc->sc_ic;
1192 struct ieee80211_node *ni;
1195 struct ieee80211_frame *wh;
1196 struct ether_header *eh;
1198 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid)
1203 * Grab a TX buffer and associated resources.
1205 bf = STAILQ_FIRST(&sc->sc_txbuf);
1207 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1209 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n",
1211 sc->sc_stats.ast_tx_qstop++;
1212 ifp->if_flags |= IFF_OACTIVE;
1216 * Poll the management queue for frames; they
1217 * have priority over normal data frames.
1219 IF_DEQUEUE(&ic->ic_mgtq, m);
1222 * No data frames go out unless we're associated.
1224 if (ic->ic_state != IEEE80211_S_RUN) {
1225 DPRINTF(sc, ATH_DEBUG_XMIT,
1226 "%s: discard data packet, state %s\n",
1228 ieee80211_state_name[ic->ic_state]);
1229 sc->sc_stats.ast_tx_discard++;
1230 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1233 m = ifq_dequeue(&ifp->if_snd, NULL);
1235 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1239 * Find the node for the destination so we can do
1240 * things like power save and fast frames aggregation.
1242 if (m->m_len < sizeof(struct ether_header) &&
1243 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) {
1244 ic->ic_stats.is_tx_nobuf++; /* XXX */
1248 eh = mtod(m, struct ether_header *);
1249 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1251 /* NB: ieee80211_find_txnode does stat+msg */
1255 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) &&
1256 (m->m_flags & M_PWR_SAV) == 0) {
1258 * Station in power save mode; pass the frame
1259 * to the 802.11 layer and continue. We'll get
1260 * the frame back when the time is right.
1262 ieee80211_pwrsave(ic, ni, m);
1265 /* calculate priority so we can find the tx queue */
1266 if (ieee80211_classify(ic, m, ni)) {
1267 DPRINTF(sc, ATH_DEBUG_XMIT,
1268 "%s: discard, classification failure\n",
1276 * Encapsulate the packet in prep for transmission.
1278 m = ieee80211_encap(ic, m, ni);
1280 DPRINTF(sc, ATH_DEBUG_XMIT,
1281 "%s: encapsulation failure\n",
1283 sc->sc_stats.ast_tx_encap++;
1288 * Hack! The referenced node pointer is in the
1289 * rcvif field of the packet header. This is
1290 * placed there by ieee80211_mgmt_output because
1291 * we need to hold the reference with the frame
1292 * and there's no other way (other than packet
1293 * tags which we consider too expensive to use)
1296 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1297 m->m_pkthdr.rcvif = NULL;
1299 wh = mtod(m, struct ieee80211_frame *);
1300 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1301 IEEE80211_FC0_SUBTYPE_PROBE_RESP) {
1302 /* fill time stamp */
1306 tsf = ath_hal_gettsf64(ah);
1307 /* XXX: adjust 100us delay to xmit */
1309 tstamp = (uint32_t *)&wh[1];
1310 tstamp[0] = htole32(tsf & 0xffffffff);
1311 tstamp[1] = htole32(tsf >> 32);
1313 sc->sc_stats.ast_tx_mgmt++;
1316 if (ath_tx_start(sc, ni, bf, m)) {
1320 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1322 ieee80211_free_node(ni);
1326 sc->sc_tx_timer = 5;
1332 ath_media_change(struct ifnet *ifp)
1334 #define IS_UP(ifp) \
1335 ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_RUNNING | IFF_UP))
1338 error = ieee80211_media_change(ifp);
1339 if (error == ENETRESET) {
1340 struct ath_softc *sc = ifp->if_softc;
1341 struct ieee80211com *ic = &sc->sc_ic;
1343 if (ic->ic_opmode == IEEE80211_M_AHDEMO) {
1345 * Adhoc demo mode is just ibss mode w/o beacons
1346 * (mostly). The hal knows nothing about it;
1347 * tell it we're operating in ibss mode.
1349 sc->sc_opmode = HAL_M_IBSS;
1351 sc->sc_opmode = ic->ic_opmode;
1353 ath_init(ifp->if_softc); /* XXX lose error */
1362 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix,
1363 const HAL_KEYVAL *hk, const uint8_t mac[IEEE80211_ADDR_LEN])
1365 static const char *ciphers[] = {
1375 kprintf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1376 for (i = 0, n = hk->kv_len; i < n; i++)
1377 kprintf("%02x", hk->kv_val[i]);
1378 kprintf(" mac %6D", mac, ":");
1379 if (hk->kv_type == HAL_CIPHER_TKIP) {
1380 kprintf(" %s ", sc->sc_splitmic ? "mic" : "rxmic");
1381 for (i = 0; i < sizeof(hk->kv_mic); i++)
1382 kprintf("%02x", hk->kv_mic[i]);
1383 #if HAL_ABI_VERSION > 0x06052200
1384 if (!sc->sc_splitmic) {
1386 for (i = 0; i < sizeof(hk->kv_txmic); i++)
1387 kprintf("%02x", hk->kv_txmic[i]);
1396 * Set a TKIP key into the hardware. This handles the
1397 * potential distribution of key state to multiple key
1398 * cache slots for TKIP.
1401 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1402 HAL_KEYVAL *hk, const uint8_t mac[IEEE80211_ADDR_LEN])
1404 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1405 static const uint8_t zerobssid[IEEE80211_ADDR_LEN];
1406 struct ath_hal *ah = sc->sc_ah;
1408 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1409 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1410 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1411 if (sc->sc_splitmic) {
1413 * TX key goes at first index, RX key at the rx index.
1414 * The hal handles the MIC keys at index+64.
1416 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1417 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1418 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1421 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1422 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1423 /* XXX delete tx key on failure? */
1424 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1427 * Room for both TX+RX MIC keys in one key cache
1428 * slot, just set key at the first index; the hal
1429 * will handle the reset.
1431 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1432 #if HAL_ABI_VERSION > 0x06052200
1433 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic));
1435 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1436 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1438 } else if (k->wk_flags & IEEE80211_KEY_XR) {
1440 * TX/RX key goes at first index.
1441 * The hal handles the MIC keys are index+64.
1443 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ?
1444 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic));
1445 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1446 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1449 #undef IEEE80211_KEY_XR
1453 * Set a net80211 key into the hardware. This handles the
1454 * potential distribution of key state to multiple key
1455 * cache slots for TKIP with hardware MIC support.
1458 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
1459 const uint8_t mac0[IEEE80211_ADDR_LEN],
1460 struct ieee80211_node *bss)
1462 #define N(a) (sizeof(a)/sizeof(a[0]))
1463 static const uint8_t ciphermap[] = {
1464 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
1465 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
1466 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
1467 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
1468 (uint8_t) -1, /* 4 is not allocated */
1469 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
1470 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
1472 struct ath_hal *ah = sc->sc_ah;
1473 const struct ieee80211_cipher *cip = k->wk_cipher;
1474 uint8_t gmac[IEEE80211_ADDR_LEN];
1478 memset(&hk, 0, sizeof(hk));
1480 * Software crypto uses a "clear key" so non-crypto
1481 * state kept in the key cache are maintained and
1482 * so that rx frames have an entry to match.
1484 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
1485 KASSERT(cip->ic_cipher < N(ciphermap),
1486 ("invalid cipher type %u", cip->ic_cipher));
1487 hk.kv_type = ciphermap[cip->ic_cipher];
1488 hk.kv_len = k->wk_keylen;
1489 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
1491 hk.kv_type = HAL_CIPHER_CLR;
1493 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
1495 * Group keys on hardware that supports multicast frame
1496 * key search use a mac that is the sender's address with
1497 * the high bit set instead of the app-specified address.
1499 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
1505 if (hk.kv_type == HAL_CIPHER_TKIP &&
1506 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
1507 return ath_keyset_tkip(sc, k, &hk, mac);
1509 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
1510 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
1516 * Allocate tx/rx key slots for TKIP. We allocate two slots for
1517 * each key, one for decrypt/encrypt and the other for the MIC.
1520 key_alloc_2pair(struct ath_softc *sc,
1521 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1523 #define N(a) (sizeof(a)/sizeof(a[0]))
1526 KASSERT(sc->sc_splitmic, ("key cache !split"));
1527 /* XXX could optimize */
1528 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
1529 uint8_t b = sc->sc_keymap[i];
1532 * One or more slots in this byte are free.
1540 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
1541 if (isset(sc->sc_keymap, keyix+32) ||
1542 isset(sc->sc_keymap, keyix+64) ||
1543 isset(sc->sc_keymap, keyix+32+64)) {
1544 /* full pair unavailable */
1546 if (keyix == (i+1)*NBBY) {
1547 /* no slots were appropriate, advance */
1552 setbit(sc->sc_keymap, keyix);
1553 setbit(sc->sc_keymap, keyix+64);
1554 setbit(sc->sc_keymap, keyix+32);
1555 setbit(sc->sc_keymap, keyix+32+64);
1556 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1557 "%s: key pair %u,%u %u,%u\n",
1558 __func__, keyix, keyix+64,
1559 keyix+32, keyix+32+64);
1561 *rxkeyix = keyix+32;
1565 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
1571 * Allocate tx/rx key slots for TKIP. We allocate two slots for
1572 * each key, one for decrypt/encrypt and the other for the MIC.
1575 key_alloc_pair(struct ath_softc *sc,
1576 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1578 #define N(a) (sizeof(a)/sizeof(a[0]))
1581 KASSERT(!sc->sc_splitmic, ("key cache split"));
1582 /* XXX could optimize */
1583 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
1584 uint8_t b = sc->sc_keymap[i];
1587 * One or more slots in this byte are free.
1595 if (isset(sc->sc_keymap, keyix+64)) {
1596 /* full pair unavailable */
1598 if (keyix == (i+1)*NBBY) {
1599 /* no slots were appropriate, advance */
1604 setbit(sc->sc_keymap, keyix);
1605 setbit(sc->sc_keymap, keyix+64);
1606 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1607 "%s: key pair %u,%u\n",
1608 __func__, keyix, keyix+64);
1609 *txkeyix = *rxkeyix = keyix;
1613 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
1619 * Allocate a single key cache slot.
1622 key_alloc_single(struct ath_softc *sc,
1623 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1625 #define N(a) (sizeof(a)/sizeof(a[0]))
1628 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
1629 for (i = 0; i < N(sc->sc_keymap); i++) {
1630 uint8_t b = sc->sc_keymap[i];
1633 * One or more slots are free.
1638 setbit(sc->sc_keymap, keyix);
1639 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
1641 *txkeyix = *rxkeyix = keyix;
1645 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
1651 * Allocate one or more key cache slots for a uniacst key. The
1652 * key itself is needed only to identify the cipher. For hardware
1653 * TKIP with split cipher+MIC keys we allocate two key cache slot
1654 * pairs so that we can setup separate TX and RX MIC keys. Note
1655 * that the MIC key for a TKIP key at slot i is assumed by the
1656 * hardware to be at slot i+64. This limits TKIP keys to the first
1660 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k,
1661 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
1663 struct ath_softc *sc = ic->ic_ifp->if_softc;
1666 * Group key allocation must be handled specially for
1667 * parts that do not support multicast key cache search
1668 * functionality. For those parts the key id must match
1669 * the h/w key index so lookups find the right key. On
1670 * parts w/ the key search facility we install the sender's
1671 * mac address (with the high bit set) and let the hardware
1672 * find the key w/o using the key id. This is preferred as
1673 * it permits us to support multiple users for adhoc and/or
1674 * multi-station operation.
1676 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) {
1677 if (!(&ic->ic_nw_keys[0] <= k &&
1678 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) {
1679 /* should not happen */
1680 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1681 "%s: bogus group key\n", __func__);
1685 * XXX we pre-allocate the global keys so
1686 * have no way to check if they've already been allocated.
1688 *keyix = *rxkeyix = k - ic->ic_nw_keys;
1693 * We allocate two pair for TKIP when using the h/w to do
1694 * the MIC. For everything else, including software crypto,
1695 * we allocate a single entry. Note that s/w crypto requires
1696 * a pass-through slot on the 5211 and 5212. The 5210 does
1697 * not support pass-through cache entries and we map all
1698 * those requests to slot 0.
1700 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
1701 return key_alloc_single(sc, keyix, rxkeyix);
1702 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
1703 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
1704 if (sc->sc_splitmic)
1705 return key_alloc_2pair(sc, keyix, rxkeyix);
1707 return key_alloc_pair(sc, keyix, rxkeyix);
1709 return key_alloc_single(sc, keyix, rxkeyix);
1714 * Delete an entry in the key cache allocated by ath_key_alloc.
1717 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
1719 struct ath_softc *sc = ic->ic_ifp->if_softc;
1720 struct ath_hal *ah = sc->sc_ah;
1721 const struct ieee80211_cipher *cip = k->wk_cipher;
1722 u_int keyix = k->wk_keyix;
1724 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
1726 ath_hal_keyreset(ah, keyix);
1728 * Handle split tx/rx keying required for TKIP with h/w MIC.
1730 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1731 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic)
1732 ath_hal_keyreset(ah, keyix+32); /* RX key */
1733 if (keyix >= IEEE80211_WEP_NKID) {
1735 * Don't touch keymap entries for global keys so
1736 * they are never considered for dynamic allocation.
1738 clrbit(sc->sc_keymap, keyix);
1739 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1740 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
1741 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
1742 if (sc->sc_splitmic) {
1743 /* +32 for RX key, +32+64 for RX key MIC */
1744 clrbit(sc->sc_keymap, keyix+32);
1745 clrbit(sc->sc_keymap, keyix+32+64);
1753 * Set the key cache contents for the specified key. Key cache
1754 * slot(s) must already have been allocated by ath_key_alloc.
1757 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
1758 const uint8_t mac[IEEE80211_ADDR_LEN])
1760 struct ath_softc *sc = ic->ic_ifp->if_softc;
1762 return ath_keyset(sc, k, mac, ic->ic_bss);
1766 * Block/unblock tx+rx processing while a key change is done.
1767 * We assume the caller serializes key management operations
1768 * so we only need to worry about synchronization with other
1769 * uses that originate in the driver.
1772 ath_key_update_begin(struct ieee80211com *ic)
1774 struct ifnet *ifp = ic->ic_ifp;
1775 struct ath_softc *sc = ifp->if_softc;
1777 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1779 tasklet_disable(&sc->sc_rxtq);
1780 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
1785 ath_key_update_end(struct ieee80211com *ic)
1787 struct ifnet *ifp = ic->ic_ifp;
1788 struct ath_softc *sc = ifp->if_softc;
1790 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1792 IF_UNLOCK(&ifp->if_snd);
1793 tasklet_enable(&sc->sc_rxtq);
1798 * Calculate the receive filter according to the
1799 * operating mode and state:
1801 * o always accept unicast, broadcast, and multicast traffic
1802 * o maintain current state of phy error reception (the hal
1803 * may enable phy error frames for noise immunity work)
1804 * o probe request frames are accepted only when operating in
1805 * hostap, adhoc, or monitor modes
1806 * o enable promiscuous mode according to the interface state
1808 * - when operating in adhoc mode so the 802.11 layer creates
1809 * node table entries for peers,
1810 * - when operating in station mode for collecting rssi data when
1811 * the station is otherwise quiet, or
1813 * o accept control frames:
1814 * - when in monitor mode
1817 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state)
1819 #define RX_FILTER_PRESERVE (HAL_RX_FILTER_PHYERR | HAL_RX_FILTER_PHYRADAR)
1820 struct ieee80211com *ic = &sc->sc_ic;
1821 struct ath_hal *ah = sc->sc_ah;
1822 struct ifnet *ifp = &ic->ic_if;
1825 rfilt = (ath_hal_getrxfilter(ah) & RX_FILTER_PRESERVE)
1826 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
1827 if (ic->ic_opmode != IEEE80211_M_STA)
1828 rfilt |= HAL_RX_FILTER_PROBEREQ;
1829 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
1830 (ifp->if_flags & IFF_PROMISC))
1831 rfilt |= HAL_RX_FILTER_PROM;
1832 if (ic->ic_opmode == IEEE80211_M_STA ||
1833 ic->ic_opmode == IEEE80211_M_IBSS ||
1834 state == IEEE80211_S_SCAN)
1835 rfilt |= HAL_RX_FILTER_BEACON;
1836 if (ic->ic_opmode == IEEE80211_M_MONITOR)
1837 rfilt |= HAL_RX_FILTER_CONTROL;
1839 #undef RX_FILTER_PRESERVE
1843 ath_mode_init(struct ath_softc *sc)
1845 struct ieee80211com *ic = &sc->sc_ic;
1846 struct ath_hal *ah = sc->sc_ah;
1847 struct ifnet *ifp = &ic->ic_if;
1848 uint32_t rfilt, mfilt[2], val;
1850 struct ifmultiaddr *ifma;
1852 /* configure rx filter */
1853 rfilt = ath_calcrxfilter(sc, ic->ic_state);
1854 ath_hal_setrxfilter(ah, rfilt);
1856 /* configure operational mode */
1857 ath_hal_setopmode(ah);
1860 * Handle any link-level address change. Note that we only
1861 * need to force ic_myaddr; any other addresses are handled
1862 * as a byproduct of the ifnet code marking the interface
1865 * XXX should get from lladdr instead of arpcom but that's more work
1867 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
1868 ath_hal_setmac(ah, ic->ic_myaddr);
1870 /* calculate and install multicast filter */
1871 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1872 mfilt[0] = mfilt[1] = 0;
1873 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1876 /* calculate XOR of eight 6bit values */
1877 dl = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1878 val = LE_READ_4(dl + 0);
1879 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1880 val = LE_READ_4(dl + 3);
1881 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1883 mfilt[pos / 32] |= (1 << (pos % 32));
1886 mfilt[0] = mfilt[1] = ~0;
1888 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]);
1889 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n",
1890 __func__, rfilt, mfilt[0], mfilt[1]);
1894 * Set the slot time based on the current setting.
1897 ath_setslottime(struct ath_softc *sc)
1899 struct ieee80211com *ic = &sc->sc_ic;
1900 struct ath_hal *ah = sc->sc_ah;
1902 if (ic->ic_flags & IEEE80211_F_SHSLOT)
1903 ath_hal_setslottime(ah, HAL_SLOT_TIME_9);
1905 ath_hal_setslottime(ah, HAL_SLOT_TIME_20);
1906 sc->sc_updateslot = OK;
1910 * Callback from the 802.11 layer to update the
1911 * slot time based on the current setting.
1914 ath_updateslot(struct ifnet *ifp)
1916 struct ath_softc *sc = ifp->if_softc;
1917 struct ieee80211com *ic = &sc->sc_ic;
1920 * When not coordinating the BSS, change the hardware
1921 * immediately. For other operation we defer the change
1922 * until beacon updates have propagated to the stations.
1924 if (ic->ic_opmode == IEEE80211_M_HOSTAP)
1925 sc->sc_updateslot = UPDATE;
1927 ath_setslottime(sc);
1931 * Setup a h/w transmit queue for beacons.
1934 ath_beaconq_setup(struct ath_hal *ah)
1938 memset(&qi, 0, sizeof(qi));
1939 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
1940 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
1941 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
1942 /* NB: for dynamic turbo, don't enable any other interrupts */
1943 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
1944 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
1948 * Setup the transmit queue parameters for the beacon queue.
1951 ath_beaconq_config(struct ath_softc *sc)
1953 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
1954 struct ieee80211com *ic = &sc->sc_ic;
1955 struct ath_hal *ah = sc->sc_ah;
1958 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
1959 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1961 * Always burst out beacon and CAB traffic.
1963 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
1964 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
1965 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
1967 struct wmeParams *wmep =
1968 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
1970 * Adhoc mode; important thing is to use 2x cwmin.
1972 qi.tqi_aifs = wmep->wmep_aifsn;
1973 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
1974 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
1977 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
1978 device_printf(sc->sc_dev, "unable to update parameters for "
1979 "beacon hardware queue!\n");
1982 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
1985 #undef ATH_EXPONENT_TO_VALUE
1989 * Allocate and setup an initial beacon frame.
1992 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
1994 struct ieee80211com *ic = ni->ni_ic;
1999 bf = STAILQ_FIRST(&sc->sc_bbuf);
2001 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__);
2002 sc->sc_stats.ast_be_nombuf++; /* XXX */
2003 return ENOMEM; /* XXX */
2006 * NB: the beacon data buffer must be 32-bit aligned;
2007 * we assume the mbuf routines will return us something
2008 * with this alignment (perhaps should assert).
2010 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff);
2012 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n",
2014 sc->sc_stats.ast_be_nombuf++;
2018 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m,
2019 ath_dma_map_mbuf, bf, BUS_DMA_NOWAIT);
2022 bf->bf_node = ieee80211_ref_node(ni);
2030 * Setup the beacon frame for transmit.
2033 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
2035 #define USE_SHPREAMBLE(_ic) \
2036 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
2037 == IEEE80211_F_SHPREAMBLE)
2038 struct ieee80211_node *ni = bf->bf_node;
2039 struct ieee80211com *ic = ni->ni_ic;
2040 struct mbuf *m = bf->bf_m;
2041 struct ath_hal *ah = sc->sc_ah;
2042 struct ath_desc *ds;
2044 const HAL_RATE_TABLE *rt;
2047 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
2048 __func__, m, m->m_len);
2050 /* setup descriptors */
2053 flags = HAL_TXDESC_NOACK;
2054 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
2055 ds->ds_link = bf->bf_daddr; /* self-linked */
2056 flags |= HAL_TXDESC_VEOL;
2058 * Let hardware handle antenna switching.
2060 antenna = sc->sc_txantenna;
2064 * Switch antenna every 4 beacons.
2065 * XXX assumes two antenna
2067 antenna = sc->sc_txantenna != 0 ? sc->sc_txantenna
2068 : (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
2071 KASSERT(bf->bf_nseg == 1,
2072 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
2073 ds->ds_data = bf->bf_segs[0].ds_addr;
2075 * Calculate rate code.
2076 * XXX everything at min xmit rate
2078 rix = sc->sc_minrateix;
2079 rt = sc->sc_currates;
2080 rate = rt->info[rix].rateCode;
2081 if (USE_SHPREAMBLE(ic))
2082 rate |= rt->info[rix].shortPreamble;
2083 ath_hal_setuptxdesc(ah, ds
2084 , m->m_len + IEEE80211_CRC_LEN /* frame length */
2085 , sizeof(struct ieee80211_frame)/* header length */
2086 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
2087 , ni->ni_txpower /* txpower XXX */
2088 , rate, 1 /* series 0 rate/tries */
2089 , HAL_TXKEYIX_INVALID /* no encryption */
2090 , antenna /* antenna mode */
2091 , flags /* no ack, veol for beacons */
2092 , 0 /* rts/cts rate */
2093 , 0 /* rts/cts duration */
2095 /* NB: beacon's BufLen must be a multiple of 4 bytes */
2096 ath_hal_filltxdesc(ah, ds
2097 , roundup(m->m_len, 4) /* buffer length */
2098 , AH_TRUE /* first segment */
2099 , AH_TRUE /* last segment */
2100 , ds /* first descriptor */
2102 #undef USE_SHPREAMBLE
2106 * Append the contents of src to dst; both queues
2107 * are assumed to be locked.
2110 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
2112 STAILQ_CONCAT(&dst->axq_q, &src->axq_q);
2113 dst->axq_link = src->axq_link;
2114 src->axq_link = NULL;
2115 dst->axq_depth += src->axq_depth;
2120 * Transmit a beacon frame at SWBA. Dynamic updates to the
2121 * frame contents are done as needed and the slot time is
2122 * also adjusted based on current state.
2125 ath_beacon_proc(struct ath_softc *sc)
2127 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
2128 struct ieee80211_node *ni = bf->bf_node;
2129 struct ieee80211com *ic = ni->ni_ic;
2130 struct ath_hal *ah = sc->sc_ah;
2131 struct ath_txq *cabq = sc->sc_cabq;
2133 int ncabq, nmcastq, error, otherant;
2135 if (ic->ic_opmode == IEEE80211_M_STA ||
2136 ic->ic_opmode == IEEE80211_M_MONITOR ||
2137 bf == NULL || bf->bf_m == NULL) {
2138 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n",
2139 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL);
2143 * Check if the previous beacon has gone out. If
2144 * not don't try to post another, skip this period
2145 * and wait for the next. Missed beacons indicate
2146 * a problem and should not occur. If we miss too
2147 * many consecutive beacons reset the device.
2149 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
2150 sc->sc_bmisscount++;
2151 DPRINTF(sc, ATH_DEBUG_BEACON,
2152 "%s: missed %u consecutive beacons\n",
2153 __func__, sc->sc_bmisscount);
2154 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */
2155 ath_bstuck_proc(sc);
2158 if (sc->sc_bmisscount != 0) {
2159 DPRINTF(sc, ATH_DEBUG_BEACON,
2160 "%s: resume beacon xmit after %u misses\n",
2161 __func__, sc->sc_bmisscount);
2162 sc->sc_bmisscount = 0;
2166 * Update dynamic beacon contents. If this returns
2167 * non-zero then we need to remap the memory because
2168 * the beacon frame changed size (probably because
2169 * of the TIM bitmap).
2172 nmcastq = sc->sc_mcastq.axq_depth;
2173 ncabq = ath_hal_numtxpending(ah, cabq->axq_qnum);
2174 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m,
2176 /* XXX too conservative? */
2177 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2178 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m,
2179 ath_dma_map_mbuf, bf,
2182 if_printf(ic->ic_ifp,
2183 "%s: bus_dmamap_load_mbuf failed, error %u\n",
2189 if (ncabq && (sc->sc_boff.bo_tim[4] & 1)) {
2191 * CABQ traffic from the previous DTIM is still pending.
2192 * This is ok for now but when there are multiple vap's
2193 * and we are using staggered beacons we'll want to drain
2194 * the cabq before loading frames for the different vap.
2196 DPRINTF(sc, ATH_DEBUG_BEACON,
2197 "%s: cabq did not drain, mcastq %u cabq %u/%u\n",
2198 __func__, nmcastq, ncabq, cabq->axq_depth);
2199 sc->sc_stats.ast_cabq_busy++;
2203 * Handle slot time change when a non-ERP station joins/leaves
2204 * an 11g network. The 802.11 layer notifies us via callback,
2205 * we mark updateslot, then wait one beacon before effecting
2206 * the change. This gives associated stations at least one
2207 * beacon interval to note the state change.
2210 if (sc->sc_updateslot == UPDATE)
2211 sc->sc_updateslot = COMMIT; /* commit next beacon */
2212 else if (sc->sc_updateslot == COMMIT)
2213 ath_setslottime(sc); /* commit change to h/w */
2216 * Check recent per-antenna transmit statistics and flip
2217 * the default antenna if noticeably more frames went out
2218 * on the non-default antenna.
2219 * XXX assumes 2 anntenae
2221 otherant = sc->sc_defant & 1 ? 2 : 1;
2222 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
2223 ath_setdefantenna(sc, otherant);
2224 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
2227 * Construct tx descriptor.
2229 ath_beacon_setup(sc, bf);
2232 * Stop any current dma and put the new frame on the queue.
2233 * This should never fail since we check above that no frames
2234 * are still pending on the queue.
2236 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2237 DPRINTF(sc, ATH_DEBUG_ANY,
2238 "%s: beacon queue %u did not stop?\n",
2239 __func__, sc->sc_bhalq);
2241 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2244 * Enable the CAB queue before the beacon queue to
2245 * insure cab frames are triggered by this beacon.
2247 if (sc->sc_boff.bo_tim_len && (sc->sc_boff.bo_tim[4] & 1)) {
2248 /* NB: only at DTIM */
2250 struct ath_buf *bfm;
2253 * Move frames from the s/w mcast q to the h/w cab q.
2255 bfm = STAILQ_FIRST(&sc->sc_mcastq.axq_q);
2256 if (cabq->axq_link != NULL) {
2257 *cabq->axq_link = bfm->bf_daddr;
2259 ath_hal_puttxbuf(ah, cabq->axq_qnum,
2262 ath_txqmove(cabq, &sc->sc_mcastq);
2264 sc->sc_stats.ast_cabq_xmit += nmcastq;
2266 /* NB: gated by beacon so safe to start here */
2267 ath_hal_txstart(ah, cabq->axq_qnum);
2269 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
2270 ath_hal_txstart(ah, sc->sc_bhalq);
2271 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
2272 "%s: TXDP[%u] = %p (%p)\n", __func__,
2273 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc);
2275 sc->sc_stats.ast_be_xmit++;
2279 * Reset the hardware after detecting beacons have stopped.
2282 ath_bstuck_proc(struct ath_softc *sc)
2284 struct ifnet *ifp = &sc->sc_ic.ic_if;
2286 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
2292 * Reclaim beacon resources.
2295 ath_beacon_free(struct ath_softc *sc)
2299 ASSERT_SERIALIZED(sc->sc_ic.ic_if.if_serializer);
2301 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
2302 if (bf->bf_m != NULL) {
2303 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2307 if (bf->bf_node != NULL) {
2308 ieee80211_free_node(bf->bf_node);
2315 * Configure the beacon and sleep timers.
2317 * When operating as an AP this resets the TSF and sets
2318 * up the hardware to notify us when we need to issue beacons.
2320 * When operating in station mode this sets up the beacon
2321 * timers according to the timestamp of the last received
2322 * beacon and the current TSF, configures PCF and DTIM
2323 * handling, programs the sleep registers so the hardware
2324 * will wakeup in time to receive beacons, and configures
2325 * the beacon miss handling so we'll receive a BMISS
2326 * interrupt when we stop seeing beacons from the AP
2327 * we've associated with.
2330 ath_beacon_config(struct ath_softc *sc)
2332 #define TSF_TO_TU(_h,_l) \
2333 ((((uint32_t)(_h)) << 22) | (((uint32_t)(_l)) >> 10))
2335 struct ath_hal *ah = sc->sc_ah;
2336 struct ieee80211com *ic = &sc->sc_ic;
2337 struct ieee80211_node *ni = ic->ic_bss;
2338 uint32_t nexttbtt, intval, tsftu;
2341 /* extract tstamp from last beacon and convert to TU */
2342 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
2343 LE_READ_4(ni->ni_tstamp.data));
2344 /* NB: the beacon interval is kept internally in TU's */
2345 intval = ni->ni_intval & HAL_BEACON_PERIOD;
2346 if (nexttbtt == 0) /* e.g. for ap mode */
2348 else if (intval) /* NB: can be 0 for monitor mode */
2349 nexttbtt = roundup(nexttbtt, intval);
2350 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
2351 __func__, nexttbtt, intval, ni->ni_intval);
2352 if (ic->ic_opmode == IEEE80211_M_STA) {
2353 HAL_BEACON_STATE bs;
2354 int dtimperiod, dtimcount;
2355 int cfpperiod, cfpcount;
2358 * Setup dtim and cfp parameters according to
2359 * last beacon we received (which may be none).
2361 dtimperiod = ni->ni_dtim_period;
2362 if (dtimperiod <= 0) /* NB: 0 if not known */
2364 dtimcount = ni->ni_dtim_count;
2365 if (dtimcount >= dtimperiod) /* NB: sanity check */
2366 dtimcount = 0; /* XXX? */
2367 cfpperiod = 1; /* NB: no PCF support yet */
2370 * Pull nexttbtt forward to reflect the current
2371 * TSF and calculate dtim+cfp state for the result.
2373 tsf = ath_hal_gettsf64(ah);
2374 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
2377 if (--dtimcount < 0) {
2378 dtimcount = dtimperiod - 1;
2380 cfpcount = cfpperiod - 1;
2382 } while (nexttbtt < tsftu);
2383 memset(&bs, 0, sizeof(bs));
2384 bs.bs_intval = intval;
2385 bs.bs_nexttbtt = nexttbtt;
2386 bs.bs_dtimperiod = dtimperiod*intval;
2387 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
2388 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
2389 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
2390 bs.bs_cfpmaxduration = 0;
2393 * The 802.11 layer records the offset to the DTIM
2394 * bitmap while receiving beacons; use it here to
2395 * enable h/w detection of our AID being marked in
2396 * the bitmap vector (to indicate frames for us are
2397 * pending at the AP).
2398 * XXX do DTIM handling in s/w to WAR old h/w bugs
2399 * XXX enable based on h/w rev for newer chips
2401 bs.bs_timoffset = ni->ni_timoff;
2404 * Calculate the number of consecutive beacons to miss
2405 * before taking a BMISS interrupt. The configuration
2406 * is specified in ms, so we need to convert that to
2407 * TU's and then calculate based on the beacon interval.
2408 * Note that we clamp the result to at most 10 beacons.
2410 bs.bs_bmissthreshold = ic->ic_bmissthreshold;
2411 if (bs.bs_bmissthreshold > 10)
2412 bs.bs_bmissthreshold = 10;
2413 else if (bs.bs_bmissthreshold <= 0)
2414 bs.bs_bmissthreshold = 1;
2417 * Calculate sleep duration. The configuration is
2418 * given in ms. We insure a multiple of the beacon
2419 * period is used. Also, if the sleep duration is
2420 * greater than the DTIM period then it makes senses
2421 * to make it a multiple of that.
2423 * XXX fixed at 100ms
2425 bs.bs_sleepduration =
2426 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
2427 if (bs.bs_sleepduration > bs.bs_dtimperiod)
2428 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
2430 DPRINTF(sc, ATH_DEBUG_BEACON,
2431 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
2438 , bs.bs_bmissthreshold
2439 , bs.bs_sleepduration
2441 , bs.bs_cfpmaxduration
2445 ath_hal_intrset(ah, 0);
2446 ath_hal_beacontimers(ah, &bs);
2447 sc->sc_imask |= HAL_INT_BMISS;
2448 ath_hal_intrset(ah, sc->sc_imask);
2450 ath_hal_intrset(ah, 0);
2451 if (nexttbtt == intval)
2452 intval |= HAL_BEACON_RESET_TSF;
2453 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2455 * In IBSS mode enable the beacon timers but only
2456 * enable SWBA interrupts if we need to manually
2457 * prepare beacon frames. Otherwise we use a
2458 * self-linked tx descriptor and let the hardware
2461 intval |= HAL_BEACON_ENA;
2462 if (!sc->sc_hasveol)
2463 sc->sc_imask |= HAL_INT_SWBA;
2464 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
2466 * Pull nexttbtt forward to reflect
2469 tsf = ath_hal_gettsf64(ah);
2470 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
2473 } while (nexttbtt < tsftu);
2475 ath_beaconq_config(sc);
2476 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2478 * In AP mode we enable the beacon timers and
2479 * SWBA interrupts to prepare beacon frames.
2481 intval |= HAL_BEACON_ENA;
2482 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
2483 ath_beaconq_config(sc);
2485 ath_hal_beaconinit(ah, nexttbtt, intval);
2486 sc->sc_bmisscount = 0;
2487 ath_hal_intrset(ah, sc->sc_imask);
2489 * When using a self-linked beacon descriptor in
2490 * ibss mode load it once here.
2492 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
2493 ath_beacon_proc(sc);
2495 sc->sc_syncbeacon = 0;
2501 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2503 bus_addr_t *paddr = (bus_addr_t*) arg;
2504 KASSERT(error == 0, ("error %u on bus_dma callback", error));
2505 *paddr = segs->ds_addr;
2509 ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2510 ath_bufhead *head, const char *name, int nbuf, int ndesc)
2512 #define DS2PHYS(_dd, _ds) \
2513 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2514 struct ifnet *ifp = &sc->sc_ic.ic_if;
2515 struct ath_desc *ds;
2517 int i, bsize, error;
2519 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
2520 __func__, name, nbuf, ndesc);
2523 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2527 * Setup DMA descriptor area.
2529 error = bus_dma_tag_create(NULL, /* parent */
2530 PAGE_SIZE, 0, /* alignment, bounds */
2531 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2532 BUS_SPACE_MAXADDR, /* highaddr */
2533 NULL, NULL, /* filter, filterarg */
2534 dd->dd_desc_len, /* maxsize */
2536 dd->dd_desc_len, /* maxsegsize */
2537 BUS_DMA_ALLOCNOW, /* flags */
2540 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
2544 /* allocate descriptors */
2545 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_WAITOK, &dd->dd_dmamap);
2547 if_printf(ifp, "unable to create dmamap for %s descriptors, "
2548 "error %u\n", dd->dd_name, error);
2552 error = bus_dmamem_alloc(dd->dd_dmat, (void **)&dd->dd_desc,
2553 BUS_DMA_WAITOK, &dd->dd_dmamap);
2555 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
2556 "error %u\n", nbuf * ndesc, dd->dd_name, error);
2560 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
2561 dd->dd_desc, dd->dd_desc_len,
2562 ath_load_cb, &dd->dd_desc_paddr,
2565 if_printf(ifp, "unable to map %s descriptors, error %u\n",
2566 dd->dd_name, error);
2568 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2574 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2575 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
2576 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
2578 /* allocate rx buffers */
2579 bsize = sizeof(struct ath_buf) * nbuf;
2580 bf = kmalloc(bsize, M_ATHDEV, M_WAITOK | M_ZERO);
2583 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2585 bf->bf_daddr = DS2PHYS(dd, ds);
2586 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_WAITOK,
2589 if_printf(ifp, "unable to create dmamap for %s "
2590 "buffer %u, error %u\n", dd->dd_name, i, error);
2591 ath_descdma_cleanup(sc, dd, head);
2594 STAILQ_INSERT_TAIL(head, bf, bf_list);
2600 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2602 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2604 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2606 bus_dma_tag_destroy(dd->dd_dmat);
2607 memset(dd, 0, sizeof(*dd));
2614 ath_descdma_cleanup(struct ath_softc *sc,
2615 struct ath_descdma *dd, ath_bufhead *head)
2618 struct ieee80211_node *ni;
2620 if (dd->dd_desc != NULL) {
2621 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2622 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2626 if (dd->dd_dmamap != NULL) {
2627 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2628 dd->dd_dmamap = NULL;
2631 if (dd->dd_dmat != NULL) {
2632 bus_dma_tag_destroy(dd->dd_dmat);
2636 STAILQ_FOREACH(bf, head, bf_list) {
2641 if (bf->bf_dmamap != NULL) {
2642 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
2643 bf->bf_dmamap = NULL;
2649 * Reclaim node reference.
2651 ieee80211_free_node(ni);
2656 if (dd->dd_bufptr != NULL)
2657 kfree(dd->dd_bufptr, M_ATHDEV);
2658 memset(dd, 0, sizeof(*dd));
2662 ath_desc_alloc(struct ath_softc *sc)
2666 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
2667 "rx", ath_rxbuf, 1);
2671 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2672 "tx", ath_txbuf, ATH_TXDESC);
2676 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2684 ath_desc_free(struct ath_softc *sc)
2687 if (sc->sc_bdma.dd_desc_len != 0) {
2688 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2689 sc->sc_bdma.dd_desc_len = 0;
2691 if (sc->sc_txdma.dd_desc_len != 0) {
2692 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2693 sc->sc_txdma.dd_desc_len = 0;
2695 if (sc->sc_rxdma.dd_desc_len != 0) {
2696 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2697 sc->sc_rxdma.dd_desc_len = 0;
2701 static struct ieee80211_node *
2702 ath_node_alloc(struct ieee80211_node_table *nt)
2704 struct ieee80211com *ic = nt->nt_ic;
2705 struct ath_softc *sc = ic->ic_ifp->if_softc;
2706 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
2707 struct ath_node *an;
2709 an = kmalloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
2714 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER;
2715 ath_rate_node_init(sc, an);
2717 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
2718 return &an->an_node;
2722 ath_node_free(struct ieee80211_node *ni)
2724 struct ieee80211com *ic = ni->ni_ic;
2725 struct ath_softc *sc = ic->ic_ifp->if_softc;
2727 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
2729 ath_rate_node_cleanup(sc, ATH_NODE(ni));
2730 sc->sc_node_free(ni);
2734 ath_node_getrssi(const struct ieee80211_node *ni)
2736 #define HAL_EP_RND(x, mul) \
2737 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
2738 uint32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi;
2742 * When only one frame is received there will be no state in
2743 * avgrssi so fallback on the value recorded by the 802.11 layer.
2745 if (avgrssi != ATH_RSSI_DUMMY_MARKER)
2746 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER);
2749 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi;
2754 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
2756 struct ath_hal *ah = sc->sc_ah;
2759 struct ath_desc *ds;
2764 * NB: by assigning a page to the rx dma buffer we
2765 * implicitly satisfy the Atheros requirement that
2766 * this buffer be cache-line-aligned and sized to be
2767 * multiple of the cache line size. Not doing this
2768 * causes weird stuff to happen (for the 5210 at least).
2770 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2772 DPRINTF(sc, ATH_DEBUG_ANY,
2773 "%s: no mbuf/cluster\n", __func__);
2774 sc->sc_stats.ast_rx_nombuf++;
2777 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
2779 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m,
2780 ath_dma_map_mbuf, bf,
2783 DPRINTF(sc, ATH_DEBUG_ANY,
2784 "%s: bus_dmamap_load_mbuf failed; error %d\n",
2786 sc->sc_stats.ast_rx_busdma++;
2790 KASSERT(bf->bf_nseg == 1,
2791 ("multi-segment packet; nseg %u", bf->bf_nseg));
2794 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
2797 * Setup descriptors. For receive we always terminate
2798 * the descriptor list with a self-linked entry so we'll
2799 * not get overrun under high load (as can happen with a
2800 * 5212 when ANI processing enables PHY error frames).
2802 * To insure the last descriptor is self-linked we create
2803 * each descriptor as self-linked and add it to the end. As
2804 * each additional descriptor is added the previous self-linked
2805 * entry is ``fixed'' naturally. This should be safe even
2806 * if DMA is happening. When processing RX interrupts we
2807 * never remove/process the last, self-linked, entry on the
2808 * descriptor list. This insures the hardware always has
2809 * someplace to write a new frame.
2812 ds->ds_link = bf->bf_daddr; /* link to self */
2813 ds->ds_data = bf->bf_segs[0].ds_addr;
2814 ath_hal_setuprxdesc(ah, ds
2815 , m->m_len /* buffer size */
2819 if (sc->sc_rxlink != NULL)
2820 *sc->sc_rxlink = bf->bf_daddr;
2821 sc->sc_rxlink = &ds->ds_link;
2826 * Extend 15-bit time stamp from rx descriptor to
2827 * a full 64-bit TSF using the specified TSF.
2829 static __inline uint64_t
2830 ath_extend_tsf(uint32_t rstamp, uint64_t tsf)
2832 if ((tsf & 0x7fff) < rstamp)
2834 return ((tsf &~ 0x7fff) | rstamp);
2838 * Intercept management frames to collect beacon rssi data
2839 * and to do ibss merges.
2842 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
2843 struct ieee80211_node *ni,
2844 int subtype, int rssi, uint32_t rstamp)
2846 struct ath_softc *sc = ic->ic_ifp->if_softc;
2849 * Call up first so subsequent work can use information
2850 * potentially stored in the node (e.g. for ibss merge).
2852 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
2854 case IEEE80211_FC0_SUBTYPE_BEACON:
2855 /* update rssi statistics for use by the hal */
2856 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
2857 if (sc->sc_syncbeacon &&
2858 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) {
2860 * Resync beacon timers using the tsf of the beacon
2861 * frame we just received.
2863 ath_beacon_config(sc);
2866 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
2867 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2868 ic->ic_state == IEEE80211_S_RUN) {
2869 uint64_t tsf = ath_extend_tsf(rstamp,
2870 ath_hal_gettsf64(sc->sc_ah));
2872 * Handle ibss merge as needed; check the tsf on the
2873 * frame before attempting the merge. The 802.11 spec
2874 * says the station should change it's bssid to match
2875 * the oldest station with the same ssid, where oldest
2876 * is determined by the tsf. Note that hardware
2877 * reconfiguration happens through callback to
2878 * ath_newstate as the state machine will go from
2879 * RUN -> RUN when this happens.
2881 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
2882 DPRINTF(sc, ATH_DEBUG_STATE,
2883 "ibss merge, rstamp %u tsf %ju "
2884 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
2885 (uintmax_t)ni->ni_tstamp.tsf);
2886 ieee80211_ibss_merge(ni);
2894 * Set the default antenna.
2897 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
2899 struct ath_hal *ah = sc->sc_ah;
2901 /* XXX block beacon interrupts */
2902 ath_hal_setdefantenna(ah, antenna);
2903 if (sc->sc_defant != antenna)
2904 sc->sc_stats.ast_ant_defswitch++;
2905 sc->sc_defant = antenna;
2906 sc->sc_rxotherant = 0;
2910 ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
2911 const struct ath_rx_status *rs, uint64_t tsf, int16_t nf)
2915 KASSERT(sc->sc_drvbpf != NULL, ("no tap"));
2918 * Discard anything shorter than an ack or cts.
2920 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) {
2921 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n",
2922 __func__, m->m_pkthdr.len);
2923 sc->sc_stats.ast_rx_tooshort++;
2926 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf));
2928 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
2929 if (rs->rs_status & HAL_RXERR_CRC)
2930 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
2931 /* XXX propagate other error flags from descriptor */
2932 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
2933 sc->sc_rx_th.wr_antsignal = rs->rs_rssi + nf;
2934 sc->sc_rx_th.wr_antnoise = nf;
2935 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
2937 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
2943 ath_rx_proc(struct ath_softc *sc)
2945 #define PA2DESC(_sc, _pa) \
2946 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
2947 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
2949 struct ieee80211com *ic = &sc->sc_ic;
2950 struct ifnet *ifp = &ic->ic_if;
2951 struct ath_hal *ah = sc->sc_ah;
2952 struct ath_desc *ds;
2953 struct ath_rx_status *rs;
2955 struct ieee80211_node *ni;
2956 struct ath_node *an;
2957 int len, type, ngood;
2964 nf = ath_hal_getchannoise(ah, &sc->sc_curchan);
2965 tsf = ath_hal_gettsf64(ah);
2967 bf = STAILQ_FIRST(&sc->sc_rxbuf);
2968 if (bf == NULL) { /* NB: shouldn't happen */
2969 if_printf(ifp, "%s: no buffer!\n", __func__);
2973 if (m == NULL) { /* NB: shouldn't happen */
2975 * If mbuf allocation failed previously there
2976 * will be no mbuf; try again to re-populate it.
2978 /* XXX make debug msg */
2979 if_printf(ifp, "%s: no mbuf!\n", __func__);
2980 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2984 if (ds->ds_link == bf->bf_daddr) {
2985 /* NB: never process the self-linked entry at the end */
2988 /* XXX sync descriptor memory */
2990 * Must provide the virtual address of the current
2991 * descriptor, the physical address, and the virtual
2992 * address of the next descriptor in the h/w chain.
2993 * This allows the HAL to look ahead to see if the
2994 * hardware is done with a descriptor by checking the
2995 * done bit in the following descriptor and the address
2996 * of the current descriptor the DMA engine is working
2997 * on. All this is necessary because of our use of
2998 * a self-linked list to avoid rx overruns.
3000 rs = &bf->bf_status.ds_rxstat;
3001 status = ath_hal_rxprocdesc(ah, ds,
3002 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
3004 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
3005 ath_printrxbuf(bf, 0, status == HAL_OK);
3007 if (status == HAL_EINPROGRESS)
3009 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
3012 * Frame spans multiple descriptors; this
3013 * cannot happen yet as we don't support
3014 * jumbograms. If not in monitor mode,
3015 * discard the frame.
3017 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3018 sc->sc_stats.ast_rx_toobig++;
3021 /* fall thru for monitor mode handling... */
3022 } else if (rs->rs_status != 0) {
3023 if (rs->rs_status & HAL_RXERR_CRC)
3024 sc->sc_stats.ast_rx_crcerr++;
3025 if (rs->rs_status & HAL_RXERR_FIFO)
3026 sc->sc_stats.ast_rx_fifoerr++;
3027 if (rs->rs_status & HAL_RXERR_PHY) {
3028 sc->sc_stats.ast_rx_phyerr++;
3029 phyerr = rs->rs_phyerr & 0x1f;
3030 sc->sc_stats.ast_rx_phy[phyerr]++;
3033 if (rs->rs_status & HAL_RXERR_DECRYPT) {
3035 * Decrypt error. If the error occurred
3036 * because there was no hardware key, then
3037 * let the frame through so the upper layers
3038 * can process it. This is necessary for 5210
3039 * parts which have no way to setup a ``clear''
3042 * XXX do key cache faulting
3044 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
3046 sc->sc_stats.ast_rx_badcrypt++;
3048 if (rs->rs_status & HAL_RXERR_MIC) {
3049 sc->sc_stats.ast_rx_badmic++;
3051 * Do minimal work required to hand off
3052 * the 802.11 header for notifcation.
3054 /* XXX frag's and qos frames */
3055 len = rs->rs_datalen;
3056 if (len >= sizeof (struct ieee80211_frame)) {
3057 bus_dmamap_sync(sc->sc_dmat,
3059 BUS_DMASYNC_POSTREAD);
3060 ieee80211_notify_michael_failure(ic,
3061 mtod(m, struct ieee80211_frame *),
3063 rs->rs_keyix-32 : rs->rs_keyix
3069 * When a tap is present pass error frames
3070 * that have been requested. By default we
3071 * pass decrypt+mic errors but others may be
3072 * interesting (e.g. crc).
3074 if (sc->sc_drvbpf != NULL &&
3075 (rs->rs_status & sc->sc_monpass)) {
3076 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3077 BUS_DMASYNC_POSTREAD);
3078 /* NB: bpf needs the mbuf length setup */
3079 len = rs->rs_datalen;
3080 m->m_pkthdr.len = m->m_len = len;
3081 ath_rx_tap(sc, m, rs, tsf, nf);
3083 /* XXX pass MIC errors up for s/w reclaculation */
3088 * Sync and unmap the frame. At this point we're
3089 * committed to passing the mbuf somewhere so clear
3090 * bf_m; this means a new mbuf must be allocated
3091 * when the rx descriptor is setup again to receive
3094 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3095 BUS_DMASYNC_POSTREAD);
3096 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3099 m->m_pkthdr.rcvif = ifp;
3100 len = rs->rs_datalen;
3101 m->m_pkthdr.len = m->m_len = len;
3103 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
3105 if (sc->sc_drvbpf != NULL && !ath_rx_tap(sc, m, rs, tsf, nf)) {
3106 m_freem(m); /* XXX reclaim */
3111 * From this point on we assume the frame is at least
3112 * as large as ieee80211_frame_min; verify that.
3114 if (len < IEEE80211_MIN_LEN) {
3115 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
3117 sc->sc_stats.ast_rx_tooshort++;
3122 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
3123 ieee80211_dump_pkt(mtod(m, caddr_t), len,
3124 sc->sc_hwmap[rs->rs_rate].ieeerate,
3128 m_adj(m, -IEEE80211_CRC_LEN);
3131 * Locate the node for sender, track state, and then
3132 * pass the (referenced) node up to the 802.11 layer
3135 ni = ieee80211_find_rxnode_withkey(ic,
3136 mtod(m, const struct ieee80211_frame_min *),
3137 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
3138 IEEE80211_KEYIX_NONE : rs->rs_keyix);
3140 * Track rx rssi and do any rx antenna management.
3143 ATH_RSSI_LPF(an->an_avgrssi, rs->rs_rssi);
3144 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
3146 * Send frame up for processing.
3148 type = ieee80211_input(ic, m, ni, rs->rs_rssi, rs->rs_tstamp);
3149 ieee80211_free_node(ni);
3150 if (sc->sc_diversity) {
3152 * When using fast diversity, change the default rx
3153 * antenna if diversity chooses the other antenna 3
3156 if (sc->sc_defant != rs->rs_antenna) {
3157 if (++sc->sc_rxotherant >= 3)
3158 ath_setdefantenna(sc, rs->rs_antenna);
3160 sc->sc_rxotherant = 0;
3162 if (sc->sc_softled) {
3164 * Blink for any data frame. Otherwise do a
3165 * heartbeat-style blink when idle. The latter
3166 * is mainly for station mode where we depend on
3167 * periodic beacon frames to trigger the poll event.
3169 if (type == IEEE80211_FC0_TYPE_DATA) {
3170 sc->sc_rxrate = rs->rs_rate;
3171 ath_led_event(sc, ATH_LED_RX);
3172 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
3173 ath_led_event(sc, ATH_LED_POLL);
3176 * Arrange to update the last rx timestamp only for
3177 * frames from our ap when operating in station mode.
3178 * This assumes the rx key is always setup when associated.
3180 if (ic->ic_opmode == IEEE80211_M_STA &&
3181 rs->rs_keyix != HAL_RXKEYIX_INVALID)
3184 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
3185 } while (ath_rxbuf_init(sc, bf) == 0);
3187 /* rx signal state monitoring */
3188 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan);
3190 sc->sc_lastrx = tsf;
3195 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
3197 txq->axq_qnum = qnum;
3199 txq->axq_intrcnt = 0;
3200 txq->axq_link = NULL;
3201 STAILQ_INIT(&txq->axq_q);
3205 * Setup a h/w transmit queue.
3207 static struct ath_txq *
3208 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
3210 #define N(a) (sizeof(a)/sizeof(a[0]))
3211 struct ath_hal *ah = sc->sc_ah;
3215 memset(&qi, 0, sizeof(qi));
3216 qi.tqi_subtype = subtype;
3217 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
3218 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
3219 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
3221 * Enable interrupts only for EOL and DESC conditions.
3222 * We mark tx descriptors to receive a DESC interrupt
3223 * when a tx queue gets deep; otherwise waiting for the
3224 * EOL to reap descriptors. Note that this is done to
3225 * reduce interrupt load and this only defers reaping
3226 * descriptors, never transmitting frames. Aside from
3227 * reducing interrupts this also permits more concurrency.
3228 * The only potential downside is if the tx queue backs
3229 * up in which case the top half of the kernel may backup
3230 * due to a lack of tx descriptors.
3232 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
3233 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
3236 * NB: don't print a message, this happens
3237 * normally on parts with too few tx queues
3241 if (qnum >= N(sc->sc_txq)) {
3242 device_printf(sc->sc_dev,
3243 "hal qnum %u out of range, max %zu!\n",
3244 qnum, N(sc->sc_txq));
3245 ath_hal_releasetxqueue(ah, qnum);
3248 if (!IS_ATH_TXQ_SETUP(sc, qnum)) {
3249 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
3250 ATH_TXQ_SETUP(sc, qnum);
3252 return &sc->sc_txq[qnum];
3257 * Setup a hardware data transmit queue for the specified
3258 * access control. The hal may not support all requested
3259 * queues in which case it will return a reference to a
3260 * previously setup queue. We record the mapping from ac's
3261 * to h/w queues for use by ath_tx_start and also track
3262 * the set of h/w queues being used to optimize work in the
3263 * transmit interrupt handler and related routines.
3266 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
3268 #define N(a) (sizeof(a)/sizeof(a[0]))
3269 struct ath_txq *txq;
3271 if (ac >= N(sc->sc_ac2q)) {
3272 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
3273 ac, N(sc->sc_ac2q));
3276 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
3278 sc->sc_ac2q[ac] = txq;
3287 * Update WME parameters for a transmit queue.
3290 ath_txq_update(struct ath_softc *sc, int ac)
3292 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
3293 #define ATH_TXOP_TO_US(v) (v<<5)
3294 struct ieee80211com *ic = &sc->sc_ic;
3295 struct ath_txq *txq = sc->sc_ac2q[ac];
3296 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3297 struct ath_hal *ah = sc->sc_ah;
3300 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3301 qi.tqi_aifs = wmep->wmep_aifsn;
3302 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3303 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3304 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3306 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3307 device_printf(sc->sc_dev, "unable to update hardware queue "
3308 "parameters for %s traffic!\n",
3309 ieee80211_wme_acnames[ac]);
3312 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3315 #undef ATH_TXOP_TO_US
3316 #undef ATH_EXPONENT_TO_VALUE
3320 * Callback from the 802.11 layer to update WME parameters.
3323 ath_wme_update(struct ieee80211com *ic)
3325 struct ath_softc *sc = ic->ic_ifp->if_softc;
3327 return !ath_txq_update(sc, WME_AC_BE) ||
3328 !ath_txq_update(sc, WME_AC_BK) ||
3329 !ath_txq_update(sc, WME_AC_VI) ||
3330 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3334 * Reclaim resources for a setup queue.
3337 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3339 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3340 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3344 * Reclaim all tx queue resources.
3347 ath_tx_cleanup(struct ath_softc *sc)
3351 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3352 if (IS_ATH_TXQ_SETUP(sc, i))
3353 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3357 * Defragment an mbuf chain, returning at most maxfrags separate
3358 * mbufs+clusters. If this is not possible NULL is returned and
3359 * the original mbuf chain is left in it's present (potentially
3360 * modified) state. We use two techniques: collapsing consecutive
3361 * mbufs and replacing consecutive mbufs by a cluster.
3363 static struct mbuf *
3364 ath_defrag(struct mbuf *m0, int how, int maxfrags)
3366 struct mbuf *m, *n, *n2, **prev;
3370 * Calculate the current number of frags.
3373 for (m = m0; m != NULL; m = m->m_next)
3376 * First, try to collapse mbufs. Note that we always collapse
3377 * towards the front so we don't need to deal with moving the
3378 * pkthdr. This may be suboptimal if the first mbuf has much
3379 * less data than the following.
3387 if (n->m_len < M_TRAILINGSPACE(m)) {
3388 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
3390 m->m_len += n->m_len;
3391 m->m_next = n->m_next;
3393 if (--curfrags <= maxfrags)
3398 KASSERT(maxfrags > 1,
3399 ("maxfrags %u, but normal collapse failed", maxfrags));
3401 * Collapse consecutive mbufs to a cluster.
3403 prev = &m0->m_next; /* NB: not the first mbuf */
3404 while ((n = *prev) != NULL) {
3405 if ((n2 = n->m_next) != NULL &&
3406 n->m_len + n2->m_len < MCLBYTES) {
3407 m = m_getcl(how, MT_DATA, 0);
3410 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
3411 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
3413 m->m_len = n->m_len + n2->m_len;
3414 m->m_next = n2->m_next;
3418 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
3421 * Still not there, try the normal collapse
3422 * again before we allocate another cluster.
3429 * No place where we can collapse to a cluster; punt.
3430 * This can occur if, for example, you request 2 frags
3431 * but the packet requires that both be clusters (we
3432 * never reallocate the first mbuf to avoid moving the
3440 * Return h/w rate index for an IEEE rate (w/o basic rate bit).
3443 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate)
3447 for (i = 0; i < rt->rateCount; i++)
3448 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate)
3450 return 0; /* NB: lowest rate */
3454 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
3455 struct ath_buf *bf, struct mbuf *m0)
3457 struct ieee80211com *ic = &sc->sc_ic;
3458 struct ath_hal *ah = sc->sc_ah;
3459 struct ifnet *ifp = &ic->ic_if;
3460 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
3461 int i, error, iswep, ismcast, ismrr;
3462 int keyix, hdrlen, pktlen, try0;
3463 uint8_t rix, txrate, ctsrate;
3464 uint8_t cix = 0xff; /* NB: silence compiler */
3465 struct ath_desc *ds, *ds0;
3466 struct ath_txq *txq;
3467 struct ieee80211_frame *wh;
3468 u_int subtype, flags, ctsduration;
3470 const HAL_RATE_TABLE *rt;
3471 HAL_BOOL shortPreamble;
3472 struct ath_node *an;
3476 wh = mtod(m0, struct ieee80211_frame *);
3477 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
3478 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3479 hdrlen = ieee80211_anyhdrsize(wh);
3481 * Packet length must not include any
3482 * pad bytes; deduct them here.
3484 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
3487 const struct ieee80211_cipher *cip;
3488 struct ieee80211_key *k;
3491 * Construct the 802.11 header+trailer for an encrypted
3492 * frame. The only reason this can fail is because of an
3493 * unknown or unsupported cipher/key type.
3495 k = ieee80211_crypto_encap(ic, ni, m0);
3498 * This can happen when the key is yanked after the
3499 * frame was queued. Just discard the frame; the
3500 * 802.11 layer counts failures and provides
3501 * debugging/diagnostics.
3507 * Adjust the packet + header lengths for the crypto
3508 * additions and calculate the h/w key index. When
3509 * a s/w mic is done the frame will have had any mic
3510 * added to it prior to entry so m0->m_pkthdr.len above will
3511 * account for it. Otherwise we need to add it to the
3515 hdrlen += cip->ic_header;
3516 pktlen += cip->ic_header + cip->ic_trailer;
3517 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
3518 pktlen += cip->ic_miclen;
3519 keyix = k->wk_keyix;
3521 /* packet header may have moved, reset our local pointer */
3522 wh = mtod(m0, struct ieee80211_frame *);
3523 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
3525 * Use station key cache slot, if assigned.
3527 keyix = ni->ni_ucastkey.wk_keyix;
3528 if (keyix == IEEE80211_KEYIX_NONE)
3529 keyix = HAL_TXKEYIX_INVALID;
3531 keyix = HAL_TXKEYIX_INVALID;
3533 pktlen += IEEE80211_CRC_LEN;
3536 * Load the DMA map so any coalescing is done. This
3537 * also calculates the number of descriptors we need.
3539 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0,
3540 ath_dma_map_mbuf, bf, BUS_DMA_NOWAIT);
3541 if (error == EFBIG) {
3542 /* XXX packet requires too many descriptors */
3543 bf->bf_nseg = ATH_TXDESC+1;
3544 } else if (error != 0) {
3545 sc->sc_stats.ast_tx_busdma++;
3550 * Discard null packets and check for packets that
3551 * require too many TX descriptors. We try to convert
3552 * the latter to a cluster.
3554 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
3555 sc->sc_stats.ast_tx_linear++;
3556 m = ath_defrag(m0, MB_DONTWAIT, ATH_TXDESC);
3559 sc->sc_stats.ast_tx_nombuf++;
3563 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0,
3564 ath_dma_map_mbuf, bf,
3567 sc->sc_stats.ast_tx_busdma++;
3571 KASSERT(bf->bf_nseg <= ATH_TXDESC,
3572 ("too many segments after defrag; nseg %u", bf->bf_nseg));
3573 } else if (bf->bf_nseg == 0) { /* null packet, discard */
3574 sc->sc_stats.ast_tx_nodata++;
3578 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen);
3579 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3581 bf->bf_node = ni; /* NB: held reference */
3583 /* setup descriptors */
3585 rt = sc->sc_currates;
3586 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3589 * NB: the 802.11 layer marks whether or not we should
3590 * use short preamble based on the current mode and
3591 * negotiated parameters.
3593 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3594 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
3595 shortPreamble = AH_TRUE;
3596 sc->sc_stats.ast_tx_shortpre++;
3598 shortPreamble = AH_FALSE;
3602 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
3603 ismrr = 0; /* default no multi-rate retry*/
3605 * Calculate Atheros packet type from IEEE80211 packet header,
3606 * setup for rate calculations, and select h/w transmit queue.
3608 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
3609 case IEEE80211_FC0_TYPE_MGT:
3610 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3611 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
3612 atype = HAL_PKT_TYPE_BEACON;
3613 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3614 atype = HAL_PKT_TYPE_PROBE_RESP;
3615 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
3616 atype = HAL_PKT_TYPE_ATIM;
3618 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
3619 rix = sc->sc_minrateix;
3620 txrate = rt->info[rix].rateCode;
3622 txrate |= rt->info[rix].shortPreamble;
3623 try0 = ATH_TXMGTTRY;
3624 /* NB: force all management frames to highest queue */
3625 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3626 /* NB: force all management frames to highest queue */
3630 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3632 case IEEE80211_FC0_TYPE_CTL:
3633 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
3634 rix = sc->sc_minrateix;
3635 txrate = rt->info[rix].rateCode;
3637 txrate |= rt->info[rix].shortPreamble;
3638 try0 = ATH_TXMGTTRY;
3639 /* NB: force all ctl frames to highest queue */
3640 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3641 /* NB: force all ctl frames to highest queue */
3645 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3647 case IEEE80211_FC0_TYPE_DATA:
3648 atype = HAL_PKT_TYPE_NORMAL; /* default */
3650 * Data frames: multicast frames go out at a fixed rate,
3651 * otherwise consult the rate control module for the
3656 * Check mcast rate setting in case it's changed.
3657 * XXX move out of fastpath
3659 if (ic->ic_mcast_rate != sc->sc_mcastrate) {
3661 ath_tx_findrix(rt, ic->ic_mcast_rate);
3662 sc->sc_mcastrate = ic->ic_mcast_rate;
3664 rix = sc->sc_mcastrix;
3665 txrate = rt->info[rix].rateCode;
3667 txrate |= rt->info[rix].shortPreamble;
3670 ath_rate_findrate(sc, an, shortPreamble, pktlen,
3671 &rix, &try0, &txrate);
3672 sc->sc_txrate = txrate; /* for LED blinking */
3673 if (try0 != ATH_TXMAXTRY)
3676 pri = M_WME_GETAC(m0);
3677 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
3678 flags |= HAL_TXDESC_NOACK;
3681 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
3682 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
3687 txq = sc->sc_ac2q[pri];
3690 * When servicing one or more stations in power-save mode
3691 * (or) if there is some mcast data waiting on the mcast
3692 * queue (to prevent out of order delivery) multicast
3693 * frames must be buffered until after the beacon.
3695 if (ismcast && (ic->ic_ps_sta || sc->sc_mcastq.axq_depth)) {
3696 txq = &sc->sc_mcastq;
3697 /* XXX? more bit in 802.11 frame header */
3701 * Calculate miscellaneous flags.
3704 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
3705 } else if (pktlen > ic->ic_rtsthreshold) {
3706 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
3707 cix = rt->info[rix].controlRate;
3708 sc->sc_stats.ast_tx_rts++;
3710 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
3711 sc->sc_stats.ast_tx_noack++;
3714 * If 802.11g protection is enabled, determine whether
3715 * to use RTS/CTS or just CTS. Note that this is only
3716 * done for OFDM unicast frames.
3718 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3719 rt->info[rix].phy == IEEE80211_T_OFDM &&
3720 (flags & HAL_TXDESC_NOACK) == 0) {
3721 /* XXX fragments must use CCK rates w/ protection */
3722 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3723 flags |= HAL_TXDESC_RTSENA;
3724 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3725 flags |= HAL_TXDESC_CTSENA;
3726 cix = rt->info[sc->sc_protrix].controlRate;
3727 sc->sc_stats.ast_tx_protect++;
3731 * Calculate duration. This logically belongs in the 802.11
3732 * layer but it lacks sufficient information to calculate it.
3734 if ((flags & HAL_TXDESC_NOACK) == 0 &&
3735 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
3738 * XXX not right with fragmentation.
3741 dur = rt->info[rix].spAckDuration;
3743 dur = rt->info[rix].lpAckDuration;
3744 *(uint16_t *)wh->i_dur = htole16(dur);
3748 * Calculate RTS/CTS rate and duration if needed.
3751 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
3753 * CTS transmit rate is derived from the transmit rate
3754 * by looking in the h/w rate table. We must also factor
3755 * in whether or not a short preamble is to be used.
3757 /* NB: cix is set above where RTS/CTS is enabled */
3758 KASSERT(cix != 0xff, ("cix not setup"));
3759 ctsrate = rt->info[cix].rateCode;
3761 * Compute the transmit duration based on the frame
3762 * size and the size of an ACK frame. We call into the
3763 * HAL to do the computation since it depends on the
3764 * characteristics of the actual PHY being used.
3766 * NB: CTS is assumed the same size as an ACK so we can
3767 * use the precalculated ACK durations.
3769 if (shortPreamble) {
3770 ctsrate |= rt->info[cix].shortPreamble;
3771 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3772 ctsduration += rt->info[cix].spAckDuration;
3773 ctsduration += ath_hal_computetxtime(ah,
3774 rt, pktlen, rix, AH_TRUE);
3775 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3776 ctsduration += rt->info[rix].spAckDuration;
3778 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3779 ctsduration += rt->info[cix].lpAckDuration;
3780 ctsduration += ath_hal_computetxtime(ah,
3781 rt, pktlen, rix, AH_FALSE);
3782 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3783 ctsduration += rt->info[rix].lpAckDuration;
3786 * Must disable multi-rate retry when using RTS/CTS.
3789 try0 = ATH_TXMGTTRY; /* XXX */
3793 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
3794 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len,
3795 sc->sc_hwmap[txrate].ieeerate, -1);
3798 bpf_mtap(ic->ic_rawbpf, m0);
3799 if (sc->sc_drvbpf) {
3800 uint64_t tsf = ath_hal_gettsf64(ah);
3802 sc->sc_tx_th.wt_tsf = htole64(tsf);
3803 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags;
3805 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3806 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate;
3807 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
3808 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
3810 bpf_ptap(sc->sc_drvbpf, m0, &sc->sc_tx_th, sc->sc_tx_th_len);
3814 * Determine if a tx interrupt should be generated for
3815 * this descriptor. We take a tx interrupt to reap
3816 * descriptors when the h/w hits an EOL condition or
3817 * when the descriptor is specifically marked to generate
3818 * an interrupt. We periodically mark descriptors in this
3819 * way to insure timely replenishing of the supply needed
3820 * for sending frames. Defering interrupts reduces system
3821 * load and potentially allows more concurrent work to be
3822 * done but if done to aggressively can cause senders to
3825 * NB: use >= to deal with sc_txintrperiod changing
3826 * dynamically through sysctl.
3828 if (flags & HAL_TXDESC_INTREQ) {
3829 txq->axq_intrcnt = 0;
3830 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
3831 flags |= HAL_TXDESC_INTREQ;
3832 txq->axq_intrcnt = 0;
3836 * Formulate first tx descriptor with tx controls.
3838 /* XXX check return value? */
3839 ath_hal_setuptxdesc(ah, ds
3840 , pktlen /* packet length */
3841 , hdrlen /* header length */
3842 , atype /* Atheros packet type */
3843 , ni->ni_txpower /* txpower */
3844 , txrate, try0 /* series 0 rate/tries */
3845 , keyix /* key cache index */
3846 , sc->sc_txantenna /* antenna mode */
3848 , ctsrate /* rts/cts rate */
3849 , ctsduration /* rts/cts duration */
3851 bf->bf_flags = flags;
3853 * Setup the multi-rate retry state only when we're
3854 * going to use it. This assumes ath_hal_setuptxdesc
3855 * initializes the descriptors (so we don't have to)
3856 * when the hardware supports multi-rate retry and
3860 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
3863 * Fillin the remainder of the descriptor info.
3866 for (i = 0; i < bf->bf_nseg; i++, ds++) {
3867 ds->ds_data = bf->bf_segs[i].ds_addr;
3868 if (i == bf->bf_nseg - 1)
3871 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
3872 ath_hal_filltxdesc(ah, ds
3873 , bf->bf_segs[i].ds_len /* segment length */
3874 , i == 0 /* first segment */
3875 , i == bf->bf_nseg - 1 /* last segment */
3876 , ds0 /* first descriptor */
3878 DPRINTF(sc, ATH_DEBUG_XMIT,
3879 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
3880 __func__, i, ds->ds_link, ds->ds_data,
3881 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
3884 * Insert the frame on the outbound list and pass it on
3885 * to the hardware. Multicast frames buffered for power
3886 * save stations and transmit from the CAB queue are stored
3887 * on a s/w only queue and loaded on to the CAB queue in
3888 * the SWBA handler since frames only go out on DTIM and
3889 * to avoid possible races.
3891 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
3892 if (txq != &sc->sc_mcastq) {
3893 if (txq->axq_link == NULL) {
3894 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
3895 DPRINTF(sc, ATH_DEBUG_XMIT,
3896 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__,
3897 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc,
3900 *txq->axq_link = bf->bf_daddr;
3901 DPRINTF(sc, ATH_DEBUG_XMIT,
3902 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
3903 txq->axq_qnum, txq->axq_link,
3904 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
3906 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
3907 ath_hal_txstart(ah, txq->axq_qnum);
3909 if (txq->axq_link != NULL)
3910 *txq->axq_link = bf->bf_daddr;
3911 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
3918 * Process completed xmit descriptors from the specified queue.
3921 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3923 struct ath_hal *ah = sc->sc_ah;
3924 struct ieee80211com *ic = &sc->sc_ic;
3926 struct ath_desc *ds, *ds0;
3927 struct ath_tx_status *ts;
3928 struct ieee80211_node *ni;
3929 struct ath_node *an;
3930 int sr, lr, pri, nacked;
3933 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3934 __func__, txq->axq_qnum,
3935 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
3939 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3940 bf = STAILQ_FIRST(&txq->axq_q);
3943 ds0 = &bf->bf_desc[0];
3944 ds = &bf->bf_desc[bf->bf_nseg - 1];
3945 ts = &bf->bf_status.ds_txstat;
3946 status = ath_hal_txprocdesc(ah, ds, ts);
3948 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3949 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK);
3951 if (status == HAL_EINPROGRESS)
3953 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3954 if (txq->axq_depth == 0)
3955 txq->axq_link = NULL;
3960 if (ts->ts_status == 0) {
3961 uint8_t txant = ts->ts_antenna;
3962 sc->sc_stats.ast_ant_tx[txant]++;
3963 sc->sc_ant_tx[txant]++;
3964 if (ts->ts_rate & HAL_TXSTAT_ALTRATE)
3965 sc->sc_stats.ast_tx_altrate++;
3966 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
3967 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
3969 pri = M_WME_GETAC(bf->bf_m);
3970 if (pri >= WME_AC_VO)
3971 ic->ic_wme.wme_hipri_traffic++;
3972 ni->ni_inact = ni->ni_inact_reload;
3974 if (ts->ts_status & HAL_TXERR_XRETRY)
3975 sc->sc_stats.ast_tx_xretries++;
3976 if (ts->ts_status & HAL_TXERR_FIFO)
3977 sc->sc_stats.ast_tx_fifoerr++;
3978 if (ts->ts_status & HAL_TXERR_FILT)
3979 sc->sc_stats.ast_tx_filtered++;
3981 sr = ts->ts_shortretry;
3982 lr = ts->ts_longretry;
3983 sc->sc_stats.ast_tx_shortretry += sr;
3984 sc->sc_stats.ast_tx_longretry += lr;
3986 * Hand the descriptor to the rate control algorithm.
3988 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
3989 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
3991 * If frame was ack'd update the last rx time
3992 * used to workaround phantom bmiss interrupts.
3994 if (ts->ts_status == 0)
3996 ath_rate_tx_complete(sc, an, bf);
3999 * Reclaim reference to node.
4001 * NB: the node may be reclaimed here if, for example
4002 * this is a DEAUTH message that was sent and the
4003 * node was timed out due to inactivity.
4005 ieee80211_free_node(ni);
4007 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4008 BUS_DMASYNC_POSTWRITE);
4009 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4014 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4020 txqactive(struct ath_hal *ah, int qnum)
4022 uint32_t txqs = 1<<qnum;
4023 ath_hal_gettxintrtxqs(ah, &txqs);
4024 return (txqs & (1<<qnum));
4028 * Deferred processing of transmit interrupt; special-cased
4029 * for a single hardware transmit queue (e.g. 5210 and 5211).
4032 ath_tx_proc_q0(struct ath_softc *sc)
4034 struct ifnet *ifp = &sc->sc_ic.ic_if;
4036 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]))
4037 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4038 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
4039 ath_tx_processq(sc, sc->sc_cabq);
4040 ifp->if_flags &= ~IFF_OACTIVE;
4041 sc->sc_tx_timer = 0;
4044 ath_led_event(sc, ATH_LED_TX);
4050 * Deferred processing of transmit interrupt; special-cased
4051 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
4054 ath_tx_proc_q0123(struct ath_softc *sc)
4056 struct ifnet *ifp = &sc->sc_ic.ic_if;
4060 * Process each active queue.
4063 if (txqactive(sc->sc_ah, 0))
4064 nacked += ath_tx_processq(sc, &sc->sc_txq[0]);
4065 if (txqactive(sc->sc_ah, 1))
4066 nacked += ath_tx_processq(sc, &sc->sc_txq[1]);
4067 if (txqactive(sc->sc_ah, 2))
4068 nacked += ath_tx_processq(sc, &sc->sc_txq[2]);
4069 if (txqactive(sc->sc_ah, 3))
4070 nacked += ath_tx_processq(sc, &sc->sc_txq[3]);
4071 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
4072 ath_tx_processq(sc, sc->sc_cabq);
4074 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4076 ifp->if_flags &= ~IFF_OACTIVE;
4077 sc->sc_tx_timer = 0;
4080 ath_led_event(sc, ATH_LED_TX);
4086 * Deferred processing of transmit interrupt.
4089 ath_tx_proc(struct ath_softc *sc)
4091 struct ifnet *ifp = &sc->sc_ic.ic_if;
4095 * Process each active queue.
4098 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4099 if (IS_ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i))
4100 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
4102 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4104 ifp->if_flags &= ~IFF_OACTIVE;
4105 sc->sc_tx_timer = 0;
4108 ath_led_event(sc, ATH_LED_TX);
4114 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
4117 struct ath_hal *ah = sc->sc_ah;
4119 struct ieee80211_node *ni;
4124 * NB: this assumes output has been stopped and
4125 * we do not need to block ath_tx_tasklet
4127 for (ix = 0;; ix++) {
4128 bf = STAILQ_FIRST(&txq->axq_q);
4130 txq->axq_link = NULL;
4133 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
4135 if (sc->sc_debug & ATH_DEBUG_RESET) {
4136 ath_printtxbuf(bf, txq->axq_qnum, ix,
4137 ath_hal_txprocdesc(ah, bf->bf_desc,
4138 &bf->bf_status.ds_txstat) == HAL_OK);
4139 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t),
4140 bf->bf_m->m_len, 0, -1);
4142 #endif /* ATH_DEBUG */
4143 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4150 * Reclaim node reference.
4152 ieee80211_free_node(ni);
4154 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4159 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
4161 struct ath_hal *ah = sc->sc_ah;
4163 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
4164 __func__, txq->axq_qnum,
4165 (caddr_t)(uintptr_t)ath_hal_gettxbuf(ah, txq->axq_qnum),
4167 ath_hal_stoptxdma(ah, txq->axq_qnum);
4171 * Drain the transmit queues and reclaim resources.
4174 ath_draintxq(struct ath_softc *sc)
4176 struct ath_hal *ah = sc->sc_ah;
4177 struct ifnet *ifp = &sc->sc_ic.ic_if;
4180 ASSERT_SERIALIZED(ifp->if_serializer);
4182 /* XXX return value */
4183 if (!sc->sc_invalid) {
4184 /* don't touch the hardware if marked invalid */
4185 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p\n",
4186 __func__, sc->sc_bhalq,
4187 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq));
4188 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4189 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4190 if (IS_ATH_TXQ_SETUP(sc, i))
4191 ath_tx_stopdma(sc, &sc->sc_txq[i]);
4193 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4194 if (IS_ATH_TXQ_SETUP(sc, i))
4195 ath_tx_draintxq(sc, &sc->sc_txq[i]);
4196 ath_tx_draintxq(sc, &sc->sc_mcastq);
4198 if (sc->sc_debug & ATH_DEBUG_RESET) {
4199 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
4200 if (bf != NULL && bf->bf_m != NULL) {
4201 ath_printtxbuf(bf, sc->sc_bhalq, 0,
4202 ath_hal_txprocdesc(ah, bf->bf_desc,
4203 &bf->bf_status.ds_txstat) == HAL_OK);
4204 ieee80211_dump_pkt(mtod(bf->bf_m, caddr_t),
4205 bf->bf_m->m_len, 0, -1);
4208 #endif /* ATH_DEBUG */
4209 ifp->if_flags &= ~IFF_OACTIVE;
4210 sc->sc_tx_timer = 0;
4214 * Disable the receive h/w in preparation for a reset.
4217 ath_stoprecv(struct ath_softc *sc)
4219 #define PA2DESC(_sc, _pa) \
4220 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
4221 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
4222 struct ath_hal *ah = sc->sc_ah;
4224 ASSERT_SERIALIZED(sc->sc_ic.ic_if.if_serializer);
4226 ath_hal_stoppcurecv(ah); /* disable PCU */
4227 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
4228 ath_hal_stopdmarecv(ah); /* disable DMA engine */
4229 DELAY(3000); /* 3ms is long enough for 1 frame */
4231 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
4235 kprintf("%s: rx queue %p, link %p\n", __func__,
4236 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah),
4239 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4240 struct ath_desc *ds = bf->bf_desc;
4241 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
4244 status = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
4245 PA2DESC(sc, ds->ds_link),
4247 if (status == HAL_OK ||
4248 (sc->sc_debug & ATH_DEBUG_FATAL))
4249 ath_printrxbuf(bf, ix, status == HAL_OK);
4254 sc->sc_rxlink = NULL; /* just in case */
4259 * Enable the receive h/w following a reset.
4262 ath_startrecv(struct ath_softc *sc)
4264 struct ath_hal *ah = sc->sc_ah;
4267 ASSERT_SERIALIZED(sc->sc_ic.ic_if.if_serializer);
4269 sc->sc_rxlink = NULL;
4270 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4271 int error = ath_rxbuf_init(sc, bf);
4273 DPRINTF(sc, ATH_DEBUG_RECV,
4274 "%s: ath_rxbuf_init failed %d\n",
4280 bf = STAILQ_FIRST(&sc->sc_rxbuf);
4281 ath_hal_putrxbuf(ah, bf->bf_daddr);
4282 ath_hal_rxena(ah); /* enable recv descriptors */
4283 ath_mode_init(sc); /* set filters, etc. */
4284 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
4289 * Update internal state after a channel change.
4292 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
4294 struct ieee80211com *ic = &sc->sc_ic;
4295 enum ieee80211_phymode mode;
4299 * Change channels and update the h/w rate map
4300 * if we're switching; e.g. 11a to 11b/g.
4302 mode = ieee80211_chan2mode(ic, chan);
4303 if (mode != sc->sc_curmode)
4304 ath_setcurmode(sc, mode);
4306 * Update BPF state. NB: ethereal et. al. don't handle
4307 * merged flags well so pick a unique mode for their use.
4309 if (IEEE80211_IS_CHAN_A(chan))
4310 flags = IEEE80211_CHAN_A;
4311 /* XXX 11g schizophrenia */
4312 else if (IEEE80211_IS_CHAN_G(chan) ||
4313 IEEE80211_IS_CHAN_PUREG(chan))
4314 flags = IEEE80211_CHAN_G;
4316 flags = IEEE80211_CHAN_B;
4317 if (IEEE80211_IS_CHAN_T(chan))
4318 flags |= IEEE80211_CHAN_TURBO;
4319 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
4320 htole16(chan->ic_freq);
4321 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
4326 * Poll for a channel clear indication; this is required
4327 * for channels requiring DFS and not previously visited
4328 * and/or with a recent radar detection.
4331 ath_dfswait(void *arg)
4333 struct ath_softc *sc = arg;
4334 struct ath_hal *ah = sc->sc_ah;
4335 struct ifnet *ifp = &sc->sc_ic.ic_if;
4338 lwkt_serialize_enter(ifp->if_serializer);
4340 ath_hal_radar_wait(ah, &hchan);
4341 DPRINTF(sc, ATH_DEBUG_DFS, "%s: radar_wait %u/%x/%x\n",
4342 __func__, hchan.channel, hchan.channelFlags, hchan.privFlags);
4344 if (hchan.privFlags & CHANNEL_INTERFERENCE) {
4345 if_printf(ifp, "channel %u/0x%x/0x%x has interference\n",
4346 hchan.channel, hchan.channelFlags, hchan.privFlags);
4349 if ((hchan.privFlags & CHANNEL_DFS) == 0) {
4350 /* XXX should not happen */
4353 if (hchan.privFlags & CHANNEL_DFS_CLEAR) {
4354 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR;
4355 ifp->if_flags &= ~IFF_OACTIVE;
4356 if_printf(ifp, "channel %u/0x%x/0x%x marked clear\n",
4357 hchan.channel, hchan.channelFlags, hchan.privFlags);
4359 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc);
4363 lwkt_serialize_exit(ifp->if_serializer);
4367 * Set/change channels. If the channel is really being changed,
4368 * it's done by reseting the chip. To accomplish this we must
4369 * first cleanup any pending DMA, then restart stuff after a la
4373 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4375 struct ath_hal *ah = sc->sc_ah;
4376 struct ieee80211com *ic = &sc->sc_ic;
4377 struct ifnet *ifp = &ic->ic_if;
4381 * Convert to a HAL channel description with
4382 * the flags constrained to reflect the current
4385 hchan.channel = chan->ic_freq;
4386 hchan.channelFlags = ath_chan2flags(ic, chan);
4388 DPRINTF(sc, ATH_DEBUG_RESET,
4389 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n",
4391 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel,
4392 sc->sc_curchan.channelFlags),
4393 sc->sc_curchan.channel, sc->sc_curchan.channelFlags,
4394 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags),
4395 hchan.channel, hchan.channelFlags);
4396 if (hchan.channel != sc->sc_curchan.channel ||
4397 hchan.channelFlags != sc->sc_curchan.channelFlags) {
4401 * To switch channels clear any pending DMA operations;
4402 * wait long enough for the RX fifo to drain, reset the
4403 * hardware at the new frequency, and then re-enable
4404 * the relevant bits of the h/w.
4406 ath_hal_intrset(ah, 0); /* disable interrupts */
4407 ath_draintxq(sc); /* clear pending tx frames */
4408 ath_stoprecv(sc); /* turn off frame recv */
4409 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_FALSE, &status)) {
4410 if_printf(ifp, "%s: unable to reset "
4411 "channel %u (%u Mhz, flags 0x%x hal flags 0x%x)\n",
4412 __func__, ieee80211_chan2ieee(ic, chan),
4413 chan->ic_freq, chan->ic_flags, hchan.channelFlags);
4416 sc->sc_curchan = hchan;
4417 ath_update_txpow(sc); /* update tx power state */
4418 sc->sc_diversity = ath_hal_getdiversity(ah);
4419 sc->sc_calinterval = 1;
4420 sc->sc_caltries = 0;
4423 * Re-enable rx framework.
4425 if (ath_startrecv(sc) != 0) {
4426 if_printf(ic->ic_ifp,
4427 "%s: unable to restart recv logic\n", __func__);
4432 * Change channels and update the h/w rate map
4433 * if we're switching; e.g. 11a to 11b/g.
4435 ic->ic_ibss_chan = chan;
4436 ath_chan_change(sc, chan);
4439 * Handle DFS required waiting period to determine
4440 * if channel is clear of radar traffic.
4442 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
4443 #define DFS_AND_NOT_CLEAR(_c) \
4444 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS)
4445 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) {
4447 "wait for DFS clear channel signal\n");
4449 ifp->if_flags |= IFF_OACTIVE;
4450 callout_reset(&sc->sc_dfs_ch,
4451 2 * hz, ath_dfswait, sc);
4453 callout_stop(&sc->sc_dfs_ch);
4455 #undef DFS_NOT_CLEAR
4459 * Re-enable interrupts.
4461 ath_hal_intrset(ah, sc->sc_imask);
4467 ath_next_scan(void *arg)
4469 struct ath_softc *sc = arg;
4470 struct ieee80211com *ic = &sc->sc_ic;
4471 struct ifnet *ifp = &ic->ic_if;
4473 lwkt_serialize_enter(ifp->if_serializer);
4475 if (ic->ic_state == IEEE80211_S_SCAN)
4476 ieee80211_next_scan(ic);
4478 lwkt_serialize_exit(ifp->if_serializer);
4482 * Periodically recalibrate the PHY to account
4483 * for temperature/environment changes.
4486 ath_calibrate(void *arg)
4488 struct ath_softc *sc = arg;
4489 struct ath_hal *ah = sc->sc_ah;
4490 struct ifnet *ifp = &sc->sc_ic.ic_if;
4493 lwkt_serialize_enter(ifp->if_serializer);
4495 sc->sc_stats.ast_per_cal++;
4497 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4499 * Rfgain is out of bounds, reset the chip
4500 * to load new gain values.
4502 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
4503 "%s: rfgain change\n", __func__);
4504 sc->sc_stats.ast_per_rfgain++;
4505 ath_reset(&sc->sc_ic.ic_if);
4507 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) {
4508 DPRINTF(sc, ATH_DEBUG_ANY,
4509 "%s: calibration of channel %u failed\n",
4510 __func__, sc->sc_curchan.channel);
4511 sc->sc_stats.ast_per_calfail++;
4514 * Calibrate noise floor data again in case of change.
4516 ath_hal_process_noisefloor(ah);
4518 * Poll more frequently when the IQ calibration is in
4519 * progress to speedup loading the final settings.
4520 * We temper this aggressive polling with an exponential
4521 * back off after 4 tries up to ath_calinterval.
4523 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) {
4524 sc->sc_caltries = 0;
4525 sc->sc_calinterval = ath_calinterval;
4526 } else if (sc->sc_caltries > 4) {
4527 sc->sc_caltries = 0;
4528 sc->sc_calinterval <<= 1;
4529 if (sc->sc_calinterval > ath_calinterval)
4530 sc->sc_calinterval = ath_calinterval;
4532 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval,
4533 ("bad calibration interval %u", sc->sc_calinterval));
4535 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
4536 "%s: next +%u (%siqCalDone tries %u)\n", __func__,
4537 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries);
4539 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz,
4542 lwkt_serialize_exit(ifp->if_serializer);
4546 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
4548 struct ifnet *ifp = ic->ic_ifp;
4549 struct ath_softc *sc = ifp->if_softc;
4550 struct ath_hal *ah = sc->sc_ah;
4551 struct ieee80211_node *ni;
4553 const uint8_t *bssid;
4555 static const HAL_LED_STATE leds[] = {
4556 HAL_LED_INIT, /* IEEE80211_S_INIT */
4557 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
4558 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
4559 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
4560 HAL_LED_RUN, /* IEEE80211_S_RUN */
4563 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4564 ieee80211_state_name[ic->ic_state],
4565 ieee80211_state_name[nstate]);
4567 callout_stop(&sc->sc_scan_ch);
4568 callout_stop(&sc->sc_cal_ch);
4569 callout_stop(&sc->sc_dfs_ch);
4570 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
4572 if (nstate == IEEE80211_S_INIT) {
4573 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4575 * NB: disable interrupts so we don't rx frames.
4577 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
4579 * Notify the rate control algorithm.
4581 ath_rate_newstate(sc, nstate);
4585 error = ath_chan_set(sc, ic->ic_curchan);
4588 rfilt = ath_calcrxfilter(sc, nstate);
4589 if (nstate == IEEE80211_S_SCAN)
4590 bssid = ifp->if_broadcastaddr;
4592 bssid = ni->ni_bssid;
4593 ath_hal_setrxfilter(ah, rfilt);
4594 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %6D\n",
4595 __func__, rfilt, bssid, ":");
4597 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA)
4598 ath_hal_setassocid(ah, bssid, ni->ni_associd);
4600 ath_hal_setassocid(ah, bssid, 0);
4601 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
4602 for (i = 0; i < IEEE80211_WEP_NKID; i++)
4603 if (ath_hal_keyisvalid(ah, i))
4604 ath_hal_keysetmac(ah, i, bssid);
4608 * Notify the rate control algorithm so rates
4609 * are setup should ath_beacon_alloc be called.
4611 ath_rate_newstate(sc, nstate);
4613 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4614 /* nothing to do */;
4615 } else if (nstate == IEEE80211_S_RUN) {
4616 DPRINTF(sc, ATH_DEBUG_STATE,
4617 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%6D "
4618 "capinfo=0x%04x chan=%d\n"
4624 , ieee80211_chan2ieee(ic, ic->ic_curchan));
4626 switch (ic->ic_opmode) {
4627 case IEEE80211_M_HOSTAP:
4628 case IEEE80211_M_IBSS:
4630 * Allocate and setup the beacon frame.
4632 * Stop any previous beacon DMA. This may be
4633 * necessary, for example, when an ibss merge
4634 * causes reconfiguration; there will be a state
4635 * transition from RUN->RUN that means we may
4636 * be called with beacon transmission active.
4638 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4639 ath_beacon_free(sc);
4640 error = ath_beacon_alloc(sc, ni);
4644 * If joining an adhoc network defer beacon timer
4645 * configuration to the next beacon frame so we
4646 * have a current TSF to use. Otherwise we're
4647 * starting an ibss/bss so there's no need to delay.
4649 if (ic->ic_opmode == IEEE80211_M_IBSS &&
4650 ic->ic_bss->ni_tstamp.tsf != 0)
4651 sc->sc_syncbeacon = 1;
4653 ath_beacon_config(sc);
4655 case IEEE80211_M_STA:
4657 * Allocate a key cache slot to the station.
4659 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 &&
4661 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
4662 ath_setup_stationkey(ni);
4664 * Defer beacon timer configuration to the next
4665 * beacon frame so we have a current TSF to use
4666 * (any TSF collected when scanning is likely old).
4668 sc->sc_syncbeacon = 1;
4675 * Let the hal process statistics collected during a
4676 * scan so it can provide calibrated noise floor data.
4678 ath_hal_process_noisefloor(ah);
4680 * Reset rssi stats; maybe not the best place...
4682 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
4683 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
4684 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
4687 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
4688 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4692 * Invoke the parent method to complete the work.
4694 error = sc->sc_newstate(ic, nstate, arg);
4696 * Finally, start any timers.
4698 if (nstate == IEEE80211_S_RUN) {
4699 /* start periodic recalibration timer */
4700 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz,
4702 } else if (nstate == IEEE80211_S_SCAN) {
4703 /* start ap/neighbor scan timer */
4704 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000,
4712 * Allocate a key cache slot to the station so we can
4713 * setup a mapping from key index to node. The key cache
4714 * slot is needed for managing antenna state and for
4715 * compression when stations do not use crypto. We do
4716 * it uniliaterally here; if crypto is employed this slot
4717 * will be reassigned.
4720 ath_setup_stationkey(struct ieee80211_node *ni)
4722 struct ieee80211com *ic = ni->ni_ic;
4723 struct ath_softc *sc = ic->ic_ifp->if_softc;
4724 ieee80211_keyix keyix, rxkeyix;
4726 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
4728 * Key cache is full; we'll fall back to doing
4729 * the more expensive lookup in software. Note
4730 * this also means no h/w compression.
4732 /* XXX msg+statistic */
4735 ni->ni_ucastkey.wk_keyix = keyix;
4736 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
4737 /* NB: this will create a pass-thru key entry */
4738 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss);
4743 * Setup driver-specific state for a newly associated node.
4744 * Note that we're called also on a re-associate, the isnew
4745 * param tells us if this is the first time or not.
4748 ath_newassoc(struct ieee80211_node *ni, int isnew)
4750 struct ieee80211com *ic = ni->ni_ic;
4751 struct ath_softc *sc = ic->ic_ifp->if_softc;
4753 ath_rate_newassoc(sc, ATH_NODE(ni), isnew);
4755 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) {
4756 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE,
4757 ("new assoc with a unicast key already setup (keyix %u)",
4758 ni->ni_ucastkey.wk_keyix));
4759 ath_setup_stationkey(ni);
4764 ath_getchannels(struct ath_softc *sc, u_int cc,
4765 HAL_BOOL outdoor, HAL_BOOL xchanmode)
4767 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE)
4768 struct ieee80211com *ic = &sc->sc_ic;
4769 struct ifnet *ifp = &ic->ic_if;
4770 struct ath_hal *ah = sc->sc_ah;
4774 chans = kmalloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), M_TEMP,
4777 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan,
4779 cc, HAL_MODE_ALL, outdoor, xchanmode)) {
4782 (void) ath_hal_getregdomain(ah, &rd);
4783 if_printf(ifp, "unable to collect channel list from hal; "
4784 "regdomain likely %u country code %u\n", rd, cc);
4785 kfree(chans, M_TEMP);
4790 * Convert HAL channels to ieee80211 ones and insert
4791 * them in the table according to their channel number.
4793 for (i = 0; i < nchan; i++) {
4794 HAL_CHANNEL *c = &chans[i];
4797 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags);
4798 if (ix > IEEE80211_CHAN_MAX) {
4799 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n",
4800 ix, c->channel, c->channelFlags);
4804 /* XXX can't handle stuff <2400 right now */
4806 if_printf(ifp, "hal channel %d (%u/%x) "
4807 "cannot be handled; ignored\n",
4808 ix, c->channel, c->channelFlags);
4812 * Calculate net80211 flags; most are compatible
4813 * but some need massaging. Note the static turbo
4814 * conversion can be removed once net80211 is updated
4815 * to understand static vs. dynamic turbo.
4817 flags = c->channelFlags & COMPAT;
4818 if (c->channelFlags & CHANNEL_STURBO)
4819 flags |= IEEE80211_CHAN_TURBO;
4820 if (ic->ic_channels[ix].ic_freq == 0) {
4821 ic->ic_channels[ix].ic_freq = c->channel;
4822 ic->ic_channels[ix].ic_flags = flags;
4824 /* channels overlap; e.g. 11g and 11b */
4825 ic->ic_channels[ix].ic_flags |= flags;
4828 kfree(chans, M_TEMP);
4834 ath_led_done(void *arg)
4836 struct ath_softc *sc = arg;
4838 sc->sc_blinking = 0;
4842 * Turn the LED off: flip the pin and then set a timer so no
4843 * update will happen for the specified duration.
4846 ath_led_off(void *arg)
4848 struct ath_softc *sc = arg;
4850 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
4851 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
4855 * Blink the LED according to the specified on/off times.
4858 ath_led_blink(struct ath_softc *sc, int on, int off)
4860 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
4861 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
4862 sc->sc_blinking = 1;
4863 sc->sc_ledoff = off;
4864 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
4868 ath_led_event(struct ath_softc *sc, int event)
4871 sc->sc_ledevent = ticks; /* time of last event */
4872 if (sc->sc_blinking) /* don't interrupt active blink */
4876 ath_led_blink(sc, sc->sc_hwmap[0].ledon,
4877 sc->sc_hwmap[0].ledoff);
4880 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon,
4881 sc->sc_hwmap[sc->sc_txrate].ledoff);
4884 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon,
4885 sc->sc_hwmap[sc->sc_rxrate].ledoff);
4891 ath_update_txpow(struct ath_softc *sc)
4893 struct ieee80211com *ic = &sc->sc_ic;
4894 struct ath_hal *ah = sc->sc_ah;
4897 if (sc->sc_curtxpow != ic->ic_txpowlimit) {
4898 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
4899 /* read back in case value is clamped */
4900 (void) ath_hal_gettxpowlimit(ah, &txpow);
4901 ic->ic_txpowlimit = sc->sc_curtxpow = txpow;
4904 * Fetch max tx power level for status requests.
4906 (void) ath_hal_getmaxtxpow(sc->sc_ah, &txpow);
4907 ic->ic_bss->ni_txpower = txpow;
4911 rate_setup(struct ath_softc *sc,
4912 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs)
4916 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) {
4917 DPRINTF(sc, ATH_DEBUG_ANY,
4918 "%s: rate table too small (%u > %u)\n",
4919 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE);
4920 maxrates = IEEE80211_RATE_MAXSIZE;
4922 maxrates = rt->rateCount;
4923 for (i = 0; i < maxrates; i++)
4924 rs->rs_rates[i] = rt->info[i].dot11Rate;
4925 rs->rs_nrates = maxrates;
4929 ath_rate_setup(struct ath_softc *sc, u_int mode)
4931 struct ath_hal *ah = sc->sc_ah;
4932 struct ieee80211com *ic = &sc->sc_ic;
4933 const HAL_RATE_TABLE *rt;
4936 case IEEE80211_MODE_11A:
4937 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
4939 case IEEE80211_MODE_11B:
4940 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
4942 case IEEE80211_MODE_11G:
4943 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
4945 case IEEE80211_MODE_TURBO_A:
4946 /* XXX until static/dynamic turbo is fixed */
4947 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
4949 case IEEE80211_MODE_TURBO_G:
4950 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
4953 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
4957 sc->sc_rates[mode] = rt;
4959 rate_setup(sc, rt, &ic->ic_sup_rates[mode]);
4966 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
4968 #define N(a) (sizeof(a)/sizeof(a[0]))
4969 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
4970 static const struct {
4971 u_int rate; /* tx/rx 802.11 rate */
4972 uint16_t timeOn; /* LED on time (ms) */
4973 uint16_t timeOff; /* LED off time (ms) */
4990 const HAL_RATE_TABLE *rt;
4993 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
4994 rt = sc->sc_rates[mode];
4995 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
4996 for (i = 0; i < rt->rateCount; i++)
4997 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i;
4998 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
4999 for (i = 0; i < 32; i++) {
5000 uint8_t ix = rt->rateCodeToIndex[i];
5002 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
5003 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
5006 sc->sc_hwmap[i].ieeerate =
5007 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
5008 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
5009 if (rt->info[ix].shortPreamble ||
5010 rt->info[ix].phy == IEEE80211_T_OFDM)
5011 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
5012 /* NB: receive frames include FCS */
5013 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags |
5014 IEEE80211_RADIOTAP_F_FCS;
5015 /* setup blink rate table to avoid per-packet lookup */
5016 for (j = 0; j < N(blinkrates)-1; j++)
5017 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
5019 /* NB: this uses the last entry if the rate isn't found */
5020 /* XXX beware of overlow */
5021 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
5022 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
5024 sc->sc_currates = rt;
5025 sc->sc_curmode = mode;
5027 * All protection frames are transmited at 2Mb/s for
5028 * 11g, otherwise at 1Mb/s.
5030 if (mode == IEEE80211_MODE_11G)
5031 sc->sc_protrix = ath_tx_findrix(rt, 2 * 2);
5033 sc->sc_protrix = ath_tx_findrix(rt, 2 * 1);
5034 /* rate index used to send management frames */
5035 sc->sc_minrateix = 0;
5037 * Setup multicast rate state.
5039 /* XXX layering violation */
5040 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate);
5041 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate;
5042 /* NB: caller is responsible for reseting rate control state */
5048 ath_printrxbuf(const struct ath_buf *bf, u_int ix, int done)
5050 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
5051 const struct ath_desc *ds;
5054 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
5055 kprintf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n"
5056 " %08x %08x %08x %08x\n",
5057 ix, ds, (const struct ath_desc *)bf->bf_daddr + i,
5058 ds->ds_link, ds->ds_data,
5059 !done ? "" : (rs->rs_status == 0) ? " *" : " !",
5060 ds->ds_ctl0, ds->ds_ctl1,
5061 ds->ds_hw[0], ds->ds_hw[1]);
5066 ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done)
5068 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
5069 const struct ath_desc *ds;
5072 kprintf("Q%u[%3u]", qnum, ix);
5073 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
5074 kprintf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n"
5075 " %08x %08x %08x %08x %08x %08x\n",
5076 ds, (const struct ath_desc *)bf->bf_daddr + i,
5077 ds->ds_link, ds->ds_data, bf->bf_flags,
5078 !done ? "" : (ts->ts_status == 0) ? " *" : " !",
5079 ds->ds_ctl0, ds->ds_ctl1,
5080 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
5083 #endif /* ATH_DEBUG */
5086 ath_watchdog(struct ifnet *ifp)
5088 struct ath_softc *sc = ifp->if_softc;
5089 struct ieee80211com *ic = &sc->sc_ic;
5092 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid)
5094 if (sc->sc_tx_timer) {
5095 if (--sc->sc_tx_timer == 0) {
5096 if_printf(ifp, "device timeout\n");
5099 sc->sc_stats.ast_watchdog++;
5103 ieee80211_watchdog(ic);
5108 * Diagnostic interface to the HAL. This is used by various
5109 * tools to do things like retrieve register contents for
5110 * debugging. The mechanism is intentionally opaque so that
5111 * it can change frequently w/o concern for compatiblity.
5114 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
5116 struct ath_hal *ah = sc->sc_ah;
5117 u_int id = ad->ad_id & ATH_DIAG_ID;
5118 void *indata = NULL;
5119 void *outdata = NULL;
5120 uint32_t insize = ad->ad_in_size;
5121 uint32_t outsize = ad->ad_out_size;
5124 if (ad->ad_id & ATH_DIAG_IN) {
5128 indata = kmalloc(insize, M_TEMP, M_NOWAIT);
5129 if (indata == NULL) {
5133 error = copyin(ad->ad_in_data, indata, insize);
5137 if (ad->ad_id & ATH_DIAG_DYN) {
5139 * Allocate a buffer for the results (otherwise the HAL
5140 * returns a pointer to a buffer where we can read the
5141 * results). Note that we depend on the HAL leaving this
5142 * pointer for us to use below in reclaiming the buffer;
5143 * may want to be more defensive.
5145 outdata = kmalloc(outsize, M_TEMP, M_NOWAIT);
5146 if (outdata == NULL) {
5151 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
5152 if (outsize < ad->ad_out_size)
5153 ad->ad_out_size = outsize;
5154 if (outdata != NULL)
5155 error = copyout(outdata, ad->ad_out_data,
5161 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
5162 kfree(indata, M_TEMP);
5163 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
5164 kfree(outdata, M_TEMP);
5167 #endif /* ATH_DIAGAPI */
5170 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
5172 #define IS_RUNNING(ifp) \
5173 ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
5174 struct ath_softc *sc = ifp->if_softc;
5175 struct ieee80211com *ic = &sc->sc_ic;
5176 struct ifreq *ifr = (struct ifreq *)data;
5179 ASSERT_SERIALIZED(ifp->if_serializer);
5183 if (IS_RUNNING(ifp)) {
5185 * To avoid rescanning another access point,
5186 * do not call ath_init() here. Instead,
5187 * only reflect promisc mode settings.
5190 } else if (ifp->if_flags & IFF_UP) {
5192 * Beware of being called during attach/detach
5193 * to reset promiscuous mode. In that case we
5194 * will still be marked UP but not RUNNING.
5195 * However trying to re-init the interface
5196 * is the wrong thing to do as we've already
5197 * torn down much of our state. There's
5198 * probably a better way to deal with this.
5200 if (!sc->sc_invalid && ic->ic_bss != NULL)
5201 ath_init(sc); /* XXX lose error */
5203 ath_stop_no_pwchg(ifp);
5208 * The upper layer has already installed/removed
5209 * the multicast address(es), just recalculate the
5210 * multicast filter for the card.
5212 if (ifp->if_flags & IFF_RUNNING)
5216 /* NB: embed these numbers to get a consistent view */
5217 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
5218 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
5219 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic);
5220 sc->sc_stats.ast_rx_noise =
5221 ath_hal_getchannoise(sc->sc_ah, &sc->sc_curchan);
5222 sc->sc_stats.ast_tx_rate = sc->sc_hwmap[sc->sc_txrate].ieeerate;
5223 return copyout(&sc->sc_stats,
5224 ifr->ifr_data, sizeof (sc->sc_stats));
5227 error = ath_ioctl_diag(sc, (struct ath_diag *)ifr);
5231 error = ieee80211_ioctl(ic, cmd, data, cr);
5232 if (error == ENETRESET) {
5233 if (IS_RUNNING(ifp) &&
5234 ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
5235 ath_init(sc); /* XXX lose error */
5238 if (error == ERESTART)
5239 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0;
5247 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
5249 struct ath_softc *sc = arg1;
5250 struct ifnet *ifp = &sc->sc_ic.ic_if;
5254 lwkt_serialize_enter(ifp->if_serializer);
5256 slottime = ath_hal_getslottime(sc->sc_ah);
5257 error = sysctl_handle_int(oidp, &slottime, 0, req);
5258 if (error || !req->newptr)
5260 error = !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
5262 lwkt_serialize_exit(ifp->if_serializer);
5267 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
5269 struct ath_softc *sc = arg1;
5270 struct ifnet *ifp = &sc->sc_ic.ic_if;
5274 lwkt_serialize_enter(ifp->if_serializer);
5276 acktimeout = ath_hal_getacktimeout(sc->sc_ah);
5277 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
5278 if (error || !req->newptr)
5280 error = !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
5282 lwkt_serialize_exit(ifp->if_serializer);
5287 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
5289 struct ath_softc *sc = arg1;
5290 struct ifnet *ifp = &sc->sc_ic.ic_if;
5294 lwkt_serialize_enter(ifp->if_serializer);
5296 ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
5297 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
5298 if (error || !req->newptr)
5300 error = !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
5302 lwkt_serialize_exit(ifp->if_serializer);
5307 ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
5309 struct ath_softc *sc = arg1;
5310 struct ifnet *ifp = &sc->sc_ic.ic_if;
5314 lwkt_serialize_enter(ifp->if_serializer);
5316 softled = sc->sc_softled;
5317 error = sysctl_handle_int(oidp, &softled, 0, req);
5318 if (error || !req->newptr)
5320 softled = (softled != 0);
5321 if (softled != sc->sc_softled) {
5323 /* NB: handle any sc_ledpin change */
5324 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
5325 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
5328 sc->sc_softled = softled;
5331 lwkt_serialize_exit(ifp->if_serializer);
5336 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
5338 struct ath_softc *sc = arg1;
5339 struct ifnet *ifp = &sc->sc_ic.ic_if;
5343 lwkt_serialize_enter(ifp->if_serializer);
5345 defantenna = ath_hal_getdefantenna(sc->sc_ah);
5346 error = sysctl_handle_int(oidp, &defantenna, 0, req);
5347 if (!error && req->newptr)
5348 ath_hal_setdefantenna(sc->sc_ah, defantenna);
5350 lwkt_serialize_exit(ifp->if_serializer);
5355 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
5357 struct ath_softc *sc = arg1;
5358 struct ifnet *ifp = &sc->sc_ic.ic_if;
5362 lwkt_serialize_enter(ifp->if_serializer);
5364 diversity = ath_hal_getdiversity(sc->sc_ah);
5365 error = sysctl_handle_int(oidp, &diversity, 0, req);
5366 if (error || !req->newptr)
5368 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) {
5372 sc->sc_diversity = diversity;
5375 lwkt_serialize_exit(ifp->if_serializer);
5380 ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
5382 struct ath_softc *sc = arg1;
5383 struct ifnet *ifp = &sc->sc_ic.ic_if;
5387 lwkt_serialize_enter(ifp->if_serializer);
5389 if (!ath_hal_getdiag(sc->sc_ah, &diag)) {
5393 error = sysctl_handle_int(oidp, &diag, 0, req);
5394 if (error || !req->newptr)
5396 error = !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
5398 lwkt_serialize_exit(ifp->if_serializer);
5403 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
5405 struct ath_softc *sc = arg1;
5406 struct ifnet *ifp = &sc->sc_ic.ic_if;
5410 lwkt_serialize_enter(ifp->if_serializer);
5412 (void) ath_hal_gettpscale(sc->sc_ah, &scale);
5413 error = sysctl_handle_int(oidp, &scale, 0, req);
5414 if (error || !req->newptr)
5416 error = !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp);
5418 lwkt_serialize_exit(ifp->if_serializer);
5423 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
5425 struct ath_softc *sc = arg1;
5426 struct ifnet *ifp = &sc->sc_ic.ic_if;
5430 lwkt_serialize_enter(ifp->if_serializer);
5432 tpc = ath_hal_gettpc(sc->sc_ah);
5433 error = sysctl_handle_int(oidp, &tpc, 0, req);
5434 if (error || !req->newptr)
5436 error = !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
5438 lwkt_serialize_exit(ifp->if_serializer);
5443 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS)
5445 struct ath_softc *sc = arg1;
5446 struct ifnet *ifp = &sc->sc_ic.ic_if;
5447 struct ath_hal *ah = sc->sc_ah;
5451 lwkt_serialize_enter(ifp->if_serializer);
5453 rfkill = ath_hal_getrfkill(ah);
5454 error = sysctl_handle_int(oidp, &rfkill, 0, req);
5455 if (error || !req->newptr)
5460 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */
5463 if (!ath_hal_setrfkill(ah, rfkill) || ath_reset(&sc->sc_ic.ic_if) != 0)
5466 lwkt_serialize_exit(ifp->if_serializer);
5471 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS)
5473 struct ath_softc *sc = arg1;
5474 struct ifnet *ifp = &sc->sc_ic.ic_if;
5478 lwkt_serialize_enter(ifp->if_serializer);
5480 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent);
5481 error = sysctl_handle_int(oidp, &rfsilent, 0, req);
5482 if (error || !req->newptr)
5484 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) {
5488 sc->sc_rfsilentpin = rfsilent & 0x1c;
5489 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0;
5492 lwkt_serialize_exit(ifp->if_serializer);
5497 ath_sysctl_regdomain(SYSCTL_HANDLER_ARGS)
5499 struct ath_softc *sc = arg1;
5500 struct ifnet *ifp = &sc->sc_ic.ic_if;
5504 lwkt_serialize_enter(ifp->if_serializer);
5506 if (!ath_hal_getregdomain(sc->sc_ah, &rd)) {
5510 error = sysctl_handle_int(oidp, &rd, 0, req);
5511 if (error || !req->newptr)
5513 error = !ath_hal_setregdomain(sc->sc_ah, rd) ? EINVAL : 0;
5515 lwkt_serialize_exit(ifp->if_serializer);
5520 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS)
5522 struct ath_softc *sc = arg1;
5523 struct ifnet *ifp = &sc->sc_ic.ic_if;
5527 lwkt_serialize_enter(ifp->if_serializer);
5529 (void) ath_hal_gettpack(sc->sc_ah, &tpack);
5530 error = sysctl_handle_int(oidp, &tpack, 0, req);
5531 if (error || !req->newptr)
5533 error = !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0;
5535 lwkt_serialize_exit(ifp->if_serializer);
5540 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS)
5542 struct ath_softc *sc = arg1;
5543 struct ifnet *ifp = &sc->sc_ic.ic_if;
5547 lwkt_serialize_enter(ifp->if_serializer);
5549 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts);
5550 error = sysctl_handle_int(oidp, &tpcts, 0, req);
5551 if (error || !req->newptr)
5553 error = !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0;
5555 lwkt_serialize_exit(ifp->if_serializer);
5560 ath_sysctlattach(struct ath_softc *sc)
5562 struct sysctl_ctx_list *ctx = &sc->sc_sysctl_ctx;
5563 struct sysctl_oid *tree = sc->sc_sysctl_tree;
5564 struct ath_hal *ah = sc->sc_ah;
5566 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode);
5567 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5568 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0,
5569 "EEPROM country code");
5570 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5571 "regdomain", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5572 ath_sysctl_regdomain, "I", "EEPROM regdomain code");
5574 sc->sc_debug = ath_debug;
5575 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5576 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
5577 "control debugging kprintfs");
5579 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5580 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5581 ath_sysctl_slottime, "I", "802.11 slot time (us)");
5582 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5583 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5584 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
5585 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5586 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5587 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
5588 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5589 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5590 ath_sysctl_softled, "I", "enable/disable software LED support");
5591 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5592 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0,
5593 "GPIO pin connected to LED");
5594 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5595 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
5596 "setting to turn LED on");
5597 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5598 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
5599 "idle time for inactivity LED (ticks)");
5600 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5601 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0,
5602 "tx antenna (0=auto)");
5603 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5604 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5605 ath_sysctl_rxantenna, "I", "default/rx antenna");
5606 if (ath_hal_hasdiversity(ah))
5607 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5608 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5609 ath_sysctl_diversity, "I", "antenna diversity");
5610 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
5611 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5612 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
5613 "tx descriptor batching");
5614 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5615 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5616 ath_sysctl_diag, "I", "h/w diagnostic control");
5617 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5618 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5619 ath_sysctl_tpscale, "I", "tx power scaling");
5620 if (ath_hal_hastpc(ah)) {
5621 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5622 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5623 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
5624 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5625 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5626 ath_sysctl_tpack, "I", "tx power for ack frames");
5627 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5628 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5629 ath_sysctl_tpcts, "I", "tx power for cts frames");
5631 if (ath_hal_hasrfsilent(ah)) {
5632 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5633 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5634 ath_sysctl_rfsilent, "I", "h/w RF silent config");
5635 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5636 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5637 ath_sysctl_rfkill, "I", "enable/disable RF kill switch");
5639 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
5640 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5641 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
5642 "mask of error frames to pass when monitoring");
5646 ath_bpfattach(struct ath_softc *sc)
5648 struct ifnet *ifp = &sc->sc_ic.ic_if;
5650 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
5651 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
5654 * Initialize constant fields.
5655 * XXX make header lengths a multiple of 32-bits so subsequent
5656 * headers are properly aligned; this is a kludge to keep
5657 * certain applications happy.
5659 * NB: the channel is setup each time we transition to the
5660 * RUN state to avoid filling it in for each frame.
5662 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
5663 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
5664 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT);
5666 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
5667 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
5668 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT);
5672 * Announce various information on device/driver attach.
5675 ath_announce(struct ath_softc *sc)
5677 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B)
5678 struct ifnet *ifp = &sc->sc_ic.ic_if;
5679 struct ath_hal *ah = sc->sc_ah;
5682 if_printf(ifp, "mac %d.%d phy %d.%d",
5683 ah->ah_macVersion, ah->ah_macRev,
5684 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
5686 * Print radio revision(s). We check the wireless modes
5687 * to avoid falsely printing revs for inoperable parts.
5688 * Dual-band radio revs are returned in the 5Ghz rev number.
5690 ath_hal_getcountrycode(ah, &cc);
5691 modes = ath_hal_getwirelessmodes(ah, cc);
5692 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) {
5693 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev)
5694 kprintf(" 5ghz radio %d.%d 2ghz radio %d.%d",
5695 ah->ah_analog5GhzRev >> 4,
5696 ah->ah_analog5GhzRev & 0xf,
5697 ah->ah_analog2GhzRev >> 4,
5698 ah->ah_analog2GhzRev & 0xf);
5700 kprintf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5701 ah->ah_analog5GhzRev & 0xf);
5703 kprintf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5704 ah->ah_analog5GhzRev & 0xf);
5708 for (i = 0; i <= WME_AC_VO; i++) {
5709 struct ath_txq *txq = sc->sc_ac2q[i];
5710 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5711 txq->axq_qnum, ieee80211_wme_acnames[i]);
5713 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5714 sc->sc_cabq->axq_qnum);
5715 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5717 if (ath_rxbuf != ATH_RXBUF)
5718 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
5719 if (ath_txbuf != ATH_TXBUF)
5720 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
5721 #undef HAL_MODE_DUALBAND
5725 ath_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nseg,
5726 bus_size_t mapsize, int error)
5728 struct ath_buf *bf = arg;
5733 KASSERT(nseg <= ATH_MAX_SCATTER, ("too many DMA segments"));
5734 bcopy(segs, bf->bf_segs, nseg * sizeof(bus_dma_segment_t));