2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
31 #include <machine/globaldata.h>
32 #include <machine/smp.h>
33 #include <machine/md_var.h>
34 #include <machine/pmap.h>
35 #include <machine_base/apic/mpapic.h>
36 #include <machine/segments.h>
37 #include <sys/thread2.h>
39 #include <machine/intr_machdep.h>
43 /* EISA Edge/Level trigger control registers */
44 #define ELCR0 0x4d0 /* eisa irq 0-7 */
45 #define ELCR1 0x4d1 /* eisa irq 8-15 */
47 volatile lapic_t *lapic;
49 static void lapic_timer_calibrate(void);
50 static void lapic_timer_set_divisor(int);
51 static void lapic_timer_fixup_handler(void *);
52 static void lapic_timer_restart_handler(void *);
54 void lapic_timer_process(void);
55 void lapic_timer_process_frame(struct intrframe *);
56 void lapic_timer_always(struct intrframe *);
58 static int lapic_timer_enable = 1;
59 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
61 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
62 static void lapic_timer_intr_enable(struct cputimer_intr *);
63 static void lapic_timer_intr_restart(struct cputimer_intr *);
64 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
66 static struct cputimer_intr lapic_cputimer_intr = {
68 .reload = lapic_timer_intr_reload,
69 .enable = lapic_timer_intr_enable,
70 .config = cputimer_intr_default_config,
71 .restart = lapic_timer_intr_restart,
72 .pmfixup = lapic_timer_intr_pmfixup,
73 .initclock = cputimer_intr_default_initclock,
74 .next = SLIST_ENTRY_INITIALIZER,
76 .type = CPUTIMER_INTR_LAPIC,
77 .prio = CPUTIMER_INTR_PRIO_LAPIC,
78 .caps = CPUTIMER_INTR_CAP_NONE
82 * pointers to pmapped apic hardware.
85 volatile ioapic_t **ioapic;
87 static int lapic_timer_divisor_idx = -1;
88 static const uint32_t lapic_timer_divisors[] = {
89 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
90 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
92 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
104 * Enable LAPIC, configure interrupts.
107 apic_initialize(boolean_t bsp)
113 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
114 * aggregate interrupt input from the 8259. The INTA cycle
115 * will be routed to the external controller (the 8259) which
116 * is expected to supply the vector.
118 * Must be setup edge triggered, active high.
120 * Disable LINT0 on the APs. It doesn't matter what delivery
121 * mode we use because we leave it masked.
123 temp = lapic->lvt_lint0;
124 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
125 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
126 if (mycpu->gd_cpuid == 0)
127 temp |= APIC_LVT_DM_EXTINT;
129 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
130 lapic->lvt_lint0 = temp;
133 * Setup LINT1 as NMI, masked till later.
134 * Edge trigger, active high.
136 temp = lapic->lvt_lint1;
137 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
138 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
139 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
140 lapic->lvt_lint1 = temp;
143 * Mask the LAPIC error interrupt, LAPIC performance counter
146 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
147 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
150 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
152 timer = lapic->lvt_timer;
153 timer &= ~APIC_LVTT_VECTOR;
154 timer |= XTIMER_OFFSET;
155 timer |= APIC_LVTT_MASKED;
156 lapic->lvt_timer = timer;
159 * Set the Task Priority Register as needed. At the moment allow
160 * interrupts on all cpus (the APs will remain CLId until they are
161 * ready to deal). We could disable all but IPIs by setting
162 * temp |= TPR_IPI for cpu != 0.
165 temp &= ~APIC_TPR_PRIO; /* clear priority field */
166 #ifdef SMP /* APIC-IO */
167 if (!apic_io_enable) {
170 * If we are NOT running the IO APICs, the LAPIC will only be used
171 * for IPIs. Set the TPR to prevent any unintentional interrupts.
174 #ifdef SMP /* APIC-IO */
183 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
184 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
187 * Set the spurious interrupt vector. The low 4 bits of the vector
190 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
191 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
192 temp &= ~APIC_SVR_VECTOR;
193 temp |= XSPURIOUSINT_OFFSET;
198 * Pump out a few EOIs to clean out interrupts that got through
199 * before we were able to set the TPR.
206 lapic_timer_calibrate();
207 if (lapic_timer_enable) {
208 cputimer_intr_register(&lapic_cputimer_intr);
209 cputimer_intr_select(&lapic_cputimer_intr, 0);
212 lapic_timer_set_divisor(lapic_timer_divisor_idx);
216 apic_dump("apic_initialize()");
220 lapic_timer_set_divisor(int divisor_idx)
222 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
223 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
227 lapic_timer_oneshot(u_int count)
231 value = lapic->lvt_timer;
232 value &= ~APIC_LVTT_PERIODIC;
233 lapic->lvt_timer = value;
234 lapic->icr_timer = count;
238 lapic_timer_oneshot_quick(u_int count)
240 lapic->icr_timer = count;
244 lapic_timer_calibrate(void)
248 /* Try to calibrate the local APIC timer. */
249 for (lapic_timer_divisor_idx = 0;
250 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
251 lapic_timer_divisor_idx++) {
252 lapic_timer_set_divisor(lapic_timer_divisor_idx);
253 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
255 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
256 if (value != APIC_TIMER_MAX_COUNT)
259 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
260 panic("lapic: no proper timer divisor?!\n");
261 lapic_cputimer_intr.freq = value / 2;
263 kprintf("lapic: divisor index %d, frequency %u Hz\n",
264 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
268 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
272 gd->gd_timer_running = 0;
274 count = sys_cputimer->count();
275 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
276 systimer_intr(&count, 0, frame);
280 lapic_timer_process(void)
282 lapic_timer_process_oncpu(mycpu, NULL);
286 lapic_timer_process_frame(struct intrframe *frame)
288 lapic_timer_process_oncpu(mycpu, frame);
292 * This manual debugging code is called unconditionally from Xtimer
293 * (the lapic timer interrupt) whether the current thread is in a
294 * critical section or not) and can be useful in tracking down lockups.
296 * NOTE: MANUAL DEBUG CODE
299 static int saveticks[SMP_MAXCPU];
300 static int savecounts[SMP_MAXCPU];
304 lapic_timer_always(struct intrframe *frame)
307 globaldata_t gd = mycpu;
308 int cpu = gd->gd_cpuid;
314 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
315 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
318 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
319 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
321 for (i = 0; buf[i]; ++i) {
322 gptr[i] = 0x0700 | (unsigned char)buf[i];
326 if (saveticks[gd->gd_cpuid] != ticks) {
327 saveticks[gd->gd_cpuid] = ticks;
328 savecounts[gd->gd_cpuid] = 0;
330 ++savecounts[gd->gd_cpuid];
331 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
332 panic("cpud %d panicing on ticks failure",
335 for (i = 0; i < ncpus; ++i) {
337 if (saveticks[i] && panicstr == NULL) {
338 delta = saveticks[i] - ticks;
339 if (delta < -10 || delta > 10) {
340 panic("cpu %d panicing on cpu %d watchdog",
350 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
352 struct globaldata *gd = mycpu;
354 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
358 if (gd->gd_timer_running) {
359 if (reload < lapic->ccr_timer)
360 lapic_timer_oneshot_quick(reload);
362 gd->gd_timer_running = 1;
363 lapic_timer_oneshot_quick(reload);
368 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
372 timer = lapic->lvt_timer;
373 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
374 lapic->lvt_timer = timer;
376 lapic_timer_fixup_handler(NULL);
380 lapic_timer_fixup_handler(void *arg)
387 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
389 * Detect the presence of C1E capability mostly on latest
390 * dual-cores (or future) k8 family. This feature renders
391 * the local APIC timer dead, so we disable it by reading
392 * the Interrupt Pending Message register and clearing both
393 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
396 * "BIOS and Kernel Developer's Guide for AMD NPT
397 * Family 0Fh Processors"
398 * #32559 revision 3.00
400 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
401 (cpu_id & 0x0fff0000) >= 0x00040000) {
404 msr = rdmsr(0xc0010055);
405 if (msr & 0x18000000) {
406 struct globaldata *gd = mycpu;
408 kprintf("cpu%d: AMD C1E detected\n",
410 wrmsr(0xc0010055, msr & ~0x18000000ULL);
413 * We are kinda stalled;
416 gd->gd_timer_running = 1;
417 lapic_timer_oneshot_quick(2);
427 lapic_timer_restart_handler(void *dummy __unused)
431 lapic_timer_fixup_handler(&started);
433 struct globaldata *gd = mycpu;
435 gd->gd_timer_running = 1;
436 lapic_timer_oneshot_quick(2);
441 * This function is called only by ACPI-CA code currently:
442 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
443 * module controls PM. So once ACPI-CA is attached, we try
444 * to apply the fixup to prevent LAPIC timer from hanging.
447 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
449 lwkt_send_ipiq_mask(smp_active_mask,
450 lapic_timer_fixup_handler, NULL);
454 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
456 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
461 * dump contents of local APIC registers
466 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
467 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
468 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
472 #ifdef SMP /* APIC-IO */
478 #define IOAPIC_ISA_INTS 16
479 #define REDIRCNT_IOAPIC(A) \
480 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
482 static int trigger (int apic, int pin, u_int32_t * flags);
483 static void polarity (int apic, int pin, u_int32_t * flags, int level);
485 #define DEFAULT_FLAGS \
491 #define DEFAULT_ISA_FLAGS \
500 io_apic_set_id(int apic, int id)
504 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* get current contents */
505 if (((ux & APIC_ID_MASK) >> 24) != id) {
506 kprintf("Changing APIC ID for IO APIC #%d"
507 " from %d to %d on chip\n",
508 apic, ((ux & APIC_ID_MASK) >> 24), id);
509 ux &= ~APIC_ID_MASK; /* clear the ID field */
511 ioapic_write(ioapic[apic], IOAPIC_ID, ux); /* write new value */
512 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* re-read && test */
513 if (((ux & APIC_ID_MASK) >> 24) != id)
514 panic("can't control IO APIC #%d ID, reg: 0x%08x",
521 io_apic_get_id(int apic)
523 return (ioapic_read(ioapic[apic], IOAPIC_ID) & APIC_ID_MASK) >> 24;
532 io_apic_setup_intpin(int apic, int pin)
534 int bus, bustype, irq;
535 u_char select; /* the select register is 8 bits */
536 u_int32_t flags; /* the window register is 32 bits */
537 u_int32_t target; /* the window register is 32 bits */
538 u_int32_t vector; /* the window register is 32 bits */
543 select = pin * 2 + IOAPIC_REDTBL0; /* register */
546 * Always clear an IO APIC pin before [re]programming it. This is
547 * particularly important if the pin is set up for a level interrupt
548 * as the IOART_REM_IRR bit might be set. When we reprogram the
549 * vector any EOI from pending ints on this pin could be lost and
550 * IRR might never get reset.
552 * To fix this problem, clear the vector and make sure it is
553 * programmed as an edge interrupt. This should theoretically
554 * clear IRR so we can later, safely program it as a level
559 flags = ioapic_read(ioapic[apic], select) & IOART_RESV;
560 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
561 flags |= IOART_DESTPHY | IOART_DELFIXED;
563 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
564 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
568 ioapic_write(ioapic[apic], select, flags | vector);
569 ioapic_write(ioapic[apic], select + 1, target);
574 * We only deal with vectored interrupts here. ? documentation is
575 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
578 * This test also catches unconfigured pins.
580 if (apic_int_type(apic, pin) != 0)
584 * Leave the pin unprogrammed if it does not correspond to
587 irq = apic_irq(apic, pin);
591 /* determine the bus type for this pin */
592 bus = apic_src_bus_id(apic, pin);
595 bustype = apic_bus_type(bus);
597 if ((bustype == ISA) &&
598 (pin < IOAPIC_ISA_INTS) &&
600 (apic_polarity(apic, pin) == 0x1) &&
601 (apic_trigger(apic, pin) == 0x3)) {
603 * A broken BIOS might describe some ISA
604 * interrupts as active-high level-triggered.
605 * Use default ISA flags for those interrupts.
607 flags = DEFAULT_ISA_FLAGS;
610 * Program polarity and trigger mode according to
613 flags = DEFAULT_FLAGS;
614 level = trigger(apic, pin, &flags);
616 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
617 polarity(apic, pin, &flags, level);
621 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
622 kgetenv_int(envpath, &cpuid);
624 /* ncpus may not be available yet */
629 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
630 apic, pin, irq, cpuid);
634 * Program the appropriate registers. This routing may be
635 * overridden when an interrupt handler for a device is
636 * actually added (see register_int(), which calls through
637 * the MACHINTR ABI to set up an interrupt handler/vector).
639 * The order in which we must program the two registers for
640 * safety is unclear! XXX
644 vector = IDT_OFFSET + irq; /* IDT vec */
645 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
646 /* Deliver all interrupts to CPU0 (BSP) */
647 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
649 flags |= ioapic_read(ioapic[apic], select) & IOART_RESV;
650 ioapic_write(ioapic[apic], select, flags | vector);
651 ioapic_write(ioapic[apic], select + 1, target);
657 io_apic_setup(int apic)
662 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
663 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
665 for (pin = 0; pin < maxpin; ++pin) {
666 io_apic_setup_intpin(apic, pin);
669 if (apic_int_type(apic, pin) >= 0) {
670 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
671 " cannot program!\n", apic, pin);
676 /* return GOOD status */
679 #undef DEFAULT_ISA_FLAGS
683 #define DEFAULT_EXTINT_FLAGS \
692 * XXX this function is only used by 8254 setup
693 * Setup the source of External INTerrupts.
696 ext_int_setup(int apic, int intr)
698 u_char select; /* the select register is 8 bits */
699 u_int32_t flags; /* the window register is 32 bits */
700 u_int32_t target; /* the window register is 32 bits */
701 u_int32_t vector; /* the window register is 32 bits */
705 if (apic_int_type(apic, intr) != 3)
709 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
710 kgetenv_int(envpath, &cpuid);
712 /* ncpus may not be available yet */
716 /* Deliver interrupts to CPU0 (BSP) */
717 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
719 select = IOAPIC_REDTBL0 + (2 * intr);
720 vector = IDT_OFFSET + intr;
721 flags = DEFAULT_EXTINT_FLAGS;
723 ioapic_write(ioapic[apic], select, flags | vector);
724 ioapic_write(ioapic[apic], select + 1, target);
728 #undef DEFAULT_EXTINT_FLAGS
732 * Set the trigger level for an IO APIC pin.
735 trigger(int apic, int pin, u_int32_t * flags)
740 static int intcontrol = -1;
742 switch (apic_trigger(apic, pin)) {
748 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
752 *flags |= IOART_TRGRLVL;
760 if ((id = apic_src_bus_id(apic, pin)) == -1)
763 switch (apic_bus_type(id)) {
765 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
769 eirq = apic_src_bus_irq(apic, pin);
771 if (eirq < 0 || eirq > 15) {
772 kprintf("EISA IRQ %d?!?!\n", eirq);
776 if (intcontrol == -1) {
777 intcontrol = inb(ELCR1) << 8;
778 intcontrol |= inb(ELCR0);
779 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
782 /* Use ELCR settings to determine level or edge mode */
783 level = (intcontrol >> eirq) & 1;
786 * Note that on older Neptune chipset based systems, any
787 * pci interrupts often show up here and in the ELCR as well
788 * as level sensitive interrupts attributed to the EISA bus.
792 *flags |= IOART_TRGRLVL;
794 *flags &= ~IOART_TRGRLVL;
799 *flags |= IOART_TRGRLVL;
808 panic("bad APIC IO INT flags");
813 * Set the polarity value for an IO APIC pin.
816 polarity(int apic, int pin, u_int32_t * flags, int level)
820 switch (apic_polarity(apic, pin)) {
826 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
830 *flags |= IOART_INTALO;
838 if ((id = apic_src_bus_id(apic, pin)) == -1)
841 switch (apic_bus_type(id)) {
843 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
847 /* polarity converter always gives active high */
848 *flags &= ~IOART_INTALO;
852 *flags |= IOART_INTALO;
861 panic("bad APIC IO INT flags");
866 * Print contents of unmasked IRQs.
873 kprintf("SMP: enabled INTs: ");
874 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
875 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
883 * Inter Processor Interrupt functions.
886 #endif /* SMP APIC-IO */
889 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
891 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
892 * vector is any valid SYSTEM INT vector
893 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
895 * A backlog of requests can create a deadlock between cpus. To avoid this
896 * we have to be able to accept IPIs at the same time we are trying to send
897 * them. The critical section prevents us from attempting to send additional
898 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
899 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
900 * to occur but fortunately it does not happen too often.
903 apic_ipi(int dest_type, int vector, int delivery_mode)
908 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
909 unsigned long rflags = read_rflags();
911 DEBUG_PUSH_INFO("apic_ipi");
912 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
916 write_rflags(rflags);
919 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
920 delivery_mode | vector;
921 lapic->icr_lo = icr_lo;
927 single_apic_ipi(int cpu, int vector, int delivery_mode)
933 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
934 unsigned long rflags = read_rflags();
936 DEBUG_PUSH_INFO("single_apic_ipi");
937 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
941 write_rflags(rflags);
943 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
944 icr_hi |= (CPU_TO_ID(cpu) << 24);
945 lapic->icr_hi = icr_hi;
948 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
949 | APIC_DEST_DESTFLD | delivery_mode | vector;
952 lapic->icr_lo = icr_lo;
959 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
961 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
962 * to the target, and the scheduler does not 'poll' for IPI messages.
965 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
971 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
975 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
976 icr_hi |= (CPU_TO_ID(cpu) << 24);
977 lapic->icr_hi = icr_hi;
980 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
981 | APIC_DEST_DESTFLD | delivery_mode | vector;
984 lapic->icr_lo = icr_lo;
992 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
994 * target is a bitmask of destination cpus. Vector is any
995 * valid system INT vector. Delivery mode may be either
996 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
999 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
1003 int n = BSFCPUMASK(target);
1004 target &= ~CPUMASK(n);
1005 single_apic_ipi(n, vector, delivery_mode);
1011 * Timer code, in development...
1012 * - suggested by rgrimes@gndrsh.aac.dev.com
1015 get_apic_timer_frequency(void)
1017 return(lapic_cputimer_intr.freq);
1021 * Load a 'downcount time' in uSeconds.
1024 set_apic_timer(int us)
1029 * When we reach here, lapic timer's frequency
1030 * must have been calculated as well as the
1031 * divisor (lapic->dcr_timer is setup during the
1032 * divisor calculation).
1034 KKASSERT(lapic_cputimer_intr.freq != 0 &&
1035 lapic_timer_divisor_idx >= 0);
1037 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
1038 lapic_timer_oneshot(count);
1043 * Read remaining time in timer.
1046 read_apic_timer(void)
1049 /** XXX FIXME: we need to return the actual remaining time,
1050 * for now we just return the remaining count.
1053 return lapic->ccr_timer;
1059 * Spin-style delay, set delay time in uS, spin till it drains.
1064 set_apic_timer(count);
1065 while (read_apic_timer())
1070 lapic_map(vm_offset_t lapic_addr)
1072 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
1074 kprintf("lapic: at 0x%08lx\n", lapic_addr);
1077 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1078 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1083 struct lapic_enumerator *e;
1086 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1087 error = e->lapic_probe(e);
1092 panic("can't config lapic\n");
1094 e->lapic_enumerate(e);
1098 lapic_enumerator_register(struct lapic_enumerator *ne)
1100 struct lapic_enumerator *e;
1102 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1103 if (e->lapic_prio < ne->lapic_prio) {
1104 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1108 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
1111 static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
1112 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
1117 struct ioapic_enumerator *e;
1120 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1121 error = e->ioapic_probe(e);
1127 panic("can't config I/O APIC\n");
1129 kprintf("no I/O APIC\n");
1134 e->ioapic_enumerate(e);
1138 ioapic_enumerator_register(struct ioapic_enumerator *ne)
1140 struct ioapic_enumerator *e;
1142 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1143 if (e->ioapic_prio < ne->ioapic_prio) {
1144 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
1148 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);