2 * Copyright (c) 2000 Matthew C. Forman
4 * Based (heavily) on alpm.c which is:
6 * Copyright (c) 1998, 1999 Nicolas Souchu
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/sys/pci/amdpm.c,v 1.22 2008/06/06 18:29:56 jhb Exp $
35 * Power management function/SMBus function support for the AMD 756 chip.
38 #include <sys/param.h>
40 #include <sys/globaldata.h>
41 #include <sys/kernel.h>
43 #include <sys/module.h>
45 #include <sys/systm.h>
47 #include <bus/pci/pcivar.h>
48 #include <bus/pci/pcireg.h>
50 #include <bus/smbus/smbconf.h>
53 #define AMDPM_DEBUG(x) if (amdpm_debug) (x)
56 static int amdpm_debug = 1;
58 static int amdpm_debug = 0;
61 #define AMDPM_VENDORID_AMD 0x1022
62 #define AMDPM_DEVICEID_AMD756PM 0x740b
63 #define AMDPM_DEVICEID_AMD766PM 0x7413
64 #define AMDPM_DEVICEID_AMD768PM 0x7443
65 #define AMDPM_DEVICEID_AMD8111PM 0x746B
67 /* nVidia nForce chipset */
68 #define AMDPM_VENDORID_NVIDIA 0x10de
69 #define AMDPM_DEVICEID_NF_SMB 0x01b4
71 /* PCI Configuration space registers */
72 #define AMDPCI_PMBASE 0x58
73 #define NFPCI_PMBASE 0x14
75 #define AMDPCI_GEN_CONFIG_PM 0x41
76 #define AMDPCI_PMIOEN (1<<7)
78 #define AMDPCI_SCIINT_CONFIG_PM 0x42
79 #define AMDPCI_SCISEL_IRQ11 11
81 #define AMDPCI_REVID 0x08
85 * Base address programmed via AMDPCI_PMBASE.
88 #define AMDSMB_GLOBAL_STATUS (0x00)
89 #define AMDSMB_GS_TO_STS (1<<5)
90 #define AMDSMB_GS_HCYC_STS (1<<4)
91 #define AMDSMB_GS_HST_STS (1<<3)
92 #define AMDSMB_GS_PRERR_STS (1<<2)
93 #define AMDSMB_GS_COL_STS (1<<1)
94 #define AMDSMB_GS_ABRT_STS (1<<0)
95 #define AMDSMB_GS_CLEAR_STS (AMDSMB_GS_TO_STS|AMDSMB_GS_HCYC_STS|AMDSMB_GS_PRERR_STS|AMDSMB_GS_COL_STS|AMDSMB_GS_ABRT_STS)
97 #define AMDSMB_GLOBAL_ENABLE (0x02)
98 #define AMDSMB_GE_ABORT (1<<5)
99 #define AMDSMB_GE_HCYC_EN (1<<4)
100 #define AMDSMB_GE_HOST_STC (1<<3)
101 #define AMDSMB_GE_CYC_QUICK 0
102 #define AMDSMB_GE_CYC_BYTE 1
103 #define AMDSMB_GE_CYC_BDATA 2
104 #define AMDSMB_GE_CYC_WDATA 3
105 #define AMDSMB_GE_CYC_PROCCALL 4
106 #define AMDSMB_GE_CYC_BLOCK 5
108 #define LSB 0x1 /* XXX: Better name: Read/Write? */
110 #define AMDSMB_HSTADDR (0x04)
111 #define AMDSMB_HSTDATA (0x06)
112 #define AMDSMB_HSTCMD (0x08)
113 #define AMDSMB_HSTDFIFO (0x09)
114 #define AMDSMB_HSLVDATA (0x0A)
115 #define AMDSMB_HSLVDA (0x0C)
116 #define AMDSMB_HSLVDDR (0x0E)
117 #define AMDSMB_SNPADDR (0x0F)
122 struct resource *res;
127 #define AMDPM_LOCK(amdpm) lockmgr(&(amdpm)->lock, LK_EXCLUSIVE)
128 #define AMDPM_UNLOCK(amdpm) lockmgr(&(amdpm)->lock, LK_RELEASE)
129 #define AMDPM_LOCK_ASSERT(amdpm) KKASSERT(lockstatus(&(amdpm)->lock, curthread) != 0)
131 #define AMDPM_SMBINB(amdpm,register) \
132 (bus_read_1(amdpm->res, register))
133 #define AMDPM_SMBOUTB(amdpm,register,value) \
134 (bus_write_1(amdpm->res, register, value))
135 #define AMDPM_SMBINW(amdpm,register) \
136 (bus_read_2(amdpm->res, register))
137 #define AMDPM_SMBOUTW(amdpm,register,value) \
138 (bus_write_2(amdpm->res, register, value))
140 static int amdpm_detach(device_t dev);
143 amdpm_probe(device_t dev)
149 vid = pci_get_vendor(dev);
150 did = pci_get_device(dev);
151 if ((vid == AMDPM_VENDORID_AMD) &&
152 ((did == AMDPM_DEVICEID_AMD756PM) ||
153 (did == AMDPM_DEVICEID_AMD766PM) ||
154 (did == AMDPM_DEVICEID_AMD768PM) ||
155 (did == AMDPM_DEVICEID_AMD8111PM))) {
156 device_set_desc(dev, "AMD 756/766/768/8111 Power Management Controller");
159 * We have to do this, since the BIOS won't give us the
160 * resource info (not mine, anyway).
162 base = pci_read_config(dev, AMDPCI_PMBASE, 4);
164 bus_set_resource(dev, SYS_RES_IOPORT, AMDPCI_PMBASE,
166 return (BUS_PROBE_DEFAULT);
169 if ((vid == AMDPM_VENDORID_NVIDIA) &&
170 (did == AMDPM_DEVICEID_NF_SMB)) {
171 device_set_desc(dev, "nForce SMBus Controller");
174 * We have to do this, since the BIOS won't give us the
175 * resource info (not mine, anyway).
177 base = pci_read_config(dev, NFPCI_PMBASE, 4);
179 bus_set_resource(dev, SYS_RES_IOPORT, NFPCI_PMBASE,
182 return (BUS_PROBE_DEFAULT);
189 amdpm_attach(device_t dev)
191 struct amdpm_softc *amdpm_sc = device_get_softc(dev);
194 /* Enable I/O block access */
195 val_b = pci_read_config(dev, AMDPCI_GEN_CONFIG_PM, 1);
196 pci_write_config(dev, AMDPCI_GEN_CONFIG_PM, val_b | AMDPCI_PMIOEN, 1);
198 /* Allocate I/O space */
199 if (pci_get_vendor(dev) == AMDPM_VENDORID_AMD)
200 amdpm_sc->rid = AMDPCI_PMBASE;
202 amdpm_sc->rid = NFPCI_PMBASE;
203 amdpm_sc->res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
204 &amdpm_sc->rid, RF_ACTIVE);
206 if (amdpm_sc->res == NULL) {
207 device_printf(dev, "could not map i/o space\n");
211 lockinit(&amdpm_sc->lock, "amdpm", 0, LK_CANRECURSE);
213 /* Allocate a new smbus device */
214 amdpm_sc->smbus = device_add_child(dev, "smbus", -1);
215 if (!amdpm_sc->smbus) {
220 bus_generic_attach(dev);
226 amdpm_detach(device_t dev)
228 struct amdpm_softc *amdpm_sc = device_get_softc(dev);
230 if (amdpm_sc->smbus) {
231 device_delete_child(dev, amdpm_sc->smbus);
232 amdpm_sc->smbus = NULL;
235 lockuninit(&amdpm_sc->lock);
237 bus_release_resource(dev, SYS_RES_IOPORT, amdpm_sc->rid,
244 amdpm_callback(device_t dev, int index, void *data)
249 case SMB_REQUEST_BUS:
250 case SMB_RELEASE_BUS:
260 amdpm_clear(struct amdpm_softc *sc)
263 AMDPM_LOCK_ASSERT(sc);
264 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_STATUS, AMDSMB_GS_CLEAR_STS);
272 amdpm_abort(struct amdpm_softc *sc)
276 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
277 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, l | AMDSMB_GE_ABORT);
284 amdpm_idle(struct amdpm_softc *sc)
288 AMDPM_LOCK_ASSERT(sc);
289 sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
291 AMDPM_DEBUG(kprintf("amdpm: busy? STS=0x%x\n", sts));
293 return (~(sts & AMDSMB_GS_HST_STS));
297 * Poll the SMBus controller
300 amdpm_wait(struct amdpm_softc *sc)
306 AMDPM_LOCK_ASSERT(sc);
307 /* Wait for command to complete (SMBus controller is idle) */
310 sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
311 if (!(sts & AMDSMB_GS_HST_STS))
315 AMDPM_DEBUG(kprintf("amdpm: STS=0x%x (count=%d)\n", sts, count));
320 error |= SMB_ETIMEOUT;
322 if (sts & AMDSMB_GS_ABRT_STS)
325 if (sts & AMDSMB_GS_COL_STS)
328 if (sts & AMDSMB_GS_PRERR_STS)
329 error |= SMB_EBUSERR;
331 if (error != SMB_ENOERR)
338 amdpm_quick(device_t dev, u_char slave, int how)
340 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
346 if (!amdpm_idle(sc)) {
353 AMDPM_DEBUG(kprintf("amdpm: QWRITE to 0x%x", slave));
354 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
357 AMDPM_DEBUG(kprintf("amdpm: QREAD to 0x%x", slave));
358 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
361 panic("%s: unknown QUICK command (%x)!", __func__, how);
363 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
364 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_QUICK | AMDSMB_GE_HOST_STC);
366 error = amdpm_wait(sc);
368 AMDPM_DEBUG(kprintf(", error=0x%x\n", error));
375 amdpm_sendb(device_t dev, u_char slave, char byte)
377 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
383 if (!amdpm_idle(sc)) {
388 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
389 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
390 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
391 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
393 error = amdpm_wait(sc);
395 AMDPM_DEBUG(kprintf("amdpm: SENDB to 0x%x, byte=0x%x, error=0x%x\n", slave, byte, error));
402 amdpm_recvb(device_t dev, u_char slave, char *byte)
404 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
410 if (!amdpm_idle(sc)) {
415 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
416 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
417 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
419 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
420 *byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
422 AMDPM_DEBUG(kprintf("amdpm: RECVB from 0x%x, byte=0x%x, error=0x%x\n", slave, *byte, error));
429 amdpm_writeb(device_t dev, u_char slave, char cmd, char byte)
431 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
437 if (!amdpm_idle(sc)) {
442 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
443 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
444 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
445 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
446 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
448 error = amdpm_wait(sc);
450 AMDPM_DEBUG(kprintf("amdpm: WRITEB to 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, byte, error));
457 amdpm_readb(device_t dev, u_char slave, char cmd, char *byte)
459 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
465 if (!amdpm_idle(sc)) {
470 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
471 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
472 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
473 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
475 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
476 *byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
478 AMDPM_DEBUG(kprintf("amdpm: READB from 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, *byte, error));
485 amdpm_writew(device_t dev, u_char slave, char cmd, short word)
487 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
493 if (!amdpm_idle(sc)) {
498 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
499 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, word);
500 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
501 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
502 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
504 error = amdpm_wait(sc);
506 AMDPM_DEBUG(kprintf("amdpm: WRITEW to 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, word, error));
513 amdpm_readw(device_t dev, u_char slave, char cmd, short *word)
515 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
521 if (!amdpm_idle(sc)) {
526 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
527 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
528 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
529 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
531 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
532 *word = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
534 AMDPM_DEBUG(kprintf("amdpm: READW from 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, *word, error));
541 amdpm_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
543 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
548 if (count < 1 || count > 32)
553 if (!amdpm_idle(sc)) {
558 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
561 * Do we have to reset the internal 32-byte buffer?
562 * Can't see how to do this from the data sheet.
564 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, count);
566 /* Fill the 32-byte internal buffer */
567 for (i = 0; i < count; i++) {
568 AMDPM_SMBOUTB(sc, AMDSMB_HSTDFIFO, buf[i]);
571 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
572 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
573 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE,
574 (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
576 error = amdpm_wait(sc);
578 AMDPM_DEBUG(kprintf("amdpm: WRITEBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, count, cmd, error));
585 amdpm_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
587 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
592 if (*count < 1 || *count > 32)
597 if (!amdpm_idle(sc)) {
602 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
604 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
606 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
607 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE,
608 (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
610 if ((error = amdpm_wait(sc)) != SMB_ENOERR)
613 len = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
615 /* Read the 32-byte internal buffer */
616 for (i = 0; i < len; i++) {
617 data = AMDPM_SMBINB(sc, AMDSMB_HSTDFIFO);
625 AMDPM_DEBUG(kprintf("amdpm: READBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, *count, cmd, error));
631 static devclass_t amdpm_devclass;
633 static device_method_t amdpm_methods[] = {
634 /* Device interface */
635 DEVMETHOD(device_probe, amdpm_probe),
636 DEVMETHOD(device_attach, amdpm_attach),
637 DEVMETHOD(device_detach, amdpm_detach),
639 /* SMBus interface */
640 DEVMETHOD(smbus_callback, amdpm_callback),
641 DEVMETHOD(smbus_quick, amdpm_quick),
642 DEVMETHOD(smbus_sendb, amdpm_sendb),
643 DEVMETHOD(smbus_recvb, amdpm_recvb),
644 DEVMETHOD(smbus_writeb, amdpm_writeb),
645 DEVMETHOD(smbus_readb, amdpm_readb),
646 DEVMETHOD(smbus_writew, amdpm_writew),
647 DEVMETHOD(smbus_readw, amdpm_readw),
648 DEVMETHOD(smbus_bwrite, amdpm_bwrite),
649 DEVMETHOD(smbus_bread, amdpm_bread),
654 static driver_t amdpm_driver = {
657 sizeof(struct amdpm_softc),
660 DRIVER_MODULE(amdpm, pci, amdpm_driver, amdpm_devclass, NULL, NULL);
661 DRIVER_MODULE(smbus, amdpm, smbus_driver, smbus_devclass, NULL, NULL);
663 MODULE_DEPEND(amdpm, pci, 1, 1, 1);
664 MODULE_DEPEND(amdpm, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
665 MODULE_VERSION(amdpm, 1);