2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/ar/if_ar.c,v 1.52.2.1 2002/06/17 15:10:57 jhay Exp $
29 * $DragonFly: src/sys/dev/netif/ar/if_ar.c,v 1.6 2004/01/06 01:40:46 dillon Exp $
33 * Programming assumptions and other issues.
35 * The descriptors of a DMA channel will fit in a 16K memory window.
37 * The buffers of a transmit DMA channel will fit in a 16K memory window.
39 * Only the ISA bus cards with X.21 and V.35 is tested.
41 * When interface is going up, handshaking is set and it is only cleared
42 * when the interface is down'ed.
44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
45 * internal/external clock, etc.....
49 #include "opt_netgraph.h"
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/kernel.h>
54 #include <sys/malloc.h>
56 #include <sys/socket.h>
57 #include <sys/sockio.h>
58 #include <sys/module.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
62 #include <machine/bus_pio.h>
63 #include <machine/bus_memio.h>
68 #include <netgraph/ng_message.h>
69 #include <netgraph/netgraph.h>
70 #include <sys/syslog.h>
73 #include <net/sppp/if_sppp.h>
77 #include <machine/clock.h>
78 #include <machine/md_var.h>
80 #include "../ic_layer/hd64570.h"
81 #include "if_arregs.h"
91 #define PPP_HEADER_LEN 4
97 int unit; /* With regards to all ar devices */
98 int subunit; /* With regards to this card */
102 u_int txdesc; /* On card address */
103 u_int txstart; /* On card address */
104 u_int txend; /* On card address */
105 u_int txtail; /* Index of first unused buffer */
106 u_int txmax; /* number of usable buffers/descriptors */
107 u_int txeda; /* Error descriptor addresses */
108 }block[AR_TX_BLOCKS];
110 char xmit_busy; /* Transmitter is busy */
111 char txb_inuse; /* Number of tx blocks currently in use */
112 u_char txb_new; /* Index to where new buffer will be added */
113 u_char txb_next_tx; /* Index to next block ready to tx */
115 u_int rxdesc; /* On card address */
116 u_int rxstart; /* On card address */
117 u_int rxend; /* On card address */
118 u_int rxhind; /* Index to the head of the rx buffers. */
119 u_int rxmax; /* number of usable buffers/descriptors */
125 int running; /* something is attached so we are running */
126 int dcd; /* do we have dcd? */
127 /* ---netgraph bits --- */
128 char nodename[NG_NODELEN + 1]; /* store our node name */
129 int datahooks; /* number of data hooks attached */
130 node_p node; /* netgraph node */
131 hook_p hook; /* data hook */
133 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
134 struct ifqueue xmitq; /* transmit queue */
135 int flags; /* state */
136 #define SCF_RUNNING 0x01 /* board is active */
137 #define SCF_OACTIVE 0x02 /* output is active */
138 int out_dog; /* watchdog cycles output count-down */
139 struct callout_handle handle; /* timeout(9) handle */
140 u_long inbytes, outbytes; /* stats */
141 u_long lastinbytes, lastoutbytes; /* a second ago */
142 u_long inrate, outrate; /* highest rate seen */
143 u_long inlast; /* last input N secs ago */
144 u_long out_deficit; /* output since last input */
145 u_long oerrors, ierrors[6];
146 u_long opackets, ipackets;
147 #endif /* NETGRAPH */
150 static int next_ar_unit = 0;
153 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
154 #define QUITE_A_WHILE 300 /* 5 MINUTES */
155 #define LOTS_OF_PACKETS 100
156 #endif /* NETGRAPH */
159 * This translate from irq numbers to
160 * the value that the arnet card needs
161 * in the lower part of the AR_INT_SEL
164 static int irqtable[16] = {
184 DECLARE_DUMMY_MODULE(if_ar);
185 MODULE_DEPEND(if_ar, sppp, 1, 1, 1);
187 MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1);
190 static void arintr(void *arg);
191 static void ar_xmit(struct ar_softc *sc);
193 static void arstart(struct ifnet *ifp);
194 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
195 static void arwatchdog(struct ifnet *ifp);
197 static void arstart(struct ar_softc *sc);
198 static void arwatchdog(struct ar_softc *sc);
199 #endif /* NETGRAPH */
200 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat);
201 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len);
202 static void ar_eat_packet(struct ar_softc *sc, int single);
203 static void ar_get_packets(struct ar_softc *sc);
205 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel);
206 static void ar_up(struct ar_softc *sc);
207 static void ar_down(struct ar_softc *sc);
208 static void arc_init(struct ar_hardc *hc);
209 static void ar_init_sca(struct ar_hardc *hc, int scano);
210 static void ar_init_msci(struct ar_softc *sc);
211 static void ar_init_rx_dmac(struct ar_softc *sc);
212 static void ar_init_tx_dmac(struct ar_softc *sc);
213 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr);
214 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr);
215 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr);
218 static void ngar_watchdog_frame(void * arg);
219 static void ngar_init(void* ignored);
221 static ng_constructor_t ngar_constructor;
222 static ng_rcvmsg_t ngar_rcvmsg;
223 static ng_shutdown_t ngar_rmnode;
224 static ng_newhook_t ngar_newhook;
225 /*static ng_findhook_t ngar_findhook; */
226 static ng_connect_t ngar_connect;
227 static ng_rcvdata_t ngar_rcvdata;
228 static ng_disconnect_t ngar_disconnect;
230 static struct ng_type typestruct = {
246 static int ngar_done_init = 0;
247 #endif /* NETGRAPH */
250 ar_attach(device_t device)
257 #endif /* NETGRAPH */
260 hc = (struct ar_hardc *)device_get_softc(device);
262 printf("arc%d: %uK RAM, %u ports, rev %u.\n",
270 if(BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
271 INTR_TYPE_NET, arintr, hc, &hc->intr_cookie) != 0)
276 for(unit=0;unit<hc->numports;unit+=NCHAN)
277 ar_init_sca(hc, unit / NCHAN);
280 * Now configure each port on the card.
282 for(unit=0;unit<hc->numports;sc++,unit++) {
285 sc->unit = next_ar_unit;
287 sc->scano = unit / NCHAN;
288 sc->scachan = unit%NCHAN;
295 ifp = &sc->ifsppp.pp_if;
298 if_initname(ifp, "ar", unit);
299 ifp->if_mtu = PP_MTU;
300 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
301 ifp->if_ioctl = arioctl;
302 ifp->if_start = arstart;
303 ifp->if_watchdog = arwatchdog;
305 sc->ifsppp.pp_flags = PP_KEEPALIVE;
307 switch(hc->interface[unit]) {
308 default: iface = "UNKNOWN"; break;
309 case AR_IFACE_EIA_232: iface = "EIA-232"; break;
310 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break;
311 case AR_IFACE_EIA_530: iface = "EIA-530"; break;
312 case AR_IFACE_X_21: iface = "X.21"; break;
313 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break;
316 printf("ar%d: Adapter %d, port %d, interface %s.\n",
322 sppp_attach((struct ifnet *)&sc->ifsppp);
325 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
328 * we have found a node, make sure our 'type' is availabe.
330 if (ngar_done_init == 0) ngar_init(NULL);
331 if (ng_make_node_common(&typestruct, &sc->node) != 0)
333 sc->node->private = sc;
334 callout_handle_init(&sc->handle);
335 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
336 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
337 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
338 if (ng_name_node(sc->node, sc->nodename)) {
344 #endif /* NETGRAPH */
347 if(hc->bustype == AR_BUS_ISA)
348 ARC_SET_OFF(hc->iobase);
354 ar_detach(device_t device)
356 device_t parent = device_get_parent(device);
357 struct ar_hardc *hc = device_get_softc(device);
359 if (hc->intr_cookie != NULL) {
360 if (BUS_TEARDOWN_INTR(parent, device,
361 hc->res_irq, hc->intr_cookie) != 0) {
362 printf("intr teardown failed.. continuing\n");
364 hc->intr_cookie = NULL;
368 * deallocate any system resources we may have
369 * allocated on behalf of this driver.
371 FREE(hc->sc, M_DEVBUF);
373 hc->mem_start = NULL;
374 return (ar_deallocate_resources(device));
378 ar_allocate_ioport(device_t device, int rid, u_long size)
380 struct ar_hardc *hc = device_get_softc(device);
382 hc->rid_ioport = rid;
383 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
384 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
385 if (hc->res_ioport == NULL) {
391 ar_deallocate_resources(device);
396 ar_allocate_irq(device_t device, int rid, u_long size)
398 struct ar_hardc *hc = device_get_softc(device);
401 hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ,
402 &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE);
403 if (hc->res_irq == NULL) {
409 ar_deallocate_resources(device);
414 ar_allocate_memory(device_t device, int rid, u_long size)
416 struct ar_hardc *hc = device_get_softc(device);
418 hc->rid_memory = rid;
419 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
420 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
421 if (hc->res_memory == NULL) {
427 ar_deallocate_resources(device);
432 ar_allocate_plx_memory(device_t device, int rid, u_long size)
434 struct ar_hardc *hc = device_get_softc(device);
436 hc->rid_plx_memory = rid;
437 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
438 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
439 if (hc->res_plx_memory == NULL) {
445 ar_deallocate_resources(device);
450 ar_deallocate_resources(device_t device)
452 struct ar_hardc *hc = device_get_softc(device);
454 if (hc->res_irq != 0) {
455 bus_deactivate_resource(device, SYS_RES_IRQ,
456 hc->rid_irq, hc->res_irq);
457 bus_release_resource(device, SYS_RES_IRQ,
458 hc->rid_irq, hc->res_irq);
461 if (hc->res_ioport != 0) {
462 bus_deactivate_resource(device, SYS_RES_IOPORT,
463 hc->rid_ioport, hc->res_ioport);
464 bus_release_resource(device, SYS_RES_IOPORT,
465 hc->rid_ioport, hc->res_ioport);
468 if (hc->res_memory != 0) {
469 bus_deactivate_resource(device, SYS_RES_MEMORY,
470 hc->rid_memory, hc->res_memory);
471 bus_release_resource(device, SYS_RES_MEMORY,
472 hc->rid_memory, hc->res_memory);
475 if (hc->res_plx_memory != 0) {
476 bus_deactivate_resource(device, SYS_RES_MEMORY,
477 hc->rid_plx_memory, hc->res_plx_memory);
478 bus_release_resource(device, SYS_RES_MEMORY,
479 hc->rid_plx_memory, hc->res_plx_memory);
480 hc->res_plx_memory = 0;
486 * First figure out which SCA gave the interrupt.
488 * See if there is other interrupts pending.
489 * Repeat until there is no more interrupts.
494 struct ar_hardc *hc = (struct ar_hardc *)arg;
496 u_char isr0, isr1, isr2, arisr;
499 /* XXX Use the PCI interrupt score board register later */
500 if(hc->bustype == AR_BUS_PCI)
501 arisr = hc->orbase[AR_ISTAT * 4];
503 arisr = inb(hc->iobase + AR_ISTAT);
505 while(arisr & AR_BD_INT) {
506 TRC(printf("arisr = %x\n", arisr));
509 else if(arisr & AR_INT_1)
512 /* XXX Oops this shouldn't happen. */
513 printf("arc%d: Interrupted with no interrupt.\n",
517 sca = hc->sca[scano];
519 if(hc->bustype == AR_BUS_ISA)
520 ARC_SET_SCA(hc->iobase, scano);
526 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n",
532 ar_msci_intr(hc, scano, isr0);
535 ar_dmac_intr(hc, scano, isr1);
538 ar_timer_intr(hc, scano, isr2);
541 * Proccess the second sca's interrupt if available.
542 * Else see if there are any new interrupts.
544 if((arisr & AR_INT_0) && (arisr & AR_INT_1))
547 if(hc->bustype == AR_BUS_PCI)
548 arisr = hc->orbase[AR_ISTAT * 4];
550 arisr = inb(hc->iobase + AR_ISTAT);
554 if(hc->bustype == AR_BUS_ISA)
555 ARC_SET_OFF(hc->iobase);
560 * This will only start the transmitter. It is assumed that the data
561 * is already there. It is normally called from arstart() or ar_dmac_intr().
565 ar_xmit(struct ar_softc *sc)
569 #endif /* NETGRAPH */
573 ifp = &sc->ifsppp.pp_if;
574 #endif /* NETGRAPH */
575 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
577 if(sc->hc->bustype == AR_BUS_ISA)
578 ARC_SET_SCA(sc->hc->iobase, sc->scano);
579 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff);
581 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff);
582 dmac->dsr = SCA_DSR_DE;
587 if(sc->txb_next_tx == AR_TX_BLOCKS)
591 ifp->if_timer = 2; /* Value in seconds. */
593 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
594 #endif /* NETGRAPH */
595 if(sc->hc->bustype == AR_BUS_ISA)
596 ARC_SET_OFF(sc->hc->iobase);
600 * This function will be called from the upper level when a user add a
601 * packet to be send, and from the interrupt handler after a finished
604 * NOTE: it should run at spl_imp().
606 * This function only place the data in the oncard buffers. It does not
607 * start the transmition. ar_xmit() does that.
609 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function
610 * that clears that should ensure that the transmitter and its DMA is
611 * in a "good" idle state.
615 arstart(struct ifnet *ifp)
617 struct ar_softc *sc = ifp->if_softc;
620 arstart(struct ar_softc *sc)
622 #endif /* NETGRAPH */
626 sca_descriptor *txdesc;
627 struct buf_block *blkp;
630 if(!(ifp->if_flags & IFF_RUNNING))
634 #endif /* NETGRAPH */
639 * See if we have space for more packets.
641 if(sc->txb_inuse == AR_TX_BLOCKS) {
643 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
645 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
646 #endif /* NETGRAPH */
651 mtx = sppp_dequeue(ifp);
653 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
655 IF_DEQUEUE(&sc->xmitq, mtx);
657 #endif /* NETGRAPH */
662 * It is OK to set the memory window outside the loop because
663 * all tx buffers and descriptors are assumed to be in the same
666 if(sc->hc->bustype == AR_BUS_ISA)
667 ARC_SET_MEM(sc->hc->iobase, sc->block[0].txdesc);
670 * We stay in this loop until there is nothing in the
671 * TX queue left or the tx buffer is full.
674 blkp = &sc->block[sc->txb_new];
675 txdesc = (sca_descriptor *)
676 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk));
677 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk));
679 len = mtx->m_pkthdr.len;
681 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len));
684 * We can do this because the tx buffers don't wrap.
686 m_copydata(mtx, 0, len, txdata);
688 while(tlen > AR_BUF_SIZ) {
690 txdesc->len = AR_BUF_SIZ;
693 txdata += AR_BUF_SIZ;
696 /* XXX Move into the loop? */
697 txdesc->stat = SCA_DESC_EOM;
700 txdata += AR_BUF_SIZ;
707 ++sc->ifsppp.pp_if.if_opackets;
712 #endif /* NETGRAPH */
715 * Check if we have space for another mbuf.
716 * XXX This is hardcoded. A packet won't be larger
717 * than 3 buffers (3 x 512).
719 if((i + 3) >= blkp->txmax)
723 mtx = sppp_dequeue(ifp);
725 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
727 IF_DEQUEUE(&sc->xmitq, mtx);
729 #endif /* NETGRAPH */
737 * Mark the last descriptor, so that the SCA know where
741 txdesc->stat |= SCA_DESC_EOT;
743 txdesc = (sca_descriptor *)blkp->txdesc;
744 blkp->txeda = (u_short)((u_int)&txdesc[i]);
747 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp);
748 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp);
749 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb);
750 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len);
751 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat);
756 if(sc->txb_new == AR_TX_BLOCKS)
759 if(sc->xmit_busy == 0)
762 if(sc->hc->bustype == AR_BUS_ISA)
763 ARC_SET_OFF(sc->hc->iobase);
770 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
773 int was_up, should_be_up;
774 struct ar_softc *sc = ifp->if_softc;
776 TRC(printf("%s: arioctl.\n", ifp->if_xname);)
778 was_up = ifp->if_flags & IFF_RUNNING;
780 error = sppp_ioctl(ifp, cmd, data);
781 TRC(printf("%s: ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
782 ifp->if_xname, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);)
786 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR))
789 TRC(printf("%s: arioctl %s.\n", ifp->if_xname,
790 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
793 should_be_up = ifp->if_flags & IFF_RUNNING;
795 if(!was_up && should_be_up) {
796 /* Interface should be up -- start it. */
799 /* XXX Maybe clear the IFF_UP flag so that the link
800 * will only go up after sppp lcp and ipcp negotiation.
802 } else if(was_up && !should_be_up) {
803 /* Interface should be down -- stop it. */
810 #endif /* NETGRAPH */
813 * This is to catch lost tx interrupts.
817 arwatchdog(struct ifnet *ifp)
819 struct ar_softc *sc = ifp->if_softc;
821 arwatchdog(struct ar_softc *sc)
823 #endif /* NETGRAPH */
824 msci_channel *msci = &sc->sca->msci[sc->scachan];
827 if(!(ifp->if_flags & IFF_RUNNING))
829 #endif /* NETGRAPH */
831 if(sc->hc->bustype == AR_BUS_ISA)
832 ARC_SET_SCA(sc->hc->iobase, sc->scano);
834 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */
835 printf("ar%d: transmit failed, "
836 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n",
841 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr);
843 if(msci->st1 & SCA_ST1_UDRN) {
844 msci->cmd = SCA_CMD_TXABORT;
845 msci->cmd = SCA_CMD_TXENABLE;
846 msci->st1 = SCA_ST1_UDRN;
851 ifp->if_flags &= ~IFF_OACTIVE;
853 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */
854 #endif /* NETGRAPH */
856 if(sc->txb_inuse && --sc->txb_inuse)
863 #endif /* NETGRAPH */
867 ar_up(struct ar_softc *sc)
873 msci = &sca->msci[sc->scachan];
875 TRC(printf("ar%d: sca %p, msci %p, ch %d\n",
876 sc->unit, sca, msci, sc->scachan));
879 * Enable transmitter and receiver.
883 if(sc->hc->bustype == AR_BUS_ISA)
884 ARC_SET_SCA(sc->hc->iobase, sc->scano);
887 * What about using AUTO mode in msci->md0 ???
888 * And what about CTS/DCD etc... ?
890 if(sc->hc->handshake & AR_SHSK_RTS)
891 msci->ctl &= ~SCA_CTL_RTS;
892 if(sc->hc->handshake & AR_SHSK_DTR) {
893 sc->hc->txc_dtr[sc->scano] &= sc->scachan ?
894 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0;
895 if(sc->hc->bustype == AR_BUS_PCI)
896 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
897 sc->hc->txc_dtr[sc->scano];
899 outb(sc->hc->iobase + sc->hc->txc_dtr_off[sc->scano],
900 sc->hc->txc_dtr[sc->scano]);
903 if(sc->scachan == 0) {
911 msci->cmd = SCA_CMD_RXENABLE;
912 if(sc->hc->bustype == AR_BUS_ISA)
913 inb(sc->hc->iobase + AR_ID_5); /* XXX slow it down a bit. */
914 msci->cmd = SCA_CMD_TXENABLE;
916 if(sc->hc->bustype == AR_BUS_ISA)
917 ARC_SET_OFF(sc->hc->iobase);
919 untimeout(ngar_watchdog_frame, sc, sc->handle);
920 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
922 #endif /* NETGRAPH */
926 ar_down(struct ar_softc *sc)
932 msci = &sca->msci[sc->scachan];
935 untimeout(ngar_watchdog_frame, sc, sc->handle);
937 #endif /* NETGRAPH */
939 * Disable transmitter and receiver.
941 * Disable interrupts.
943 if(sc->hc->bustype == AR_BUS_ISA)
944 ARC_SET_SCA(sc->hc->iobase, sc->scano);
945 msci->cmd = SCA_CMD_RXDISABLE;
946 if(sc->hc->bustype == AR_BUS_ISA)
947 inb(sc->hc->iobase + AR_ID_5); /* XXX slow it down a bit. */
948 msci->cmd = SCA_CMD_TXDISABLE;
950 if(sc->hc->handshake & AR_SHSK_RTS)
951 msci->ctl |= SCA_CTL_RTS;
952 if(sc->hc->handshake & AR_SHSK_DTR) {
953 sc->hc->txc_dtr[sc->scano] |= sc->scachan ?
954 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0;
955 if(sc->hc->bustype == AR_BUS_PCI)
956 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
957 sc->hc->txc_dtr[sc->scano];
959 outb(sc->hc->iobase + sc->hc->txc_dtr_off[sc->scano],
960 sc->hc->txc_dtr[sc->scano]);
963 if(sc->scachan == 0) {
971 if(sc->hc->bustype == AR_BUS_ISA)
972 ARC_SET_OFF(sc->hc->iobase);
976 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel)
978 int ctype, i, val, x;
979 volatile u_char *pimctrl;
984 pimctrl = hc->orbase + AR_PIMCTRL;
988 *pimctrl = AR_PIM_STROBE;
990 /* Check if there is a PIM */
992 *pimctrl = AR_PIM_READ;
994 TRC(printf("x = %x", x));
995 if(x & AR_PIM_DATA) {
996 printf("No PIM installed\n");
997 return (AR_IFACE_UNKNOWN);
1000 x = (x >> 1) & 0x01;
1003 /* Now read the next 15 bits */
1004 for(i = 1; i < 16; i++) {
1005 *pimctrl = AR_PIM_READ;
1006 *pimctrl = AR_PIM_READ | AR_PIM_STROBE;
1008 TRC(printf(" %x ", x));
1009 x = (x >> 1) & 0x01;
1011 if(i == 8 && (val & 0x000f) == 0x0004) {
1015 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1016 *pimctrl = AR_PIM_A2D_DOUT;
1019 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1020 *pimctrl = AR_PIM_A2D_DOUT;
1023 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1024 *pimctrl = AR_PIM_A2D_DOUT;
1026 /* Select channel */
1027 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2);
1028 *pimctrl = ((channel & 2) << 2);
1029 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3);
1030 *pimctrl = ((channel & 1) << 3);
1032 *pimctrl = AR_PIM_A2D_STROBE;
1036 printf("\nOops A2D start bit not zero (%X)\n", x);
1038 for(ii = 7; ii >= 0; ii--) {
1040 *pimctrl = AR_PIM_A2D_STROBE;
1047 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype));
1048 *pimctrl = AR_PIM_MODEG;
1049 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1051 return (AR_IFACE_UNKNOWN);
1053 return (AR_IFACE_V_35);
1055 return (AR_IFACE_EIA_232);
1057 return (AR_IFACE_X_21);
1059 return (AR_IFACE_EIA_530);
1061 return (AR_IFACE_UNKNOWN);
1063 return (AR_IFACE_LOOPBACK);
1064 return (AR_IFACE_UNKNOWN);
1068 * Initialize the card, allocate memory for the ar_softc structures
1069 * and fill in the pointers.
1072 arc_init(struct ar_hardc *hc)
1074 struct ar_softc *sc;
1082 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc),
1083 M_DEVBUF, M_WAITOK | M_ZERO);
1088 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET |
1089 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1090 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1091 hc->txc_dtr_off[0] = AR_TXC_DTR0;
1092 hc->txc_dtr_off[1] = AR_TXC_DTR2;
1093 if(hc->bustype == AR_BUS_PCI) {
1094 hc->txc_dtr_off[0] *= 4;
1095 hc->txc_dtr_off[1] *= 4;
1099 * reset the card and wait at least 1uS.
1101 if(hc->bustype == AR_BUS_PCI)
1102 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET &
1105 outb(hc->iobase + AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET &
1108 if(hc->bustype == AR_BUS_PCI)
1109 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1111 outb(hc->iobase + AR_TXC_DTR0, hc->txc_dtr[0]);
1113 if(hc->bustype == AR_BUS_ISA) {
1115 * Configure the card.
1118 mar = kvtop(hc->mem_start) >> 16;
1119 isr = irqtable[hc->isa_irq] << 1;
1121 printf("ar%d: Warning illegal interrupt %d\n",
1122 hc->cunit, hc->isa_irq);
1123 isr = isr | ((kvtop(hc->mem_start) & 0xc000) >> 10);
1125 hc->sca[0] = (sca_regs *)hc->mem_start;
1126 hc->sca[1] = (sca_regs *)hc->mem_start;
1128 outb(hc->iobase + AR_MEM_SEL, mar);
1129 outb(hc->iobase + AR_INT_SEL, isr | AR_INTS_CEN);
1132 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM)
1133 for(x = 0; x < hc->numports; x++)
1134 hc->interface[x] = ar_read_pim_iface(hc, x);
1137 * Set the TX clock direction and enable TX.
1139 for(x=0;x<hc->numports;x++) {
1140 switch(hc->interface[x]) {
1142 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1143 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1144 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1145 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1;
1147 case AR_IFACE_EIA_530:
1148 case AR_IFACE_COMBO:
1150 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1151 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1156 if(hc->bustype == AR_BUS_PCI)
1157 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1159 outb(hc->iobase + AR_TXC_DTR0, hc->txc_dtr[0]);
1160 if(hc->numports > NCHAN) {
1161 if(hc->bustype == AR_BUS_PCI)
1162 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1];
1164 outb(hc->iobase + AR_TXC_DTR2, hc->txc_dtr[1]);
1167 chanmem = hc->memsize / hc->numports;
1170 for(x=0;x<hc->numports;x++, sc++) {
1173 sc->sca = hc->sca[x / NCHAN];
1175 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1176 sc->block[blk].txdesc = next;
1177 bufmem = (16 * 1024) / AR_TX_BLOCKS;
1178 descneeded = bufmem / AR_BUF_SIZ;
1179 sc->block[blk].txstart = sc->block[blk].txdesc +
1180 ((((descneeded * sizeof(sca_descriptor)) /
1181 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1182 sc->block[blk].txend = next + bufmem;
1183 sc->block[blk].txmax =
1184 (sc->block[blk].txend - sc->block[blk].txstart)
1188 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, "
1189 "txend %x, txmax %d\n",
1192 sc->block[blk].txdesc,
1193 sc->block[blk].txstart,
1194 sc->block[blk].txend,
1195 sc->block[blk].txmax));
1199 bufmem = chanmem - (bufmem * AR_TX_BLOCKS);
1200 descneeded = bufmem / AR_BUF_SIZ;
1201 sc->rxstart = sc->rxdesc +
1202 ((((descneeded * sizeof(sca_descriptor)) /
1203 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1204 sc->rxend = next + bufmem;
1205 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ;
1207 TRC(printf("ar%d: rxdesc %x, rxstart %x, "
1208 "rxend %x, rxmax %d\n",
1209 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax));
1212 if(hc->bustype == AR_BUS_PCI)
1213 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1218 * The things done here are channel independent.
1220 * Configure the sca waitstates.
1221 * Configure the global interrupt registers.
1222 * Enable master dma enable.
1225 ar_init_sca(struct ar_hardc *hc, int scano)
1229 sca = hc->sca[scano];
1230 if(hc->bustype == AR_BUS_ISA)
1231 ARC_SET_SCA(hc->iobase, scano);
1234 * Do the wait registers.
1235 * Set everything to 0 wait states.
1244 * Configure the interrupt registers.
1245 * Most are cleared until the interface is configured.
1247 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */
1248 sca->ier1 = 0x00; /* DMAC interrupts */
1249 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */
1250 sca->itcr = 0x00; /* Use ivr and no intr ack */
1251 sca->ivr = 0x40; /* Fill in the interrupt vector. */
1255 * Configure the timers.
1261 * Set the DMA channel priority to rotate between
1262 * all four channels.
1264 * Enable all dma channels.
1266 if(hc->bustype == AR_BUS_PCI) {
1270 * Stupid problem with the PCI interface chip that break
1275 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2;
1276 t[AR_PCI_SCA_DMER] = SCA_DMER_EN;
1278 sca->pcr = SCA_PCR_PR2;
1279 sca->dmer = SCA_DMER_EN;
1285 * Configure the msci
1287 * NOTE: The serial port configuration is hardcoded at the moment.
1290 ar_init_msci(struct ar_softc *sc)
1294 msci = &sc->sca->msci[sc->scachan];
1296 if(sc->hc->bustype == AR_BUS_ISA)
1297 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1299 msci->cmd = SCA_CMD_RESET;
1301 msci->md0 = SCA_MD0_CRC_1 |
1303 SCA_MD0_CRC_ENABLE |
1305 msci->md1 = SCA_MD1_NOADDRCHK;
1306 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ;
1309 * Acording to the manual I should give a reset after changing the
1312 msci->cmd = SCA_CMD_RXRESET;
1313 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS;
1316 * For now all interfaces are programmed to use the RX clock for
1319 switch(sc->hc->interface[sc->subunit]) {
1321 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1322 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1;
1325 case AR_IFACE_EIA_530:
1326 case AR_IFACE_COMBO:
1327 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1328 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1;
1331 msci->tmc = 153; /* This give 64k for loopback */
1334 * Disable all interrupts for now. I think if you are using
1335 * the dmac you don't use these interrupts.
1338 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
1345 msci->idl = 0x7E; /* XXX This is what cisco does. */
1348 * This is what the ARNET diags use.
1356 * Configure the rx dma controller.
1359 ar_init_rx_dmac(struct ar_softc *sc)
1362 sca_descriptor *rxd;
1368 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1370 if(sc->hc->bustype == AR_BUS_ISA)
1371 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
1373 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk));
1374 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk);
1376 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) {
1377 rxda = (u_int)&rxd[1] - rxda_d;
1378 rxd->cp = (u_short)(rxda & 0xfffful);
1382 TRC(printf("Descrp %p, data pt %x, data %x, ",
1385 rxd->bp = (u_short)(rxbuf & 0xfffful);
1386 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff);
1388 rxd->stat = 0xff; /* The sca write here when it is finished. */
1391 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp));
1394 rxd->cp = (u_short)(sc->rxdesc & 0xfffful);
1398 if(sc->hc->bustype == AR_BUS_ISA)
1399 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1401 dmac->dsr = 0; /* Disable DMA transfer */
1402 dmac->dcr = SCA_DCR_ABRT;
1404 /* XXX maybe also SCA_DMR_CNTE */
1405 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1406 dmac->bfl = AR_BUF_SIZ;
1408 dmac->cda = (u_short)(sc->rxdesc & 0xffff);
1409 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff);
1411 rxd = (sca_descriptor *)sc->rxstart;
1412 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff);
1416 dmac->dsr = SCA_DSR_DE;
1420 * Configure the TX DMA descriptors.
1421 * Initialize the needed values and chain the descriptors.
1424 ar_init_tx_dmac(struct ar_softc *sc)
1427 struct buf_block *blkp;
1429 sca_descriptor *txd;
1434 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
1436 if(sc->hc->bustype == AR_BUS_ISA)
1437 ARC_SET_MEM(sc->hc->iobase, sc->block[0].txdesc);
1439 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1440 blkp = &sc->block[blk];
1441 txd = (sca_descriptor *)(sc->hc->mem_start +
1442 (blkp->txdesc&sc->hc->winmsk));
1443 txda_d = (u_int)sc->hc->mem_start -
1444 (blkp->txdesc & ~sc->hc->winmsk);
1446 txbuf=blkp->txstart;
1447 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) {
1448 txda = (u_int)&txd[1] - txda_d;
1449 txd->cp = (u_short)(txda & 0xfffful);
1451 txd->bp = (u_short)(txbuf & 0xfffful);
1452 txd->bpb = (u_char)((txbuf >> 16) & 0xff);
1453 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n",
1454 sc->unit, txbuf, txd->bpb, txd->bp));
1459 txd->cp = (u_short)(blkp->txdesc & 0xfffful);
1461 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start;
1462 TRC(printf("TX Descriptors start %x, end %x.\n",
1467 if(sc->hc->bustype == AR_BUS_ISA)
1468 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1470 dmac->dsr = 0; /* Disable DMA */
1471 dmac->dcr = SCA_DCR_ABRT;
1472 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1473 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF;
1475 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff);
1480 * Look through the descriptors to see if there is a complete packet
1481 * available. Stop if we get to where the sca is busy.
1483 * Return the length and status of the packet.
1484 * Return nonzero if there is a packet available.
1487 * It seems that we get the interrupt a bit early. The updateing of
1488 * descriptor values is not always completed when this is called.
1491 ar_packet_avail(struct ar_softc *sc,
1496 sca_descriptor *rxdesc;
1497 sca_descriptor *endp;
1498 sca_descriptor *cda;
1500 if(sc->hc->bustype == AR_BUS_ISA)
1501 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1502 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1503 cda = (sca_descriptor *)(sc->hc->mem_start +
1504 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1506 if(sc->hc->bustype == AR_BUS_ISA)
1507 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
1508 rxdesc = (sca_descriptor *)
1509 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1511 rxdesc = &rxdesc[sc->rxhind];
1512 endp = &endp[sc->rxmax];
1516 while(rxdesc != cda) {
1517 *len += rxdesc->len;
1519 if(rxdesc->stat & SCA_DESC_EOM) {
1520 *rxstat = rxdesc->stat;
1521 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n",
1522 sc->unit, *len, *rxstat));
1528 rxdesc = (sca_descriptor *)
1529 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1539 * Copy a packet from the on card memory into a provided mbuf.
1540 * Take into account that buffers wrap and that a packet may
1541 * be larger than a buffer.
1544 ar_copy_rxbuf(struct mbuf *m,
1545 struct ar_softc *sc,
1548 sca_descriptor *rxdesc;
1554 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ);
1555 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ);
1557 rxdesc = (sca_descriptor *)
1558 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1559 rxdesc = &rxdesc[sc->rxhind];
1562 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ;
1563 if(sc->hc->bustype == AR_BUS_ISA)
1564 ARC_SET_MEM(sc->hc->iobase, rxdata);
1565 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk),
1566 mtod(m, caddr_t) + off,
1572 if(sc->hc->bustype == AR_BUS_ISA)
1573 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
1575 rxdesc->stat = 0xff;
1577 rxdata += AR_BUF_SIZ;
1579 if(rxdata == rxmax) {
1580 rxdata = sc->rxstart;
1581 rxdesc = (sca_descriptor *)
1582 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1588 * If single is set, just eat a packet. Otherwise eat everything up to
1589 * where cda points. Update pointers to point to the next packet.
1592 ar_eat_packet(struct ar_softc *sc, int single)
1595 sca_descriptor *rxdesc;
1596 sca_descriptor *endp;
1597 sca_descriptor *cda;
1601 if(sc->hc->bustype == AR_BUS_ISA)
1602 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1603 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1604 cda = (sca_descriptor *)(sc->hc->mem_start +
1605 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1608 * Loop until desc->stat == (0xff || EOM)
1609 * Clear the status and length in the descriptor.
1610 * Increment the descriptor.
1612 if(sc->hc->bustype == AR_BUS_ISA)
1613 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
1614 rxdesc = (sca_descriptor *)
1615 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1617 rxdesc = &rxdesc[sc->rxhind];
1618 endp = &endp[sc->rxmax];
1620 while(rxdesc != cda) {
1622 if(loopcnt > sc->rxmax) {
1623 printf("ar%d: eat pkt %d loop, cda %p, "
1624 "rxdesc %p, stat %x.\n",
1633 stat = rxdesc->stat;
1636 rxdesc->stat = 0xff;
1640 if(rxdesc == endp) {
1641 rxdesc = (sca_descriptor *)
1642 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1646 if(single && (stat == SCA_DESC_EOM))
1651 * Update the eda to the previous descriptor.
1653 if(sc->hc->bustype == AR_BUS_ISA)
1654 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1656 rxdesc = (sca_descriptor *)sc->rxdesc;
1657 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1659 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1660 (u_short)((u_int)rxdesc & 0xffff);
1665 * While there is packets available in the rx buffer, read them out
1666 * into mbufs and ship them off.
1669 ar_get_packets(struct ar_softc *sc)
1671 sca_descriptor *rxdesc;
1672 struct mbuf *m = NULL;
1677 while(ar_packet_avail(sc, &len, &rxstat)) {
1678 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat));
1679 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1680 MGETHDR(m, M_DONTWAIT, MT_DATA);
1682 /* eat packet if get mbuf fail!! */
1683 ar_eat_packet(sc, 1);
1687 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if;
1688 #else /* NETGRAPH */
1689 m->m_pkthdr.rcvif = NULL;
1692 #endif /* NETGRAPH */
1693 m->m_pkthdr.len = m->m_len = len;
1695 MCLGET(m, M_DONTWAIT);
1696 if((m->m_flags & M_EXT) == 0) {
1698 ar_eat_packet(sc, 1);
1702 ar_copy_rxbuf(m, sc, len);
1704 if(sc->ifsppp.pp_if.if_bpf)
1705 bpf_mtap(&sc->ifsppp.pp_if, m);
1706 sppp_input(&sc->ifsppp.pp_if, m);
1707 sc->ifsppp.pp_if.if_ipackets++;
1708 #else /* NETGRAPH */
1709 ng_queue_data(sc->hook, m, NULL);
1711 #endif /* NETGRAPH */
1714 * Update the eda to the previous descriptor.
1716 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ;
1717 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
1719 if(sc->hc->bustype == AR_BUS_ISA)
1720 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1722 rxdesc = (sca_descriptor *)sc->rxdesc;
1724 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1726 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1727 (u_short)((u_int)rxdesc & 0xffff);
1731 while((rxstat == 0xff) && --tries)
1732 ar_packet_avail(sc, &len, &rxstat);
1735 * It look like we get an interrupt early
1736 * sometimes and then the status is not
1739 if(tries && (tries != 5))
1742 ar_eat_packet(sc, 1);
1745 sc->ifsppp.pp_if.if_ierrors++;
1746 #else /* NETGRAPH */
1748 #endif /* NETGRAPH */
1750 if(sc->hc->bustype == AR_BUS_ISA)
1751 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1753 TRCL(printf("ar%d: Receive error chan %d, "
1754 "stat %x, msci st3 %x,"
1755 "rxhind %d, cda %x, eda %x.\n",
1759 sc->sca->msci[sc->scachan].st3,
1762 DMAC_RXCH(sc->scachan)].cda,
1764 DMAC_RXCH(sc->scachan)].eda));
1771 * All DMA interrupts come here.
1773 * Each channel has two interrupts.
1774 * Interrupt A for errors and Interrupt B for normal stuff like end
1775 * of transmit or receive dmas.
1778 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1)
1781 u_char dotxstart = isr1;
1783 struct ar_softc *sc;
1787 sca = hc->sca[scano];
1790 * Shortcut if there is no interrupts for dma channel 0 or 1
1792 if((isr1 & 0x0F) == 0) {
1798 sc = &hc->sc[mch + (NCHAN * scano)];
1804 dmac = &sca->dmac[DMAC_TXCH(mch)];
1806 if(hc->bustype == AR_BUS_ISA)
1807 ARC_SET_SCA(hc->iobase, scano);
1812 /* Counter overflow */
1813 if(dsr & SCA_DSR_COF) {
1814 printf("ar%d: TX DMA Counter overflow, "
1815 "txpacket no %lu.\n",
1818 sc->ifsppp.pp_if.if_opackets);
1819 sc->ifsppp.pp_if.if_oerrors++;
1820 #else /* NETGRAPH */
1823 #endif /* NETGRAPH */
1826 /* Buffer overflow */
1827 if(dsr & SCA_DSR_BOF) {
1828 printf("ar%d: TX DMA Buffer overflow, "
1829 "txpacket no %lu, dsr %02x, "
1830 "cda %04x, eda %04x.\n",
1833 sc->ifsppp.pp_if.if_opackets,
1834 #else /* NETGRAPH */
1836 #endif /* NETGRAPH */
1841 sc->ifsppp.pp_if.if_oerrors++;
1842 #else /* NETGRAPH */
1844 #endif /* NETGRAPH */
1847 /* End of Transfer */
1848 if(dsr & SCA_DSR_EOT) {
1850 * This should be the most common case.
1852 * Clear the IFF_OACTIVE flag.
1854 * Call arstart to start a new transmit if
1855 * there is data to transmit.
1859 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
1860 sc->ifsppp.pp_if.if_timer = 0;
1861 #else /* NETGRAPH */
1862 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */
1863 sc->out_dog = 0; /* XXX */
1864 #endif /* NETGRAPH */
1866 if(sc->txb_inuse && --sc->txb_inuse)
1875 dmac = &sca->dmac[DMAC_RXCH(mch)];
1877 if(hc->bustype == AR_BUS_ISA)
1878 ARC_SET_SCA(hc->iobase, scano);
1883 TRC(printf("AR: RX DSR %x\n", dsr));
1886 if(dsr & SCA_DSR_EOM) {
1887 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;)
1888 TRC(int ind = sc->rxhind;)
1893 if(tt == sc->ifsppp.pp_if.if_ipackets) {
1894 #else /* NETGRAPH */
1895 if(tt == sc->ipackets) {
1896 #endif /* NETGRAPH */
1897 sca_descriptor *rxdesc;
1900 if(hc->bustype == AR_BUS_ISA)
1901 ARC_SET_SCA(hc->iobase, scano);
1902 printf("AR: RXINTR isr1 %x, dsr %x, "
1903 "no data %d pkts, orxhind %d.\n",
1908 printf("AR: rxdesc %x, rxstart %x, "
1909 "rxend %x, rxhind %d, "
1916 printf("AR: cda %x, eda %x.\n",
1920 if(sc->hc->bustype == AR_BUS_ISA)
1921 ARC_SET_MEM(sc->hc->iobase,
1923 rxdesc = (sca_descriptor *)
1924 (sc->hc->mem_start +
1925 (sc->rxdesc & sc->hc->winmsk));
1926 rxdesc = &rxdesc[sc->rxhind];
1927 for(i=0;i<3;i++,rxdesc++)
1928 printf("AR: rxdesc->stat %x, "
1935 /* Counter overflow */
1936 if(dsr & SCA_DSR_COF) {
1937 printf("ar%d: RX DMA Counter overflow, "
1941 sc->ifsppp.pp_if.if_ipackets);
1942 sc->ifsppp.pp_if.if_ierrors++;
1943 #else /* NETGRAPH */
1946 #endif /* NETGRAPH */
1949 /* Buffer overflow */
1950 if(dsr & SCA_DSR_BOF) {
1951 if(hc->bustype == AR_BUS_ISA)
1952 ARC_SET_SCA(hc->iobase, scano);
1953 printf("ar%d: RX DMA Buffer overflow, "
1954 "rxpkts %lu, rxind %d, "
1955 "cda %x, eda %x, dsr %x.\n",
1958 sc->ifsppp.pp_if.if_ipackets,
1959 #else /* NETGRAPH */
1961 #endif /* NETGRAPH */
1967 * Make sure we eat as many as possible.
1968 * Then get the system running again.
1970 ar_eat_packet(sc, 0);
1972 sc->ifsppp.pp_if.if_ierrors++;
1973 #else /* NETGRAPH */
1975 #endif /* NETGRAPH */
1976 if(hc->bustype == AR_BUS_ISA)
1977 ARC_SET_SCA(hc->iobase, scano);
1978 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ;
1979 dmac->dsr = SCA_DSR_DE;
1981 TRC(printf("ar%d: RX DMA Buffer overflow, "
1982 "rxpkts %lu, rxind %d, "
1983 "cda %x, eda %x, dsr %x. After\n",
1985 sc->ifsppp.pp_if.if_ipackets,
1992 /* End of Transfer */
1993 if(dsr & SCA_DSR_EOT) {
1995 * If this happen, it means that we are
1996 * receiving faster than what the processor
1999 * XXX We should enable the dma again.
2001 printf("ar%d: RX End of transfer, rxpkts %lu.\n",
2004 sc->ifsppp.pp_if.if_ipackets);
2005 sc->ifsppp.pp_if.if_ierrors++;
2006 #else /* NETGRAPH */
2009 #endif /* NETGRAPH */
2016 }while((mch<NCHAN) && isr1);
2019 * Now that we have done all the urgent things, see if we
2020 * can fill the transmit buffers.
2022 for(mch = 0; mch < NCHAN; mch++) {
2023 if(dotxstart & 0x0C) {
2024 sc = &hc->sc[mch + (NCHAN * scano)];
2026 arstart(&sc->ifsppp.pp_if);
2027 #else /* NETGRAPH */
2029 #endif /* NETGRAPH */
2036 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0)
2038 printf("arc%d: ARINTR: MSCI\n", hc->cunit);
2042 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2)
2044 printf("arc%d: ARINTR: TIMER\n", hc->cunit);
2049 /*****************************************
2050 * Device timeout/watchdog routine.
2051 * called once per second.
2052 * checks to see that if activity was expected, that it hapenned.
2053 * At present we only look to see if expected output was completed.
2056 ngar_watchdog_frame(void * arg)
2058 struct ar_softc * sc = arg;
2062 if(sc->running == 0)
2063 return; /* if we are not running let timeouts die */
2065 * calculate the apparent throughputs
2069 speed = sc->inbytes - sc->lastinbytes;
2070 sc->lastinbytes = sc->inbytes;
2071 if ( sc->inrate < speed )
2073 speed = sc->outbytes - sc->lastoutbytes;
2074 sc->lastoutbytes = sc->outbytes;
2075 if ( sc->outrate < speed )
2076 sc->outrate = speed;
2080 if ((sc->inlast > QUITE_A_WHILE)
2081 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2082 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit);
2086 sc->inlast = sc->out_deficit = 0;
2088 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2089 if (sc->out_dog == 0) {
2090 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n",
2099 sc->inlast = sc->out_deficit = 0;
2104 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
2107 /***********************************************************************
2108 * This section contains the methods for the Netgraph interface
2109 ***********************************************************************/
2111 * It is not possible or allowable to create a node of this type.
2112 * If the hardware exists, it will already have created it.
2115 ngar_constructor(node_p *nodep)
2121 * give our ok for a hook to be added...
2122 * If we are not running this should kick the device into life.
2123 * The hook's private info points to our stash of info about that
2127 ngar_newhook(node_p node, hook_p hook, const char *name)
2129 struct ar_softc * sc = node->private;
2132 * check if it's our friend the debug hook
2134 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) {
2135 hook->private = NULL; /* paranoid */
2136 sc->debug_hook = hook;
2141 * Check for raw mode hook.
2143 if (strcmp(name, NG_AR_HOOK_RAW) != 0) {
2154 * incoming messages.
2155 * Just respond to the generic TEXT_STATUS message
2158 ngar_rcvmsg(node_p node,
2159 struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2161 struct ar_softc * sc;
2165 switch (msg->header.typecookie) {
2169 case NGM_GENERIC_COOKIE:
2170 switch(msg->header.cmd) {
2171 case NGM_TEXT_STATUS: {
2174 int resplen = sizeof(struct ng_mesg) + 512;
2175 MALLOC(*resp, struct ng_mesg *, resplen,
2176 M_NETGRAPH, M_NOWAIT | M_ZERO);
2177 if (*resp == NULL) {
2181 arg = (*resp)->data;
2184 * Put in the throughput information.
2186 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2187 "highest rate seen: %ld B/S in, %ld B/S out\n",
2188 sc->inbytes, sc->outbytes,
2189 sc->inrate, sc->outrate);
2190 pos += sprintf(arg + pos,
2191 "%ld output errors\n",
2193 pos += sprintf(arg + pos,
2194 "ierrors = %ld, %ld, %ld, %ld\n",
2200 (*resp)->header.version = NG_VERSION;
2201 (*resp)->header.arglen = strlen(arg) + 1;
2202 (*resp)->header.token = msg->header.token;
2203 (*resp)->header.typecookie = NG_AR_COOKIE;
2204 (*resp)->header.cmd = msg->header.cmd;
2205 strncpy((*resp)->header.cmdstr, "status",
2218 free(msg, M_NETGRAPH);
2223 * get data from another node and transmit it to the correct channel
2226 ngar_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2230 struct ar_softc * sc = hook->node->private;
2231 struct ifqueue *xmitq_p;
2234 * data doesn't come in from just anywhere (e.g control hook)
2236 if ( hook->private == NULL) {
2242 * Now queue the data for when it can be sent
2244 if (meta && meta->priority > 0) {
2245 xmitq_p = (&sc->xmitq_hipri);
2247 xmitq_p = (&sc->xmitq);
2250 if (IF_QFULL(xmitq_p)) {
2256 IF_ENQUEUE(xmitq_p, m);
2263 * It was an error case.
2264 * check if we need to free the mbuf, and then return the error
2266 NG_FREE_DATA(m, meta);
2271 * do local shutdown processing..
2272 * this node will refuse to go away, unless the hardware says to..
2273 * don't unref the node, or remove our name. just clear our links up.
2276 ngar_rmnode(node_p node)
2278 struct ar_softc * sc = node->private;
2282 node->flags &= ~NG_INVALID; /* bounce back to life */
2286 /* already linked */
2288 ngar_connect(hook_p hook)
2290 /* be really amiable and just say "YUP that's OK by me! " */
2295 * notify on hook disconnection (destruction)
2297 * Invalidate the private data associated with this dlci.
2298 * For this type, removal of the last link resets tries to destroy the node.
2299 * As the device still exists, the shutdown method will not actually
2300 * destroy the node, but reset the device and leave it 'fresh' :)
2302 * The node removal code will remove all references except that owned by the
2306 ngar_disconnect(hook_p hook)
2308 struct ar_softc * sc = hook->node->private;
2311 * If it's the data hook, then free resources etc.
2313 if (hook->private) {
2316 if (sc->datahooks == 0)
2320 sc->debug_hook = NULL;
2326 * called during bootup
2327 * or LKM loading to put this type into the list of known modules
2330 ngar_init(void *ignored)
2332 if (ng_newtype(&typestruct))
2333 printf("ngar install failed\n");
2336 #endif /* NETGRAPH */
2339 ********************************* END ************************************