2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/pci/if_pcn.c,v 1.5.2.10 2003/03/05 18:42:33 njl Exp $
34 * $DragonFly: src/sys/dev/netif/pcn/if_pcn.c,v 1.25 2005/11/22 00:24:33 dillon Exp $
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available
39 * from http://www.amd.com.
41 * Written by Bill Paul <wpaul@osd.bsdi.com>
45 * The AMD PCnet/PCI controllers are more advanced and functional
46 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
47 * backwards compatibility with the LANCE and thus can be made
48 * to work with older LANCE drivers. This is in fact how the
49 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
50 * is that the PCnet/PCI devices offer several performance enhancements
51 * which can't be exploited in LANCE compatibility mode. Chief among
52 * these enhancements is the ability to perform PCI DMA operations
53 * using 32-bit addressing (which eliminates the need for ISA
54 * bounce-buffering), and special receive buffer alignment (which
55 * allows the receive handler to pass packets to the upper protocol
56 * layers without copying on both the x86 and alpha platforms).
59 #include <sys/param.h>
60 #include <sys/systm.h>
61 #include <sys/sockio.h>
63 #include <sys/malloc.h>
64 #include <sys/kernel.h>
65 #include <sys/socket.h>
66 #include <sys/thread2.h>
69 #include <net/ifq_var.h>
70 #include <net/if_arp.h>
71 #include <net/ethernet.h>
72 #include <net/if_dl.h>
73 #include <net/if_media.h>
77 #include <vm/vm.h> /* for vtophys */
78 #include <vm/pmap.h> /* for vtophys */
79 #include <machine/clock.h> /* for DELAY */
80 #include <machine/bus_pio.h>
81 #include <machine/bus_memio.h>
82 #include <machine/bus.h>
83 #include <machine/resource.h>
87 #include "../mii_layer/mii.h"
88 #include "../mii_layer/miivar.h"
90 #include <bus/pci/pcireg.h>
91 #include <bus/pci/pcivar.h>
93 #define PCN_USEIOSPACE
95 #include "if_pcnreg.h"
97 /* "controller miibus0" required. See GENERIC if you get errors here. */
98 #include "miibus_if.h"
101 * Various supported device vendors/types and their names.
103 static struct pcn_type pcn_devs[] = {
104 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
105 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
109 static u_int32_t pcn_csr_read (struct pcn_softc *, int);
110 static u_int16_t pcn_csr_read16 (struct pcn_softc *, int);
111 static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int);
112 static void pcn_csr_write (struct pcn_softc *, int, int);
113 static u_int32_t pcn_bcr_read (struct pcn_softc *, int);
114 static void pcn_bcr_write (struct pcn_softc *, int, int);
116 static int pcn_probe (device_t);
117 static int pcn_attach (device_t);
118 static int pcn_detach (device_t);
120 static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *);
121 static int pcn_encap (struct pcn_softc *,
122 struct mbuf *, u_int32_t *);
123 static void pcn_rxeof (struct pcn_softc *);
124 static void pcn_txeof (struct pcn_softc *);
125 static void pcn_intr (void *);
126 static void pcn_tick (void *);
127 static void pcn_start (struct ifnet *);
128 static int pcn_ioctl (struct ifnet *, u_long, caddr_t,
130 static void pcn_init (void *);
131 static void pcn_stop (struct pcn_softc *);
132 static void pcn_watchdog (struct ifnet *);
133 static void pcn_shutdown (device_t);
134 static int pcn_ifmedia_upd (struct ifnet *);
135 static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *);
137 static int pcn_miibus_readreg (device_t, int, int);
138 static int pcn_miibus_writereg (device_t, int, int, int);
139 static void pcn_miibus_statchg (device_t);
141 static void pcn_setfilt (struct ifnet *);
142 static void pcn_setmulti (struct pcn_softc *);
143 static u_int32_t pcn_crc (caddr_t);
144 static void pcn_reset (struct pcn_softc *);
145 static int pcn_list_rx_init (struct pcn_softc *);
146 static int pcn_list_tx_init (struct pcn_softc *);
148 #ifdef PCN_USEIOSPACE
149 #define PCN_RES SYS_RES_IOPORT
150 #define PCN_RID PCN_PCI_LOIO
152 #define PCN_RES SYS_RES_MEMORY
153 #define PCN_RID PCN_PCI_LOMEM
156 static device_method_t pcn_methods[] = {
157 /* Device interface */
158 DEVMETHOD(device_probe, pcn_probe),
159 DEVMETHOD(device_attach, pcn_attach),
160 DEVMETHOD(device_detach, pcn_detach),
161 DEVMETHOD(device_shutdown, pcn_shutdown),
164 DEVMETHOD(bus_print_child, bus_generic_print_child),
165 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
168 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
169 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
170 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
175 static driver_t pcn_driver = {
178 sizeof(struct pcn_softc)
181 static devclass_t pcn_devclass;
183 DECLARE_DUMMY_MODULE(if_pcn);
184 DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0);
185 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
187 #define PCN_CSR_SETBIT(sc, reg, x) \
188 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
190 #define PCN_CSR_CLRBIT(sc, reg, x) \
191 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
193 #define PCN_BCR_SETBIT(sc, reg, x) \
194 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
196 #define PCN_BCR_CLRBIT(sc, reg, x) \
197 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
199 static u_int32_t pcn_csr_read(sc, reg)
200 struct pcn_softc *sc;
203 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
204 return(CSR_READ_4(sc, PCN_IO32_RDP));
207 static u_int16_t pcn_csr_read16(sc, reg)
208 struct pcn_softc *sc;
211 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
212 return(CSR_READ_2(sc, PCN_IO16_RDP));
215 static void pcn_csr_write(sc, reg, val)
216 struct pcn_softc *sc;
219 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
220 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
224 static u_int32_t pcn_bcr_read(sc, reg)
225 struct pcn_softc *sc;
228 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
229 return(CSR_READ_4(sc, PCN_IO32_BDP));
232 static u_int16_t pcn_bcr_read16(sc, reg)
233 struct pcn_softc *sc;
236 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
237 return(CSR_READ_2(sc, PCN_IO16_BDP));
240 static void pcn_bcr_write(sc, reg, val)
241 struct pcn_softc *sc;
244 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
245 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
249 static int pcn_miibus_readreg(dev, phy, reg)
253 struct pcn_softc *sc;
256 sc = device_get_softc(dev);
258 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
261 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
262 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
266 sc->pcn_phyaddr = phy;
271 static int pcn_miibus_writereg(dev, phy, reg, data)
275 struct pcn_softc *sc;
277 sc = device_get_softc(dev);
279 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
280 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
285 static void pcn_miibus_statchg(dev)
288 struct pcn_softc *sc;
289 struct mii_data *mii;
291 sc = device_get_softc(dev);
292 mii = device_get_softc(sc->pcn_miibus);
294 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
295 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
297 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
303 #define DC_POLY 0xEDB88320
305 static u_int32_t pcn_crc(addr)
308 u_int32_t idx, bit, data, crc;
310 /* Compute CRC for the address value. */
311 crc = 0xFFFFFFFF; /* initial value */
313 for (idx = 0; idx < 6; idx++) {
314 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
315 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
318 return ((crc >> 26) & 0x3F);
321 static void pcn_setmulti(sc)
322 struct pcn_softc *sc;
325 struct ifmultiaddr *ifma;
327 u_int16_t hashes[4] = { 0, 0, 0, 0 };
329 ifp = &sc->arpcom.ac_if;
331 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
333 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
334 for (i = 0; i < 4; i++)
335 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
336 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
340 /* first, zot all the existing hash bits */
341 for (i = 0; i < 4; i++)
342 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
344 /* now program new ones */
345 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
346 if (ifma->ifma_addr->sa_family != AF_LINK)
348 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
349 hashes[h >> 4] |= 1 << (h & 0xF);
352 for (i = 0; i < 4; i++)
353 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
355 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
360 static void pcn_reset(sc)
361 struct pcn_softc *sc;
364 * Issue a reset by reading from the RESET register.
365 * Note that we don't know if the chip is operating in
366 * 16-bit or 32-bit mode at this point, so we attempt
367 * to reset the chip both ways. If one fails, the other
370 CSR_READ_2(sc, PCN_IO16_RESET);
371 CSR_READ_4(sc, PCN_IO32_RESET);
373 /* Wait a little while for the chip to get its brains in order. */
376 /* Select 32-bit (DWIO) mode */
377 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
379 /* Select software style 3. */
380 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
386 * Probe for an AMD chip. Check the PCI vendor and device
387 * IDs against our list and return a device name if we find a match.
389 static int pcn_probe(dev)
393 struct pcn_softc *sc;
398 sc = device_get_softc(dev);
400 while(t->pcn_name != NULL) {
401 if ((pci_get_vendor(dev) == t->pcn_vid) &&
402 (pci_get_device(dev) == t->pcn_did)) {
404 * Temporarily map the I/O space
405 * so we can read the chip ID register.
408 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES,
410 if (sc->pcn_res == NULL) {
412 "couldn't map ports/memory\n");
415 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
416 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
418 * Note: we can *NOT* put the chip into
419 * 32-bit mode yet. The lnc driver will only
420 * work in 16-bit mode, and once the chip
421 * goes into 32-bit mode, the only way to
422 * get it out again is with a hardware reset.
423 * So if pcn_probe() is called before the
424 * lnc driver's probe routine, the chip will
425 * be locked into 32-bit operation and the lnc
426 * driver will be unable to attach to it.
427 * Note II: if the chip happens to already
428 * be in 32-bit mode, we still need to check
429 * the chip ID, but first we have to detect
430 * 32-bit mode using only 16-bit operations.
431 * The safest way to do this is to read the
432 * PCI subsystem ID from BCR23/24 and compare
433 * that with the value read from PCI config
436 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
438 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
440 * Note III: the test for 0x10001000 is a hack to
441 * pacify VMware, who's pseudo-PCnet interface is
442 * broken. Reading the subsystem register from PCI
443 * config space yeilds 0x00000000 while reading the
444 * same value from I/O space yeilds 0x10001000. It's
445 * not supposed to be that way.
447 if (chip_id == pci_read_config(dev,
448 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
449 /* We're in 16-bit mode. */
450 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
452 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
454 /* We're in 32-bit mode. */
455 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
457 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
459 bus_release_resource(dev, PCN_RES,
460 PCN_RID, sc->pcn_res);
462 sc->pcn_type = chip_id & PART_MASK;
463 switch(sc->pcn_type) {
475 device_set_desc(dev, t->pcn_name);
485 * Attach the interface. Allocate softc structures, do ifmedia
486 * setup and ethernet/BPF attach.
488 static int pcn_attach(dev)
491 uint8_t eaddr[ETHER_ADDR_LEN];
493 struct pcn_softc *sc;
495 int unit, error = 0, rid;
497 sc = device_get_softc(dev);
498 unit = device_get_unit(dev);
501 * Handle power management nonsense.
504 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF;
505 if (command == 0x01) {
507 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4);
508 if (command & PCN_PSTATE_MASK) {
509 u_int32_t iobase, membase, irq;
511 /* Save important PCI config data. */
512 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4);
513 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4);
514 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4);
516 /* Reset the power state. */
517 printf("pcn%d: chip is in D%d power mode "
518 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK);
519 command &= 0xFFFFFFFC;
520 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4);
522 /* Restore PCI config data. */
523 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4);
524 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4);
525 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4);
530 * Map control/status registers.
532 command = pci_read_config(dev, PCIR_COMMAND, 4);
533 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
534 pci_write_config(dev, PCIR_COMMAND, command, 4);
535 command = pci_read_config(dev, PCIR_COMMAND, 4);
537 #ifdef PCN_USEIOSPACE
538 if (!(command & PCIM_CMD_PORTEN)) {
539 printf("pcn%d: failed to enable I/O ports!\n", unit);
544 if (!(command & PCIM_CMD_MEMEN)) {
545 printf("pcn%d: failed to enable memory mapping!\n", unit);
552 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
554 if (sc->pcn_res == NULL) {
555 printf("pcn%d: couldn't map ports/memory\n", unit);
560 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
561 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
563 /* Allocate interrupt */
565 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
566 RF_SHAREABLE | RF_ACTIVE);
568 if (sc->pcn_irq == NULL) {
569 printf("pcn%d: couldn't map interrupt\n", unit);
574 /* Reset the adapter. */
578 * Get station address from the EEPROM.
580 *(uint32_t *)eaddr = CSR_READ_4(sc, PCN_IO32_APROM00);
581 *(uint16_t *)(eaddr + 4) = CSR_READ_2(sc, PCN_IO32_APROM01);
584 callout_init(&sc->pcn_stat_timer);
586 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
587 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
589 if (sc->pcn_ldata == NULL) {
590 printf("pcn%d: no memory for list buffers!\n", unit);
594 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
596 ifp = &sc->arpcom.ac_if;
598 if_initname(ifp, "pcn", unit);
599 ifp->if_mtu = ETHERMTU;
600 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
601 ifp->if_ioctl = pcn_ioctl;
602 ifp->if_start = pcn_start;
603 ifp->if_watchdog = pcn_watchdog;
604 ifp->if_init = pcn_init;
605 ifp->if_baudrate = 10000000;
606 ifq_set_maxlen(&ifp->if_snd, PCN_TX_LIST_CNT - 1);
607 ifq_set_ready(&ifp->if_snd);
612 if (mii_phy_probe(dev, &sc->pcn_miibus,
613 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
614 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
620 * Call MI attach routine.
622 ether_ifattach(ifp, eaddr);
624 error = bus_setup_intr(dev, sc->pcn_irq, 0,
625 pcn_intr, sc, &sc->pcn_intrhand, NULL);
628 device_printf(dev, "couldn't set up irq\n");
637 static int pcn_detach(dev)
640 struct pcn_softc *sc = device_get_softc(dev);
641 struct ifnet *ifp = &sc->arpcom.ac_if;
645 if (device_is_attached(dev)) {
651 if (sc->pcn_miibus != NULL)
652 device_delete_child(dev, sc->pcn_miibus);
653 bus_generic_detach(dev);
655 if (sc->pcn_intrhand)
656 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
661 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
663 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
666 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
674 * Initialize the transmit descriptors.
676 static int pcn_list_tx_init(sc)
677 struct pcn_softc *sc;
679 struct pcn_list_data *ld;
680 struct pcn_ring_data *cd;
686 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
687 cd->pcn_tx_chain[i] = NULL;
688 ld->pcn_tx_list[i].pcn_tbaddr = 0;
689 ld->pcn_tx_list[i].pcn_txctl = 0;
690 ld->pcn_tx_list[i].pcn_txstat = 0;
693 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
700 * Initialize the RX descriptors and allocate mbufs for them.
702 static int pcn_list_rx_init(sc)
703 struct pcn_softc *sc;
705 struct pcn_list_data *ld;
706 struct pcn_ring_data *cd;
712 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
713 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
723 * Initialize an RX descriptor and attach an MBUF cluster.
725 static int pcn_newbuf(sc, idx, m)
726 struct pcn_softc *sc;
730 struct mbuf *m_new = NULL;
731 struct pcn_rx_desc *c;
733 c = &sc->pcn_ldata->pcn_rx_list[idx];
736 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
740 MCLGET(m_new, MB_DONTWAIT);
741 if (!(m_new->m_flags & M_EXT)) {
745 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
748 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
749 m_new->m_data = m_new->m_ext.ext_buf;
752 m_adj(m_new, ETHER_ALIGN);
754 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
755 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
756 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
757 c->pcn_bufsz |= PCN_RXLEN_MBO;
758 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
764 * A frame has been uploaded: pass the resulting mbuf chain up to
765 * the higher level protocols.
767 static void pcn_rxeof(sc)
768 struct pcn_softc *sc;
772 struct pcn_rx_desc *cur_rx;
775 ifp = &sc->arpcom.ac_if;
776 i = sc->pcn_cdata.pcn_rx_prod;
778 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
779 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
780 m = sc->pcn_cdata.pcn_rx_chain[i];
781 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
784 * If an error occurs, update stats, clear the
785 * status word and leave the mbuf cluster in place:
786 * it should simply get re-used next time this descriptor
787 * comes up in the ring.
789 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
791 pcn_newbuf(sc, i, m);
792 PCN_INC(i, PCN_RX_LIST_CNT);
796 if (pcn_newbuf(sc, i, NULL)) {
797 /* Ran out of mbufs; recycle this one. */
798 pcn_newbuf(sc, i, m);
800 PCN_INC(i, PCN_RX_LIST_CNT);
804 PCN_INC(i, PCN_RX_LIST_CNT);
806 /* No errors; receive the packet. */
808 m->m_len = m->m_pkthdr.len =
809 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
810 m->m_pkthdr.rcvif = ifp;
812 (*ifp->if_input)(ifp, m);
815 sc->pcn_cdata.pcn_rx_prod = i;
821 * A frame was downloaded to the chip. It's safe for us to clean up
825 static void pcn_txeof(sc)
826 struct pcn_softc *sc;
828 struct pcn_tx_desc *cur_tx = NULL;
832 ifp = &sc->arpcom.ac_if;
835 * Go through our tx list and free mbufs for those
836 * frames that have been transmitted.
838 idx = sc->pcn_cdata.pcn_tx_cons;
839 while (idx != sc->pcn_cdata.pcn_tx_prod) {
840 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
842 if (!PCN_OWN_TXDESC(cur_tx))
845 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
846 sc->pcn_cdata.pcn_tx_cnt--;
847 PCN_INC(idx, PCN_TX_LIST_CNT);
851 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
853 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
854 ifp->if_collisions++;
855 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
856 ifp->if_collisions++;
859 ifp->if_collisions +=
860 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
863 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
864 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
865 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
868 sc->pcn_cdata.pcn_tx_cnt--;
869 PCN_INC(idx, PCN_TX_LIST_CNT);
872 if (idx != sc->pcn_cdata.pcn_tx_cons) {
873 /* Some buffers have been freed. */
874 sc->pcn_cdata.pcn_tx_cons = idx;
875 ifp->if_flags &= ~IFF_OACTIVE;
877 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
882 static void pcn_tick(xsc)
885 struct pcn_softc *sc = xsc;
886 struct mii_data *mii;
887 struct ifnet *ifp = &sc->arpcom.ac_if;
891 mii = device_get_softc(sc->pcn_miibus);
894 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
899 if (mii->mii_media_status & IFM_ACTIVE &&
900 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
902 if (!ifq_is_empty(&ifp->if_snd))
906 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc);
911 static void pcn_intr(arg)
914 struct pcn_softc *sc;
919 ifp = &sc->arpcom.ac_if;
921 /* Supress unwanted interrupts */
922 if (!(ifp->if_flags & IFF_UP)) {
927 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
929 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
930 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
932 if (status & PCN_CSR_RINT)
935 if (status & PCN_CSR_TINT)
938 if (status & PCN_CSR_ERR) {
944 if (!ifq_is_empty(&ifp->if_snd))
951 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
952 * pointers to the fragment pointers.
954 static int pcn_encap(sc, m_head, txidx)
955 struct pcn_softc *sc;
959 struct pcn_tx_desc *f = NULL;
961 int frag, cur, cnt = 0;
964 * Start packing the mbufs in this chain into
965 * the fragment pointers. Stop when we run out
966 * of fragments or hit the end of the mbuf chain.
971 for (m = m_head; m != NULL; m = m->m_next) {
973 if ((PCN_TX_LIST_CNT -
974 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
976 f = &sc->pcn_ldata->pcn_tx_list[frag];
977 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
978 f->pcn_txctl |= PCN_TXCTL_MBO;
979 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
981 f->pcn_txctl |= PCN_TXCTL_STP;
983 f->pcn_txctl |= PCN_TXCTL_OWN;
985 PCN_INC(frag, PCN_TX_LIST_CNT);
993 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
994 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
995 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
996 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
997 sc->pcn_cdata.pcn_tx_cnt += cnt;
1004 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1005 * to the mbuf data regions directly in the transmit lists. We also save a
1006 * copy of the pointers since the transmit list fragment pointers are
1007 * physical addresses.
1009 static void pcn_start(ifp)
1012 struct pcn_softc *sc;
1013 struct mbuf *m_head = NULL;
1022 idx = sc->pcn_cdata.pcn_tx_prod;
1024 if (ifp->if_flags & IFF_OACTIVE)
1028 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1029 m_head = ifq_poll(&ifp->if_snd);
1033 if (pcn_encap(sc, m_head, &idx)) {
1034 ifp->if_flags |= IFF_OACTIVE;
1037 ifq_dequeue(&ifp->if_snd, m_head);
1040 BPF_MTAP(ifp, m_head);
1047 sc->pcn_cdata.pcn_tx_prod = idx;
1048 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1051 * Set a timeout in case the chip goes out to lunch.
1056 void pcn_setfilt(ifp)
1059 struct pcn_softc *sc;
1063 /* If we want promiscuous mode, set the allframes bit. */
1064 if (ifp->if_flags & IFF_PROMISC) {
1065 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1067 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1070 /* Set the capture broadcast bit to capture broadcast frames. */
1071 if (ifp->if_flags & IFF_BROADCAST) {
1072 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1074 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1080 static void pcn_init(xsc)
1083 struct pcn_softc *sc = xsc;
1084 struct ifnet *ifp = &sc->arpcom.ac_if;
1085 struct mii_data *mii = NULL;
1090 * Cancel pending I/O and free all RX/TX buffers.
1095 mii = device_get_softc(sc->pcn_miibus);
1097 /* Set MAC address */
1098 pcn_csr_write(sc, PCN_CSR_PAR0,
1099 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1100 pcn_csr_write(sc, PCN_CSR_PAR1,
1101 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1102 pcn_csr_write(sc, PCN_CSR_PAR2,
1103 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1105 /* Init circular RX list. */
1106 if (pcn_list_rx_init(sc) == ENOBUFS) {
1107 printf("pcn%d: initialization failed: no "
1108 "memory for rx buffers\n", sc->pcn_unit);
1115 /* Set up RX filter. */
1119 * Init tx descriptors.
1121 pcn_list_tx_init(sc);
1123 /* Set up the mode register. */
1124 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1127 * Load the multicast filter.
1132 * Load the addresses of the RX and TX lists.
1134 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1135 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1136 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1137 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1138 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1139 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1140 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1141 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1143 /* Set the RX and TX ring sizes. */
1144 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1145 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1147 /* We're not using the initialization block. */
1148 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1150 /* Enable fast suspend mode. */
1151 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1154 * Enable burst read and write. Also set the no underflow
1155 * bit. This will avoid transmit underruns in certain
1156 * conditions while still providing decent performance.
1158 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1159 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1161 /* Enable graceful recovery from underflow. */
1162 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1164 /* Enable auto-padding of short TX frames. */
1165 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1167 /* Disable MII autoneg (we handle this ourselves). */
1168 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1170 if (sc->pcn_type == Am79C978)
1171 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1172 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1174 /* Enable interrupts and start the controller running. */
1175 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1179 ifp->if_flags |= IFF_RUNNING;
1180 ifp->if_flags &= ~IFF_OACTIVE;
1182 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc);
1188 * Set media options.
1190 static int pcn_ifmedia_upd(ifp)
1193 struct pcn_softc *sc;
1194 struct mii_data *mii;
1197 mii = device_get_softc(sc->pcn_miibus);
1200 if (mii->mii_instance) {
1201 struct mii_softc *miisc;
1202 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1203 miisc = LIST_NEXT(miisc, mii_list))
1204 mii_phy_reset(miisc);
1212 * Report current media status.
1214 static void pcn_ifmedia_sts(ifp, ifmr)
1216 struct ifmediareq *ifmr;
1218 struct pcn_softc *sc;
1219 struct mii_data *mii;
1223 mii = device_get_softc(sc->pcn_miibus);
1225 ifmr->ifm_active = mii->mii_media_active;
1226 ifmr->ifm_status = mii->mii_media_status;
1231 static int pcn_ioctl(ifp, command, data, cr)
1237 struct pcn_softc *sc = ifp->if_softc;
1238 struct ifreq *ifr = (struct ifreq *) data;
1239 struct mii_data *mii = NULL;
1246 if (ifp->if_flags & IFF_UP) {
1247 if (ifp->if_flags & IFF_RUNNING &&
1248 ifp->if_flags & IFF_PROMISC &&
1249 !(sc->pcn_if_flags & IFF_PROMISC)) {
1250 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1253 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1255 pcn_csr_write(sc, PCN_CSR_CSR,
1256 PCN_CSR_INTEN|PCN_CSR_START);
1257 } else if (ifp->if_flags & IFF_RUNNING &&
1258 !(ifp->if_flags & IFF_PROMISC) &&
1259 sc->pcn_if_flags & IFF_PROMISC) {
1260 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1263 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1265 pcn_csr_write(sc, PCN_CSR_CSR,
1266 PCN_CSR_INTEN|PCN_CSR_START);
1267 } else if (!(ifp->if_flags & IFF_RUNNING))
1270 if (ifp->if_flags & IFF_RUNNING)
1273 sc->pcn_if_flags = ifp->if_flags;
1283 mii = device_get_softc(sc->pcn_miibus);
1284 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1287 error = ether_ioctl(ifp, command, data);
1296 static void pcn_watchdog(ifp)
1299 struct pcn_softc *sc;
1304 printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
1310 if (!ifq_is_empty(&ifp->if_snd))
1317 * Stop the adapter and free any mbufs allocated to the
1320 static void pcn_stop(sc)
1321 struct pcn_softc *sc;
1326 ifp = &sc->arpcom.ac_if;
1329 callout_stop(&sc->pcn_stat_timer);
1330 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1334 * Free data in the RX lists.
1336 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1337 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1338 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1339 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1342 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1343 sizeof(sc->pcn_ldata->pcn_rx_list));
1346 * Free the TX list buffers.
1348 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1349 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1350 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1351 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1355 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1356 sizeof(sc->pcn_ldata->pcn_tx_list));
1358 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1364 * Stop all chip I/O so that the kernel's probe routines don't
1365 * get confused by errant DMAs when rebooting.
1367 static void pcn_shutdown(dev)
1370 struct pcn_softc *sc;
1372 sc = device_get_softc(dev);