2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
50 #include "opt_msgbuf.h"
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/sysproto.h>
56 #include <sys/signalvar.h>
57 #include <sys/kernel.h>
58 #include <sys/linker.h>
59 #include <sys/malloc.h>
63 #include <sys/reboot.h>
65 #include <sys/msgbuf.h>
66 #include <sys/sysent.h>
67 #include <sys/sysctl.h>
68 #include <sys/vmmeter.h>
70 #include <sys/usched.h>
73 #include <sys/ctype.h>
74 #include <sys/serialize.h>
75 #include <sys/systimer.h>
78 #include <vm/vm_param.h>
80 #include <vm/vm_kern.h>
81 #include <vm/vm_object.h>
82 #include <vm/vm_page.h>
83 #include <vm/vm_map.h>
84 #include <vm/vm_pager.h>
85 #include <vm/vm_extern.h>
87 #include <sys/thread2.h>
88 #include <sys/mplock2.h>
89 #include <sys/mutex2.h>
97 #include <machine/cpu.h>
98 #include <machine/clock.h>
99 #include <machine/specialreg.h>
101 #include <machine/bootinfo.h>
103 #include <machine/md_var.h>
104 #include <machine/metadata.h>
105 #include <machine/pc/bios.h>
106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
107 #include <machine/globaldata.h> /* CPU_prvspace */
108 #include <machine/smp.h>
110 #include <machine/perfmon.h>
112 #include <machine/cputypes.h>
113 #include <machine/intr_machdep.h>
116 #include <bus/isa/isa_device.h>
118 #include <machine_base/isa/isa_intr.h>
119 #include <bus/isa/rtc.h>
120 #include <sys/random.h>
121 #include <sys/ptrace.h>
122 #include <machine/sigframe.h>
124 #include <sys/machintr.h>
125 #include <machine_base/icu/icu_abi.h>
126 #include <machine_base/icu/elcr_var.h>
127 #include <machine_base/apic/lapic.h>
128 #include <machine_base/apic/ioapic.h>
129 #include <machine_base/apic/ioapic_abi.h>
130 #include <machine/mptable.h>
132 #define PHYSMAP_ENTRIES 10
134 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
136 extern void printcpuinfo(void); /* XXX header file */
137 extern void identify_cpu(void);
139 extern void finishidentcpu(void);
141 extern void panicifcpuunsupported(void);
143 static void cpu_startup(void *);
144 static void pic_finish(void *);
145 static void cpu_finish(void *);
147 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
148 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
150 extern void ffs_rawread_setup(void);
151 #endif /* DIRECTIO */
152 static void init_locks(void);
154 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
155 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL);
156 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL);
159 extern vm_offset_t ksym_start, ksym_end;
162 struct privatespace CPU_prvspace_bsp __aligned(4096);
163 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp };
165 int _udatasel, _ucodesel, _ucode32sel;
167 int64_t tsc_offsets[MAXCPU];
169 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
171 #if defined(SWTCH_OPTIM_STATS)
172 extern int swtch_optim_stats;
173 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
174 CTLFLAG_RD, &swtch_optim_stats, 0, "");
175 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
176 CTLFLAG_RD, &tlb_flush_count, 0, "");
178 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
179 CTLFLAG_RD, &cpu_mwait_halt_global, 0, "");
180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0,
181 "monitor/mwait target state");
183 #define CPU_MWAIT_HAS_CX \
184 ((cpu_feature2 & CPUID2_MON) && \
185 (cpu_mwait_feature & CPUID_MWAIT_EXT))
187 #define CPU_MWAIT_CX_NAMELEN 16
189 #define CPU_MWAIT_C1 1
190 #define CPU_MWAIT_C2 2
191 #define CPU_MWAIT_C3 3
192 #define CPU_MWAIT_CX_MAX 8
194 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
195 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
197 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features");
198 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
200 struct cpu_mwait_cx {
203 struct sysctl_ctx_list sysctl_ctx;
204 struct sysctl_oid *sysctl_tree;
206 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
207 static char cpu_mwait_cx_supported[256];
209 static int cpu_mwait_c1_hints_cnt;
210 static int cpu_mwait_hints_cnt;
211 static int *cpu_mwait_hints;
213 static int cpu_mwait_deep_hints_cnt;
214 static int *cpu_mwait_deep_hints;
216 #define CPU_IDLE_REPEAT_DEFAULT 750
218 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT;
219 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT;
220 static u_int cpu_mwait_repeat_shift = 1;
222 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
223 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
225 static int cpu_mwait_c3_preamble =
226 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
227 CPU_MWAIT_C3_PREAMBLE_BM_STS;
229 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
230 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
231 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD,
232 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask");
234 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
236 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
237 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS);
238 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
240 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
241 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
242 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
243 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
244 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW,
245 &cpu_mwait_repeat_shift, 0, "");
249 u_long ebda_addr = 0;
251 int imcr_present = 0;
253 int naps = 0; /* # of Applications processors */
256 struct mtx dt_lock; /* lock for GDT and LDT */
259 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
261 u_long pmem = ctob(physmem);
263 int error = sysctl_handle_long(oidp, &pmem, 0, req);
267 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
268 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
271 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
273 int error = sysctl_handle_int(oidp, 0,
274 ctob(physmem - vmstats.v_wire_count), req);
278 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
279 0, 0, sysctl_hw_usermem, "IU", "");
282 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
284 int error = sysctl_handle_int(oidp, 0,
285 x86_64_btop(avail_end - avail_start), req);
289 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
290 0, 0, sysctl_hw_availpages, "I", "");
296 * The number of PHYSMAP entries must be one less than the number of
297 * PHYSSEG entries because the PHYSMAP entry that spans the largest
298 * physical address that is accessible by ISA DMA is split into two
301 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
303 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
304 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
306 /* must be 2 less so 0 0 can signal end of chunks */
307 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
308 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
310 static vm_offset_t buffer_sva, buffer_eva;
311 vm_offset_t clean_sva, clean_eva;
312 static vm_offset_t pager_sva, pager_eva;
313 static struct trapframe proc0_tf;
316 cpu_startup(void *dummy)
320 vm_offset_t firstaddr;
323 * Good {morning,afternoon,evening,night}.
325 kprintf("%s", version);
328 panicifcpuunsupported();
332 kprintf("real memory = %ju (%ju MB)\n",
334 (intmax_t)Realmem / 1024 / 1024);
336 * Display any holes after the first chunk of extended memory.
341 kprintf("Physical memory chunk(s):\n");
342 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
343 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
345 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
346 (intmax_t)phys_avail[indx],
347 (intmax_t)phys_avail[indx + 1] - 1,
349 (intmax_t)(size1 / PAGE_SIZE));
354 * Allocate space for system data structures.
355 * The first available kernel virtual address is in "v".
356 * As pages of kernel virtual memory are allocated, "v" is incremented.
357 * As pages of memory are allocated and cleared,
358 * "firstaddr" is incremented.
359 * An index into the kernel page table corresponding to the
360 * virtual memory address maintained in "v" is kept in "mapaddr".
364 * Make two passes. The first pass calculates how much memory is
365 * needed and allocates it. The second pass assigns virtual
366 * addresses to the various data structures.
370 v = (caddr_t)firstaddr;
372 #define valloc(name, type, num) \
373 (name) = (type *)v; v = (caddr_t)((name)+(num))
374 #define valloclim(name, type, num, lim) \
375 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
378 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
379 * For the first 64MB of ram nominally allocate sufficient buffers to
380 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
381 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
382 * the buffer cache we limit the eventual kva reservation to
385 * factor represents the 1/4 x ram conversion.
388 long factor = 4 * BKVASIZE / 1024;
389 long kbytes = physmem * (PAGE_SIZE / 1024);
393 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
395 nbuf += (kbytes - 65536) * 2 / (factor * 5);
396 if (maxbcache && nbuf > maxbcache / BKVASIZE)
397 nbuf = maxbcache / BKVASIZE;
401 * Do not allow the buffer_map to be more then 1/2 the size of the
404 if (nbuf > (virtual_end - virtual_start +
405 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
406 nbuf = (virtual_end - virtual_start +
407 virtual2_end - virtual2_start) / (BKVASIZE * 2);
408 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
412 * Do not allow the buffer_map to use more than 50% of available
413 * physical-equivalent memory. Since the VM pages which back
414 * individual buffers are typically wired, having too many bufs
415 * can prevent the system from paging properly.
417 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
418 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
419 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
423 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
424 * the valloc space which is just the virtual_end - virtual_start
425 * section. We use valloc() to allocate the buf header array.
427 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
428 nbuf = (virtual_end - virtual_start) /
429 sizeof(struct buf) / 2;
430 kprintf("Warning: nbufs capped at %ld due to valloc "
431 "considerations", nbuf);
434 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
436 if (nswbuf < NSWBUF_MIN)
443 valloc(swbuf, struct buf, nswbuf);
444 valloc(buf, struct buf, nbuf);
447 * End of first pass, size has been calculated so allocate memory
449 if (firstaddr == 0) {
450 size = (vm_size_t)(v - firstaddr);
451 firstaddr = kmem_alloc(&kernel_map, round_page(size));
453 panic("startup: no room for tables");
458 * End of second pass, addresses have been assigned
460 * nbuf is an int, make sure we don't overflow the field.
462 * On 64-bit systems we always reserve maximal allocations for
463 * buffer cache buffers and there are no fragmentation issues,
464 * so the KVA segment does not have to be excessively oversized.
466 if ((vm_size_t)(v - firstaddr) != size)
467 panic("startup: table size inconsistency");
469 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
470 ((vm_offset_t)(nbuf + 16) * BKVASIZE) +
471 (nswbuf * MAXPHYS) + pager_map_size);
472 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
473 ((vm_offset_t)(nbuf + 16) * BKVASIZE));
474 buffer_map.system_map = 1;
475 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
476 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
477 pager_map.system_map = 1;
479 #if defined(USERCONFIG)
481 cninit(); /* the preferred console may have changed */
484 kprintf("avail memory = %ju (%ju MB)\n",
485 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
486 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
490 struct cpu_idle_stat {
498 u_long mwait_cx[CPU_MWAIT_CX_MAX];
501 #define CPU_IDLE_STAT_HALT -1
502 #define CPU_IDLE_STAT_SPIN -2
504 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
507 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
509 int idx = arg2, cpu, error;
512 if (idx == CPU_IDLE_STAT_HALT) {
513 for (cpu = 0; cpu < ncpus; ++cpu)
514 val += cpu_idle_stats[cpu].halt;
515 } else if (idx == CPU_IDLE_STAT_SPIN) {
516 for (cpu = 0; cpu < ncpus; ++cpu)
517 val += cpu_idle_stats[cpu].spin;
519 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
520 ("invalid index %d", idx));
521 for (cpu = 0; cpu < ncpus; ++cpu)
522 val += cpu_idle_stats[cpu].mwait_cx[idx];
525 error = sysctl_handle_quad(oidp, &val, 0, req);
526 if (error || req->newptr == NULL)
529 if (idx == CPU_IDLE_STAT_HALT) {
530 for (cpu = 0; cpu < ncpus; ++cpu)
531 cpu_idle_stats[cpu].halt = 0;
532 cpu_idle_stats[0].halt = val;
533 } else if (idx == CPU_IDLE_STAT_SPIN) {
534 for (cpu = 0; cpu < ncpus; ++cpu)
535 cpu_idle_stats[cpu].spin = 0;
536 cpu_idle_stats[0].spin = val;
538 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
539 ("invalid index %d", idx));
540 for (cpu = 0; cpu < ncpus; ++cpu)
541 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
542 cpu_idle_stats[0].mwait_cx[idx] = val;
548 cpu_mwait_attach(void)
553 if (!CPU_MWAIT_HAS_CX)
556 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
557 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
558 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
559 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
563 * Pentium dual-core, Core 2 and beyond do not need any
564 * additional activities to enter deep C-state, i.e. C3(+).
566 cpu_mwait_cx_no_bmarb();
568 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts);
570 cpu_mwait_cx_no_bmsts();
573 sbuf_new(&sb, cpu_mwait_cx_supported,
574 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
576 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
577 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
580 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
582 sysctl_ctx_init(&cx->sysctl_ctx);
583 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
584 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
585 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
586 if (cx->sysctl_tree == NULL)
589 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
590 SYSCTL_ADD_INT(&cx->sysctl_ctx,
591 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
592 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
594 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
595 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
596 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
597 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
599 for (sub = 0; sub < cx->subcnt; ++sub)
600 sbuf_printf(&sb, "C%d/%d ", i, sub);
608 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt;
609 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
610 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
611 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
615 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
618 subcnt = cpu_mwait_cx_info[i].subcnt;
619 for (j = 0; j < subcnt; ++j) {
620 KASSERT(hint_idx < cpu_mwait_hints_cnt,
621 ("invalid mwait hint index %d", hint_idx));
622 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
626 KASSERT(hint_idx == cpu_mwait_hints_cnt,
627 ("mwait hint count %d != index %d",
628 cpu_mwait_hints_cnt, hint_idx));
631 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt);
632 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
633 int hint = cpu_mwait_hints[i];
635 kprintf(" C%d/%d hint 0x%04x\n",
636 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
644 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
645 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
646 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
650 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
653 subcnt = cpu_mwait_cx_info[i].subcnt;
654 for (j = 0; j < subcnt; ++j) {
655 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
656 ("invalid mwait deep hint index %d", hint_idx));
657 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
661 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
662 ("mwait deep hint count %d != index %d",
663 cpu_mwait_deep_hints_cnt, hint_idx));
666 kprintf("MWAIT deep hints:\n");
667 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
668 int hint = cpu_mwait_deep_hints[i];
670 kprintf(" C%d/%d hint 0x%04x\n",
671 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
675 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt;
677 for (i = 0; i < ncpus; ++i) {
680 ksnprintf(name, sizeof(name), "idle%d", i);
681 SYSCTL_ADD_PROC(NULL,
682 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO,
683 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i],
684 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", "");
689 cpu_finish(void *dummy __unused)
696 pic_finish(void *dummy __unused)
698 /* Log ELCR information */
701 /* Log MPTABLE information */
702 mptable_pci_int_dump();
705 MachIntrABI.finalize();
709 * Send an interrupt to process.
711 * Stack is set up to allow sigcode stored
712 * at top to call routine, followed by kcall
713 * to sigreturn routine below. After sigreturn
714 * resets the signal mask, the stack, and the
715 * frame pointer, it returns to the user
719 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
721 struct lwp *lp = curthread->td_lwp;
722 struct proc *p = lp->lwp_proc;
723 struct trapframe *regs;
724 struct sigacts *psp = p->p_sigacts;
725 struct sigframe sf, *sfp;
729 regs = lp->lwp_md.md_regs;
730 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
732 /* Save user context */
733 bzero(&sf, sizeof(struct sigframe));
734 sf.sf_uc.uc_sigmask = *mask;
735 sf.sf_uc.uc_stack = lp->lwp_sigstk;
736 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
737 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
738 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
740 /* Make the size of the saved context visible to userland */
741 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
743 /* Allocate and validate space for the signal handler context. */
744 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
745 SIGISMEMBER(psp->ps_sigonstack, sig)) {
746 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
747 sizeof(struct sigframe));
748 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
750 /* We take red zone into account */
751 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
755 * XXX AVX needs 64-byte alignment but sigframe has other fields and
756 * the embedded ucontext is not at the front, so aligning this won't
757 * help us. Fortunately we bcopy in/out of the sigframe, so the
760 * The problem though is if userland winds up trying to use the
763 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
765 /* Translate the signal is appropriate */
766 if (p->p_sysent->sv_sigtbl) {
767 if (sig <= p->p_sysent->sv_sigsize)
768 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
772 * Build the argument list for the signal handler.
774 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
776 regs->tf_rdi = sig; /* argument 1 */
777 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
779 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
781 * Signal handler installed with SA_SIGINFO.
783 * action(signo, siginfo, ucontext)
785 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
786 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
787 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
789 /* fill siginfo structure */
790 sf.sf_si.si_signo = sig;
791 sf.sf_si.si_code = code;
792 sf.sf_si.si_addr = (void *)regs->tf_addr;
795 * Old FreeBSD-style arguments.
797 * handler (signo, code, [uc], addr)
799 regs->tf_rsi = (register_t)code; /* argument 2 */
800 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
801 sf.sf_ahu.sf_handler = catcher;
805 * If we're a vm86 process, we want to save the segment registers.
806 * We also change eflags to be our emulated eflags, not the actual
810 if (regs->tf_eflags & PSL_VM) {
811 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
812 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
814 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
815 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
816 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
817 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
819 if (vm86->vm86_has_vme == 0)
820 sf.sf_uc.uc_mcontext.mc_eflags =
821 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
822 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
825 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
826 * syscalls made by the signal handler. This just avoids
827 * wasting time for our lazy fixup of such faults. PSL_NT
828 * does nothing in vm86 mode, but vm86 programs can set it
829 * almost legitimately in probes for old cpu types.
831 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
836 * Save the FPU state and reinit the FP unit
838 npxpush(&sf.sf_uc.uc_mcontext);
841 * Copy the sigframe out to the user's stack.
843 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
845 * Something is wrong with the stack pointer.
846 * ...Kill the process.
851 regs->tf_rsp = (register_t)sfp;
852 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
855 * i386 abi specifies that the direction flag must be cleared
858 regs->tf_rflags &= ~(PSL_T|PSL_D);
861 * 64 bit mode has a code and stack selector but
862 * no data or extra selector. %fs and %gs are not
865 regs->tf_cs = _ucodesel;
866 regs->tf_ss = _udatasel;
871 * Sanitize the trapframe for a virtual kernel passing control to a custom
872 * VM context. Remove any items that would otherwise create a privilage
875 * XXX at the moment we allow userland to set the resume flag. Is this a
879 cpu_sanitize_frame(struct trapframe *frame)
881 frame->tf_cs = _ucodesel;
882 frame->tf_ss = _udatasel;
883 /* XXX VM (8086) mode not supported? */
884 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
885 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
891 * Sanitize the tls so loading the descriptor does not blow up
892 * on us. For x86_64 we don't have to do anything.
895 cpu_sanitize_tls(struct savetls *tls)
901 * sigreturn(ucontext_t *sigcntxp)
903 * System call to cleanup state after a signal
904 * has been taken. Reset signal mask and
905 * stack state from context left by sendsig (above).
906 * Return to previous pc and psl as specified by
907 * context left by sendsig. Check carefully to
908 * make sure that the user has not modified the
909 * state to gain improper privileges.
913 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
914 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
917 sys_sigreturn(struct sigreturn_args *uap)
919 struct lwp *lp = curthread->td_lwp;
920 struct trapframe *regs;
928 * We have to copy the information into kernel space so userland
929 * can't modify it while we are sniffing it.
931 regs = lp->lwp_md.md_regs;
932 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
936 rflags = ucp->uc_mcontext.mc_rflags;
938 /* VM (8086) mode not supported */
939 rflags &= ~PSL_VM_UNSUPP;
942 if (eflags & PSL_VM) {
943 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
944 struct vm86_kernel *vm86;
947 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
948 * set up the vm86 area, and we can't enter vm86 mode.
950 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
952 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
953 if (vm86->vm86_inited == 0)
956 /* go back to user mode if both flags are set */
957 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
958 trapsignal(lp, SIGBUS, 0);
960 if (vm86->vm86_has_vme) {
961 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
962 (eflags & VME_USERCHANGE) | PSL_VM;
964 vm86->vm86_eflags = eflags; /* save VIF, VIP */
965 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
966 (eflags & VM_USERCHANGE) | PSL_VM;
968 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
969 tf->tf_eflags = eflags;
970 tf->tf_vm86_ds = tf->tf_ds;
971 tf->tf_vm86_es = tf->tf_es;
972 tf->tf_vm86_fs = tf->tf_fs;
973 tf->tf_vm86_gs = tf->tf_gs;
974 tf->tf_ds = _udatasel;
975 tf->tf_es = _udatasel;
976 tf->tf_fs = _udatasel;
977 tf->tf_gs = _udatasel;
982 * Don't allow users to change privileged or reserved flags.
985 * XXX do allow users to change the privileged flag PSL_RF.
986 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
987 * should sometimes set it there too. tf_eflags is kept in
988 * the signal context during signal handling and there is no
989 * other place to remember it, so the PSL_RF bit may be
990 * corrupted by the signal handler without us knowing.
991 * Corruption of the PSL_RF bit at worst causes one more or
992 * one less debugger trap, so allowing it is fairly harmless.
994 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
995 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
1000 * Don't allow users to load a valid privileged %cs. Let the
1001 * hardware check for invalid selectors, excess privilege in
1002 * other selectors, invalid %eip's and invalid %esp's.
1004 cs = ucp->uc_mcontext.mc_cs;
1005 if (!CS_SECURE(cs)) {
1006 kprintf("sigreturn: cs = 0x%x\n", cs);
1007 trapsignal(lp, SIGBUS, T_PROTFLT);
1010 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
1014 * Restore the FPU state from the frame
1017 npxpop(&ucp->uc_mcontext);
1019 if (ucp->uc_mcontext.mc_onstack & 1)
1020 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
1022 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
1024 lp->lwp_sigmask = ucp->uc_sigmask;
1025 SIG_CANTMASK(lp->lwp_sigmask);
1028 return(EJUSTRETURN);
1032 * Machine dependent boot() routine
1034 * I haven't seen anything to put here yet
1035 * Possibly some stuff might be grafted back here from boot()
1043 * Shutdown the CPU as much as possible
1049 __asm__ __volatile("hlt");
1053 * cpu_idle() represents the idle LWKT. You cannot return from this function
1054 * (unless you want to blow things up!). Instead we look for runnable threads
1055 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1057 * The main loop is entered with a critical section held, we must release
1058 * the critical section before doing anything else. lwkt_switch() will
1059 * check for pending interrupts due to entering and exiting its own
1062 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1063 * However, there are cases where the idlethread will be entered with
1064 * the possibility that no IPI will occur and in such cases
1065 * lwkt_switch() sets TDF_IDLE_NOHLT.
1067 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1068 * must occur before it starts using ACPI halt.
1070 * NOTE: Value overridden in hammer_time().
1072 static int cpu_idle_hlt = 2;
1073 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1074 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1075 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1076 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1078 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1079 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1080 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1081 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1084 cpu_idle_default_hook(void)
1087 * We must guarentee that hlt is exactly the instruction
1088 * following the sti.
1090 __asm __volatile("sti; hlt");
1093 /* Other subsystems (e.g., ACPI) can hook this later. */
1094 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1097 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1106 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >>
1107 cpu_mwait_repeat_shift;
1108 if (idx >= cpu_mwait_c1_hints_cnt) {
1109 /* Step up faster, once we walked through all C1 states */
1110 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1);
1112 if (hint == CPU_MWAIT_HINT_AUTODEEP) {
1113 if (idx >= cpu_mwait_deep_hints_cnt)
1114 idx = cpu_mwait_deep_hints_cnt - 1;
1115 hint = cpu_mwait_deep_hints[idx];
1117 if (idx >= cpu_mwait_hints_cnt)
1118 idx = cpu_mwait_hints_cnt - 1;
1119 hint = cpu_mwait_hints[idx];
1122 cx_idx = MWAIT_EAX_TO_CX(hint);
1123 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1124 stat->mwait_cx[cx_idx]++;
1131 globaldata_t gd = mycpu;
1132 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1133 struct thread *td __debugvar = gd->gd_curthread;
1137 stat->repeat = stat->repeat_last = cpu_idle_repeat_max;
1140 KKASSERT(td->td_critcount == 0);
1144 * See if there are any LWKTs ready to go.
1149 * When halting inside a cli we must check for reqflags
1150 * races, particularly [re]schedule requests. Running
1151 * splz() does the job.
1154 * 0 Never halt, just spin
1156 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1158 * Better default for modern (Haswell+) Intel
1161 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1162 * use the ACPI halt (default). This is a hybrid
1163 * approach. See machdep.cpu_idle_repeat.
1165 * Better default for modern AMD cpus and older
1168 * 3 Always use the ACPI halt. This typically
1169 * eats the least amount of power but the cpu
1170 * will be slow waking up. Slows down e.g.
1171 * compiles and other pipe/event oriented stuff.
1175 * NOTE: Interrupts are enabled and we are not in a critical
1178 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1179 * don't bother capping gd_idle_repeat, it is ok if
1182 if (gd->gd_idle_repeat == 0) {
1183 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1184 if (stat->repeat > cpu_idle_repeat_max)
1185 stat->repeat = cpu_idle_repeat_max;
1186 stat->repeat_last = 0;
1187 stat->repeat_delta = 0;
1189 ++stat->repeat_last;
1191 ++gd->gd_idle_repeat;
1192 reqflags = gd->gd_reqflags;
1193 quick = (cpu_idle_hlt == 1) ||
1194 (cpu_idle_hlt < 3 &&
1195 gd->gd_idle_repeat < cpu_idle_repeat);
1197 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1198 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1200 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1201 cpu_mwait_cx_hint(stat), 0);
1203 } else if (cpu_idle_hlt) {
1204 __asm __volatile("cli");
1206 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1208 cpu_idle_default_hook();
1212 __asm __volatile("sti");
1216 __asm __volatile("sti");
1223 * This routine is called if a spinlock has been held through the
1224 * exponential backoff period and is seriously contested. On a real cpu
1228 cpu_spinlock_contested(void)
1234 * Clear registers on exec
1237 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1239 struct thread *td = curthread;
1240 struct lwp *lp = td->td_lwp;
1241 struct pcb *pcb = td->td_pcb;
1242 struct trapframe *regs = lp->lwp_md.md_regs;
1244 /* was i386_user_cleanup() in NetBSD */
1248 bzero((char *)regs, sizeof(struct trapframe));
1249 regs->tf_rip = entry;
1250 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1251 regs->tf_rdi = stack; /* argv */
1252 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1253 regs->tf_ss = _udatasel;
1254 regs->tf_cs = _ucodesel;
1255 regs->tf_rbx = ps_strings;
1258 * Reset the hardware debug registers if they were in use.
1259 * They won't have any meaning for the newly exec'd process.
1261 if (pcb->pcb_flags & PCB_DBREGS) {
1267 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1268 if (pcb == td->td_pcb) {
1270 * Clear the debug registers on the running
1271 * CPU, otherwise they will end up affecting
1272 * the next process we switch to.
1276 pcb->pcb_flags &= ~PCB_DBREGS;
1280 * Initialize the math emulator (if any) for the current process.
1281 * Actually, just clear the bit that says that the emulator has
1282 * been initialized. Initialization is delayed until the process
1283 * traps to the emulator (if it is done at all) mainly because
1284 * emulators don't provide an entry point for initialization.
1286 pcb->pcb_flags &= ~FP_SOFTFP;
1289 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1290 * gd_npxthread. Otherwise a preemptive interrupt thread
1291 * may panic in npxdna().
1294 load_cr0(rcr0() | CR0_MP);
1297 * NOTE: The MSR values must be correct so we can return to
1298 * userland. gd_user_fs/gs must be correct so the switch
1299 * code knows what the current MSR values are.
1301 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1302 pcb->pcb_gsbase = 0;
1303 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1304 mdcpu->gd_user_gs = 0;
1305 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1306 wrmsr(MSR_KGSBASE, 0);
1308 /* Initialize the npx (if any) for the current process. */
1312 pcb->pcb_ds = _udatasel;
1313 pcb->pcb_es = _udatasel;
1314 pcb->pcb_fs = _udatasel;
1315 pcb->pcb_gs = _udatasel;
1324 cr0 |= CR0_NE; /* Done by npxinit() */
1325 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1326 cr0 |= CR0_WP | CR0_AM;
1332 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1335 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1337 if (!error && req->newptr)
1342 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1343 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1345 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1346 CTLFLAG_RW, &disable_rtc_set, 0, "");
1349 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1350 CTLFLAG_RD, &bootinfo, bootinfo, "");
1353 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1354 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1356 extern u_long bootdev; /* not a cdev_t - encoding is different */
1357 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1358 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1361 * Initialize 386 and configure to run kernel
1365 * Initialize segments & interrupt table
1369 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1370 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1372 union descriptor ldt[NLDT]; /* local descriptor table */
1375 /* table descriptors - used to load tables by cpu */
1376 struct region_descriptor r_gdt;
1377 struct region_descriptor r_idt_arr[MAXCPU];
1379 /* JG proc0paddr is a virtual address */
1382 char proc0paddr_buff[LWKT_THREAD_STACK];
1385 /* software prototypes -- in more palatable form */
1386 struct soft_segment_descriptor gdt_segs[] = {
1387 /* GNULL_SEL 0 Null Descriptor */
1388 { 0x0, /* segment base address */
1390 0, /* segment type */
1391 0, /* segment descriptor priority level */
1392 0, /* segment descriptor present */
1394 0, /* default 32 vs 16 bit size */
1395 0 /* limit granularity (byte/page units)*/ },
1396 /* GCODE_SEL 1 Code Descriptor for kernel */
1397 { 0x0, /* segment base address */
1398 0xfffff, /* length - all address space */
1399 SDT_MEMERA, /* segment type */
1400 SEL_KPL, /* segment descriptor priority level */
1401 1, /* segment descriptor present */
1403 0, /* default 32 vs 16 bit size */
1404 1 /* limit granularity (byte/page units)*/ },
1405 /* GDATA_SEL 2 Data Descriptor for kernel */
1406 { 0x0, /* segment base address */
1407 0xfffff, /* length - all address space */
1408 SDT_MEMRWA, /* segment type */
1409 SEL_KPL, /* segment descriptor priority level */
1410 1, /* segment descriptor present */
1412 0, /* default 32 vs 16 bit size */
1413 1 /* limit granularity (byte/page units)*/ },
1414 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1415 { 0x0, /* segment base address */
1416 0xfffff, /* length - all address space */
1417 SDT_MEMERA, /* segment type */
1418 SEL_UPL, /* segment descriptor priority level */
1419 1, /* segment descriptor present */
1421 1, /* default 32 vs 16 bit size */
1422 1 /* limit granularity (byte/page units)*/ },
1423 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1424 { 0x0, /* segment base address */
1425 0xfffff, /* length - all address space */
1426 SDT_MEMRWA, /* segment type */
1427 SEL_UPL, /* segment descriptor priority level */
1428 1, /* segment descriptor present */
1430 1, /* default 32 vs 16 bit size */
1431 1 /* limit granularity (byte/page units)*/ },
1432 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1433 { 0x0, /* segment base address */
1434 0xfffff, /* length - all address space */
1435 SDT_MEMERA, /* segment type */
1436 SEL_UPL, /* segment descriptor priority level */
1437 1, /* segment descriptor present */
1439 0, /* default 32 vs 16 bit size */
1440 1 /* limit granularity (byte/page units)*/ },
1441 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1443 0x0, /* segment base address */
1444 sizeof(struct x86_64tss)-1,/* length - all address space */
1445 SDT_SYSTSS, /* segment type */
1446 SEL_KPL, /* segment descriptor priority level */
1447 1, /* segment descriptor present */
1449 0, /* unused - default 32 vs 16 bit size */
1450 0 /* limit granularity (byte/page units)*/ },
1451 /* Actually, the TSS is a system descriptor which is double size */
1452 { 0x0, /* segment base address */
1454 0, /* segment type */
1455 0, /* segment descriptor priority level */
1456 0, /* segment descriptor present */
1458 0, /* default 32 vs 16 bit size */
1459 0 /* limit granularity (byte/page units)*/ },
1460 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1461 { 0x0, /* segment base address */
1462 0xfffff, /* length - all address space */
1463 SDT_MEMRWA, /* segment type */
1464 SEL_UPL, /* segment descriptor priority level */
1465 1, /* segment descriptor present */
1467 1, /* default 32 vs 16 bit size */
1468 1 /* limit granularity (byte/page units)*/ },
1472 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1476 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1477 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1479 ip->gd_looffset = (uintptr_t)func;
1480 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1486 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1491 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1493 struct gate_descriptor *ip;
1495 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1497 ip = &idt_arr[cpu][idx];
1498 ip->gd_looffset = (uintptr_t)func;
1499 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1505 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1508 #define IDTVEC(name) __CONCAT(X,name)
1511 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1512 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1513 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1514 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1515 IDTVEC(xmm), IDTVEC(dblfault),
1516 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1518 #ifdef DEBUG_INTERRUPTS
1519 extern inthand_t *Xrsvdary[256];
1523 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1525 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1526 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1527 ssd->ssd_type = sd->sd_type;
1528 ssd->ssd_dpl = sd->sd_dpl;
1529 ssd->ssd_p = sd->sd_p;
1530 ssd->ssd_def32 = sd->sd_def32;
1531 ssd->ssd_gran = sd->sd_gran;
1535 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1538 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1539 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1540 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1541 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1542 sd->sd_type = ssd->ssd_type;
1543 sd->sd_dpl = ssd->ssd_dpl;
1544 sd->sd_p = ssd->ssd_p;
1545 sd->sd_long = ssd->ssd_long;
1546 sd->sd_def32 = ssd->ssd_def32;
1547 sd->sd_gran = ssd->ssd_gran;
1551 ssdtosyssd(struct soft_segment_descriptor *ssd,
1552 struct system_segment_descriptor *sd)
1555 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1556 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1557 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1558 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1559 sd->sd_type = ssd->ssd_type;
1560 sd->sd_dpl = ssd->ssd_dpl;
1561 sd->sd_p = ssd->ssd_p;
1562 sd->sd_gran = ssd->ssd_gran;
1566 * Populate the (physmap) array with base/bound pairs describing the
1567 * available physical memory in the system, then test this memory and
1568 * build the phys_avail array describing the actually-available memory.
1570 * If we cannot accurately determine the physical memory map, then use
1571 * value from the 0xE801 call, and failing that, the RTC.
1573 * Total memory size may be set by the kernel environment variable
1574 * hw.physmem or the compile-time define MAXMEM.
1576 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1577 * of PAGE_SIZE. This also greatly reduces the memory test time
1578 * which would otherwise be excessive on machines with > 8G of ram.
1580 * XXX first should be vm_paddr_t.
1583 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1584 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1585 vm_paddr_t physmap[PHYSMAP_SIZE];
1586 struct bios_smap *smapbase, *smap, *smapend;
1590 getmemsize(caddr_t kmdp, u_int64_t first)
1592 int off, physmap_idx, pa_indx, da_indx;
1595 vm_paddr_t msgbuf_size;
1596 u_long physmem_tunable;
1598 quad_t dcons_addr, dcons_size;
1600 bzero(physmap, sizeof(physmap));
1604 * get memory map from INT 15:E820, kindly supplied by the loader.
1606 * subr_module.c says:
1607 * "Consumer may safely assume that size value precedes data."
1608 * ie: an int32_t immediately precedes smap.
1610 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1611 MODINFO_METADATA | MODINFOMD_SMAP);
1612 if (smapbase == NULL)
1613 panic("No BIOS smap info from loader!");
1615 smapsize = *((u_int32_t *)smapbase - 1);
1616 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1618 for (smap = smapbase; smap < smapend; smap++) {
1619 if (boothowto & RB_VERBOSE)
1620 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1621 smap->type, smap->base, smap->length);
1623 if (smap->type != SMAP_TYPE_MEMORY)
1626 if (smap->length == 0)
1629 for (i = 0; i <= physmap_idx; i += 2) {
1630 if (smap->base < physmap[i + 1]) {
1631 if (boothowto & RB_VERBOSE) {
1632 kprintf("Overlapping or non-monotonic "
1633 "memory region, ignoring "
1639 if (i <= physmap_idx)
1642 Realmem += smap->length;
1644 if (smap->base == physmap[physmap_idx + 1]) {
1645 physmap[physmap_idx + 1] += smap->length;
1650 if (physmap_idx == PHYSMAP_SIZE) {
1651 kprintf("Too many segments in the physical "
1652 "address map, giving up\n");
1655 physmap[physmap_idx] = smap->base;
1656 physmap[physmap_idx + 1] = smap->base + smap->length;
1659 base_memory = physmap[1] / 1024;
1660 /* make hole for AP bootstrap code */
1661 physmap[1] = mp_bootaddress(base_memory);
1663 /* Save EBDA address, if any */
1664 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1668 * Maxmem isn't the "maximum memory", it's one larger than the
1669 * highest page of the physical address space. It should be
1670 * called something like "Maxphyspage". We may adjust this
1671 * based on ``hw.physmem'' and the results of the memory test.
1673 Maxmem = atop(physmap[physmap_idx + 1]);
1676 Maxmem = MAXMEM / 4;
1679 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1680 Maxmem = atop(physmem_tunable);
1683 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1686 if (Maxmem > atop(physmap[physmap_idx + 1]))
1687 Maxmem = atop(physmap[physmap_idx + 1]);
1690 * Blowing out the DMAP will blow up the system.
1692 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1693 kprintf("Limiting Maxmem due to DMAP size\n");
1694 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1697 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1698 (boothowto & RB_VERBOSE)) {
1699 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1703 * Call pmap initialization to make new kernel address space
1707 pmap_bootstrap(&first);
1708 physmap[0] = PAGE_SIZE;
1711 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1714 for (i = j = 0; i <= physmap_idx; i += 2) {
1715 if (physmap[i+1] > ptoa(Maxmem))
1716 physmap[i+1] = ptoa(Maxmem);
1717 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1718 ~PHYSMAP_ALIGN_MASK;
1719 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1721 physmap[j] = physmap[i];
1722 physmap[j+1] = physmap[i+1];
1724 if (physmap[i] < physmap[i+1])
1727 physmap_idx = j - 2;
1730 * Align anything else used in the validation loop.
1732 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1735 * Size up each available chunk of physical memory.
1739 phys_avail[pa_indx++] = physmap[0];
1740 phys_avail[pa_indx] = physmap[0];
1741 dump_avail[da_indx] = physmap[0];
1745 * Get dcons buffer address
1747 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1748 kgetenv_quad("dcons.size", &dcons_size) == 0)
1752 * Validate the physical memory. The physical memory segments
1753 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1756 for (i = 0; i <= physmap_idx; i += 2) {
1759 end = physmap[i + 1];
1761 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1762 int tmp, page_bad, full;
1763 int *ptr = (int *)CADDR1;
1767 * block out kernel memory as not available.
1769 if (pa >= 0x200000 && pa < first)
1773 * block out dcons buffer
1776 && pa >= trunc_page(dcons_addr)
1777 && pa < dcons_addr + dcons_size) {
1784 * map page into kernel: valid, read/write,non-cacheable
1787 kernel_pmap.pmap_bits[PG_V_IDX] |
1788 kernel_pmap.pmap_bits[PG_RW_IDX] |
1789 kernel_pmap.pmap_bits[PG_N_IDX];
1794 * Test for alternating 1's and 0's
1796 *(volatile int *)ptr = 0xaaaaaaaa;
1798 if (*(volatile int *)ptr != 0xaaaaaaaa)
1801 * Test for alternating 0's and 1's
1803 *(volatile int *)ptr = 0x55555555;
1805 if (*(volatile int *)ptr != 0x55555555)
1810 *(volatile int *)ptr = 0xffffffff;
1812 if (*(volatile int *)ptr != 0xffffffff)
1817 *(volatile int *)ptr = 0x0;
1819 if (*(volatile int *)ptr != 0x0)
1822 * Restore original value.
1827 * Adjust array of valid/good pages.
1829 if (page_bad == TRUE)
1832 * If this good page is a continuation of the
1833 * previous set of good pages, then just increase
1834 * the end pointer. Otherwise start a new chunk.
1835 * Note that "end" points one higher than end,
1836 * making the range >= start and < end.
1837 * If we're also doing a speculative memory
1838 * test and we at or past the end, bump up Maxmem
1839 * so that we keep going. The first bad page
1840 * will terminate the loop.
1842 if (phys_avail[pa_indx] == pa) {
1843 phys_avail[pa_indx] += PHYSMAP_ALIGN;
1846 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1848 "Too many holes in the physical address space, giving up\n");
1853 phys_avail[pa_indx++] = pa;
1854 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
1856 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
1858 if (dump_avail[da_indx] == pa) {
1859 dump_avail[da_indx] += PHYSMAP_ALIGN;
1862 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1866 dump_avail[da_indx++] = pa;
1867 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
1878 * The last chunk must contain at least one page plus the message
1879 * buffer to avoid complicating other code (message buffer address
1880 * calculation, etc.).
1882 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1884 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1885 msgbuf_size >= phys_avail[pa_indx]) {
1886 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1887 phys_avail[pa_indx--] = 0;
1888 phys_avail[pa_indx--] = 0;
1891 Maxmem = atop(phys_avail[pa_indx]);
1893 /* Trim off space for the message buffer. */
1894 phys_avail[pa_indx] -= msgbuf_size;
1896 avail_end = phys_avail[pa_indx];
1898 /* Map the message buffer. */
1899 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1900 pmap_kenter((vm_offset_t)msgbufp + off,
1901 phys_avail[pa_indx] + off);
1905 struct machintr_abi MachIntrABI;
1916 * 7 Device Not Available (x87)
1918 * 9 Coprocessor Segment overrun (unsupported, reserved)
1920 * 11 Segment not present
1922 * 13 General Protection
1925 * 16 x87 FP Exception pending
1926 * 17 Alignment Check
1928 * 19 SIMD floating point
1930 * 32-255 INTn/external sources
1933 hammer_time(u_int64_t modulep, u_int64_t physfree)
1936 int gsel_tss, x, cpu;
1938 int metadata_missing, off;
1940 struct mdglobaldata *gd;
1944 * Prevent lowering of the ipl if we call tsleep() early.
1946 gd = &CPU_prvspace[0]->mdglobaldata;
1947 bzero(gd, sizeof(*gd));
1950 * Note: on both UP and SMP curthread must be set non-NULL
1951 * early in the boot sequence because the system assumes
1952 * that 'curthread' is never NULL.
1955 gd->mi.gd_curthread = &thread0;
1956 thread0.td_gd = &gd->mi;
1958 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1961 metadata_missing = 0;
1962 if (bootinfo.bi_modulep) {
1963 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1964 preload_bootstrap_relocate(KERNBASE);
1966 metadata_missing = 1;
1968 if (bootinfo.bi_envp)
1969 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1972 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1973 preload_bootstrap_relocate(PTOV_OFFSET);
1974 kmdp = preload_search_by_type("elf kernel");
1976 kmdp = preload_search_by_type("elf64 kernel");
1977 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1978 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1980 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1981 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1984 if (boothowto & RB_VERBOSE)
1988 * Default MachIntrABI to ICU
1990 MachIntrABI = MachIntrABI_ICU;
1993 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1994 * and ncpus_fit_mask remain 0.
1999 /* Init basic tunables, hz etc */
2003 * make gdt memory segments
2005 gdt_segs[GPROC0_SEL].ssd_base =
2006 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss;
2008 gd->mi.gd_prvspace = CPU_prvspace[0];
2010 for (x = 0; x < NGDT; x++) {
2011 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
2012 ssdtosd(&gdt_segs[x], &gdt[x]);
2014 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2015 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
2017 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
2018 r_gdt.rd_base = (long) gdt;
2021 wrmsr(MSR_FSBASE, 0); /* User value */
2022 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
2023 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
2025 mi_gdinit(&gd->mi, 0);
2027 proc0paddr = proc0paddr_buff;
2028 mi_proc0init(&gd->mi, proc0paddr);
2029 safepri = TDPRI_MAX;
2031 /* spinlocks and the BGL */
2035 for (x = 0; x < NIDT; x++)
2036 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
2037 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
2038 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
2039 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
2040 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
2041 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
2042 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
2043 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
2044 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
2045 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
2046 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
2047 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
2048 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
2049 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
2050 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
2051 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
2052 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
2053 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
2054 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
2055 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
2057 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2058 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2059 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2062 lidt(&r_idt_arr[0]);
2065 * Initialize the console before we print anything out.
2070 if (metadata_missing)
2071 kprintf("WARNING: loader(8) metadata is missing!\n");
2081 * Initialize IRQ mapping
2084 * SHOULD be after elcr_probe()
2086 MachIntrABI_ICU.initmap();
2087 MachIntrABI_IOAPIC.initmap();
2091 if (boothowto & RB_KDB)
2092 Debugger("Boot flags requested debugger");
2096 finishidentcpu(); /* Final stage of CPU initialization */
2097 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2098 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2100 identify_cpu(); /* Final stage of CPU initialization */
2101 initializecpu(0); /* Initialize CPU registers */
2104 * On modern intel cpus, haswell or later, cpu_idle_hlt=1 is better
2105 * becaue the cpu does significant power management in HLT
2106 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP).
2108 * On modern amd cpus or on any older amd or intel cpu,
2109 * cpu_idle_hlt=2 is better because ACPI is needed to reduce power
2112 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
2113 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */
2117 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2118 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2119 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2120 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt);
2123 * Some of the virtual machines do not work w/ I/O APIC
2124 * enabled. If the user does not explicitly enable or
2125 * disable the I/O APIC (ioapic_enable < 0), then we
2126 * disable I/O APIC on all virtual machines.
2129 * This must be done after identify_cpu(), which sets
2132 if (ioapic_enable < 0) {
2133 if (cpu_feature2 & CPUID2_VMM)
2139 /* make an initial tss so cpu can get interrupt stack on syscall! */
2140 gd->gd_common_tss.tss_rsp0 =
2141 (register_t)(thread0.td_kstack +
2142 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2143 /* Ensure the stack is aligned to 16 bytes */
2144 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2146 /* double fault stack */
2147 gd->gd_common_tss.tss_ist1 =
2148 (long)&gd->mi.gd_prvspace->idlestack[
2149 sizeof(gd->mi.gd_prvspace->idlestack)];
2151 /* Set the IO permission bitmap (empty due to tss seg limit) */
2152 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2154 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2155 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2156 gd->gd_common_tssd = *gd->gd_tss_gdt;
2159 /* Set up the fast syscall stuff */
2160 msr = rdmsr(MSR_EFER) | EFER_SCE;
2161 wrmsr(MSR_EFER, msr);
2162 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2163 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2164 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2165 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2166 wrmsr(MSR_STAR, msr);
2167 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2169 getmemsize(kmdp, physfree);
2170 init_param2(physmem);
2172 /* now running on new page tables, configured,and u/iom is accessible */
2174 /* Map the message buffer. */
2176 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2177 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2180 msgbufinit(msgbufp, MSGBUF_SIZE);
2183 /* transfer to user mode */
2185 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2186 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2187 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2193 /* setup proc 0's pcb */
2194 thread0.td_pcb->pcb_flags = 0;
2195 thread0.td_pcb->pcb_cr3 = KPML4phys;
2196 thread0.td_pcb->pcb_ext = NULL;
2197 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2199 /* Location of kernel stack for locore */
2200 return ((u_int64_t)thread0.td_pcb);
2204 * Initialize machine-dependant portions of the global data structure.
2205 * Note that the global data area and cpu0's idlestack in the private
2206 * data space were allocated in locore.
2208 * Note: the idlethread's cpl is 0
2210 * WARNING! Called from early boot, 'mycpu' may not work yet.
2213 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2216 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2218 lwkt_init_thread(&gd->mi.gd_idlethread,
2219 gd->mi.gd_prvspace->idlestack,
2220 sizeof(gd->mi.gd_prvspace->idlestack),
2222 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2223 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2224 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2225 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2229 * We only have to check for DMAP bounds, the globaldata space is
2230 * actually part of the kernel_map so we don't have to waste time
2231 * checking CPU_prvspace[*].
2234 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2237 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2238 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2242 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2248 globaldata_find(int cpu)
2250 KKASSERT(cpu >= 0 && cpu < ncpus);
2251 return(&CPU_prvspace[cpu]->mdglobaldata.mi);
2255 * This path should be safe from the SYSRET issue because only stopped threads
2256 * can have their %rip adjusted this way (and all heavy weight thread switches
2257 * clear QUICKREF and thus do not use SYSRET). However, the code path is
2258 * convoluted so add a safety by forcing %rip to be cannonical.
2261 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2263 if (addr & 0x0000800000000000LLU)
2264 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU;
2266 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU;
2271 ptrace_single_step(struct lwp *lp)
2273 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2278 fill_regs(struct lwp *lp, struct reg *regs)
2280 struct trapframe *tp;
2282 if ((tp = lp->lwp_md.md_regs) == NULL)
2284 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2289 set_regs(struct lwp *lp, struct reg *regs)
2291 struct trapframe *tp;
2293 tp = lp->lwp_md.md_regs;
2294 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2295 !CS_SECURE(regs->r_cs))
2297 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2303 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2305 struct env87 *penv_87 = &sv_87->sv_env;
2306 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2309 /* FPU control/status */
2310 penv_87->en_cw = penv_xmm->en_cw;
2311 penv_87->en_sw = penv_xmm->en_sw;
2312 penv_87->en_tw = penv_xmm->en_tw;
2313 penv_87->en_fip = penv_xmm->en_fip;
2314 penv_87->en_fcs = penv_xmm->en_fcs;
2315 penv_87->en_opcode = penv_xmm->en_opcode;
2316 penv_87->en_foo = penv_xmm->en_foo;
2317 penv_87->en_fos = penv_xmm->en_fos;
2320 for (i = 0; i < 8; ++i)
2321 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2325 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2327 struct env87 *penv_87 = &sv_87->sv_env;
2328 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2331 /* FPU control/status */
2332 penv_xmm->en_cw = penv_87->en_cw;
2333 penv_xmm->en_sw = penv_87->en_sw;
2334 penv_xmm->en_tw = penv_87->en_tw;
2335 penv_xmm->en_fip = penv_87->en_fip;
2336 penv_xmm->en_fcs = penv_87->en_fcs;
2337 penv_xmm->en_opcode = penv_87->en_opcode;
2338 penv_xmm->en_foo = penv_87->en_foo;
2339 penv_xmm->en_fos = penv_87->en_fos;
2342 for (i = 0; i < 8; ++i)
2343 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2347 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2349 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2352 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2353 (struct save87 *)fpregs);
2356 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2361 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2364 set_fpregs_xmm((struct save87 *)fpregs,
2365 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2368 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2373 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2378 dbregs->dr[0] = rdr0();
2379 dbregs->dr[1] = rdr1();
2380 dbregs->dr[2] = rdr2();
2381 dbregs->dr[3] = rdr3();
2382 dbregs->dr[4] = rdr4();
2383 dbregs->dr[5] = rdr5();
2384 dbregs->dr[6] = rdr6();
2385 dbregs->dr[7] = rdr7();
2388 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2390 dbregs->dr[0] = pcb->pcb_dr0;
2391 dbregs->dr[1] = pcb->pcb_dr1;
2392 dbregs->dr[2] = pcb->pcb_dr2;
2393 dbregs->dr[3] = pcb->pcb_dr3;
2396 dbregs->dr[6] = pcb->pcb_dr6;
2397 dbregs->dr[7] = pcb->pcb_dr7;
2402 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2405 load_dr0(dbregs->dr[0]);
2406 load_dr1(dbregs->dr[1]);
2407 load_dr2(dbregs->dr[2]);
2408 load_dr3(dbregs->dr[3]);
2409 load_dr4(dbregs->dr[4]);
2410 load_dr5(dbregs->dr[5]);
2411 load_dr6(dbregs->dr[6]);
2412 load_dr7(dbregs->dr[7]);
2415 struct ucred *ucred;
2417 uint64_t mask1, mask2;
2420 * Don't let an illegal value for dr7 get set. Specifically,
2421 * check for undefined settings. Setting these bit patterns
2422 * result in undefined behaviour and can lead to an unexpected
2425 /* JG this loop looks unreadable */
2426 /* Check 4 2-bit fields for invalid patterns.
2427 * These fields are R/Wi, for i = 0..3
2429 /* Is 10 in LENi allowed when running in compatibility mode? */
2430 /* Pattern 10 in R/Wi might be used to indicate
2431 * breakpoint on I/O. Further analysis should be
2432 * carried to decide if it is safe and useful to
2433 * provide access to that capability
2435 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2436 i++, mask1 <<= 4, mask2 <<= 4)
2437 if ((dbregs->dr[7] & mask1) == mask2)
2440 pcb = lp->lwp_thread->td_pcb;
2441 ucred = lp->lwp_proc->p_ucred;
2444 * Don't let a process set a breakpoint that is not within the
2445 * process's address space. If a process could do this, it
2446 * could halt the system by setting a breakpoint in the kernel
2447 * (if ddb was enabled). Thus, we need to check to make sure
2448 * that no breakpoints are being enabled for addresses outside
2449 * process's address space, unless, perhaps, we were called by
2452 * XXX - what about when the watched area of the user's
2453 * address space is written into from within the kernel
2454 * ... wouldn't that still cause a breakpoint to be generated
2455 * from within kernel mode?
2458 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2459 if (dbregs->dr[7] & 0x3) {
2460 /* dr0 is enabled */
2461 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2465 if (dbregs->dr[7] & (0x3<<2)) {
2466 /* dr1 is enabled */
2467 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2471 if (dbregs->dr[7] & (0x3<<4)) {
2472 /* dr2 is enabled */
2473 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2477 if (dbregs->dr[7] & (0x3<<6)) {
2478 /* dr3 is enabled */
2479 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2484 pcb->pcb_dr0 = dbregs->dr[0];
2485 pcb->pcb_dr1 = dbregs->dr[1];
2486 pcb->pcb_dr2 = dbregs->dr[2];
2487 pcb->pcb_dr3 = dbregs->dr[3];
2488 pcb->pcb_dr6 = dbregs->dr[6];
2489 pcb->pcb_dr7 = dbregs->dr[7];
2491 pcb->pcb_flags |= PCB_DBREGS;
2498 * Return > 0 if a hardware breakpoint has been hit, and the
2499 * breakpoint was in user space. Return 0, otherwise.
2502 user_dbreg_trap(void)
2504 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2505 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2506 int nbp; /* number of breakpoints that triggered */
2507 caddr_t addr[4]; /* breakpoint addresses */
2511 if ((dr7 & 0xff) == 0) {
2513 * all GE and LE bits in the dr7 register are zero,
2514 * thus the trap couldn't have been caused by the
2515 * hardware debug registers
2526 * None of the breakpoint bits are set meaning this
2527 * trap was not caused by any of the debug registers
2533 * at least one of the breakpoints were hit, check to see
2534 * which ones and if any of them are user space addresses
2538 addr[nbp++] = (caddr_t)rdr0();
2541 addr[nbp++] = (caddr_t)rdr1();
2544 addr[nbp++] = (caddr_t)rdr2();
2547 addr[nbp++] = (caddr_t)rdr3();
2550 for (i=0; i<nbp; i++) {
2552 (caddr_t)VM_MAX_USER_ADDRESS) {
2554 * addr[i] is in user space
2561 * None of the breakpoints are in user space.
2569 Debugger(const char *msg)
2571 kprintf("Debugger(\"%s\") called.\n", msg);
2578 * Provide inb() and outb() as functions. They are normally only
2579 * available as macros calling inlined functions, thus cannot be
2580 * called inside DDB.
2582 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2588 /* silence compiler warnings */
2590 void outb(u_int, u_char);
2597 * We use %%dx and not %1 here because i/o is done at %dx and not at
2598 * %edx, while gcc generates inferior code (movw instead of movl)
2599 * if we tell it to load (u_short) port.
2601 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2606 outb(u_int port, u_char data)
2610 * Use an unnecessary assignment to help gcc's register allocator.
2611 * This make a large difference for gcc-1.40 and a tiny difference
2612 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2613 * best results. gcc-2.6.0 can't handle this.
2616 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2624 * initialize all the SMP locks
2627 /* critical region when masking or unmasking interupts */
2628 struct spinlock_deprecated imen_spinlock;
2630 /* critical region for old style disable_intr/enable_intr */
2631 struct spinlock_deprecated mpintr_spinlock;
2633 /* critical region around INTR() routines */
2634 struct spinlock_deprecated intr_spinlock;
2636 /* lock region used by kernel profiling */
2637 struct spinlock_deprecated mcount_spinlock;
2639 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2640 struct spinlock_deprecated com_spinlock;
2642 /* lock regions around the clock hardware */
2643 struct spinlock_deprecated clock_spinlock;
2649 * Get the initial mplock with a count of 1 for the BSP.
2650 * This uses a LOGICAL cpu ID, ie BSP == 0.
2652 cpu_get_initial_mplock();
2654 spin_lock_init(&mcount_spinlock);
2655 spin_lock_init(&intr_spinlock);
2656 spin_lock_init(&mpintr_spinlock);
2657 spin_lock_init(&imen_spinlock);
2658 spin_lock_init(&com_spinlock);
2659 spin_lock_init(&clock_spinlock);
2661 /* our token pool needs to work early */
2662 lwkt_token_pool_init();
2666 cpu_mwait_hint_valid(uint32_t hint)
2670 cx_idx = MWAIT_EAX_TO_CX(hint);
2671 if (cx_idx >= CPU_MWAIT_CX_MAX)
2674 sub = MWAIT_EAX_TO_CX_SUB(hint);
2675 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2682 cpu_mwait_cx_no_bmsts(void)
2684 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
2688 cpu_mwait_cx_no_bmarb(void)
2690 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB);
2694 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto)
2696 int old_cx_idx, sub = 0;
2699 old_cx_idx = MWAIT_EAX_TO_CX(hint);
2700 sub = MWAIT_EAX_TO_CX_SUB(hint);
2701 } else if (hint == CPU_MWAIT_HINT_AUTO) {
2702 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
2703 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
2704 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
2706 old_cx_idx = CPU_MWAIT_CX_MAX;
2709 if (!CPU_MWAIT_HAS_CX)
2710 strlcpy(name, "NONE", namelen);
2711 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
2712 strlcpy(name, "AUTO", namelen);
2713 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
2714 strlcpy(name, "AUTODEEP", namelen);
2715 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
2716 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
2717 strlcpy(name, "INVALID", namelen);
2719 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub);
2725 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto)
2727 int cx_idx, sub, hint;
2730 if (allow_auto && strcmp(name, "AUTO") == 0) {
2731 hint = CPU_MWAIT_HINT_AUTO;
2732 cx_idx = CPU_MWAIT_C2;
2735 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
2736 hint = CPU_MWAIT_HINT_AUTODEEP;
2737 cx_idx = CPU_MWAIT_C3;
2741 if (strlen(name) < 4 || toupper(name[0]) != 'C')
2746 cx_idx = strtol(start, &ptr, 10);
2747 if (ptr == start || *ptr != '/')
2749 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
2755 sub = strtol(start, &ptr, 10);
2758 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2761 hint = MWAIT_EAX_HINT(cx_idx, sub);
2768 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx)
2770 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
2772 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
2775 error = cputimer_intr_powersave_addreq();
2778 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
2779 cputimer_intr_powersave_remreq();
2785 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
2786 boolean_t allow_auto)
2788 int error, cx_idx, old_cx_idx, hint;
2789 char name[CPU_MWAIT_CX_NAMELEN];
2792 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name),
2795 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2796 if (error != 0 || req->newptr == NULL)
2799 if (!CPU_MWAIT_HAS_CX)
2802 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto);
2806 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
2815 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name)
2817 int error, cx_idx, old_cx_idx, hint;
2818 char name[CPU_MWAIT_CX_NAMELEN];
2820 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension"));
2823 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
2825 strlcpy(name, cx_name, sizeof(name));
2826 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
2830 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
2839 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
2841 int hint = cpu_mwait_halt_global;
2842 int error, cx_idx, cpu;
2843 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN];
2845 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
2847 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2848 if (error != 0 || req->newptr == NULL)
2851 if (!CPU_MWAIT_HAS_CX)
2854 /* Save name for later per-cpu CX configuration */
2855 strlcpy(cx_name, name, sizeof(cx_name));
2857 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
2861 /* Change per-cpu CX configuration */
2862 for (cpu = 0; cpu < ncpus; ++cpu) {
2863 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name);
2868 cpu_mwait_halt_global = hint;
2873 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
2875 struct cpu_idle_stat *stat = arg1;
2878 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2884 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
2888 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2889 &cpu_mwait_spin, FALSE);