4 * (c)Copyright 2016, Matthew Dillon, All Rights Reserved. See the
5 * COPYRIGHT file at the base of the distribution.
8 #define X86_REG_RAX (0x0000 | X86_SIZE_UNSPEC)
9 #define X86_REG_RCX (0x0001 | X86_SIZE_UNSPEC)
10 #define X86_REG_RDX (0x0002 | X86_SIZE_UNSPEC)
11 #define X86_REG_RBX (0x0003 | X86_SIZE_UNSPEC)
12 #define X86_REG_RSP (0x0004 | X86_SIZE_UNSPEC)
13 #define X86_REG_RBP (0x0005 | X86_SIZE_UNSPEC)
14 #define X86_REG_RSI (0x0006 | X86_SIZE_UNSPEC)
15 #define X86_REG_RDI (0x0007 | X86_SIZE_UNSPEC)
16 #define X86_REG_R8 (0x0008 | X86_SIZE_UNSPEC)
17 #define X86_REG_R9 (0x0009 | X86_SIZE_UNSPEC)
18 #define X86_REG_R10 (0x000A | X86_SIZE_UNSPEC)
19 #define X86_REG_R11 (0x000B | X86_SIZE_UNSPEC)
20 #define X86_REG_R12 (0x000C | X86_SIZE_UNSPEC)
21 #define X86_REG_R13 (0x000D | X86_SIZE_UNSPEC)
22 #define X86_REG_R14 (0x000E | X86_SIZE_UNSPEC)
23 #define X86_REG_R15 (0x000F | X86_SIZE_UNSPEC)
24 #define X86_REG_RIP (0x0010 | X86_SIZE_UNSPEC)
26 #define X86_REG_XMM0 (0x0020 | X86_SIZE_UNSPEC)
27 #define X86_REG_XMM1 (0x0021 | X86_SIZE_UNSPEC)
28 #define X86_REG_XMM2 (0x0022 | X86_SIZE_UNSPEC)
29 #define X86_REG_XMM3 (0x0023 | X86_SIZE_UNSPEC)
30 #define X86_REG_XMM4 (0x0024 | X86_SIZE_UNSPEC)
31 #define X86_REG_XMM5 (0x0025 | X86_SIZE_UNSPEC)
32 #define X86_REG_XMM6 (0x0026 | X86_SIZE_UNSPEC)
33 #define X86_REG_XMM7 (0x0027 | X86_SIZE_UNSPEC)
34 #define X86_REG_XMM8 (0x0028 | X86_SIZE_UNSPEC)
35 #define X86_REG_XMM9 (0x0029 | X86_SIZE_UNSPEC)
36 #define X86_REG_XMM10 (0x002A | X86_SIZE_UNSPEC)
37 #define X86_REG_XMM11 (0x002B | X86_SIZE_UNSPEC)
38 #define X86_REG_XMM12 (0x002C | X86_SIZE_UNSPEC)
39 #define X86_REG_XMM13 (0x002D | X86_SIZE_UNSPEC)
40 #define X86_REG_XMM14 (0x002E | X86_SIZE_UNSPEC)
41 #define X86_REG_XMM15 (0x002F | X86_SIZE_UNSPEC)
43 #define X86_REGF_RAX (1LLU << (X86_REG_RAX & X86_REG_MASK))
44 #define X86_REGF_RCX (1LLU << (X86_REG_RCX & X86_REG_MASK))
45 #define X86_REGF_RDX (1LLU << (X86_REG_RDX & X86_REG_MASK))
46 #define X86_REGF_RBX (1LLU << (X86_REG_RBX & X86_REG_MASK))
47 #define X86_REGF_RSP (1LLU << (X86_REG_RSP & X86_REG_MASK))
48 #define X86_REGF_RBP (1LLU << (X86_REG_RBP & X86_REG_MASK))
49 #define X86_REGF_RSI (1LLU << (X86_REG_RSI & X86_REG_MASK))
50 #define X86_REGF_RDI (1LLU << (X86_REG_RDI & X86_REG_MASK))
51 #define X86_REGF_R8 (1LLU << (X86_REG_R8 & X86_REG_MASK))
52 #define X86_REGF_R9 (1LLU << (X86_REG_R9 & X86_REG_MASK))
53 #define X86_REGF_R10 (1LLU << (X86_REG_R10 & X86_REG_MASK))
54 #define X86_REGF_R11 (1LLU << (X86_REG_R11 & X86_REG_MASK))
55 #define X86_REGF_R12 (1LLU << (X86_REG_R12 & X86_REG_MASK))
56 #define X86_REGF_R13 (1LLU << (X86_REG_R13 & X86_REG_MASK))
57 #define X86_REGF_R14 (1LLU << (X86_REG_R14 & X86_REG_MASK))
58 #define X86_REGF_R15 (1LLU << (X86_REG_R15 & X86_REG_MASK))
59 #define X86_REGF_RIP (1LLU << (X86_REG_RIP & X86_REG_MASK))
61 #define X86_REGF_XMM0 (1LLU << (X86_REG_XMM0 & X86_REG_MASK))
62 #define X86_REGF_XMM1 (1LLU << (X86_REG_XMM1 & X86_REG_MASK))
63 #define X86_REGF_XMM2 (1LLU << (X86_REG_XMM2 & X86_REG_MASK))
64 #define X86_REGF_XMM3 (1LLU << (X86_REG_XMM3 & X86_REG_MASK))
65 #define X86_REGF_XMM4 (1LLU << (X86_REG_XMM4 & X86_REG_MASK))
66 #define X86_REGF_XMM5 (1LLU << (X86_REG_XMM5 & X86_REG_MASK))
67 #define X86_REGF_XMM6 (1LLU << (X86_REG_XMM6 & X86_REG_MASK))
68 #define X86_REGF_XMM7 (1LLU << (X86_REG_XMM7 & X86_REG_MASK))
69 #define X86_REGF_XMM8 (1LLU << (X86_REG_XMM8 & X86_REG_MASK))
70 #define X86_REGF_XMM9 (1LLU << (X86_REG_XMM9 & X86_REG_MASK))
71 #define X86_REGF_XMM10 (1LLU << (X86_REG_XMM10 & X86_REG_MASK))
72 #define X86_REGF_XMM11 (1LLU << (X86_REG_XMM11 & X86_REG_MASK))
73 #define X86_REGF_XMM12 (1LLU << (X86_REG_XMM12 & X86_REG_MASK))
74 #define X86_REGF_XMM13 (1LLU << (X86_REG_XMM13 & X86_REG_MASK))
75 #define X86_REGF_XMM14 (1LLU << (X86_REG_XMM14 & X86_REG_MASK))
76 #define X86_REGF_XMM15 (1LLU << (X86_REG_XMM15 & X86_REG_MASK))
78 #define X86_REG_MASK 0x00FF
79 #define X86_SIZE_UNSPEC 0x0100
80 #define X86_REG_ILIMIT 0x0010 /* 0x00-0x0F */
81 #define X86_REG_IOVMAX 0x002F /* 0x00-0x1F */
82 #define X86_REG_FBASE 0x0020 /* 0x20-0x2F */
83 #define X86_REG_FLIMIT 0x0030 /* 0x20-0x2F */
84 #define X86_REG_FOVMAX 0x003F /* 0x20-0x3F */
86 #define X86_REGF_FMASK 0xFFFFFFFF00000000LLU
87 #define X86_REGF_IMASK 0x00000000FFFFFFFFLLU
88 #define X86_REGF_GOOD 0x0000FFFF0000FFFFLLU
91 * Relaxed additional procedure-crossing registerization at the cost of
92 * saving and restoring (up to) these registers across procedure calls.
94 * NOTE: Specifying XMM0 and XMM1 here would be a big waste.
96 #define X86_REGF_SPECIAL_SAVE \
97 (X86_REGF_R8 | X86_REGF_R9 | X86_REGF_R10 | X86_REGF_R11 | \
98 X86_REGF_XMM8 | X86_REGF_XMM9 | X86_REGF_XMM10 | X86_REGF_XMM11)
101 * Standard x86-64 calling convention (BSD/Linux)
103 * This ABI is used for system calls. Note that (currently) in Rune,
104 * arguments are passed on the stack.
106 * Call-saved registers:
107 * RBX, RBP, R12, R13, R14, R15, and RSP
113 #define X86_REGF_CALLSAVE_STD \
114 (X86_REGF_RBX | X86_REGF_RBP | \
115 X86_REGF_R12 | X86_REGF_R13 | X86_REGF_R14 | X86_REGF_R15)
117 #define X86_STDF_ARG1 X86_REGF_RDI
118 #define X86_STDF_ARG2 X86_REGF_RSI
119 #define X86_STDF_ARG3 X86_REGF_RDX
121 #define X86_STD_ARG1 X86_REG_RDI
122 #define X86_STD_ARG2 X86_REG_RSI
123 #define X86_STD_ARG3 X86_REG_RDX
126 * Our run-time library calling convention. We use the microsoft ABI
127 * for this because it retains more registers across the call and the
128 * RAS registerizer needs as many registers as it can get. This can
129 * be specified in GCC and CLANG in a way that allows ABI mixing
130 * (we don't want to force libc and dynamic libs to be recompiled too!).
132 * This ABI is not used for system and library interfacing calls.
135 * Call-saved registers:
136 * RBX, RBP, R12, R13, R14, R15, and RSP
137 * + RDI, RSI, XMM6-XMM15 (additional)
143 * We want our run-time calls to preserve more registers to reduce the
144 * burden on the RAS register allocator. Note that the RAS instruction
145 * generator itself needs to use %rax, %rcx, %xmm0-3, and the run-time
146 * argument registers. Those must never be specified on the call-saved
149 * This must match the RUNERUNTIME() API in libruntime.
151 #define X86_REGF_CALLSAVE_RUNTIME \
152 (X86_REGF_RBX | X86_REGF_RBP | X86_REGF_RDI | X86_REGF_RSI | \
153 X86_REGF_R12 | X86_REGF_R13 | X86_REGF_R14 | X86_REGF_R15 | \
154 X86_REGF_XMM6 | X86_REGF_XMM7 | 0 | 0 | \
155 X86_REGF_XMM8 | X86_REGF_XMM9 | X86_REGF_XMM10| X86_REGF_XMM11 | \
156 X86_REGF_XMM12| X86_REGF_XMM13| X86_REGF_XMM14| X86_REGF_XMM15)
158 #define X86_RUNTIMEF_ARG1 X86_REGF_RCX
159 #define X86_RUNTIMEF_ARG2 X86_REGF_RDX
160 #define X86_RUNTIMEF_ARG3 X86_REGF_R8
162 #define X86_RUNTIME_ARG1 X86_REG_RCX
163 #define X86_RUNTIME_ARG2 X86_REG_RDX
164 #define X86_RUNTIME_ARG3 X86_REG_R8
167 * Our standard Rune calling convention also needs to preserve as many
168 * registers as possible to make the RAS register allocator work better.
169 * Use the same convention as RUNTIME.
171 * These conventions are used for rune-to-rune calls.
173 * WARNING! rune_entry_main's ABI (e.g. set to ms_abi) must be compatible.
175 #define X86_REGF_CALLSAVE_RUNE X86_REGF_CALLSAVE_RUNTIME
177 #define X86_RUNEF_ARG1 X86_REGF_RCX
178 #define X86_RUNEF_ARG2 X86_REGF_RDX
179 #define X86_RUNEF_ARG3 X86_REGF_R8
181 #define X86_RUNE_ARG1 X86_REG_RCX
182 #define X86_RUNE_ARG2 X86_REG_RDX
183 #define X86_RUNE_ARG3 X86_REG_R8
186 * Scratch on return registers
188 #define X86_REGF_CALLSCR_STD (~X86_REGF_CALLSAVE_STD & X86_REGF_GOOD)
189 #define X86_REGF_CALLSCR_RUNTIME (~X86_REGF_CALLSAVE_RUNTIME & X86_REGF_GOOD)
190 #define X86_REGF_CALLSCR_RUNE (~X86_REGF_CALLSAVE_RUNE & X86_REGF_GOOD)