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9c80d176 SZ |
1 | /****************************************************************************** |
2 | ||
01a55482 | 3 | Copyright (c) 2001-2019, Intel Corporation |
9c80d176 SZ |
4 | All rights reserved. |
5 | ||
6 | Redistribution and use in source and binary forms, with or without | |
7 | modification, are permitted provided that the following conditions are met: | |
8 | ||
9 | 1. Redistributions of source code must retain the above copyright notice, | |
10 | this list of conditions and the following disclaimer. | |
11 | ||
12 | 2. Redistributions in binary form must reproduce the above copyright | |
13 | notice, this list of conditions and the following disclaimer in the | |
14 | documentation and/or other materials provided with the distribution. | |
15 | ||
16 | 3. Neither the name of the Intel Corporation nor the names of its | |
17 | contributors may be used to endorse or promote products derived from | |
18 | this software without specific prior written permission. | |
19 | ||
20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
30 | POSSIBILITY OF SUCH DAMAGE. | |
31 | ||
32 | ******************************************************************************/ | |
74dc3754 | 33 | /*$FreeBSD$*/ |
9c80d176 SZ |
34 | |
35 | #ifndef _E1000_REGS_H_ | |
36 | #define _E1000_REGS_H_ | |
37 | ||
01a55482 | 38 | /* General Register Descriptions */ |
4be59a01 SZ |
39 | #define E1000_CTRL 0x00000 /* Device Control - RW */ |
40 | #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ | |
41 | #define E1000_STATUS 0x00008 /* Device Status - RO */ | |
42 | #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ | |
43 | #define E1000_EERD 0x00014 /* EEPROM Read - RW */ | |
44 | #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ | |
45 | #define E1000_FLA 0x0001C /* Flash Access - RW */ | |
46 | #define E1000_MDIC 0x00020 /* MDI Control - RW */ | |
47 | #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */ | |
48 | #define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */ | |
49 | #define E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */ | |
50 | #define E1000_EEPROM_PCIE_CTRL_WORD_2 0x28 /* EEPROM PCIe Ctrl Word 2 */ | |
51 | #define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */ | |
52 | #define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */ | |
53 | #define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */ | |
379ebbe7 SZ |
54 | #define E1000_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */ |
55 | #define E1000_MPHY_DATA 0x0E10 /* GBE MPHY Data */ | |
56 | #define E1000_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */ | |
57 | #define E1000_PPHY_CTRL 0x5b48 /* PCIe PHY Control */ | |
4be59a01 SZ |
58 | #define E1000_I350_BARCTRL 0x5BFC /* BAR ctrl reg */ |
59 | #define E1000_I350_DTXMXPKTSZ 0x355C /* Maximum sent packet size reg*/ | |
60 | #define E1000_SCTL 0x00024 /* SerDes Control - RW */ | |
61 | #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ | |
62 | #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ | |
4765c386 | 63 | #define E1000_FEXT 0x0002C /* Future Extended - RW */ |
4be59a01 | 64 | #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ |
4be59a01 SZ |
65 | #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */ |
66 | #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ | |
01a55482 | 67 | #define E1000_FEXTNVM5 0x00014 /* Future Extended NVM 5 - RW */ |
379ebbe7 SZ |
68 | #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */ |
69 | #define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */ | |
74dc3754 SZ |
70 | #define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */ |
71 | #define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */ | |
72 | #define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */ | |
4be59a01 SZ |
73 | #define E1000_FCT 0x00030 /* Flow Control Type - RW */ |
74 | #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ | |
75 | #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ | |
76 | #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ | |
77 | #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ | |
78 | #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ | |
79 | #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ | |
80 | #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ | |
81 | #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ | |
82 | #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ | |
379ebbe7 SZ |
83 | #define E1000_SVCR 0x000F0 |
84 | #define E1000_SVT 0x000F4 | |
85 | #define E1000_LPIC 0x000FC /* Low Power IDLE control */ | |
4be59a01 SZ |
86 | #define E1000_RCTL 0x00100 /* Rx Control - RW */ |
87 | #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ | |
88 | #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ | |
89 | #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ | |
90 | #define E1000_PBA_ECC 0x01100 /* PBA ECC Register */ | |
91 | #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ | |
92 | #define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) | |
93 | #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ | |
94 | #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ | |
95 | #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ | |
96 | #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ | |
97 | #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ | |
98 | #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */ | |
99 | #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ | |
100 | #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ | |
101 | #define E1000_TCTL 0x00400 /* Tx Control - RW */ | |
102 | #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ | |
103 | #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */ | |
104 | #define E1000_TBT 0x00448 /* Tx Burst Timer - RW */ | |
105 | #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ | |
106 | #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ | |
379ebbe7 | 107 | #define E1000_LEDMUX 0x08130 /* LED MUX Control */ |
4be59a01 SZ |
108 | #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ |
109 | #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ | |
110 | #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ | |
111 | #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */ | |
112 | #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ | |
113 | #define E1000_PBS 0x01008 /* Packet Buffer Size */ | |
379ebbe7 | 114 | #define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */ |
74dc3754 | 115 | #define E1000_IOSFPC 0x00F28 /* TX corrupted data */ |
4be59a01 | 116 | #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ |
65aebe9f | 117 | #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ |
a40fda39 | 118 | #define E1000_EEMNGCTL_I210 0x01010 /* i210 MNG EEprom Mode Control */ |
4be59a01 | 119 | #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ |
ba0123e0 | 120 | #define E1000_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */ |
4be59a01 SZ |
121 | #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ |
122 | #define E1000_FLSWCTL 0x01030 /* FLASH control register */ | |
123 | #define E1000_FLSWDATA 0x01034 /* FLASH data register */ | |
124 | #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ | |
125 | #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ | |
126 | #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ | |
127 | #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ | |
128 | #define E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */ | |
129 | #define E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */ | |
130 | #define E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */ | |
131 | #define E1000_I2C_DATA_OE_N 0x00000800 /* I2C- Data Output Enable */ | |
132 | #define E1000_I2C_DATA_IN 0x00001000 /* I2C- Data In */ | |
133 | #define E1000_I2C_CLK_OE_N 0x00002000 /* I2C- Clock Output Enable */ | |
134 | #define E1000_I2C_CLK_IN 0x00004000 /* I2C- Clock In */ | |
135 | #define E1000_I2C_CLK_STRETCH_DIS 0x00008000 /* I2C- Dis Clk Stretching */ | |
136 | #define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */ | |
137 | #define E1000_SWDSTS 0x01044 /* SW Device Status - RW */ | |
138 | #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ | |
139 | #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ | |
140 | #define E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */ | |
141 | #define E1000_ICR_V2 0x01500 /* Intr Cause - new location - RC */ | |
142 | #define E1000_ICS_V2 0x01504 /* Intr Cause Set - new location - WO */ | |
143 | #define E1000_IMS_V2 0x01508 /* Intr Mask Set/Read - new location - RW */ | |
144 | #define E1000_IMC_V2 0x0150C /* Intr Mask Clear - new location - WO */ | |
145 | #define E1000_IAM_V2 0x01510 /* Intr Ack Auto Mask - new location - RW */ | |
146 | #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ | |
147 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ | |
148 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ | |
149 | #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ | |
379ebbe7 SZ |
150 | #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */ |
151 | #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */ | |
152 | #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */ | |
153 | #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */ | |
154 | #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */ | |
4be59a01 SZ |
155 | #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */ |
156 | #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ | |
9c80d176 | 157 | /* Split and Replication Rx Control - RW */ |
4be59a01 SZ |
158 | #define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */ |
159 | #define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */ | |
160 | #define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */ | |
161 | #define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ | |
162 | #define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ | |
163 | #define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */ | |
164 | #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ | |
165 | #define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */ | |
166 | #define E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */ | |
167 | #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ | |
168 | #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ | |
379ebbe7 SZ |
169 | #define E1000_EMIADD 0x10 /* Extended Memory Indirect Address */ |
170 | #define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */ | |
4be59a01 SZ |
171 | #define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */ |
172 | #define E1000_I210_FLMNGCTL 0x12038 | |
173 | #define E1000_I210_FLMNGDATA 0x1203C | |
174 | #define E1000_I210_FLMNGCNT 0x12040 | |
175 | ||
176 | #define E1000_I210_FLSWCTL 0x12048 | |
177 | #define E1000_I210_FLSWDATA 0x1204C | |
178 | #define E1000_I210_FLSWCNT 0x12050 | |
179 | ||
180 | #define E1000_I210_FLA 0x1201C | |
181 | ||
01a55482 SZ |
182 | #define E1000_EEC_REG 0x12010 |
183 | ||
184 | ||
185 | #define E1000_SHADOWINF 0x12068 | |
186 | #define E1000_FLFWUPDATE 0x12108 | |
187 | ||
4be59a01 SZ |
188 | #define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n)) |
189 | #define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */ | |
190 | ||
191 | /* QAV Tx mode control register */ | |
192 | #define E1000_I210_TQAVCTRL 0x3570 | |
193 | ||
194 | /* QAV Tx mode control register bitfields masks */ | |
195 | /* QAV enable */ | |
196 | #define E1000_TQAVCTRL_MODE (1 << 0) | |
197 | /* Fetching arbitration type */ | |
198 | #define E1000_TQAVCTRL_FETCH_ARB (1 << 4) | |
199 | /* Fetching timer enable */ | |
200 | #define E1000_TQAVCTRL_FETCH_TIMER_ENABLE (1 << 5) | |
201 | /* Launch arbitration type */ | |
202 | #define E1000_TQAVCTRL_LAUNCH_ARB (1 << 8) | |
203 | /* Launch timer enable */ | |
204 | #define E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE (1 << 9) | |
205 | /* SP waits for SR enable */ | |
206 | #define E1000_TQAVCTRL_SP_WAIT_SR (1 << 10) | |
207 | /* Fetching timer correction */ | |
208 | #define E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET 16 | |
209 | #define E1000_TQAVCTRL_FETCH_TIMER_DELTA \ | |
210 | (0xFFFF << E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET) | |
211 | ||
212 | /* High credit registers where _n can be 0 or 1. */ | |
213 | #define E1000_I210_TQAVHC(_n) (0x300C + 0x40 * (_n)) | |
214 | ||
215 | /* Queues fetch arbitration priority control register */ | |
216 | #define E1000_I210_TQAVARBCTRL 0x3574 | |
217 | /* Queues priority masks where _n and _p can be 0-3. */ | |
ba0123e0 | 218 | #define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * (_n))) |
4be59a01 SZ |
219 | /* QAV Tx mode control registers where _n can be 0 or 1. */ |
220 | #define E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n)) | |
221 | ||
222 | /* QAV Tx mode control register bitfields masks */ | |
223 | #define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */ | |
224 | #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */ | |
225 | #define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ | |
226 | ||
227 | /* Good transmitted packets counter registers */ | |
228 | #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n))) | |
229 | ||
230 | /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */ | |
ba0123e0 | 231 | #define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * (_n))) |
4be59a01 | 232 | |
379ebbe7 SZ |
233 | #define E1000_MMDAC 13 /* MMD Access Control */ |
234 | #define E1000_MMDAAD 14 /* MMD Access Address/Data */ | |
235 | ||
236 | /* Convenience macros | |
9c80d176 SZ |
237 | * |
238 | * Note: "_n" is the queue number of the register to be written to. | |
239 | * | |
240 | * Example usage: | |
241 | * E1000_RDBAL_REG(current_rx_queue) | |
242 | */ | |
4be59a01 SZ |
243 | #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ |
244 | (0x0C000 + ((_n) * 0x40))) | |
245 | #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ | |
246 | (0x0C004 + ((_n) * 0x40))) | |
247 | #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ | |
248 | (0x0C008 + ((_n) * 0x40))) | |
249 | #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ | |
250 | (0x0C00C + ((_n) * 0x40))) | |
251 | #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ | |
252 | (0x0C010 + ((_n) * 0x40))) | |
253 | #define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \ | |
254 | (0x0C014 + ((_n) * 0x40))) | |
255 | #define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n) | |
256 | #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ | |
257 | (0x0C018 + ((_n) * 0x40))) | |
258 | #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ | |
259 | (0x0C028 + ((_n) * 0x40))) | |
260 | #define E1000_RQDPC(_n) ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \ | |
261 | (0x0C030 + ((_n) * 0x40))) | |
262 | #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ | |
263 | (0x0E000 + ((_n) * 0x40))) | |
264 | #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ | |
265 | (0x0E004 + ((_n) * 0x40))) | |
266 | #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ | |
267 | (0x0E008 + ((_n) * 0x40))) | |
268 | #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ | |
269 | (0x0E010 + ((_n) * 0x40))) | |
270 | #define E1000_TXCTL(_n) ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \ | |
271 | (0x0E014 + ((_n) * 0x40))) | |
6a5a645e | 272 | #define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n) |
4be59a01 SZ |
273 | #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ |
274 | (0x0E018 + ((_n) * 0x40))) | |
275 | #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ | |
276 | (0x0E028 + ((_n) * 0x40))) | |
277 | #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \ | |
278 | (0x0E038 + ((_n) * 0x40))) | |
279 | #define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \ | |
280 | (0x0E03C + ((_n) * 0x40))) | |
281 | #define E1000_TARC(_n) (0x03840 + ((_n) * 0x100)) | |
282 | #define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */ | |
283 | #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ | |
284 | #define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */ | |
285 | #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ | |
286 | #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) | |
287 | #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ | |
288 | (0x054E0 + ((_i - 16) * 8))) | |
289 | #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ | |
290 | (0x054E4 + ((_i - 16) * 8))) | |
01a55482 | 291 | |
4be59a01 SZ |
292 | #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) |
293 | #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) | |
294 | #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) | |
295 | #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) | |
296 | #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) | |
297 | #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) | |
298 | #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) | |
299 | #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) | |
300 | #define E1000_PBSLAC 0x03100 /* Pkt Buffer Slave Access Control */ | |
301 | #define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Pkt Buffer DWORD */ | |
302 | #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ | |
303 | /* Same as TXPBS, renamed for newer Si - RW */ | |
304 | #define E1000_ITPBS 0x03404 | |
305 | #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ | |
306 | #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ | |
307 | #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ | |
308 | #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ | |
309 | #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ | |
310 | #define E1000_TDPUMB 0x0357C /* DMA Tx Desc uC Mail Box - RW */ | |
311 | #define E1000_TDPUAD 0x03580 /* DMA Tx Desc uC Addr Command - RW */ | |
312 | #define E1000_TDPUWD 0x03584 /* DMA Tx Desc uC Data Write - RW */ | |
313 | #define E1000_TDPURD 0x03588 /* DMA Tx Desc uC Data Read - RW */ | |
314 | #define E1000_TDPUCTL 0x0358C /* DMA Tx Desc uC Control - RW */ | |
315 | #define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */ | |
316 | #define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */ | |
317 | #define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */ | |
318 | /* DMA Tx Max Total Allow Size Reqs - RW */ | |
319 | #define E1000_DTXMXSZRQ 0x03540 | |
320 | #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ | |
321 | #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ | |
322 | #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ | |
01a55482 | 323 | /* Statistics Register Descriptions */ |
4be59a01 SZ |
324 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ |
325 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ | |
326 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ | |
327 | #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ | |
328 | #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ | |
329 | #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ | |
330 | #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ | |
331 | #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ | |
332 | #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ | |
333 | #define E1000_COLC 0x04028 /* Collision Count - R/clr */ | |
334 | #define E1000_DC 0x04030 /* Defer Count - R/clr */ | |
335 | #define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */ | |
336 | #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ | |
337 | #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ | |
338 | #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ | |
339 | #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */ | |
340 | #define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */ | |
341 | #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ | |
342 | #define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ | |
343 | #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ | |
344 | #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ | |
345 | #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ | |
346 | #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ | |
347 | #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ | |
348 | #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ | |
349 | #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ | |
350 | #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ | |
351 | #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ | |
352 | #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ | |
353 | #define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ | |
354 | #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ | |
355 | #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ | |
356 | #define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ | |
357 | #define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ | |
358 | #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ | |
359 | #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */ | |
360 | #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */ | |
361 | #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */ | |
362 | #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */ | |
363 | #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ | |
364 | #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ | |
365 | #define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ | |
366 | #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ | |
367 | #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */ | |
368 | #define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ | |
369 | #define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */ | |
370 | #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */ | |
371 | #define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */ | |
372 | #define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ | |
373 | #define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ | |
374 | #define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ | |
375 | #define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ | |
376 | #define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ | |
377 | #define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ | |
378 | #define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ | |
379 | #define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ | |
380 | #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ | |
381 | #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ | |
382 | #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ | |
01a55482 | 383 | /* Interrupt Cause */ |
4be59a01 SZ |
384 | #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ |
385 | #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ | |
386 | #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ | |
387 | #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ | |
388 | #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ | |
389 | #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ | |
390 | #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ | |
391 | #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ | |
392 | #define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */ | |
9c80d176 | 393 | |
4be59a01 SZ |
394 | #define E1000_VFGPRC 0x00F10 |
395 | #define E1000_VFGORC 0x00F18 | |
396 | #define E1000_VFMPRC 0x00F3C | |
397 | #define E1000_VFGPTC 0x00F14 | |
398 | #define E1000_VFGOTC 0x00F34 | |
399 | #define E1000_VFGOTLBC 0x00F50 | |
400 | #define E1000_VFGPTLBC 0x00F44 | |
401 | #define E1000_VFGORLBC 0x00F48 | |
402 | #define E1000_VFGPRLBC 0x00F40 | |
62583d18 | 403 | /* Virtualization statistical counters */ |
4be59a01 SZ |
404 | #define E1000_PFVFGPRC(_n) (0x010010 + (0x100 * (_n))) |
405 | #define E1000_PFVFGPTC(_n) (0x010014 + (0x100 * (_n))) | |
406 | #define E1000_PFVFGORC(_n) (0x010018 + (0x100 * (_n))) | |
407 | #define E1000_PFVFGOTC(_n) (0x010034 + (0x100 * (_n))) | |
408 | #define E1000_PFVFMPRC(_n) (0x010038 + (0x100 * (_n))) | |
409 | #define E1000_PFVFGPRLBC(_n) (0x010040 + (0x100 * (_n))) | |
410 | #define E1000_PFVFGPTLBC(_n) (0x010044 + (0x100 * (_n))) | |
411 | #define E1000_PFVFGORLBC(_n) (0x010048 + (0x100 * (_n))) | |
412 | #define E1000_PFVFGOTLBC(_n) (0x010050 + (0x100 * (_n))) | |
62583d18 | 413 | |
4be59a01 SZ |
414 | /* LinkSec */ |
415 | #define E1000_LSECTXUT 0x04300 /* Tx Untagged Pkt Cnt */ | |
416 | #define E1000_LSECTXPKTE 0x04304 /* Encrypted Tx Pkts Cnt */ | |
417 | #define E1000_LSECTXPKTP 0x04308 /* Protected Tx Pkt Cnt */ | |
418 | #define E1000_LSECTXOCTE 0x0430C /* Encrypted Tx Octets Cnt */ | |
419 | #define E1000_LSECTXOCTP 0x04310 /* Protected Tx Octets Cnt */ | |
420 | #define E1000_LSECRXUT 0x04314 /* Untagged non-Strict Rx Pkt Cnt */ | |
421 | #define E1000_LSECRXOCTD 0x0431C /* Rx Octets Decrypted Count */ | |
422 | #define E1000_LSECRXOCTV 0x04320 /* Rx Octets Validated */ | |
423 | #define E1000_LSECRXBAD 0x04324 /* Rx Bad Tag */ | |
424 | #define E1000_LSECRXNOSCI 0x04328 /* Rx Packet No SCI Count */ | |
425 | #define E1000_LSECRXUNSCI 0x0432C /* Rx Packet Unknown SCI Count */ | |
426 | #define E1000_LSECRXUNCH 0x04330 /* Rx Unchecked Packets Count */ | |
427 | #define E1000_LSECRXDELAY 0x04340 /* Rx Delayed Packet Count */ | |
428 | #define E1000_LSECRXLATE 0x04350 /* Rx Late Packets Count */ | |
429 | #define E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */ | |
430 | #define E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */ | |
431 | #define E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */ | |
432 | #define E1000_LSECRXUNSA 0x043C0 /* Rx Unused SA Count */ | |
433 | #define E1000_LSECRXNUSA 0x043D0 /* Rx Not Using SA Count */ | |
434 | #define E1000_LSECTXCAP 0x0B000 /* Tx Capabilities Register - RO */ | |
435 | #define E1000_LSECRXCAP 0x0B300 /* Rx Capabilities Register - RO */ | |
436 | #define E1000_LSECTXCTRL 0x0B004 /* Tx Control - RW */ | |
437 | #define E1000_LSECRXCTRL 0x0B304 /* Rx Control - RW */ | |
438 | #define E1000_LSECTXSCL 0x0B008 /* Tx SCI Low - RW */ | |
439 | #define E1000_LSECTXSCH 0x0B00C /* Tx SCI High - RW */ | |
440 | #define E1000_LSECTXSA 0x0B010 /* Tx SA0 - RW */ | |
441 | #define E1000_LSECTXPN0 0x0B018 /* Tx SA PN 0 - RW */ | |
442 | #define E1000_LSECTXPN1 0x0B01C /* Tx SA PN 1 - RW */ | |
443 | #define E1000_LSECRXSCL 0x0B3D0 /* Rx SCI Low - RW */ | |
444 | #define E1000_LSECRXSCH 0x0B3E0 /* Rx SCI High - RW */ | |
445 | /* LinkSec Tx 128-bit Key 0 - WO */ | |
446 | #define E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n))) | |
447 | /* LinkSec Tx 128-bit Key 1 - WO */ | |
448 | #define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n))) | |
449 | #define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */ | |
450 | #define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */ | |
379ebbe7 | 451 | /* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit |
62583d18 SZ |
452 | * key - RW. |
453 | */ | |
4be59a01 | 454 | #define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m))) |
62583d18 | 455 | |
4be59a01 SZ |
456 | #define E1000_SSVPC 0x041A0 /* Switch Security Violation Pkt Cnt */ |
457 | #define E1000_IPSCTRL 0xB430 /* IpSec Control Register */ | |
458 | #define E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */ | |
459 | #define E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */ | |
460 | /* IPSec Rx IPv4/v6 Address - RW */ | |
461 | #define E1000_IPSRXIPADDR(_n) (0x0B420 + (0x04 * (_n))) | |
462 | /* IPSec Rx 128-bit Key - RW */ | |
463 | #define E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n))) | |
464 | #define E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */ | |
465 | #define E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */ | |
466 | /* IPSec Tx 128-bit Key - RW */ | |
467 | #define E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n))) | |
468 | #define E1000_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */ | |
469 | #define E1000_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */ | |
470 | #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ | |
471 | #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ | |
472 | #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ | |
473 | #define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */ | |
474 | #define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ | |
475 | #define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */ | |
476 | #define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */ | |
477 | #define E1000_RPTHC 0x04104 /* Rx Packets To Host */ | |
478 | #define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */ | |
479 | #define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */ | |
480 | #define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ | |
481 | #define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ | |
482 | #define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ | |
483 | #define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ | |
484 | #define E1000_LENERRS 0x04138 /* Length Errors Count */ | |
485 | #define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ | |
486 | #define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */ | |
487 | #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ | |
488 | #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ | |
489 | #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ | |
490 | #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Pg - RW */ | |
4be59a01 SZ |
491 | #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ |
492 | #define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */ | |
493 | #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ | |
494 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ | |
495 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ | |
496 | #define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */ | |
497 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ | |
498 | #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */ | |
499 | #define E1000_CIAA 0x05B88 /* Config Indirect Access Address - RW */ | |
500 | #define E1000_CIAD 0x05B8C /* Config Indirect Access Data - RW */ | |
501 | #define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */ | |
502 | #define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */ | |
503 | #define E1000_WUC 0x05800 /* Wakeup Control - RW */ | |
504 | #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ | |
505 | #define E1000_WUS 0x05810 /* Wakeup Status - RO */ | |
01a55482 | 506 | /* Management registers */ |
4be59a01 SZ |
507 | #define E1000_MANC 0x05820 /* Management Control - RW */ |
508 | #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ | |
509 | #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ | |
510 | #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ | |
511 | #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ | |
512 | #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ | |
513 | #define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ | |
514 | #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ | |
515 | #define E1000_HOST_IF 0x08800 /* Host Interface */ | |
4be59a01 SZ |
516 | #define E1000_HIBBA 0x8F40 /* Host Interface Buffer Base Address */ |
517 | /* Flexible Host Filter Table */ | |
518 | #define E1000_FHFT(_n) (0x09000 + ((_n) * 0x100)) | |
519 | /* Ext Flexible Host Filter Table */ | |
520 | #define E1000_FHFT_EXT(_n) (0x09A00 + ((_n) * 0x100)) | |
62583d18 | 521 | |
9c80d176 | 522 | |
4be59a01 | 523 | #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ |
4be59a01 SZ |
524 | #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ |
525 | /* Management Decision Filters */ | |
526 | #define E1000_MDEF(_n) (0x05890 + (4 * (_n))) | |
527 | #define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */ | |
528 | #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ | |
529 | #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ | |
530 | #define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ | |
01a55482 | 531 | /* PCIe Register Description */ |
4be59a01 SZ |
532 | #define E1000_GCR 0x05B00 /* PCI-Ex Control */ |
533 | #define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ | |
534 | #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ | |
535 | #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ | |
536 | #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ | |
537 | #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ | |
01a55482 SZ |
538 | /* Function Active and Power State to MNG */ |
539 | #define E1000_FACTPS 0x05B30 | |
4be59a01 SZ |
540 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ |
541 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ | |
542 | /* Driver-only SW semaphore (not used by BOOT agents) */ | |
543 | #define E1000_SWSM2 0x05B58 | |
544 | #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ | |
545 | #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ | |
546 | #define E1000_UFUSE 0x05B78 /* UFUSE - RO */ | |
547 | #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ | |
548 | #define E1000_HICR 0x08F00 /* Host Interface Control */ | |
549 | #define E1000_FWSTS 0x08F0C /* FW Status */ | |
9c80d176 SZ |
550 | |
551 | /* RSS registers */ | |
4be59a01 SZ |
552 | #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ |
553 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ | |
554 | #define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ | |
555 | #define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/ | |
556 | #define E1000_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */ | |
557 | #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */ | |
01a55482 SZ |
558 | /* Redirection Table - RW Array */ |
559 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) | |
560 | /* RSS Random Key - RW Array */ | |
561 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) | |
4be59a01 SZ |
562 | #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ |
563 | #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ | |
62583d18 | 564 | /* VT Registers */ |
4be59a01 SZ |
565 | #define E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */ |
566 | #define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */ | |
567 | #define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */ | |
568 | #define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */ | |
569 | #define E1000_VFRE 0x00C8C /* VF Receive Enables */ | |
570 | #define E1000_VFTE 0x00C90 /* VF Transmit Enables */ | |
571 | #define E1000_QDE 0x02408 /* Queue Drop Enable - RW */ | |
572 | #define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */ | |
573 | #define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */ | |
574 | #define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */ | |
575 | #define E1000_UTA 0x0A000 /* Unicast Table Array - RW */ | |
576 | #define E1000_IOVTCL 0x05BBC /* IOV Control Register */ | |
577 | #define E1000_VMRCTL 0X05D80 /* Virtual Mirror Rule Control */ | |
578 | #define E1000_VMRVLAN 0x05D90 /* Virtual Mirror Rule VLAN */ | |
579 | #define E1000_VMRVM 0x05DA0 /* Virtual Mirror Rule VM */ | |
580 | #define E1000_MDFB 0x03558 /* Malicious Driver free block */ | |
581 | #define E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */ | |
582 | #define E1000_TXSWC 0x05ACC /* Tx Switch Control */ | |
583 | #define E1000_SCCRL 0x05DB0 /* Storm Control Control */ | |
584 | #define E1000_BSCTRH 0x05DB8 /* Broadcast Storm Control Threshold */ | |
585 | #define E1000_MSCTRH 0x05DBC /* Multicast Storm Control Threshold */ | |
62583d18 | 586 | /* These act per VF so an array friendly macro is used */ |
4be59a01 SZ |
587 | #define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) |
588 | #define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n))) | |
589 | #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) | |
590 | #define E1000_VFVMBMEM(_n) (0x00800 + (_n)) | |
591 | #define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n))) | |
592 | /* VLAN Virtual Machine Filter - RW */ | |
593 | #define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) | |
594 | #define E1000_VMVIR(_n) (0x03700 + (4 * (_n))) | |
595 | #define E1000_DVMOLR(_n) (0x0C038 + (0x40 * (_n))) /* DMA VM offload */ | |
596 | #define E1000_VTCTRL(_n) (0x10000 + (0x100 * (_n))) /* VT Control */ | |
597 | #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ | |
598 | #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ | |
599 | #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */ | |
600 | #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ | |
601 | #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ | |
602 | #define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */ | |
603 | #define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */ | |
604 | #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ | |
605 | #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ | |
606 | #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ | |
607 | #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ | |
608 | #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ | |
609 | #define E1000_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */ | |
610 | #define E1000_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */ | |
611 | #define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */ | |
74dc3754 SZ |
612 | #define E1000_SYSSTMPL 0x0B648 /* HH Timesync system stamp low register */ |
613 | #define E1000_SYSSTMPH 0x0B64C /* HH Timesync system stamp hi register */ | |
614 | #define E1000_PLTSTMPL 0x0B640 /* HH Timesync platform stamp low register */ | |
615 | #define E1000_PLTSTMPH 0x0B644 /* HH Timesync platform stamp hi register */ | |
379ebbe7 SZ |
616 | #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ |
617 | #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ | |
4be59a01 SZ |
618 | #define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */ |
619 | #define E1000_TSICR 0x0B66C /* Interrupt Cause Register */ | |
620 | #define E1000_TSIM 0x0B674 /* Interrupt Mask Register */ | |
62583d18 SZ |
621 | |
622 | /* Filtering Registers */ | |
4be59a01 SZ |
623 | #define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ |
624 | #define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */ | |
625 | #define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */ | |
626 | #define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */ | |
627 | #define E1000_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */ | |
628 | #define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */ | |
629 | #define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */ | |
62583d18 | 630 | |
4be59a01 SZ |
631 | #define E1000_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */ |
632 | #define E1000_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */ | |
633 | #define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */ | |
634 | #define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */ | |
635 | #define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */ | |
636 | /* Tx Desc plane TC Rate-scheduler config */ | |
637 | #define E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4)) | |
638 | /* Tx Packet plane TC Rate-Scheduler Config */ | |
639 | #define E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4)) | |
640 | /* Rx Packet plane TC Rate-Scheduler Config */ | |
641 | #define E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4)) | |
642 | /* Tx Desc Plane TC Rate-Scheduler Status */ | |
643 | #define E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4)) | |
644 | /* Tx Desc Plane TC Rate-Scheduler MMW */ | |
645 | #define E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4)) | |
646 | /* Tx Packet plane TC Rate-Scheduler Status */ | |
647 | #define E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4)) | |
648 | /* Tx Packet plane TC Rate-scheduler MMW */ | |
649 | #define E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4)) | |
650 | /* Rx Packet plane TC Rate-Scheduler Status */ | |
651 | #define E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4)) | |
652 | /* Rx Packet plane TC Rate-Scheduler MMW */ | |
653 | #define E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4)) | |
654 | /* Tx Desc plane VM Rate-Scheduler MMW*/ | |
655 | #define E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4)) | |
656 | /* Tx BCN Rate-Scheduler MMW */ | |
657 | #define E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4)) | |
658 | #define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */ | |
659 | #define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */ | |
660 | #define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */ | |
661 | #define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */ | |
662 | #define E1000_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */ | |
663 | #define E1000_RTTBCNCR 0xB200 /* Tx BCN Control Register */ | |
664 | #define E1000_RTTBCNTG 0x35A4 /* Tx BCN Tagging */ | |
665 | #define E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */ | |
666 | #define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */ | |
667 | #define E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */ | |
668 | #define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */ | |
669 | #define E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */ | |
670 | #define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */ | |
671 | #define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */ | |
9c80d176 | 672 | |
6a5a645e | 673 | /* DMA Coalescing registers */ |
4be59a01 SZ |
674 | #define E1000_DMACR 0x02508 /* Control Register */ |
675 | #define E1000_DMCTXTH 0x03550 /* Transmit Threshold */ | |
676 | #define E1000_DMCTLX 0x02514 /* Time to Lx Request */ | |
677 | #define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */ | |
678 | #define E1000_DMCCNT 0x05DD4 /* Current Rx Count */ | |
679 | #define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */ | |
680 | #define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */ | |
6a5a645e SZ |
681 | |
682 | /* PCIe Parity Status Register */ | |
4be59a01 | 683 | #define E1000_PCIEERRSTS 0x05BA8 |
9c80d176 | 684 | |
4be59a01 SZ |
685 | #define E1000_PROXYS 0x5F64 /* Proxying Status */ |
686 | #define E1000_PROXYFC 0x5F60 /* Proxying Filter Control */ | |
62583d18 | 687 | /* Thermal sensor configuration and status registers */ |
4be59a01 SZ |
688 | #define E1000_THMJT 0x08100 /* Junction Temperature */ |
689 | #define E1000_THLOWTC 0x08104 /* Low Threshold Control */ | |
690 | #define E1000_THMIDTC 0x08108 /* Mid Threshold Control */ | |
691 | #define E1000_THHIGHTC 0x0810C /* High Threshold Control */ | |
692 | #define E1000_THSTAT 0x08110 /* Thermal Sensor Status */ | |
62583d18 | 693 | |
4be59a01 SZ |
694 | /* Energy Efficient Ethernet "EEE" registers */ |
695 | #define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */ | |
696 | #define E1000_LTRC 0x01A0 /* Latency Tolerance Reporting Control */ | |
697 | #define E1000_EEER 0x0E30 /* Energy Efficient Ethernet "EEE"*/ | |
698 | #define E1000_EEE_SU 0x0E34 /* EEE Setup */ | |
699 | #define E1000_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */ | |
700 | #define E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */ | |
62583d18 SZ |
701 | |
702 | /* OS2BMC Registers */ | |
4be59a01 SZ |
703 | #define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */ |
704 | #define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */ | |
705 | #define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ | |
706 | #define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ | |
707 | ||
708 | ||
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709 | |
710 | #endif |