projects / dragonfly.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
nrelease - fix/improve livecd
[dragonfly.git] / sys / dev / netif / re / if_revar.h
CommitLineData
5d686fbb
SZ		 1/*
2 * Copyright (c) 2004
3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 *
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
5d686fbb
SZ		 36 */
37
70be79a4
SZ		 38#define RE_RX_DESC_CNT_DEF 256
39#define RE_TX_DESC_CNT_DEF 256
53d4588a
SZ		 40#define RE_RX_DESC_CNT_MAX 1024
41#define RE_TX_DESC_CNT_MAX 1024
42
43#define RE_RX_LIST_SZ(sc) ((sc)->re_rx_desc_cnt * sizeof(struct re_desc))
44#define RE_TX_LIST_SZ(sc) ((sc)->re_tx_desc_cnt * sizeof(struct re_desc))
998e7079
SZ		 45#define RE_RING_ALIGN 256
46#define RE_IFQ_MAXLEN 512
47#define RE_MAXSEGS 16
6525b950 48#define RE_TXDESC_SPARE 5
a7d57e62 49#define RE_JBUF_COUNT(sc) (((sc)->re_rx_desc_cnt * 3) / 2)
998e7079 50
53d4588a
SZ		 51#define RE_RXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_rx_desc_cnt)
52#define RE_TXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_tx_desc_cnt)
998e7079 53#define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN)
e5a5a436 54#define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_GFRAGLEN)
998e7079
SZ		 55#define RE_PKTSZ(x) ((x)/* >> 3*/)
56
57#define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
58#define RE_ADDR_HI(y) ((uint64_t) (y) >> 32)
59
b0c15aad
SZ		 60#define RE_MTU_6K (6 * 1024)
61#define RE_MTU_9K (9 * 1024)
62
63#define RE_ETHER_EXTRA (ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN)
64#define RE_FRAMELEN(mtu) ((mtu) + RE_ETHER_EXTRA)
65
66#define RE_FRAMELEN_6K RE_FRAMELEN(RE_MTU_6K)
67#define RE_FRAMELEN_9K RE_FRAMELEN(RE_MTU_9K)
68#define RE_FRAMELEN_MAX RE_FRAMELEN_9K
69
adfa5aa6
SZ		 70#define RE_RXBUF_ALIGN 8
71#define RE_JBUF_SIZE roundup2(RE_FRAMELEN_MAX, RE_RXBUF_ALIGN)
a7d57e62 72
a7d57e62
SZ		 73struct re_softc;
74struct re_jbuf {
75 struct re_softc *re_sc;
76 int re_inuse;
77 int re_slot;
78 caddr_t re_buf;
79 bus_addr_t re_paddr;
80 SLIST_ENTRY(re_jbuf) re_link;
81};
82
5d686fbb 83struct re_list_data {
53d4588a
SZ		 84 struct mbuf **re_tx_mbuf;
85 struct mbuf **re_rx_mbuf;
86 bus_addr_t *re_rx_paddr;
5d686fbb
SZ		 87 int re_tx_prodidx;
88 int re_rx_prodidx;
89 int re_tx_considx;
90 int re_tx_free;
53d4588a
SZ		 91 bus_dmamap_t *re_tx_dmamap;
92 bus_dmamap_t *re_rx_dmamap;
3580fc56 93 bus_dmamap_t re_rx_spare;
8aaa1e58
SZ		 94 bus_dma_tag_t re_rx_mtag; /* RX mbuf mapping tag */
95 bus_dma_tag_t re_tx_mtag; /* TX mbuf mapping tag */
5d686fbb
SZ		 96 bus_dma_tag_t re_stag; /* stats mapping tag */
97 bus_dmamap_t re_smap; /* stats map */
98 struct re_stats *re_stats;
99 bus_addr_t re_stats_addr;
100 bus_dma_tag_t re_rx_list_tag;
101 bus_dmamap_t re_rx_list_map;
102 struct re_desc *re_rx_list;
103 bus_addr_t re_rx_list_addr;
104 bus_dma_tag_t re_tx_list_tag;
105 bus_dmamap_t re_tx_list_map;
106 struct re_desc *re_tx_list;
107 bus_addr_t re_tx_list_addr;
a7d57e62
SZ		 108
109 bus_dma_tag_t re_jpool_tag;
110 bus_dmamap_t re_jpool_map;
111 caddr_t re_jpool;
112 struct re_jbuf *re_jbuf;
113 struct lwkt_serialize re_jbuf_serializer;
114 SLIST_HEAD(, re_jbuf) re_jbuf_free;
5d686fbb
SZ		 115};
116
117struct re_softc {
118 struct arpcom arpcom; /* interface info */
e5a5a436 119 device_t dev;
5d686fbb
SZ		 120 bus_space_handle_t re_bhandle; /* bus space handle */
121 bus_space_tag_t re_btag; /* bus space tag */
d511b4cf
SZ		 122 int re_res_rid;
123 int re_res_type;
5d686fbb
SZ		 124 struct resource *re_res;
125 struct resource *re_irq;
126 void *re_intrhand;
5d686fbb
SZ		 127 bus_dma_tag_t re_parent_tag;
128 bus_dma_tag_t re_tag;
7816ba83 129 struct ifpoll_compat re_npoll;
5d686fbb 130 struct re_list_data re_ldata;
80492964 131 void (*re_start_xmit)(struct re_softc *);
5d686fbb
SZ		 132 struct callout re_timer;
133 struct mbuf *re_head;
134 struct mbuf *re_tail;
5bed1fbd 135 uint32_t re_caps; /* see RE_C_ */
53d4588a
SZ		 136 int re_rx_desc_cnt;
137 int re_tx_desc_cnt;
957a8760 138 int re_bus_speed;
5d686fbb 139 int rxcycles;
a7d57e62
SZ		 140 int re_rxbuf_size;
141 int (*re_newbuf)(struct re_softc *, int, int);
4dce912a
TB		 142 int re_irq_type;
143 int re_irq_rid;
5d686fbb 144
d4d77345 145 uint32_t re_flags; /* see RE_F_ */
e5a5a436 146 int re_saved_ifflags;
d4d77345 147
80492964
SZ		 148 void (*re_write_imr)(struct re_softc *, uint32_t);
149 void (*re_write_isr)(struct re_softc *, uint32_t);
150 uint32_t (*re_read_isr)(struct re_softc *);
151 uint32_t re_intrs;
5d686fbb 152 uint16_t re_tx_ack;
1bdb2a81 153 uint16_t re_rx_ack;
d4d77345
SZ		 154 int re_tx_time;
155 int re_rx_time;
156 int re_sim_time;
157 int re_imtype; /* see RE_IMTYPE_ */
5d686fbb 158
5d686fbb
SZ		 159 uint32_t saved_maps[5]; /* pci data */
160 uint32_t saved_biosaddr;
161 uint8_t saved_intline;
162 uint8_t saved_cachelnsz;
163 uint8_t saved_lattimer;
e5a5a436
SZ		 164
165 /*
166 * Used by Realtek re(4) backend.
167 */
168 int re_if_flags;
169 uint8_t re_type;
170 u_int16_t re_device_id;
171 u_int8_t re_hw_supp_now_is_oob_ver;
172 int max_jumbo_frame_size;
173 int re_rx_mbuf_sz;
174 u_int8_t RequireAdcBiasPatch;
175 u_int16_t AdcBiasPatchIoffset;
176 u_int16_t SwrCnt1msIni;
177 u_int8_t RequireAdjustUpsTxLinkPulseTiming;
178 u_int8_t re_hw_enable_msi_msix;
179 u_int8_t re_coalesce_tx_pkt;
52bafeb8 180 u_int8_t re_pad_runt;
e5a5a436
SZ		 181 u_int8_t re_8169_MacVersion;
182 u_int8_t re_8169_PhyVersion;
183 int re_tx_cstag;
184 int re_rx_cstag;
185 struct ifmedia media;
186 u_int16_t cur_page;
187 u_int8_t re_unit;
e6e07291
SZ		 188 u_int8_t re_efuse_ver;
189 u_int16_t re_sw_ram_code_ver;
190 u_int16_t re_hw_ram_code_ver;
191 u_int8_t RequiredSecLanDonglePatch;
192 u_int8_t HwSuppDashVer;
193 u_int8_t re_dash;
194 bus_space_handle_t re_mapped_cmac_handle; /* bus space tag */
195 bus_space_tag_t re_mapped_cmac_tag; /* bus space tag */
196 bus_space_handle_t re_cmac_handle; /* bus space handle */
197 bus_space_tag_t re_cmac_tag; /* bus space tag */
198 u_int8_t HwPkgDet;
80492964
SZ		 199 u_int8_t hw_hw_supp_serdes_phy_ver;
200 u_int8_t RequirePhyMdiSwapPatch;
201 u_int16_t phy_reg_anlpar;
5d686fbb
SZ		 202};
203
5bed1fbd 204#define RE_C_HWIM 0x4 /* hardware interrupt moderation */
a7d57e62 205#define RE_C_CONTIGRX 0x400 /* need contig buf to RX jumbo frames */
043ecbf0 206
d4d77345
SZ		 207/* Interrupt moderation types */
208#define RE_IMTYPE_NONE 0
209#define RE_IMTYPE_SIM 1 /* simulated */
210#define RE_IMTYPE_HW 2 /* hardware based */
211
212#define RE_F_TIMER_INTR 0x1
a7d57e62 213#define RE_F_USE_JPOOL 0x2
ffa3a109
SZ		 214#define RE_F_DROP_RXFRAG 0x4
215#define RE_F_LINKED 0x8
216#define RE_F_SUSPENDED 0x10
d4d77345 217
5d686fbb
SZ		 218/*
219 * register space access macros
220 */
221#define CSR_WRITE_STREAM_4(sc, reg, val) \
222 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)
223#define CSR_WRITE_4(sc, reg, val) \
224 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)
225#define CSR_WRITE_2(sc, reg, val) \
226 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)
227#define CSR_WRITE_1(sc, reg, val) \
228 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)
229
230#define CSR_READ_4(sc, reg) \
231 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)
232#define CSR_READ_2(sc, reg) \
233 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)
234#define CSR_READ_1(sc, reg) \
235 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)
236
237#define CSR_SETBIT_1(sc, reg, val) \
238 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val))
239#define CSR_CLRBIT_1(sc, reg, val) \
240 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))
DragonFly Project Source