| 1 | /* |
| 2 | * Copyright (c) 1997, Stefan Esser <se@freebsd.org> |
| 3 | * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> |
| 4 | * Copyright (c) 2000, BSDi |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice unmodified, this list of conditions, and the following |
| 12 | * disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | * $FreeBSD: src/sys/i386/isa/pci_cfgreg.c,v 1.1.2.7 2001/11/28 05:47:03 imp Exp $ |
| 29 | * $DragonFly: src/sys/bus/pci/i386/pci_cfgreg.c,v 1.15 2008/08/02 05:22:20 dillon Exp $ |
| 30 | * |
| 31 | */ |
| 32 | |
| 33 | #include <sys/param.h> /* XXX trim includes */ |
| 34 | #include <sys/systm.h> |
| 35 | #include <sys/bus.h> |
| 36 | #include <sys/kernel.h> |
| 37 | #include <sys/module.h> |
| 38 | #include <sys/malloc.h> |
| 39 | #include <sys/sysctl.h> |
| 40 | #include <vm/vm.h> |
| 41 | #include <vm/pmap.h> |
| 42 | #include <machine/md_var.h> |
| 43 | #include <machine/clock.h> |
| 44 | #include <bus/pci/pcivar.h> |
| 45 | #include <bus/pci/pcireg.h> |
| 46 | #include <bus/isa/isavar.h> |
| 47 | #include "pci_cfgreg.h" |
| 48 | #include <machine/segments.h> |
| 49 | #include <machine/pc/bios.h> |
| 50 | #include <machine/smp.h> |
| 51 | |
| 52 | #define PRVERB(a) do { \ |
| 53 | if (bootverbose) \ |
| 54 | kprintf a ; \ |
| 55 | } while(0) |
| 56 | |
| 57 | static int pci_disable_bios_route = 0; |
| 58 | SYSCTL_INT(_hw, OID_AUTO, pci_disable_bios_route, CTLFLAG_RD, |
| 59 | &pci_disable_bios_route, 0, "disable interrupt routing via PCI-BIOS"); |
| 60 | TUNABLE_INT("hw.pci_disable_bios_route", &pci_disable_bios_route); |
| 61 | |
| 62 | static int cfgmech; |
| 63 | static int devmax; |
| 64 | |
| 65 | static int pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq); |
| 66 | static int pci_cfgintr_unique(struct PIR_entry *pe, int pin); |
| 67 | static int pci_cfgintr_linked(struct PIR_entry *pe, int pin); |
| 68 | static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin); |
| 69 | static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin); |
| 70 | |
| 71 | static void pci_print_irqmask(u_int16_t irqs); |
| 72 | static void pci_print_route_table(struct PIR_table *prt, int size); |
| 73 | static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); |
| 74 | static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); |
| 75 | static int pcireg_cfgopen(void); |
| 76 | |
| 77 | static struct PIR_table *pci_route_table; |
| 78 | static int pci_route_count; |
| 79 | |
| 80 | /* |
| 81 | * Some BIOS writers seem to want to ignore the spec and put |
| 82 | * 0 in the intline rather than 255 to indicate none. Some use |
| 83 | * numbers in the range 128-254 to indicate something strange and |
| 84 | * apparently undocumented anywhere. Assume these are completely bogus |
| 85 | * and map them to 255, which means "none". |
| 86 | */ |
| 87 | static int |
| 88 | pci_map_intline(int line) |
| 89 | { |
| 90 | if (line == 0 || line >= 128) |
| 91 | return (PCI_INVALID_IRQ); |
| 92 | return (line); |
| 93 | } |
| 94 | |
| 95 | static u_int16_t |
| 96 | pcibios_get_version(void) |
| 97 | { |
| 98 | struct bios_regs args; |
| 99 | |
| 100 | if (PCIbios.ventry == 0) { |
| 101 | PRVERB(("pcibios: No call entry point\n")); |
| 102 | return (0); |
| 103 | } |
| 104 | args.eax = PCIBIOS_BIOS_PRESENT; |
| 105 | if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) { |
| 106 | PRVERB(("pcibios: BIOS_PRESENT call failed\n")); |
| 107 | return (0); |
| 108 | } |
| 109 | if (args.edx != 0x20494350) { |
| 110 | PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n")); |
| 111 | return (0); |
| 112 | } |
| 113 | return (args.ebx & 0xffff); |
| 114 | } |
| 115 | |
| 116 | /* |
| 117 | * Initialise access to PCI configuration space |
| 118 | */ |
| 119 | int |
| 120 | pci_cfgregopen(void) |
| 121 | { |
| 122 | static int opened = 0; |
| 123 | u_long sigaddr; |
| 124 | static struct PIR_table *pt; |
| 125 | u_int16_t v; |
| 126 | u_int8_t ck, *cv; |
| 127 | int i; |
| 128 | |
| 129 | if (opened) |
| 130 | return (1); |
| 131 | |
| 132 | if (pcireg_cfgopen() == 0) |
| 133 | return (0); |
| 134 | |
| 135 | v = pcibios_get_version(); |
| 136 | if (v > 0) |
| 137 | kprintf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8, |
| 138 | v & 0xff); |
| 139 | |
| 140 | /* |
| 141 | * Look for the interrupt routing table. |
| 142 | * |
| 143 | * We use PCI BIOS's PIR table if it's available $PIR is the |
| 144 | * standard way to do this. Sadly some machines are not |
| 145 | * standards conforming and have _PIR instead. We shrug and cope |
| 146 | * by looking for both. |
| 147 | */ |
| 148 | if (pcibios_get_version() >= 0x0210 && pt == NULL) { |
| 149 | sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0); |
| 150 | if (sigaddr == 0) |
| 151 | sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0); |
| 152 | if (sigaddr != 0) { |
| 153 | pt = (struct PIR_table *)(uintptr_t) |
| 154 | BIOS_PADDRTOVADDR(sigaddr); |
| 155 | for (cv = (u_int8_t *)pt, ck = 0, i = 0; |
| 156 | i < (pt->pt_header.ph_length); i++) |
| 157 | ck += cv[i]; |
| 158 | if (ck == 0 && pt->pt_header.ph_length > |
| 159 | sizeof(struct PIR_header)) { |
| 160 | pci_route_table = pt; |
| 161 | pci_route_count = (pt->pt_header.ph_length - |
| 162 | sizeof(struct PIR_header)) / |
| 163 | sizeof(struct PIR_entry); |
| 164 | kprintf("Using $PIR table, %d entries at %p\n", |
| 165 | pci_route_count, pci_route_table); |
| 166 | if (bootverbose) |
| 167 | pci_print_route_table(pci_route_table, |
| 168 | pci_route_count); |
| 169 | } |
| 170 | } |
| 171 | } |
| 172 | opened = 1; |
| 173 | return (1); |
| 174 | } |
| 175 | |
| 176 | /* |
| 177 | * Read configuration space register |
| 178 | */ |
| 179 | u_int32_t |
| 180 | pci_cfgregread(int bus, int slot, int func, int reg, int bytes) |
| 181 | { |
| 182 | uint32_t line; |
| 183 | #ifdef APIC_IO |
| 184 | uint32_t pin; |
| 185 | |
| 186 | /* |
| 187 | * If we are using the APIC, the contents of the intline |
| 188 | * register will probably be wrong (since they are set up for |
| 189 | * use with the PIC. Rather than rewrite these registers |
| 190 | * (maybe that would be smarter) we trap attempts to read them |
| 191 | * and translate to our private vector numbers. |
| 192 | */ |
| 193 | if ((reg == PCIR_INTLINE) && (bytes == 1)) { |
| 194 | |
| 195 | pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1); |
| 196 | line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1); |
| 197 | |
| 198 | if (pin != 0) { |
| 199 | int airq; |
| 200 | |
| 201 | airq = pci_apic_irq(bus, slot, pin); |
| 202 | if (airq >= 0) { |
| 203 | /* PCI specific entry found in MP table */ |
| 204 | if (airq != line) |
| 205 | undirect_pci_irq(line); |
| 206 | return (airq); |
| 207 | } else { |
| 208 | /* |
| 209 | * PCI interrupts might be redirected to the |
| 210 | * ISA bus according to some MP tables. Use the |
| 211 | * same methods as used by the ISA devices |
| 212 | * devices to find the proper IOAPIC int pin. |
| 213 | */ |
| 214 | airq = isa_apic_irq(line); |
| 215 | if ((airq >= 0) && (airq != line)) { |
| 216 | /* XXX: undirect_pci_irq() ? */ |
| 217 | undirect_isa_irq(line); |
| 218 | return (airq); |
| 219 | } |
| 220 | } |
| 221 | } |
| 222 | return (line); |
| 223 | } |
| 224 | #else |
| 225 | /* |
| 226 | * Some BIOS writers seem to want to ignore the spec and put |
| 227 | * 0 in the intline rather than 255 to indicate none. The rest of |
| 228 | * the code uses 255 as an invalid IRQ. |
| 229 | */ |
| 230 | if (reg == PCIR_INTLINE && bytes == 1) { |
| 231 | line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1); |
| 232 | return pci_map_intline(line); |
| 233 | } |
| 234 | #endif /* APIC_IO */ |
| 235 | return (pcireg_cfgread(bus, slot, func, reg, bytes)); |
| 236 | } |
| 237 | |
| 238 | /* |
| 239 | * Write configuration space register |
| 240 | */ |
| 241 | void |
| 242 | pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) |
| 243 | { |
| 244 | pcireg_cfgwrite(bus, slot, func, reg, data, bytes); |
| 245 | } |
| 246 | |
| 247 | int |
| 248 | pci_cfgread(pcicfgregs *cfg, int reg, int bytes) |
| 249 | { |
| 250 | return (pci_cfgregread(cfg->bus, cfg->slot, cfg->func, reg, bytes)); |
| 251 | } |
| 252 | |
| 253 | void |
| 254 | pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes) |
| 255 | { |
| 256 | pci_cfgregwrite(cfg->bus, cfg->slot, cfg->func, reg, data, bytes); |
| 257 | } |
| 258 | |
| 259 | |
| 260 | /* |
| 261 | * Route a PCI interrupt |
| 262 | */ |
| 263 | int |
| 264 | pci_cfgintr(int bus, int device, int pin, int oldirq) |
| 265 | { |
| 266 | struct PIR_entry *pe; |
| 267 | int i, irq; |
| 268 | struct bios_regs args; |
| 269 | u_int16_t v; |
| 270 | |
| 271 | int already = 0; |
| 272 | int errok = 0; |
| 273 | |
| 274 | v = pcibios_get_version(); |
| 275 | if (v < 0x0210) { |
| 276 | PRVERB(( |
| 277 | "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n", |
| 278 | (v & 0xff00) >> 8, v & 0xff)); |
| 279 | return (PCI_INVALID_IRQ); |
| 280 | } |
| 281 | if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) || |
| 282 | (pin < 1) || (pin > 4)) |
| 283 | return (PCI_INVALID_IRQ); |
| 284 | |
| 285 | /* |
| 286 | * Scan the entry table for a contender |
| 287 | */ |
| 288 | for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count; |
| 289 | i++, pe++) { |
| 290 | if ((bus != pe->pe_bus) || (device != pe->pe_device)) |
| 291 | continue; |
| 292 | |
| 293 | /* |
| 294 | * A link of 0 means that this intpin is not connected to |
| 295 | * any other device's interrupt pins and is not connected to |
| 296 | * any of the Interrupt Router's interrupt pins, so we can't |
| 297 | * route it. |
| 298 | */ |
| 299 | if (pe->pe_intpin[pin - 1].link == 0) |
| 300 | continue; |
| 301 | |
| 302 | if (pci_cfgintr_valid(pe, pin, oldirq)) { |
| 303 | kprintf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus, |
| 304 | device, 'A' + pin - 1, oldirq); |
| 305 | return (oldirq); |
| 306 | } |
| 307 | |
| 308 | /* |
| 309 | * We try to find a linked interrupt, then we look to see |
| 310 | * if the interrupt is uniquely routed, then we look for |
| 311 | * a virgin interrupt. The virgin interrupt should return |
| 312 | * an interrupt we can route, but if that fails, maybe we |
| 313 | * should try harder to route a different interrupt. |
| 314 | * However, experience has shown that that's rarely the |
| 315 | * failure mode we see. |
| 316 | */ |
| 317 | irq = pci_cfgintr_linked(pe, pin); |
| 318 | if (irq != PCI_INVALID_IRQ) |
| 319 | already = 1; |
| 320 | if (irq == PCI_INVALID_IRQ) { |
| 321 | irq = pci_cfgintr_unique(pe, pin); |
| 322 | if (irq != PCI_INVALID_IRQ) |
| 323 | errok = 1; |
| 324 | } |
| 325 | if (irq == PCI_INVALID_IRQ) |
| 326 | irq = pci_cfgintr_virgin(pe, pin); |
| 327 | |
| 328 | if (irq == PCI_INVALID_IRQ) |
| 329 | break; |
| 330 | |
| 331 | if (pci_disable_bios_route != 0) |
| 332 | break; |
| 333 | /* |
| 334 | * Ask the BIOS to route the interrupt. If we picked an |
| 335 | * interrupt that failed, we should really try other |
| 336 | * choices that the BIOS offers us. |
| 337 | * |
| 338 | * For uniquely routed interrupts, we need to try |
| 339 | * to route them on some machines. Yet other machines |
| 340 | * fail to route, so we have to pretend that in that |
| 341 | * case it worked. Isn't PC hardware fun? |
| 342 | * |
| 343 | * NOTE: if we want to whack hardware to do this, then |
| 344 | * I think the right way to do that would be to have |
| 345 | * bridge drivers that do this. I'm not sure that the |
| 346 | * $PIR table would be valid for those interrupt |
| 347 | * routers. |
| 348 | */ |
| 349 | args.eax = PCIBIOS_ROUTE_INTERRUPT; |
| 350 | args.ebx = (bus << 8) | (device << 3); |
| 351 | /* pin value is 0xa - 0xd */ |
| 352 | args.ecx = (irq << 8) | (0xa + pin -1); |
| 353 | if (!already && |
| 354 | bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)) && |
| 355 | !errok) { |
| 356 | PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n")); |
| 357 | return (PCI_INVALID_IRQ); |
| 358 | } |
| 359 | kprintf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus, |
| 360 | device, 'A' + pin - 1, irq); |
| 361 | return(irq); |
| 362 | } |
| 363 | |
| 364 | PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c oldirq=%d\n", bus, |
| 365 | device, 'A' + pin - 1, oldirq)); |
| 366 | return (PCI_INVALID_IRQ); |
| 367 | } |
| 368 | |
| 369 | /* |
| 370 | * Check to see if an existing IRQ setting is valid. |
| 371 | */ |
| 372 | static int |
| 373 | pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq) |
| 374 | { |
| 375 | uint32_t irqmask; |
| 376 | |
| 377 | if (!PCI_INTERRUPT_VALID(irq)) |
| 378 | return (0); |
| 379 | irqmask = pe->pe_intpin[pin - 1].irqs; |
| 380 | if (irqmask & (1 << irq)) { |
| 381 | PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq)); |
| 382 | return (1); |
| 383 | } |
| 384 | return (0); |
| 385 | } |
| 386 | |
| 387 | /* |
| 388 | * Look to see if the routing table claims this pin is uniquely routed. |
| 389 | */ |
| 390 | static int |
| 391 | pci_cfgintr_unique(struct PIR_entry *pe, int pin) |
| 392 | { |
| 393 | int irq; |
| 394 | uint32_t irqmask; |
| 395 | |
| 396 | irqmask = pe->pe_intpin[pin - 1].irqs; |
| 397 | if(irqmask != 0 && powerof2(irqmask)) { |
| 398 | irq = ffs(irqmask) - 1; |
| 399 | PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq)); |
| 400 | return (irq); |
| 401 | } |
| 402 | return (PCI_INVALID_IRQ); |
| 403 | } |
| 404 | |
| 405 | /* |
| 406 | * Look for another device which shares the same link byte and |
| 407 | * already has a unique IRQ, or which has had one routed already. |
| 408 | */ |
| 409 | static int |
| 410 | pci_cfgintr_linked(struct PIR_entry *pe, int pin) |
| 411 | { |
| 412 | struct PIR_entry *oe; |
| 413 | struct PIR_intpin *pi; |
| 414 | int i, j, irq; |
| 415 | |
| 416 | /* |
| 417 | * Scan table slots. |
| 418 | */ |
| 419 | for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count; |
| 420 | i++, oe++) { |
| 421 | /* scan interrupt pins */ |
| 422 | for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) { |
| 423 | |
| 424 | /* don't look at the entry we're trying to match */ |
| 425 | if ((pe == oe) && (j == (pin - 1))) |
| 426 | continue; |
| 427 | /* compare link bytes */ |
| 428 | if (pi->link != pe->pe_intpin[pin - 1].link) |
| 429 | continue; |
| 430 | /* link destination mapped to a unique interrupt? */ |
| 431 | if (pi->irqs != 0 && powerof2(pi->irqs)) { |
| 432 | irq = ffs(pi->irqs) - 1; |
| 433 | PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n", |
| 434 | pi->link, irq)); |
| 435 | return(irq); |
| 436 | } |
| 437 | |
| 438 | /* |
| 439 | * look for the real PCI device that matches this |
| 440 | * table entry |
| 441 | */ |
| 442 | irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device, |
| 443 | j + 1, pin); |
| 444 | if (irq != PCI_INVALID_IRQ) |
| 445 | return (irq); |
| 446 | } |
| 447 | } |
| 448 | return (PCI_INVALID_IRQ); |
| 449 | } |
| 450 | |
| 451 | /* |
| 452 | * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and |
| 453 | * see if it has already been assigned an interrupt. |
| 454 | */ |
| 455 | static int |
| 456 | pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin) |
| 457 | { |
| 458 | devclass_t pci_devclass; |
| 459 | device_t *pci_devices; |
| 460 | int pci_count; |
| 461 | device_t *pci_children; |
| 462 | int pci_childcount; |
| 463 | device_t *busp, *childp; |
| 464 | int i, j, irq; |
| 465 | |
| 466 | /* |
| 467 | * Find all the PCI busses. |
| 468 | */ |
| 469 | pci_count = 0; |
| 470 | if ((pci_devclass = devclass_find("pci")) != NULL) |
| 471 | devclass_get_devices(pci_devclass, &pci_devices, &pci_count); |
| 472 | |
| 473 | /* |
| 474 | * Scan all the PCI busses/devices looking for this one. |
| 475 | */ |
| 476 | irq = PCI_INVALID_IRQ; |
| 477 | for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ); |
| 478 | i++, busp++) { |
| 479 | pci_childcount = 0; |
| 480 | device_get_children(*busp, &pci_children, &pci_childcount); |
| 481 | |
| 482 | for (j = 0, childp = pci_children; j < pci_childcount; j++, |
| 483 | childp++) { |
| 484 | if ((pci_get_bus(*childp) == bus) && |
| 485 | (pci_get_slot(*childp) == device) && |
| 486 | (pci_get_intpin(*childp) == matchpin)) { |
| 487 | irq = pci_map_intline(pci_get_irq(*childp)); |
| 488 | if (irq != PCI_INVALID_IRQ) |
| 489 | PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n", |
| 490 | pe->pe_intpin[pin - 1].link, irq, |
| 491 | pci_get_bus(*childp), |
| 492 | pci_get_slot(*childp), |
| 493 | pci_get_function(*childp))); |
| 494 | break; |
| 495 | } |
| 496 | } |
| 497 | if (pci_children != NULL) |
| 498 | kfree(pci_children, M_TEMP); |
| 499 | } |
| 500 | if (pci_devices != NULL) |
| 501 | kfree(pci_devices, M_TEMP); |
| 502 | return (irq); |
| 503 | } |
| 504 | |
| 505 | /* |
| 506 | * Pick a suitable IRQ from those listed as routable to this device. |
| 507 | */ |
| 508 | static int |
| 509 | pci_cfgintr_virgin(struct PIR_entry *pe, int pin) |
| 510 | { |
| 511 | int irq, ibit; |
| 512 | |
| 513 | /* |
| 514 | * first scan the set of PCI-only interrupts and see if any of these |
| 515 | * are routable |
| 516 | */ |
| 517 | for (irq = 0; irq < 16; irq++) { |
| 518 | ibit = (1 << irq); |
| 519 | |
| 520 | /* can we use this interrupt? */ |
| 521 | if ((pci_route_table->pt_header.ph_pci_irqs & ibit) && |
| 522 | (pe->pe_intpin[pin - 1].irqs & ibit)) { |
| 523 | PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq)); |
| 524 | return (irq); |
| 525 | } |
| 526 | } |
| 527 | |
| 528 | /* life is tough, so just pick an interrupt */ |
| 529 | for (irq = 0; irq < 16; irq++) { |
| 530 | ibit = (1 << irq); |
| 531 | |
| 532 | if (pe->pe_intpin[pin - 1].irqs & ibit) { |
| 533 | PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq)); |
| 534 | return (irq); |
| 535 | } |
| 536 | } |
| 537 | return (PCI_INVALID_IRQ); |
| 538 | } |
| 539 | |
| 540 | static void |
| 541 | pci_print_irqmask(u_int16_t irqs) |
| 542 | { |
| 543 | int i, first; |
| 544 | |
| 545 | if (irqs == 0) { |
| 546 | kprintf("none"); |
| 547 | return; |
| 548 | } |
| 549 | first = 1; |
| 550 | for (i = 0; i < 16; i++, irqs >>= 1) |
| 551 | if (irqs & 1) { |
| 552 | if (!first) |
| 553 | kprintf(" "); |
| 554 | else |
| 555 | first = 0; |
| 556 | kprintf("%d", i); |
| 557 | } |
| 558 | } |
| 559 | |
| 560 | /* |
| 561 | * Dump the contents of a PCI BIOS Interrupt Routing Table to the console. |
| 562 | */ |
| 563 | static void |
| 564 | pci_print_route_table(struct PIR_table *ptr, int size) |
| 565 | { |
| 566 | struct PIR_entry *entry; |
| 567 | struct PIR_intpin *intpin; |
| 568 | int i, pin; |
| 569 | |
| 570 | kprintf("PCI-Only Interrupts: "); |
| 571 | pci_print_irqmask(ptr->pt_header.ph_pci_irqs); |
| 572 | kprintf("\nLocation Bus Device Pin Link IRQs\n"); |
| 573 | entry = &ptr->pt_entry[0]; |
| 574 | for (i = 0; i < size; i++, entry++) { |
| 575 | intpin = &entry->pe_intpin[0]; |
| 576 | for (pin = 0; pin < 4; pin++, intpin++) |
| 577 | if (intpin->link != 0) { |
| 578 | if (entry->pe_slot == 0) |
| 579 | kprintf("embedded "); |
| 580 | else |
| 581 | kprintf("slot %-3d ", entry->pe_slot); |
| 582 | kprintf(" %3d %3d %c 0x%02x ", |
| 583 | entry->pe_bus, entry->pe_device, |
| 584 | 'A' + pin, intpin->link); |
| 585 | pci_print_irqmask(intpin->irqs); |
| 586 | kprintf("\n"); |
| 587 | } |
| 588 | } |
| 589 | } |
| 590 | |
| 591 | /* |
| 592 | * See if any interrupts for a given PCI bus are routed in the PIR. Don't |
| 593 | * even bother looking if the BIOS doesn't support routing anyways. |
| 594 | */ |
| 595 | int |
| 596 | pci_probe_route_table(int bus) |
| 597 | { |
| 598 | int i; |
| 599 | u_int16_t v; |
| 600 | |
| 601 | v = pcibios_get_version(); |
| 602 | if (v < 0x0210) |
| 603 | return (0); |
| 604 | for (i = 0; i < pci_route_count; i++) |
| 605 | if (pci_route_table->pt_entry[i].pe_bus == bus) |
| 606 | return (1); |
| 607 | return (0); |
| 608 | } |
| 609 | |
| 610 | /* |
| 611 | * Configuration space access using direct register operations |
| 612 | */ |
| 613 | |
| 614 | /* enable configuration space accesses and return data port address */ |
| 615 | static int |
| 616 | pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes) |
| 617 | { |
| 618 | int dataport = 0; |
| 619 | |
| 620 | if (bus <= PCI_BUSMAX |
| 621 | && slot < devmax |
| 622 | && func <= PCI_FUNCMAX |
| 623 | && reg <= PCI_REGMAX |
| 624 | && bytes != 3 |
| 625 | && (unsigned) bytes <= 4 |
| 626 | && (reg & (bytes - 1)) == 0) { |
| 627 | switch (cfgmech) { |
| 628 | case 1: |
| 629 | outl(CONF1_ADDR_PORT, (1 << 31) |
| 630 | | (bus << 16) | (slot << 11) |
| 631 | | (func << 8) | (reg & ~0x03)); |
| 632 | dataport = CONF1_DATA_PORT + (reg & 0x03); |
| 633 | break; |
| 634 | case 2: |
| 635 | outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1)); |
| 636 | outb(CONF2_FORWARD_PORT, bus); |
| 637 | dataport = 0xc000 | (slot << 8) | reg; |
| 638 | break; |
| 639 | } |
| 640 | } |
| 641 | return (dataport); |
| 642 | } |
| 643 | |
| 644 | /* disable configuration space accesses */ |
| 645 | static void |
| 646 | pci_cfgdisable(void) |
| 647 | { |
| 648 | switch (cfgmech) { |
| 649 | case 1: |
| 650 | outl(CONF1_ADDR_PORT, 0); |
| 651 | break; |
| 652 | case 2: |
| 653 | outb(CONF2_ENABLE_PORT, 0); |
| 654 | outb(CONF2_FORWARD_PORT, 0); |
| 655 | break; |
| 656 | } |
| 657 | } |
| 658 | |
| 659 | static int |
| 660 | pcireg_cfgread(int bus, int slot, int func, int reg, int bytes) |
| 661 | { |
| 662 | int data = -1; |
| 663 | int port; |
| 664 | |
| 665 | port = pci_cfgenable(bus, slot, func, reg, bytes); |
| 666 | if (port != 0) { |
| 667 | switch (bytes) { |
| 668 | case 1: |
| 669 | data = inb(port); |
| 670 | break; |
| 671 | case 2: |
| 672 | data = inw(port); |
| 673 | break; |
| 674 | case 4: |
| 675 | data = inl(port); |
| 676 | break; |
| 677 | } |
| 678 | pci_cfgdisable(); |
| 679 | } |
| 680 | return (data); |
| 681 | } |
| 682 | |
| 683 | static void |
| 684 | pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) |
| 685 | { |
| 686 | int port; |
| 687 | |
| 688 | port = pci_cfgenable(bus, slot, func, reg, bytes); |
| 689 | if (port != 0) { |
| 690 | switch (bytes) { |
| 691 | case 1: |
| 692 | outb(port, data); |
| 693 | break; |
| 694 | case 2: |
| 695 | outw(port, data); |
| 696 | break; |
| 697 | case 4: |
| 698 | outl(port, data); |
| 699 | break; |
| 700 | } |
| 701 | pci_cfgdisable(); |
| 702 | } |
| 703 | } |
| 704 | |
| 705 | /* check whether the configuration mechanism has been correctly identified */ |
| 706 | static int |
| 707 | pci_cfgcheck(int maxdev) |
| 708 | { |
| 709 | uint32_t id, class; |
| 710 | uint8_t header; |
| 711 | uint8_t device; |
| 712 | int port; |
| 713 | |
| 714 | if (bootverbose) |
| 715 | kprintf("pci_cfgcheck:\tdevice "); |
| 716 | |
| 717 | for (device = 0; device < maxdev; device++) { |
| 718 | if (bootverbose) |
| 719 | kprintf("%d ", device); |
| 720 | |
| 721 | port = pci_cfgenable(0, device, 0, 0, 4); |
| 722 | id = inl(port); |
| 723 | if (id == 0 || id == 0xffffffff) |
| 724 | continue; |
| 725 | |
| 726 | port = pci_cfgenable(0, device, 0, 8, 4); |
| 727 | class = inl(port) >> 8; |
| 728 | if (bootverbose) |
| 729 | kprintf("[class=%06x] ", class); |
| 730 | if (class == 0 || (class & 0xf870ff) != 0) |
| 731 | continue; |
| 732 | |
| 733 | port = pci_cfgenable(0, device, 0, 14, 1); |
| 734 | header = inb(port); |
| 735 | if (bootverbose) |
| 736 | kprintf("[hdr=%02x] ", header); |
| 737 | if ((header & 0x7e) != 0) |
| 738 | continue; |
| 739 | |
| 740 | if (bootverbose) |
| 741 | kprintf("is there (id=%08x)\n", id); |
| 742 | |
| 743 | pci_cfgdisable(); |
| 744 | return (1); |
| 745 | } |
| 746 | if (bootverbose) |
| 747 | kprintf("-- nothing found\n"); |
| 748 | |
| 749 | pci_cfgdisable(); |
| 750 | return (0); |
| 751 | } |
| 752 | |
| 753 | static int |
| 754 | pcireg_cfgopen(void) |
| 755 | { |
| 756 | uint32_t mode1res,oldval1; |
| 757 | uint8_t mode2res,oldval2; |
| 758 | |
| 759 | oldval1 = inl(CONF1_ADDR_PORT); |
| 760 | |
| 761 | if (bootverbose) { |
| 762 | kprintf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n", |
| 763 | oldval1); |
| 764 | } |
| 765 | |
| 766 | if ((oldval1 & CONF1_ENABLE_MSK) == 0) { |
| 767 | |
| 768 | cfgmech = 1; |
| 769 | devmax = 32; |
| 770 | |
| 771 | outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK); |
| 772 | DELAY(1); |
| 773 | mode1res = inl(CONF1_ADDR_PORT); |
| 774 | outl(CONF1_ADDR_PORT, oldval1); |
| 775 | |
| 776 | if (bootverbose) |
| 777 | kprintf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", |
| 778 | mode1res, CONF1_ENABLE_CHK); |
| 779 | |
| 780 | if (mode1res) { |
| 781 | if (pci_cfgcheck(32)) |
| 782 | return (cfgmech); |
| 783 | } |
| 784 | |
| 785 | outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1); |
| 786 | mode1res = inl(CONF1_ADDR_PORT); |
| 787 | outl(CONF1_ADDR_PORT, oldval1); |
| 788 | |
| 789 | if (bootverbose) |
| 790 | kprintf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", |
| 791 | mode1res, CONF1_ENABLE_CHK1); |
| 792 | |
| 793 | if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) { |
| 794 | if (pci_cfgcheck(32)) |
| 795 | return (cfgmech); |
| 796 | } |
| 797 | } |
| 798 | |
| 799 | oldval2 = inb(CONF2_ENABLE_PORT); |
| 800 | |
| 801 | if (bootverbose) { |
| 802 | kprintf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n", |
| 803 | oldval2); |
| 804 | } |
| 805 | |
| 806 | if ((oldval2 & 0xf0) == 0) { |
| 807 | |
| 808 | cfgmech = 2; |
| 809 | devmax = 16; |
| 810 | |
| 811 | outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK); |
| 812 | mode2res = inb(CONF2_ENABLE_PORT); |
| 813 | outb(CONF2_ENABLE_PORT, oldval2); |
| 814 | |
| 815 | if (bootverbose) |
| 816 | kprintf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n", |
| 817 | mode2res, CONF2_ENABLE_CHK); |
| 818 | |
| 819 | if (mode2res == CONF2_ENABLE_RES) { |
| 820 | if (bootverbose) |
| 821 | kprintf("pci_open(2a):\tnow trying mechanism 2\n"); |
| 822 | |
| 823 | if (pci_cfgcheck(16)) |
| 824 | return (cfgmech); |
| 825 | } |
| 826 | } |
| 827 | |
| 828 | cfgmech = 0; |
| 829 | devmax = 0; |
| 830 | return (cfgmech); |
| 831 | } |