2 * Copyright (c) 1993 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $FreeBSD: src/sys/i386/include/cpufunc.h,v 1.96.2.3 2002/04/28 22:50:54 dwmalone Exp $
34 * $DragonFly: src/sys/cpu/i386/include/cpufunc.h,v 1.21 2007/04/27 23:23:59 dillon Exp $
38 * Functions to provide access to special i386 instructions.
41 #ifndef _CPU_CPUFUNC_H_
42 #define _CPU_CPUFUNC_H_
45 #include <sys/types.h>
48 #include <sys/cdefs.h>
52 #define readb(va) (*(volatile u_int8_t *) (va))
53 #define readw(va) (*(volatile u_int16_t *) (va))
54 #define readl(va) (*(volatile u_int32_t *) (va))
56 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
57 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
58 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
63 #include <machine/lock.h> /* XXX */
66 #ifdef SWTCH_OPTIM_STATS
67 extern int tlb_flush_count; /* XXX */
73 __asm __volatile("int $3");
79 __asm __volatile("pause");
83 * Find the first 1 in mask, starting with bit 0 and return the
84 * bit number. If mask is 0 the result is undefined.
91 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
96 * Find the last 1 in mask, starting with bit 31 and return the
97 * bit number. If mask is 0 the result is undefined.
104 __asm __volatile("bsrl %0,%0" : "=r" (result) : "0" (mask));
109 * Test and set the specified bit (1 << bit) in the integer. The
110 * previous value of the bit is returned (0 or 1).
113 btsl(u_int *mask, int bit)
117 __asm __volatile("btsl %2,%1; movl $0,%0; adcl $0,%0" :
118 "=r"(result), "=m"(*mask) : "r" (bit));
123 * Test and clear the specified bit (1 << bit) in the integer. The
124 * previous value of the bit is returned (0 or 1).
127 btrl(u_int *mask, int bit)
131 __asm __volatile("btrl %2,%1; movl $0,%0; adcl $0,%0" :
132 "=r"(result), "=m"(*mask) : "r" (bit));
137 do_cpuid(u_int ax, u_int *p)
139 __asm __volatile("cpuid"
140 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
145 cpuid_count(u_int ax, u_int cx, u_int *p)
147 __asm __volatile("cpuid"
148 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
149 : "0" (ax), "c" (cx));
152 #ifndef _CPU_DISABLE_INTR_DEFINED
155 cpu_disable_intr(void)
157 __asm __volatile("cli" : : : "memory");
162 #ifndef _CPU_ENABLE_INTR_DEFINED
165 cpu_enable_intr(void)
167 __asm __volatile("sti");
173 * Cpu and compiler memory ordering fence. mfence ensures strong read and
176 * A serializing or fence instruction is required here. A locked bus
177 * cycle on data for which we already own cache mastership is the most
185 __asm __volatile("mfence" : : : "memory");
187 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
190 __asm __volatile("" : : : "memory");
195 * cpu_lfence() ensures strong read ordering for reads issued prior
196 * to the instruction verses reads issued afterwords.
198 * A serializing or fence instruction is required here. A locked bus
199 * cycle on data for which we already own cache mastership is the most
207 __asm __volatile("lfence" : : : "memory");
209 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
212 __asm __volatile("" : : : "memory");
217 * cpu_sfence() ensures strong write ordering for writes issued prior
218 * to the instruction verses writes issued afterwords. Writes are
219 * ordered on intel cpus so we do not actually have to do anything.
226 __asm __volatile("sfence" : : : "memory");
229 __asm __volatile("" : : : "memory");
234 * cpu_ccfence() prevents the compiler from reordering instructions, in
235 * particular stores, relative to the current cpu. Use cpu_sfence() if
236 * you need to guarentee ordering by both the compiler and by the cpu.
238 * This also prevents the compiler from caching memory loads into local
239 * variables across the routine.
244 __asm __volatile("" : : : "memory");
249 #define HAVE_INLINE_FFS
255 * Note that gcc-2's builtin ffs would be used if we didn't declare
256 * this inline or turn off the builtin. The builtin is faster but
257 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
260 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
263 #define HAVE_INLINE_FLS
268 return (mask == 0 ? mask : (int) bsrl((u_int)mask) + 1);
274 * The following complications are to get around gcc not having a
275 * constraint letter for the range 0..255. We still put "d" in the
276 * constraint because "i" isn't a valid constraint when the port
277 * isn't constant. This only matters for -O0 because otherwise
278 * the non-working version gets optimized away.
280 * Use an expression-statement instead of a conditional expression
281 * because gcc-2.6.0 would promote the operands of the conditional
282 * and produce poor code for "if ((inb(var) & const1) == const2)".
284 * The unnecessary test `(port) < 0x10000' is to generate a warning if
285 * the `port' has type u_short or smaller. Such types are pessimal.
286 * This actually only works for signed types. The range check is
287 * careful to avoid generating warnings.
289 #define inb(port) __extension__ ({ \
291 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
292 && (port) < 0x10000) \
293 _data = inbc(port); \
295 _data = inbv(port); \
298 #define outb(port, data) ( \
299 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
300 && (port) < 0x10000 \
301 ? outbc(port, data) : outbv(port, data))
303 static __inline u_char
308 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
313 outbc(u_int port, u_char data)
315 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
318 static __inline u_char
323 * We use %%dx and not %1 here because i/o is done at %dx and not at
324 * %edx, while gcc generates inferior code (movw instead of movl)
325 * if we tell it to load (u_short) port.
327 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
331 static __inline u_int
336 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
341 insb(u_int port, void *addr, size_t cnt)
343 __asm __volatile("cld; rep; insb"
344 : "=D" (addr), "=c" (cnt)
345 : "0" (addr), "1" (cnt), "d" (port)
350 insw(u_int port, void *addr, size_t cnt)
352 __asm __volatile("cld; rep; insw"
353 : "=D" (addr), "=c" (cnt)
354 : "0" (addr), "1" (cnt), "d" (port)
359 insl(u_int port, void *addr, size_t cnt)
361 __asm __volatile("cld; rep; insl"
362 : "=D" (addr), "=c" (cnt)
363 : "0" (addr), "1" (cnt), "d" (port)
370 __asm __volatile("invd");
376 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
377 * will cause the invl*() functions to be equivalent to the cpu_invl*()
381 void smp_invltlb(void);
382 void smp_invltlb_intr(void);
384 #define smp_invltlb()
387 #ifndef _CPU_INVLPG_DEFINED
390 * Invalidate a patricular VA on this cpu only
393 cpu_invlpg(void *addr)
395 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
400 #ifndef _CPU_INVLTLB_DEFINED
403 * Invalidate the TLB on this cpu only
410 * This should be implemented as load_cr3(rcr3()) when load_cr3()
413 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
415 #if defined(SWTCH_OPTIM_STATS)
425 __asm __volatile("rep; nop");
430 static __inline u_short
435 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
439 static __inline u_int
440 loadandclear(volatile u_int *addr)
444 __asm __volatile("xorl %0,%0; xchgl %1,%0"
445 : "=&r" (result) : "m" (*addr));
450 outbv(u_int port, u_char data)
454 * Use an unnecessary assignment to help gcc's register allocator.
455 * This make a large difference for gcc-1.40 and a tiny difference
456 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
457 * best results. gcc-2.6.0 can't handle this.
460 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
464 outl(u_int port, u_int data)
467 * outl() and outw() aren't used much so we haven't looked at
468 * possible micro-optimizations such as the unnecessary
469 * assignment for them.
471 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
475 outsb(u_int port, const void *addr, size_t cnt)
477 __asm __volatile("cld; rep; outsb"
478 : "=S" (addr), "=c" (cnt)
479 : "0" (addr), "1" (cnt), "d" (port));
483 outsw(u_int port, const void *addr, size_t cnt)
485 __asm __volatile("cld; rep; outsw"
486 : "=S" (addr), "=c" (cnt)
487 : "0" (addr), "1" (cnt), "d" (port));
491 outsl(u_int port, const void *addr, size_t cnt)
493 __asm __volatile("cld; rep; outsl"
494 : "=S" (addr), "=c" (cnt)
495 : "0" (addr), "1" (cnt), "d" (port));
499 outw(u_int port, u_short data)
501 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
504 static __inline u_int
509 __asm __volatile("movl %%cr2,%0" : "=r" (data));
513 static __inline u_int
518 __asm __volatile("pushfl; popl %0" : "=r" (ef));
522 static __inline u_int64_t
527 __asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr));
531 static __inline u_int64_t
536 __asm __volatile(".byte 0x0f, 0x33" : "=A" (rv) : "c" (pmc));
540 #define _RDTSC_SUPPORTED_
542 static __inline u_int64_t
547 __asm __volatile(".byte 0x0f, 0x31" : "=A" (rv));
554 __asm __volatile("wbinvd");
558 write_eflags(u_int ef)
560 __asm __volatile("pushl %0; popfl" : : "r" (ef));
564 wrmsr(u_int msr, u_int64_t newval)
566 __asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr));
569 static __inline u_int
573 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
577 static __inline u_int
581 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
588 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
594 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
597 static __inline u_int
601 __asm __volatile("movl %%dr0,%0" : "=r" (data));
608 __asm __volatile("movl %0,%%dr0" : : "r" (sel));
611 static __inline u_int
615 __asm __volatile("movl %%dr1,%0" : "=r" (data));
622 __asm __volatile("movl %0,%%dr1" : : "r" (sel));
625 static __inline u_int
629 __asm __volatile("movl %%dr2,%0" : "=r" (data));
636 __asm __volatile("movl %0,%%dr2" : : "r" (sel));
639 static __inline u_int
643 __asm __volatile("movl %%dr3,%0" : "=r" (data));
650 __asm __volatile("movl %0,%%dr3" : : "r" (sel));
653 static __inline u_int
657 __asm __volatile("movl %%dr4,%0" : "=r" (data));
664 __asm __volatile("movl %0,%%dr4" : : "r" (sel));
667 static __inline u_int
671 __asm __volatile("movl %%dr5,%0" : "=r" (data));
678 __asm __volatile("movl %0,%%dr5" : : "r" (sel));
681 static __inline u_int
685 __asm __volatile("movl %%dr6,%0" : "=r" (data));
692 __asm __volatile("movl %0,%%dr6" : : "r" (sel));
695 static __inline u_int
699 __asm __volatile("movl %%dr7,%0" : "=r" (data));
706 __asm __volatile("movl %0,%%dr7" : : "r" (sel));
709 #else /* !__GNUC__ */
711 int breakpoint (void);
712 void cpu_pause (void);
713 u_int bsfl (u_int mask);
714 u_int bsrl (u_int mask);
715 void cpu_disable_intr (void);
716 void do_cpuid (u_int ax, u_int *p);
717 void cpu_enable_intr (void);
718 u_char inb (u_int port);
719 u_int inl (u_int port);
720 void insb (u_int port, void *addr, size_t cnt);
721 void insl (u_int port, void *addr, size_t cnt);
722 void insw (u_int port, void *addr, size_t cnt);
724 u_short inw (u_int port);
725 u_int loadandclear (u_int *addr);
726 void outb (u_int port, u_char data);
727 void outl (u_int port, u_int data);
728 void outsb (u_int port, void *addr, size_t cnt);
729 void outsl (u_int port, void *addr, size_t cnt);
730 void outsw (u_int port, void *addr, size_t cnt);
731 void outw (u_int port, u_short data);
733 u_int64_t rdmsr (u_int msr);
734 u_int64_t rdpmc (u_int pmc);
735 u_int64_t rdtsc (void);
736 u_int read_eflags (void);
738 void write_eflags (u_int ef);
739 void wrmsr (u_int msr, u_int64_t newval);
742 void load_fs (u_int sel);
743 void load_gs (u_int sel);
745 #endif /* __GNUC__ */
747 void load_cr0 (u_int cr0);
748 void load_cr3 (u_int cr3);
749 void load_cr4 (u_int cr4);
750 void ltr (u_short sel);
754 void reset_dbregs (void);
757 #endif /* !_CPU_CPUFUNC_H_ */