2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
70 * MSI-X MUST NOT be enabled on 82574:
71 * <<82574 specification update>> errata #15
74 #include "opt_ifpoll.h"
78 #include <sys/param.h>
80 #include <sys/endian.h>
81 #include <sys/interrupt.h>
82 #include <sys/kernel.h>
84 #include <sys/malloc.h>
88 #include <sys/serialize.h>
89 #include <sys/serialize2.h>
90 #include <sys/socket.h>
91 #include <sys/sockio.h>
92 #include <sys/sysctl.h>
93 #include <sys/systm.h>
96 #include <net/ethernet.h>
98 #include <net/if_arp.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/ifq_var.h>
102 #include <net/toeplitz.h>
103 #include <net/toeplitz2.h>
104 #include <net/vlan/if_vlan_var.h>
105 #include <net/vlan/if_vlan_ether.h>
106 #include <net/if_poll.h>
108 #include <netinet/in_systm.h>
109 #include <netinet/in.h>
110 #include <netinet/ip.h>
111 #include <netinet/tcp.h>
112 #include <netinet/udp.h>
114 #include <bus/pci/pcivar.h>
115 #include <bus/pci/pcireg.h>
117 #include <dev/netif/ig_hal/e1000_api.h>
118 #include <dev/netif/ig_hal/e1000_82571.h>
119 #include <dev/netif/emx/if_emx.h>
122 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
124 if (sc->rss_debug >= lvl) \
125 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
127 #else /* !EMX_RSS_DEBUG */
128 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
129 #endif /* EMX_RSS_DEBUG */
131 #define EMX_NAME "Intel(R) PRO/1000 "
133 #define EMX_DEVICE(id) \
134 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
135 #define EMX_DEVICE_NULL { 0, 0, NULL }
137 static const struct emx_device {
142 EMX_DEVICE(82571EB_COPPER),
143 EMX_DEVICE(82571EB_FIBER),
144 EMX_DEVICE(82571EB_SERDES),
145 EMX_DEVICE(82571EB_SERDES_DUAL),
146 EMX_DEVICE(82571EB_SERDES_QUAD),
147 EMX_DEVICE(82571EB_QUAD_COPPER),
148 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
149 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
150 EMX_DEVICE(82571EB_QUAD_FIBER),
151 EMX_DEVICE(82571PT_QUAD_COPPER),
153 EMX_DEVICE(82572EI_COPPER),
154 EMX_DEVICE(82572EI_FIBER),
155 EMX_DEVICE(82572EI_SERDES),
159 EMX_DEVICE(82573E_IAMT),
162 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
163 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
164 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
165 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
170 /* required last entry */
174 static int emx_probe(device_t);
175 static int emx_attach(device_t);
176 static int emx_detach(device_t);
177 static int emx_shutdown(device_t);
178 static int emx_suspend(device_t);
179 static int emx_resume(device_t);
181 static void emx_init(void *);
182 static void emx_stop(struct emx_softc *);
183 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
184 static void emx_start(struct ifnet *);
186 static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
188 static void emx_watchdog(struct ifnet *);
189 static void emx_media_status(struct ifnet *, struct ifmediareq *);
190 static int emx_media_change(struct ifnet *);
191 static void emx_timer(void *);
192 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
193 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
194 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
196 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
200 static void emx_intr(void *);
201 static void emx_rxeof(struct emx_softc *, int, int);
202 static void emx_txeof(struct emx_softc *);
203 static void emx_tx_collect(struct emx_softc *);
204 static void emx_tx_purge(struct emx_softc *);
205 static void emx_enable_intr(struct emx_softc *);
206 static void emx_disable_intr(struct emx_softc *);
208 static int emx_dma_alloc(struct emx_softc *);
209 static void emx_dma_free(struct emx_softc *);
210 static void emx_init_tx_ring(struct emx_softc *);
211 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
212 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
213 static int emx_create_tx_ring(struct emx_softc *);
214 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
215 static void emx_destroy_tx_ring(struct emx_softc *, int);
216 static void emx_destroy_rx_ring(struct emx_softc *,
217 struct emx_rxdata *, int);
218 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
219 static int emx_encap(struct emx_softc *, struct mbuf **);
220 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
221 static int emx_txcsum(struct emx_softc *, struct mbuf *,
222 uint32_t *, uint32_t *);
224 static int emx_is_valid_eaddr(const uint8_t *);
225 static int emx_reset(struct emx_softc *);
226 static void emx_setup_ifp(struct emx_softc *);
227 static void emx_init_tx_unit(struct emx_softc *);
228 static void emx_init_rx_unit(struct emx_softc *);
229 static void emx_update_stats(struct emx_softc *);
230 static void emx_set_promisc(struct emx_softc *);
231 static void emx_disable_promisc(struct emx_softc *);
232 static void emx_set_multi(struct emx_softc *);
233 static void emx_update_link_status(struct emx_softc *);
234 static void emx_smartspeed(struct emx_softc *);
235 static void emx_set_itr(struct emx_softc *, uint32_t);
236 static void emx_disable_aspm(struct emx_softc *);
238 static void emx_print_debug_info(struct emx_softc *);
239 static void emx_print_nvm_info(struct emx_softc *);
240 static void emx_print_hw_stats(struct emx_softc *);
242 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
243 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
244 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
245 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
246 static void emx_add_sysctl(struct emx_softc *);
248 static void emx_serialize_skipmain(struct emx_softc *);
249 static void emx_deserialize_skipmain(struct emx_softc *);
251 /* Management and WOL Support */
252 static void emx_get_mgmt(struct emx_softc *);
253 static void emx_rel_mgmt(struct emx_softc *);
254 static void emx_get_hw_control(struct emx_softc *);
255 static void emx_rel_hw_control(struct emx_softc *);
256 static void emx_enable_wol(device_t);
258 static device_method_t emx_methods[] = {
259 /* Device interface */
260 DEVMETHOD(device_probe, emx_probe),
261 DEVMETHOD(device_attach, emx_attach),
262 DEVMETHOD(device_detach, emx_detach),
263 DEVMETHOD(device_shutdown, emx_shutdown),
264 DEVMETHOD(device_suspend, emx_suspend),
265 DEVMETHOD(device_resume, emx_resume),
269 static driver_t emx_driver = {
272 sizeof(struct emx_softc),
275 static devclass_t emx_devclass;
277 DECLARE_DUMMY_MODULE(if_emx);
278 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
279 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
284 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
285 static int emx_rxd = EMX_DEFAULT_RXD;
286 static int emx_txd = EMX_DEFAULT_TXD;
287 static int emx_smart_pwr_down = 0;
288 static int emx_rxr = 0;
290 /* Controls whether promiscuous also shows bad packets */
291 static int emx_debug_sbp = 0;
293 static int emx_82573_workaround = 1;
294 static int emx_msi_enable = 1;
296 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
297 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
298 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
299 TUNABLE_INT("hw.emx.txd", &emx_txd);
300 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
301 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
302 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
303 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
305 /* Global used in WOL setup with multiport cards */
306 static int emx_global_quad_port_a = 0;
308 /* Set this to one to display debug statistics */
309 static int emx_display_debug_stats = 0;
311 #if !defined(KTR_IF_EMX)
312 #define KTR_IF_EMX KTR_ALL
314 KTR_INFO_MASTER(if_emx);
315 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
316 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
317 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
318 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
319 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
320 #define logif(name) KTR_LOG(if_emx_ ## name)
323 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
325 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
326 /* DD bit must be cleared */
327 rxd->rxd_staterr = 0;
331 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
333 /* Ignore Checksum bit is set */
334 if (staterr & E1000_RXD_STAT_IXSM)
337 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
339 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
341 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
342 E1000_RXD_STAT_TCPCS) {
343 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
345 CSUM_FRAG_NOT_CHECKED;
346 mp->m_pkthdr.csum_data = htons(0xffff);
350 static __inline struct pktinfo *
351 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
352 uint32_t mrq, uint32_t hash, uint32_t staterr)
354 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
355 case EMX_RXDMRQ_IPV4_TCP:
356 pi->pi_netisr = NETISR_IP;
358 pi->pi_l3proto = IPPROTO_TCP;
361 case EMX_RXDMRQ_IPV6_TCP:
362 pi->pi_netisr = NETISR_IPV6;
364 pi->pi_l3proto = IPPROTO_TCP;
367 case EMX_RXDMRQ_IPV4:
368 if (staterr & E1000_RXD_STAT_IXSM)
372 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
373 E1000_RXD_STAT_TCPCS) {
374 pi->pi_netisr = NETISR_IP;
376 pi->pi_l3proto = IPPROTO_UDP;
384 m->m_flags |= M_HASH;
385 m->m_pkthdr.hash = toeplitz_hash(hash);
390 emx_probe(device_t dev)
392 const struct emx_device *d;
395 vid = pci_get_vendor(dev);
396 did = pci_get_device(dev);
398 for (d = emx_devices; d->desc != NULL; ++d) {
399 if (vid == d->vid && did == d->did) {
400 device_set_desc(dev, d->desc);
401 device_set_async_attach(dev, TRUE);
409 emx_attach(device_t dev)
411 struct emx_softc *sc = device_get_softc(dev);
412 struct ifnet *ifp = &sc->arpcom.ac_if;
413 int error = 0, i, throttle;
415 uint16_t eeprom_data, device_id, apme_mask;
417 lwkt_serialize_init(&sc->main_serialize);
418 lwkt_serialize_init(&sc->tx_serialize);
419 for (i = 0; i < EMX_NRX_RING; ++i)
420 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
423 sc->serializes[i++] = &sc->main_serialize;
424 sc->serializes[i++] = &sc->tx_serialize;
425 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
426 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
427 KKASSERT(i == EMX_NSERIALIZE);
429 callout_init_mp(&sc->timer);
431 sc->dev = sc->osdep.dev = dev;
434 * Determine hardware and mac type
436 sc->hw.vendor_id = pci_get_vendor(dev);
437 sc->hw.device_id = pci_get_device(dev);
438 sc->hw.revision_id = pci_get_revid(dev);
439 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
440 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
442 if (e1000_set_mac_type(&sc->hw))
445 /* Enable bus mastering */
446 pci_enable_busmaster(dev);
451 sc->memory_rid = EMX_BAR_MEM;
452 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
453 &sc->memory_rid, RF_ACTIVE);
454 if (sc->memory == NULL) {
455 device_printf(dev, "Unable to allocate bus resource: memory\n");
459 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
460 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
462 /* XXX This is quite goofy, it is not actually used */
463 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
468 sc->intr_type = pci_alloc_1intr(dev, emx_msi_enable,
469 &sc->intr_rid, &intr_flags);
471 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
473 if (sc->intr_res == NULL) {
474 device_printf(dev, "Unable to allocate bus resource: "
480 /* Save PCI command register for Shared Code */
481 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
482 sc->hw.back = &sc->osdep;
484 /* Do Shared Code initialization */
485 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
486 device_printf(dev, "Setup of Shared code failed\n");
490 e1000_get_bus_info(&sc->hw);
492 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
493 sc->hw.phy.autoneg_wait_to_complete = FALSE;
494 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
497 * Interrupt throttle rate
499 throttle = device_getenv_int(dev, "int_throttle_ceil",
500 emx_int_throttle_ceil);
502 sc->int_throttle_ceil = 0;
505 throttle = EMX_DEFAULT_ITR;
507 /* Recalculate the tunable value to get the exact frequency. */
508 throttle = 1000000000 / 256 / throttle;
510 /* Upper 16bits of ITR is reserved and should be zero */
511 if (throttle & 0xffff0000)
512 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
514 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
517 e1000_init_script_state_82541(&sc->hw, TRUE);
518 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
521 if (sc->hw.phy.media_type == e1000_media_type_copper) {
522 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
523 sc->hw.phy.disable_polarity_correction = FALSE;
524 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
527 /* Set the frame limits assuming standard ethernet sized frames. */
528 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
529 sc->min_frame_size = ETHER_MIN_LEN;
531 /* This controls when hardware reports transmit completion status. */
532 sc->hw.mac.report_tx_early = 1;
534 /* Calculate # of RX rings */
535 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
536 if (sc->rx_ring_cnt <= 0 || sc->rx_ring_cnt > EMX_NRX_RING ||
537 sc->rx_ring_cnt > ncpus) {
539 sc->rx_ring_cnt = EMX_NRX_RING;
544 /* Allocate RX/TX rings' busdma(9) stuffs */
545 error = emx_dma_alloc(sc);
549 /* Allocate multicast array memory. */
550 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
553 /* Indicate SOL/IDER usage */
554 if (e1000_check_reset_block(&sc->hw)) {
556 "PHY reset is blocked due to SOL/IDER session.\n");
560 * Start from a known state, this is important in reading the
561 * nvm and mac from that.
563 e1000_reset_hw(&sc->hw);
565 /* Make sure we have a good EEPROM before we read from it */
566 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
568 * Some PCI-E parts fail the first check due to
569 * the link being in sleep state, call it again,
570 * if it fails a second time its a real issue.
572 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
574 "The EEPROM Checksum Is Not Valid\n");
580 /* Copy the permanent MAC address out of the EEPROM */
581 if (e1000_read_mac_addr(&sc->hw) < 0) {
582 device_printf(dev, "EEPROM read error while reading MAC"
587 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
588 device_printf(dev, "Invalid MAC address\n");
593 /* Determine if we have to control management hardware */
594 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
599 apme_mask = EMX_EEPROM_APME;
601 switch (sc->hw.mac.type) {
608 case e1000_80003es2lan:
609 if (sc->hw.bus.func == 1) {
610 e1000_read_nvm(&sc->hw,
611 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
613 e1000_read_nvm(&sc->hw,
614 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
619 e1000_read_nvm(&sc->hw,
620 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
623 if (eeprom_data & apme_mask)
624 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
627 * We have the eeprom settings, now apply the special cases
628 * where the eeprom may be wrong or the board won't support
629 * wake on lan on a particular port
631 device_id = pci_get_device(dev);
633 case E1000_DEV_ID_82571EB_FIBER:
635 * Wake events only supported on port A for dual fiber
636 * regardless of eeprom setting
638 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
643 case E1000_DEV_ID_82571EB_QUAD_COPPER:
644 case E1000_DEV_ID_82571EB_QUAD_FIBER:
645 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
646 /* if quad port sc, disable WoL on all but port A */
647 if (emx_global_quad_port_a != 0)
649 /* Reset for multiple quad port adapters */
650 if (++emx_global_quad_port_a == 4)
651 emx_global_quad_port_a = 0;
655 /* XXX disable wol */
658 /* Setup OS specific network interface */
661 /* Add sysctl tree, must after em_setup_ifp() */
664 /* Reset the hardware */
665 error = emx_reset(sc);
667 device_printf(dev, "Unable to reset the hardware\n");
671 /* Initialize statistics */
672 emx_update_stats(sc);
674 sc->hw.mac.get_link_status = 1;
675 emx_update_link_status(sc);
677 sc->spare_tx_desc = EMX_TX_SPARE;
680 * Keep following relationship between spare_tx_desc, oact_tx_desc
682 * (spare_tx_desc + EMX_TX_RESERVED) <=
683 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
685 sc->oact_tx_desc = sc->num_tx_desc / 8;
686 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
687 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
688 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
689 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
691 sc->tx_int_nsegs = sc->num_tx_desc / 16;
692 if (sc->tx_int_nsegs < sc->oact_tx_desc)
693 sc->tx_int_nsegs = sc->oact_tx_desc;
695 /* Non-AMT based hardware can now take control from firmware */
696 if (sc->has_manage && !sc->has_amt)
697 emx_get_hw_control(sc);
699 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc,
700 &sc->intr_tag, &sc->main_serialize);
702 device_printf(dev, "Failed to register interrupt handler");
703 ether_ifdetach(&sc->arpcom.ac_if);
707 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
708 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
716 emx_detach(device_t dev)
718 struct emx_softc *sc = device_get_softc(dev);
720 if (device_is_attached(dev)) {
721 struct ifnet *ifp = &sc->arpcom.ac_if;
723 ifnet_serialize_all(ifp);
727 e1000_phy_hw_reset(&sc->hw);
730 emx_rel_hw_control(sc);
733 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
734 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
738 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
740 ifnet_deserialize_all(ifp);
744 emx_rel_hw_control(sc);
746 bus_generic_detach(dev);
748 if (sc->intr_res != NULL) {
749 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
753 if (sc->intr_type == PCI_INTR_TYPE_MSI)
754 pci_release_msi(dev);
756 if (sc->memory != NULL) {
757 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
763 /* Free sysctl tree */
764 if (sc->sysctl_tree != NULL)
765 sysctl_ctx_free(&sc->sysctl_ctx);
771 emx_shutdown(device_t dev)
773 return emx_suspend(dev);
777 emx_suspend(device_t dev)
779 struct emx_softc *sc = device_get_softc(dev);
780 struct ifnet *ifp = &sc->arpcom.ac_if;
782 ifnet_serialize_all(ifp);
787 emx_rel_hw_control(sc);
790 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
791 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
795 ifnet_deserialize_all(ifp);
797 return bus_generic_suspend(dev);
801 emx_resume(device_t dev)
803 struct emx_softc *sc = device_get_softc(dev);
804 struct ifnet *ifp = &sc->arpcom.ac_if;
806 ifnet_serialize_all(ifp);
812 ifnet_deserialize_all(ifp);
814 return bus_generic_resume(dev);
818 emx_start(struct ifnet *ifp)
820 struct emx_softc *sc = ifp->if_softc;
823 ASSERT_SERIALIZED(&sc->tx_serialize);
825 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
828 if (!sc->link_active) {
829 ifq_purge(&ifp->if_snd);
833 while (!ifq_is_empty(&ifp->if_snd)) {
834 /* Now do we at least have a minimal? */
835 if (EMX_IS_OACTIVE(sc)) {
837 if (EMX_IS_OACTIVE(sc)) {
838 ifp->if_flags |= IFF_OACTIVE;
839 sc->no_tx_desc_avail1++;
845 m_head = ifq_dequeue(&ifp->if_snd, NULL);
849 if (emx_encap(sc, &m_head)) {
855 /* Send a copy of the frame to the BPF listener */
856 ETHER_BPF_MTAP(ifp, m_head);
858 /* Set timeout in case hardware has problems transmitting. */
859 ifp->if_timer = EMX_TX_TIMEOUT;
864 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
866 struct emx_softc *sc = ifp->if_softc;
867 struct ifreq *ifr = (struct ifreq *)data;
868 uint16_t eeprom_data = 0;
869 int max_frame_size, mask, reinit;
872 ASSERT_IFNET_SERIALIZED_ALL(ifp);
876 switch (sc->hw.mac.type) {
879 * 82573 only supports jumbo frames
880 * if ASPM is disabled.
882 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
884 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
885 max_frame_size = ETHER_MAX_LEN;
890 /* Limit Jumbo Frame size */
894 case e1000_80003es2lan:
895 max_frame_size = 9234;
899 max_frame_size = MAX_JUMBO_FRAME_SIZE;
902 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
908 ifp->if_mtu = ifr->ifr_mtu;
909 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
912 if (ifp->if_flags & IFF_RUNNING)
917 if (ifp->if_flags & IFF_UP) {
918 if ((ifp->if_flags & IFF_RUNNING)) {
919 if ((ifp->if_flags ^ sc->if_flags) &
920 (IFF_PROMISC | IFF_ALLMULTI)) {
921 emx_disable_promisc(sc);
927 } else if (ifp->if_flags & IFF_RUNNING) {
930 sc->if_flags = ifp->if_flags;
935 if (ifp->if_flags & IFF_RUNNING) {
936 emx_disable_intr(sc);
939 if (!(ifp->if_flags & IFF_NPOLLING))
946 /* Check SOL/IDER usage */
947 if (e1000_check_reset_block(&sc->hw)) {
948 device_printf(sc->dev, "Media change is"
949 " blocked due to SOL/IDER session.\n");
955 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
960 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
961 if (mask & IFCAP_HWCSUM) {
962 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
965 if (mask & IFCAP_VLAN_HWTAGGING) {
966 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
969 if (mask & IFCAP_RSS)
970 ifp->if_capenable ^= IFCAP_RSS;
971 if (reinit && (ifp->if_flags & IFF_RUNNING))
976 error = ether_ioctl(ifp, command, data);
983 emx_watchdog(struct ifnet *ifp)
985 struct emx_softc *sc = ifp->if_softc;
987 ASSERT_IFNET_SERIALIZED_ALL(ifp);
990 * The timer is set to 5 every time start queues a packet.
991 * Then txeof keeps resetting it as long as it cleans at
992 * least one descriptor.
993 * Finally, anytime all descriptors are clean the timer is
997 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
998 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1000 * If we reach here, all TX jobs are completed and
1001 * the TX engine should have been idled for some time.
1002 * We don't need to call if_devstart() here.
1004 ifp->if_flags &= ~IFF_OACTIVE;
1010 * If we are in this routine because of pause frames, then
1011 * don't reset the hardware.
1013 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1014 ifp->if_timer = EMX_TX_TIMEOUT;
1018 if (e1000_check_for_link(&sc->hw) == 0)
1019 if_printf(ifp, "watchdog timeout -- resetting\n");
1022 sc->watchdog_events++;
1026 if (!ifq_is_empty(&ifp->if_snd))
1033 struct emx_softc *sc = xsc;
1034 struct ifnet *ifp = &sc->arpcom.ac_if;
1035 device_t dev = sc->dev;
1039 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1044 * Packet Buffer Allocation (PBA)
1045 * Writing PBA sets the receive portion of the buffer
1046 * the remainder is used for the transmit buffer.
1048 switch (sc->hw.mac.type) {
1049 /* Total Packet Buffer on these is 48K */
1052 case e1000_80003es2lan:
1053 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1056 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1057 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1061 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1065 /* Devices before 82547 had a Packet Buffer of 64K. */
1066 if (sc->max_frame_size > 8192)
1067 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1069 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1071 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1073 /* Get the latest mac address, User can use a LAA */
1074 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1076 /* Put the address into the Receive Address Array */
1077 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1080 * With the 82571 sc, RAR[0] may be overwritten
1081 * when the other port is reset, we make a duplicate
1082 * in RAR[14] for that eventuality, this assures
1083 * the interface continues to function.
1085 if (sc->hw.mac.type == e1000_82571) {
1086 e1000_set_laa_state_82571(&sc->hw, TRUE);
1087 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1088 E1000_RAR_ENTRIES - 1);
1091 /* Initialize the hardware */
1092 if (emx_reset(sc)) {
1093 device_printf(dev, "Unable to reset the hardware\n");
1094 /* XXX emx_stop()? */
1097 emx_update_link_status(sc);
1099 /* Setup VLAN support, basic and offload if available */
1100 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1102 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1105 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1106 ctrl |= E1000_CTRL_VME;
1107 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1110 /* Set hardware offload abilities */
1111 if (ifp->if_capenable & IFCAP_TXCSUM)
1112 ifp->if_hwassist = EMX_CSUM_FEATURES;
1114 ifp->if_hwassist = 0;
1116 /* Configure for OS presence */
1119 /* Prepare transmit descriptors and buffers */
1120 emx_init_tx_ring(sc);
1121 emx_init_tx_unit(sc);
1123 /* Setup Multicast table */
1126 /* Prepare receive descriptors and buffers */
1127 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1128 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1130 "Could not setup receive structures\n");
1135 emx_init_rx_unit(sc);
1137 /* Don't lose promiscuous settings */
1138 emx_set_promisc(sc);
1140 ifp->if_flags |= IFF_RUNNING;
1141 ifp->if_flags &= ~IFF_OACTIVE;
1143 callout_reset(&sc->timer, hz, emx_timer, sc);
1144 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1146 /* MSI/X configuration for 82574 */
1147 if (sc->hw.mac.type == e1000_82574) {
1150 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1151 tmp |= E1000_CTRL_EXT_PBA_CLR;
1152 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1155 * Set the IVAR - interrupt vector routing.
1156 * Each nibble represents a vector, high bit
1157 * is enable, other 3 bits are the MSIX table
1158 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1159 * Link (other) to 2, hence the magic number.
1161 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1164 #ifdef IFPOLL_ENABLE
1166 * Only enable interrupts if we are not polling, make sure
1167 * they are off otherwise.
1169 if (ifp->if_flags & IFF_NPOLLING)
1170 emx_disable_intr(sc);
1172 #endif /* IFPOLL_ENABLE */
1173 emx_enable_intr(sc);
1175 /* AMT based hardware can now take control from firmware */
1176 if (sc->has_manage && sc->has_amt)
1177 emx_get_hw_control(sc);
1179 /* Don't reset the phy next time init gets called */
1180 sc->hw.phy.reset_disable = TRUE;
1186 struct emx_softc *sc = xsc;
1187 struct ifnet *ifp = &sc->arpcom.ac_if;
1191 ASSERT_SERIALIZED(&sc->main_serialize);
1193 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1195 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1201 * XXX: some laptops trigger several spurious interrupts
1202 * on emx(4) when in the resume cycle. The ICR register
1203 * reports all-ones value in this case. Processing such
1204 * interrupts would lead to a freeze. I don't know why.
1206 if (reg_icr == 0xffffffff) {
1211 if (ifp->if_flags & IFF_RUNNING) {
1213 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1216 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1217 lwkt_serialize_enter(
1218 &sc->rx_data[i].rx_serialize);
1219 emx_rxeof(sc, i, -1);
1220 lwkt_serialize_exit(
1221 &sc->rx_data[i].rx_serialize);
1224 if (reg_icr & E1000_ICR_TXDW) {
1225 lwkt_serialize_enter(&sc->tx_serialize);
1227 if (!ifq_is_empty(&ifp->if_snd))
1229 lwkt_serialize_exit(&sc->tx_serialize);
1233 /* Link status change */
1234 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1235 emx_serialize_skipmain(sc);
1237 callout_stop(&sc->timer);
1238 sc->hw.mac.get_link_status = 1;
1239 emx_update_link_status(sc);
1241 /* Deal with TX cruft when link lost */
1244 callout_reset(&sc->timer, hz, emx_timer, sc);
1246 emx_deserialize_skipmain(sc);
1249 if (reg_icr & E1000_ICR_RXO)
1256 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1258 struct emx_softc *sc = ifp->if_softc;
1260 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1262 emx_update_link_status(sc);
1264 ifmr->ifm_status = IFM_AVALID;
1265 ifmr->ifm_active = IFM_ETHER;
1267 if (!sc->link_active)
1270 ifmr->ifm_status |= IFM_ACTIVE;
1272 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1273 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1274 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1276 switch (sc->link_speed) {
1278 ifmr->ifm_active |= IFM_10_T;
1281 ifmr->ifm_active |= IFM_100_TX;
1285 ifmr->ifm_active |= IFM_1000_T;
1288 if (sc->link_duplex == FULL_DUPLEX)
1289 ifmr->ifm_active |= IFM_FDX;
1291 ifmr->ifm_active |= IFM_HDX;
1296 emx_media_change(struct ifnet *ifp)
1298 struct emx_softc *sc = ifp->if_softc;
1299 struct ifmedia *ifm = &sc->media;
1301 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1303 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1306 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1308 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1309 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1315 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1316 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1320 sc->hw.mac.autoneg = FALSE;
1321 sc->hw.phy.autoneg_advertised = 0;
1322 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1323 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1325 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1329 sc->hw.mac.autoneg = FALSE;
1330 sc->hw.phy.autoneg_advertised = 0;
1331 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1332 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1334 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1338 if_printf(ifp, "Unsupported media type\n");
1343 * As the speed/duplex settings my have changed we need to
1346 sc->hw.phy.reset_disable = FALSE;
1354 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1356 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1358 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1359 struct e1000_tx_desc *ctxd = NULL;
1360 struct mbuf *m_head = *m_headp;
1361 uint32_t txd_upper, txd_lower, cmd = 0;
1362 int maxsegs, nsegs, i, j, first, last = 0, error;
1364 if (m_head->m_len < EMX_TXCSUM_MINHL &&
1365 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1367 * Make sure that ethernet header and ip.ip_hl are in
1368 * contiguous memory, since if TXCSUM is enabled, later
1369 * TX context descriptor's setup need to access ip.ip_hl.
1371 error = emx_txcsum_pullup(sc, m_headp);
1373 KKASSERT(*m_headp == NULL);
1379 txd_upper = txd_lower = 0;
1382 * Capture the first descriptor index, this descriptor
1383 * will have the index of the EOP which is the only one
1384 * that now gets a DONE bit writeback.
1386 first = sc->next_avail_tx_desc;
1387 tx_buffer = &sc->tx_buf[first];
1388 tx_buffer_mapped = tx_buffer;
1389 map = tx_buffer->map;
1391 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1392 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n"));
1393 if (maxsegs > EMX_MAX_SCATTER)
1394 maxsegs = EMX_MAX_SCATTER;
1396 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1397 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1399 if (error == ENOBUFS)
1400 sc->mbuf_alloc_failed++;
1402 sc->no_tx_dma_setup++;
1408 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1411 sc->tx_nsegs += nsegs;
1413 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1414 /* TX csum offloading will consume one TX desc */
1415 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1417 i = sc->next_avail_tx_desc;
1419 /* Set up our transmit descriptors */
1420 for (j = 0; j < nsegs; j++) {
1421 tx_buffer = &sc->tx_buf[i];
1422 ctxd = &sc->tx_desc_base[i];
1424 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1425 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1426 txd_lower | segs[j].ds_len);
1427 ctxd->upper.data = htole32(txd_upper);
1430 if (++i == sc->num_tx_desc)
1434 sc->next_avail_tx_desc = i;
1436 KKASSERT(sc->num_tx_desc_avail > nsegs);
1437 sc->num_tx_desc_avail -= nsegs;
1439 /* Handle VLAN tag */
1440 if (m_head->m_flags & M_VLANTAG) {
1441 /* Set the vlan id. */
1442 ctxd->upper.fields.special =
1443 htole16(m_head->m_pkthdr.ether_vlantag);
1445 /* Tell hardware to add tag */
1446 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1449 tx_buffer->m_head = m_head;
1450 tx_buffer_mapped->map = tx_buffer->map;
1451 tx_buffer->map = map;
1453 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1457 * Report Status (RS) is turned on
1458 * every tx_int_nsegs descriptors.
1460 cmd = E1000_TXD_CMD_RS;
1463 * Keep track of the descriptor, which will
1464 * be written back by hardware.
1466 sc->tx_dd[sc->tx_dd_tail] = last;
1467 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1468 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1472 * Last Descriptor of Packet needs End Of Packet (EOP)
1474 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1477 * Advance the Transmit Descriptor Tail (TDT), this tells
1478 * the E1000 that this frame is available to transmit.
1480 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1486 emx_set_promisc(struct emx_softc *sc)
1488 struct ifnet *ifp = &sc->arpcom.ac_if;
1491 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1493 if (ifp->if_flags & IFF_PROMISC) {
1494 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1495 /* Turn this on if you want to see bad packets */
1497 reg_rctl |= E1000_RCTL_SBP;
1498 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1499 } else if (ifp->if_flags & IFF_ALLMULTI) {
1500 reg_rctl |= E1000_RCTL_MPE;
1501 reg_rctl &= ~E1000_RCTL_UPE;
1502 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1507 emx_disable_promisc(struct emx_softc *sc)
1511 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1513 reg_rctl &= ~E1000_RCTL_UPE;
1514 reg_rctl &= ~E1000_RCTL_MPE;
1515 reg_rctl &= ~E1000_RCTL_SBP;
1516 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1520 emx_set_multi(struct emx_softc *sc)
1522 struct ifnet *ifp = &sc->arpcom.ac_if;
1523 struct ifmultiaddr *ifma;
1524 uint32_t reg_rctl = 0;
1529 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1531 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1532 if (ifma->ifma_addr->sa_family != AF_LINK)
1535 if (mcnt == EMX_MCAST_ADDR_MAX)
1538 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1539 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1543 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1544 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1545 reg_rctl |= E1000_RCTL_MPE;
1546 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1548 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1553 * This routine checks for link status and updates statistics.
1556 emx_timer(void *xsc)
1558 struct emx_softc *sc = xsc;
1559 struct ifnet *ifp = &sc->arpcom.ac_if;
1561 ifnet_serialize_all(ifp);
1563 emx_update_link_status(sc);
1564 emx_update_stats(sc);
1566 /* Reset LAA into RAR[0] on 82571 */
1567 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1568 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1570 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1571 emx_print_hw_stats(sc);
1575 callout_reset(&sc->timer, hz, emx_timer, sc);
1577 ifnet_deserialize_all(ifp);
1581 emx_update_link_status(struct emx_softc *sc)
1583 struct e1000_hw *hw = &sc->hw;
1584 struct ifnet *ifp = &sc->arpcom.ac_if;
1585 device_t dev = sc->dev;
1586 uint32_t link_check = 0;
1588 /* Get the cached link value or read phy for real */
1589 switch (hw->phy.media_type) {
1590 case e1000_media_type_copper:
1591 if (hw->mac.get_link_status) {
1592 /* Do the work to read phy */
1593 e1000_check_for_link(hw);
1594 link_check = !hw->mac.get_link_status;
1595 if (link_check) /* ESB2 fix */
1596 e1000_cfg_on_link_up(hw);
1602 case e1000_media_type_fiber:
1603 e1000_check_for_link(hw);
1604 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1607 case e1000_media_type_internal_serdes:
1608 e1000_check_for_link(hw);
1609 link_check = sc->hw.mac.serdes_has_link;
1612 case e1000_media_type_unknown:
1617 /* Now check for a transition */
1618 if (link_check && sc->link_active == 0) {
1619 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1623 * Check if we should enable/disable SPEED_MODE bit on
1626 if (sc->link_speed != SPEED_1000 &&
1627 (hw->mac.type == e1000_82571 ||
1628 hw->mac.type == e1000_82572)) {
1631 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1632 tarc0 &= ~EMX_TARC_SPEED_MODE;
1633 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1636 device_printf(dev, "Link is up %d Mbps %s\n",
1638 ((sc->link_duplex == FULL_DUPLEX) ?
1639 "Full Duplex" : "Half Duplex"));
1641 sc->link_active = 1;
1643 ifp->if_baudrate = sc->link_speed * 1000000;
1644 ifp->if_link_state = LINK_STATE_UP;
1645 if_link_state_change(ifp);
1646 } else if (!link_check && sc->link_active == 1) {
1647 ifp->if_baudrate = sc->link_speed = 0;
1648 sc->link_duplex = 0;
1650 device_printf(dev, "Link is Down\n");
1651 sc->link_active = 0;
1653 /* Link down, disable watchdog */
1656 ifp->if_link_state = LINK_STATE_DOWN;
1657 if_link_state_change(ifp);
1662 emx_stop(struct emx_softc *sc)
1664 struct ifnet *ifp = &sc->arpcom.ac_if;
1667 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1669 emx_disable_intr(sc);
1671 callout_stop(&sc->timer);
1673 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1677 * Disable multiple receive queues.
1680 * We should disable multiple receive queues before
1681 * resetting the hardware.
1683 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1685 e1000_reset_hw(&sc->hw);
1686 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1688 for (i = 0; i < sc->num_tx_desc; i++) {
1689 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1691 if (tx_buffer->m_head != NULL) {
1692 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1693 m_freem(tx_buffer->m_head);
1694 tx_buffer->m_head = NULL;
1698 for (i = 0; i < sc->rx_ring_cnt; ++i)
1699 emx_free_rx_ring(sc, &sc->rx_data[i]);
1703 sc->csum_iphlen = 0;
1711 emx_reset(struct emx_softc *sc)
1713 device_t dev = sc->dev;
1714 uint16_t rx_buffer_size;
1716 /* Set up smart power down as default off on newer adapters. */
1717 if (!emx_smart_pwr_down &&
1718 (sc->hw.mac.type == e1000_82571 ||
1719 sc->hw.mac.type == e1000_82572)) {
1720 uint16_t phy_tmp = 0;
1722 /* Speed up time to link by disabling smart power down. */
1723 e1000_read_phy_reg(&sc->hw,
1724 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1725 phy_tmp &= ~IGP02E1000_PM_SPD;
1726 e1000_write_phy_reg(&sc->hw,
1727 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1731 * These parameters control the automatic generation (Tx) and
1732 * response (Rx) to Ethernet PAUSE frames.
1733 * - High water mark should allow for at least two frames to be
1734 * received after sending an XOFF.
1735 * - Low water mark works best when it is very near the high water mark.
1736 * This allows the receiver to restart by sending XON when it has
1737 * drained a bit. Here we use an arbitary value of 1500 which will
1738 * restart after one full frame is pulled from the buffer. There
1739 * could be several smaller frames in the buffer and if so they will
1740 * not trigger the XON until their total number reduces the buffer
1742 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1744 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1746 sc->hw.fc.high_water = rx_buffer_size -
1747 roundup2(sc->max_frame_size, 1024);
1748 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1750 if (sc->hw.mac.type == e1000_80003es2lan)
1751 sc->hw.fc.pause_time = 0xFFFF;
1753 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1754 sc->hw.fc.send_xon = TRUE;
1755 sc->hw.fc.requested_mode = e1000_fc_full;
1757 /* Issue a global reset */
1758 e1000_reset_hw(&sc->hw);
1759 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1760 emx_disable_aspm(sc);
1762 if (e1000_init_hw(&sc->hw) < 0) {
1763 device_printf(dev, "Hardware Initialization Failed\n");
1767 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1768 e1000_get_phy_info(&sc->hw);
1769 e1000_check_for_link(&sc->hw);
1775 emx_setup_ifp(struct emx_softc *sc)
1777 struct ifnet *ifp = &sc->arpcom.ac_if;
1779 if_initname(ifp, device_get_name(sc->dev),
1780 device_get_unit(sc->dev));
1782 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1783 ifp->if_init = emx_init;
1784 ifp->if_ioctl = emx_ioctl;
1785 ifp->if_start = emx_start;
1786 #ifdef IFPOLL_ENABLE
1787 ifp->if_qpoll = emx_qpoll;
1789 ifp->if_watchdog = emx_watchdog;
1790 ifp->if_serialize = emx_serialize;
1791 ifp->if_deserialize = emx_deserialize;
1792 ifp->if_tryserialize = emx_tryserialize;
1794 ifp->if_serialize_assert = emx_serialize_assert;
1796 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1797 ifq_set_ready(&ifp->if_snd);
1799 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1801 ifp->if_capabilities = IFCAP_HWCSUM |
1802 IFCAP_VLAN_HWTAGGING |
1804 if (sc->rx_ring_cnt > 1)
1805 ifp->if_capabilities |= IFCAP_RSS;
1806 ifp->if_capenable = ifp->if_capabilities;
1807 ifp->if_hwassist = EMX_CSUM_FEATURES;
1810 * Tell the upper layer(s) we support long frames.
1812 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1815 * Specify the media types supported by this sc and register
1816 * callbacks to update media and link information
1818 ifmedia_init(&sc->media, IFM_IMASK,
1819 emx_media_change, emx_media_status);
1820 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1821 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1822 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1824 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1826 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1827 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1829 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1830 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1832 if (sc->hw.phy.type != e1000_phy_ife) {
1833 ifmedia_add(&sc->media,
1834 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1835 ifmedia_add(&sc->media,
1836 IFM_ETHER | IFM_1000_T, 0, NULL);
1839 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1840 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1844 * Workaround for SmartSpeed on 82541 and 82547 controllers
1847 emx_smartspeed(struct emx_softc *sc)
1851 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1852 sc->hw.mac.autoneg == 0 ||
1853 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1856 if (sc->smartspeed == 0) {
1858 * If Master/Slave config fault is asserted twice,
1859 * we assume back-to-back
1861 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1862 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1864 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1865 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1866 e1000_read_phy_reg(&sc->hw,
1867 PHY_1000T_CTRL, &phy_tmp);
1868 if (phy_tmp & CR_1000T_MS_ENABLE) {
1869 phy_tmp &= ~CR_1000T_MS_ENABLE;
1870 e1000_write_phy_reg(&sc->hw,
1871 PHY_1000T_CTRL, phy_tmp);
1873 if (sc->hw.mac.autoneg &&
1874 !e1000_phy_setup_autoneg(&sc->hw) &&
1875 !e1000_read_phy_reg(&sc->hw,
1876 PHY_CONTROL, &phy_tmp)) {
1877 phy_tmp |= MII_CR_AUTO_NEG_EN |
1878 MII_CR_RESTART_AUTO_NEG;
1879 e1000_write_phy_reg(&sc->hw,
1880 PHY_CONTROL, phy_tmp);
1885 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1886 /* If still no link, perhaps using 2/3 pair cable */
1887 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1888 phy_tmp |= CR_1000T_MS_ENABLE;
1889 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1890 if (sc->hw.mac.autoneg &&
1891 !e1000_phy_setup_autoneg(&sc->hw) &&
1892 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1893 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1894 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1898 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1899 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1904 emx_create_tx_ring(struct emx_softc *sc)
1906 device_t dev = sc->dev;
1907 struct emx_txbuf *tx_buffer;
1908 int error, i, tsize, ntxd;
1911 * Validate number of transmit descriptors. It must not exceed
1912 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1914 ntxd = device_getenv_int(dev, "txd", emx_txd);
1915 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1916 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
1917 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1918 EMX_DEFAULT_TXD, ntxd);
1919 sc->num_tx_desc = EMX_DEFAULT_TXD;
1921 sc->num_tx_desc = ntxd;
1925 * Allocate Transmit Descriptor ring
1927 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1929 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1930 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1931 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1932 &sc->tx_desc_paddr);
1933 if (sc->tx_desc_base == NULL) {
1934 device_printf(dev, "Unable to allocate tx_desc memory\n");
1938 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1939 M_DEVBUF, M_WAITOK | M_ZERO);
1942 * Create DMA tags for tx buffers
1944 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1945 1, 0, /* alignment, bounds */
1946 BUS_SPACE_MAXADDR, /* lowaddr */
1947 BUS_SPACE_MAXADDR, /* highaddr */
1948 NULL, NULL, /* filter, filterarg */
1949 EMX_TSO_SIZE, /* maxsize */
1950 EMX_MAX_SCATTER, /* nsegments */
1951 EMX_MAX_SEGSIZE, /* maxsegsize */
1952 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1953 BUS_DMA_ONEBPAGE, /* flags */
1956 device_printf(dev, "Unable to allocate TX DMA tag\n");
1957 kfree(sc->tx_buf, M_DEVBUF);
1963 * Create DMA maps for tx buffers
1965 for (i = 0; i < sc->num_tx_desc; i++) {
1966 tx_buffer = &sc->tx_buf[i];
1968 error = bus_dmamap_create(sc->txtag,
1969 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1972 device_printf(dev, "Unable to create TX DMA map\n");
1973 emx_destroy_tx_ring(sc, i);
1981 emx_init_tx_ring(struct emx_softc *sc)
1983 /* Clear the old ring contents */
1984 bzero(sc->tx_desc_base,
1985 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
1988 sc->next_avail_tx_desc = 0;
1989 sc->next_tx_to_clean = 0;
1990 sc->num_tx_desc_avail = sc->num_tx_desc;
1994 emx_init_tx_unit(struct emx_softc *sc)
1996 uint32_t tctl, tarc, tipg = 0;
1999 /* Setup the Base and Length of the Tx Descriptor Ring */
2000 bus_addr = sc->tx_desc_paddr;
2001 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2002 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2003 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2004 (uint32_t)(bus_addr >> 32));
2005 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2006 (uint32_t)bus_addr);
2007 /* Setup the HW Tx Head and Tail descriptor pointers */
2008 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2009 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2011 /* Set the default values for the Tx Inter Packet Gap timer */
2012 switch (sc->hw.mac.type) {
2013 case e1000_80003es2lan:
2014 tipg = DEFAULT_82543_TIPG_IPGR1;
2015 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2016 E1000_TIPG_IPGR2_SHIFT;
2020 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2021 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2022 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2024 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2025 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2026 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2030 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2032 /* NOTE: 0 is not allowed for TIDV */
2033 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2034 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2036 if (sc->hw.mac.type == e1000_82571 ||
2037 sc->hw.mac.type == e1000_82572) {
2038 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2039 tarc |= EMX_TARC_SPEED_MODE;
2040 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2041 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2042 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2044 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2045 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2047 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2050 /* Program the Transmit Control Register */
2051 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2052 tctl &= ~E1000_TCTL_CT;
2053 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2054 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2055 tctl |= E1000_TCTL_MULR;
2057 /* This write will effectively turn on the transmit unit. */
2058 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2062 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2064 struct emx_txbuf *tx_buffer;
2067 /* Free Transmit Descriptor ring */
2068 if (sc->tx_desc_base) {
2069 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2070 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2072 bus_dma_tag_destroy(sc->tx_desc_dtag);
2074 sc->tx_desc_base = NULL;
2077 if (sc->tx_buf == NULL)
2080 for (i = 0; i < ndesc; i++) {
2081 tx_buffer = &sc->tx_buf[i];
2083 KKASSERT(tx_buffer->m_head == NULL);
2084 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2086 bus_dma_tag_destroy(sc->txtag);
2088 kfree(sc->tx_buf, M_DEVBUF);
2093 * The offload context needs to be set when we transfer the first
2094 * packet of a particular protocol (TCP/UDP). This routine has been
2095 * enhanced to deal with inserted VLAN headers.
2097 * If the new packet's ether header length, ip header length and
2098 * csum offloading type are same as the previous packet, we should
2099 * avoid allocating a new csum context descriptor; mainly to take
2100 * advantage of the pipeline effect of the TX data read request.
2102 * This function returns number of TX descrptors allocated for
2106 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2107 uint32_t *txd_upper, uint32_t *txd_lower)
2109 struct e1000_context_desc *TXD;
2110 struct emx_txbuf *tx_buffer;
2111 struct ether_vlan_header *eh;
2113 int curr_txd, ehdrlen, csum_flags;
2114 uint32_t cmd, hdr_len, ip_hlen;
2118 * Determine where frame payload starts.
2119 * Jump over vlan headers if already present,
2120 * helpful for QinQ too.
2122 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2123 ("emx_txcsum_pullup is not called (eh)?\n"));
2124 eh = mtod(mp, struct ether_vlan_header *);
2125 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2126 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2127 ("emx_txcsum_pullup is not called (evh)?\n"));
2128 etype = ntohs(eh->evl_proto);
2129 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2131 etype = ntohs(eh->evl_encap_proto);
2132 ehdrlen = ETHER_HDR_LEN;
2136 * We only support TCP/UDP for IPv4 for the moment.
2137 * TODO: Support SCTP too when it hits the tree.
2139 if (etype != ETHERTYPE_IP)
2142 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
2143 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n"));
2145 /* NOTE: We could only safely access ip.ip_vhl part */
2146 ip = (struct ip *)(mp->m_data + ehdrlen);
2147 ip_hlen = ip->ip_hl << 2;
2149 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2151 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2152 sc->csum_flags == csum_flags) {
2154 * Same csum offload context as the previous packets;
2157 *txd_upper = sc->csum_txd_upper;
2158 *txd_lower = sc->csum_txd_lower;
2163 * Setup a new csum offload context.
2166 curr_txd = sc->next_avail_tx_desc;
2167 tx_buffer = &sc->tx_buf[curr_txd];
2168 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2172 /* Setup of IP header checksum. */
2173 if (csum_flags & CSUM_IP) {
2175 * Start offset for header checksum calculation.
2176 * End offset for header checksum calculation.
2177 * Offset of place to put the checksum.
2179 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2180 TXD->lower_setup.ip_fields.ipcse =
2181 htole16(ehdrlen + ip_hlen - 1);
2182 TXD->lower_setup.ip_fields.ipcso =
2183 ehdrlen + offsetof(struct ip, ip_sum);
2184 cmd |= E1000_TXD_CMD_IP;
2185 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2187 hdr_len = ehdrlen + ip_hlen;
2189 if (csum_flags & CSUM_TCP) {
2191 * Start offset for payload checksum calculation.
2192 * End offset for payload checksum calculation.
2193 * Offset of place to put the checksum.
2195 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2196 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2197 TXD->upper_setup.tcp_fields.tucso =
2198 hdr_len + offsetof(struct tcphdr, th_sum);
2199 cmd |= E1000_TXD_CMD_TCP;
2200 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2201 } else if (csum_flags & CSUM_UDP) {
2203 * Start offset for header checksum calculation.
2204 * End offset for header checksum calculation.
2205 * Offset of place to put the checksum.
2207 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2208 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2209 TXD->upper_setup.tcp_fields.tucso =
2210 hdr_len + offsetof(struct udphdr, uh_sum);
2211 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2214 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2215 E1000_TXD_DTYP_D; /* Data descr */
2217 /* Save the information for this csum offloading context */
2218 sc->csum_ehlen = ehdrlen;
2219 sc->csum_iphlen = ip_hlen;
2220 sc->csum_flags = csum_flags;
2221 sc->csum_txd_upper = *txd_upper;
2222 sc->csum_txd_lower = *txd_lower;
2224 TXD->tcp_seg_setup.data = htole32(0);
2225 TXD->cmd_and_length =
2226 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2228 if (++curr_txd == sc->num_tx_desc)
2231 KKASSERT(sc->num_tx_desc_avail > 0);
2232 sc->num_tx_desc_avail--;
2234 sc->next_avail_tx_desc = curr_txd;
2239 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2241 struct mbuf *m = *m0;
2242 struct ether_header *eh;
2245 sc->tx_csum_try_pullup++;
2247 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2249 if (__predict_false(!M_WRITABLE(m))) {
2250 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2251 sc->tx_csum_drop1++;
2256 eh = mtod(m, struct ether_header *);
2258 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2259 len += EVL_ENCAPLEN;
2261 if (m->m_len < len) {
2262 sc->tx_csum_drop2++;
2270 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2271 sc->tx_csum_pullup1++;
2272 m = m_pullup(m, ETHER_HDR_LEN);
2274 sc->tx_csum_pullup1_failed++;
2280 eh = mtod(m, struct ether_header *);
2282 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2283 len += EVL_ENCAPLEN;
2285 if (m->m_len < len) {
2286 sc->tx_csum_pullup2++;
2287 m = m_pullup(m, len);
2289 sc->tx_csum_pullup2_failed++;
2299 emx_txeof(struct emx_softc *sc)
2301 struct ifnet *ifp = &sc->arpcom.ac_if;
2302 struct emx_txbuf *tx_buffer;
2303 int first, num_avail;
2305 if (sc->tx_dd_head == sc->tx_dd_tail)
2308 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2311 num_avail = sc->num_tx_desc_avail;
2312 first = sc->next_tx_to_clean;
2314 while (sc->tx_dd_head != sc->tx_dd_tail) {
2315 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2316 struct e1000_tx_desc *tx_desc;
2318 tx_desc = &sc->tx_desc_base[dd_idx];
2319 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2320 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2322 if (++dd_idx == sc->num_tx_desc)
2325 while (first != dd_idx) {
2330 tx_buffer = &sc->tx_buf[first];
2331 if (tx_buffer->m_head) {
2333 bus_dmamap_unload(sc->txtag,
2335 m_freem(tx_buffer->m_head);
2336 tx_buffer->m_head = NULL;
2339 if (++first == sc->num_tx_desc)
2346 sc->next_tx_to_clean = first;
2347 sc->num_tx_desc_avail = num_avail;
2349 if (sc->tx_dd_head == sc->tx_dd_tail) {
2354 if (!EMX_IS_OACTIVE(sc)) {
2355 ifp->if_flags &= ~IFF_OACTIVE;
2357 /* All clean, turn off the timer */
2358 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2364 emx_tx_collect(struct emx_softc *sc)
2366 struct ifnet *ifp = &sc->arpcom.ac_if;
2367 struct emx_txbuf *tx_buffer;
2368 int tdh, first, num_avail, dd_idx = -1;
2370 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2373 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2374 if (tdh == sc->next_tx_to_clean)
2377 if (sc->tx_dd_head != sc->tx_dd_tail)
2378 dd_idx = sc->tx_dd[sc->tx_dd_head];
2380 num_avail = sc->num_tx_desc_avail;
2381 first = sc->next_tx_to_clean;
2383 while (first != tdh) {
2388 tx_buffer = &sc->tx_buf[first];
2389 if (tx_buffer->m_head) {
2391 bus_dmamap_unload(sc->txtag,
2393 m_freem(tx_buffer->m_head);
2394 tx_buffer->m_head = NULL;
2397 if (first == dd_idx) {
2398 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2399 if (sc->tx_dd_head == sc->tx_dd_tail) {
2404 dd_idx = sc->tx_dd[sc->tx_dd_head];
2408 if (++first == sc->num_tx_desc)
2411 sc->next_tx_to_clean = first;
2412 sc->num_tx_desc_avail = num_avail;
2414 if (!EMX_IS_OACTIVE(sc)) {
2415 ifp->if_flags &= ~IFF_OACTIVE;
2417 /* All clean, turn off the timer */
2418 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2424 * When Link is lost sometimes there is work still in the TX ring
2425 * which will result in a watchdog, rather than allow that do an
2426 * attempted cleanup and then reinit here. Note that this has been
2427 * seens mostly with fiber adapters.
2430 emx_tx_purge(struct emx_softc *sc)
2432 struct ifnet *ifp = &sc->arpcom.ac_if;
2434 if (!sc->link_active && ifp->if_timer) {
2436 if (ifp->if_timer) {
2437 if_printf(ifp, "Link lost, TX pending, reinit\n");
2445 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2448 bus_dma_segment_t seg;
2450 struct emx_rxbuf *rx_buffer;
2453 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2455 rdata->mbuf_cluster_failed++;
2457 if_printf(&sc->arpcom.ac_if,
2458 "Unable to allocate RX mbuf\n");
2462 m->m_len = m->m_pkthdr.len = MCLBYTES;
2464 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2465 m_adj(m, ETHER_ALIGN);
2467 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2468 rdata->rx_sparemap, m,
2469 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2473 if_printf(&sc->arpcom.ac_if,
2474 "Unable to load RX mbuf\n");
2479 rx_buffer = &rdata->rx_buf[i];
2480 if (rx_buffer->m_head != NULL)
2481 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2483 map = rx_buffer->map;
2484 rx_buffer->map = rdata->rx_sparemap;
2485 rdata->rx_sparemap = map;
2487 rx_buffer->m_head = m;
2488 rx_buffer->paddr = seg.ds_addr;
2490 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2495 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2497 device_t dev = sc->dev;
2498 struct emx_rxbuf *rx_buffer;
2499 int i, error, rsize, nrxd;
2502 * Validate number of receive descriptors. It must not exceed
2503 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2505 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2506 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2507 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2508 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2509 EMX_DEFAULT_RXD, nrxd);
2510 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2512 rdata->num_rx_desc = nrxd;
2516 * Allocate Receive Descriptor ring
2518 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2520 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2521 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2522 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2523 &rdata->rx_desc_paddr);
2524 if (rdata->rx_desc == NULL) {
2525 device_printf(dev, "Unable to allocate rx_desc memory\n");
2529 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2530 M_DEVBUF, M_WAITOK | M_ZERO);
2533 * Create DMA tag for rx buffers
2535 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2536 1, 0, /* alignment, bounds */
2537 BUS_SPACE_MAXADDR, /* lowaddr */
2538 BUS_SPACE_MAXADDR, /* highaddr */
2539 NULL, NULL, /* filter, filterarg */
2540 MCLBYTES, /* maxsize */
2542 MCLBYTES, /* maxsegsize */
2543 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2546 device_printf(dev, "Unable to allocate RX DMA tag\n");
2547 kfree(rdata->rx_buf, M_DEVBUF);
2548 rdata->rx_buf = NULL;
2553 * Create spare DMA map for rx buffers
2555 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2556 &rdata->rx_sparemap);
2558 device_printf(dev, "Unable to create spare RX DMA map\n");
2559 bus_dma_tag_destroy(rdata->rxtag);
2560 kfree(rdata->rx_buf, M_DEVBUF);
2561 rdata->rx_buf = NULL;
2566 * Create DMA maps for rx buffers
2568 for (i = 0; i < rdata->num_rx_desc; i++) {
2569 rx_buffer = &rdata->rx_buf[i];
2571 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2574 device_printf(dev, "Unable to create RX DMA map\n");
2575 emx_destroy_rx_ring(sc, rdata, i);
2583 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2587 for (i = 0; i < rdata->num_rx_desc; i++) {
2588 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2590 if (rx_buffer->m_head != NULL) {
2591 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2592 m_freem(rx_buffer->m_head);
2593 rx_buffer->m_head = NULL;
2597 if (rdata->fmp != NULL)
2598 m_freem(rdata->fmp);
2604 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2608 /* Reset descriptor ring */
2609 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2611 /* Allocate new ones. */
2612 for (i = 0; i < rdata->num_rx_desc; i++) {
2613 error = emx_newbuf(sc, rdata, i, 1);
2618 /* Setup our descriptor pointers */
2619 rdata->next_rx_desc_to_check = 0;
2625 emx_init_rx_unit(struct emx_softc *sc)
2627 struct ifnet *ifp = &sc->arpcom.ac_if;
2629 uint32_t rctl, itr, rfctl;
2633 * Make sure receives are disabled while setting
2634 * up the descriptor ring
2636 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2637 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2640 * Set the interrupt throttling rate. Value is calculated
2641 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2643 if (sc->int_throttle_ceil)
2644 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2647 emx_set_itr(sc, itr);
2649 /* Use extended RX descriptor */
2650 rfctl = E1000_RFCTL_EXTEN;
2652 /* Disable accelerated ackknowledge */
2653 if (sc->hw.mac.type == e1000_82574)
2654 rfctl |= E1000_RFCTL_ACK_DIS;
2656 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2659 * Receive Checksum Offload for TCP and UDP
2661 * Checksum offloading is also enabled if multiple receive
2662 * queue is to be supported, since we need it to figure out
2665 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2666 sc->rx_ring_cnt > 1) {
2669 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2673 * PCSD must be enabled to enable multiple
2676 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2678 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2682 * Configure multiple receive queue (RSS)
2684 if (sc->rx_ring_cnt > 1) {
2685 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2688 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2689 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2693 * When we reach here, RSS has already been disabled
2694 * in emx_stop(), so we could safely configure RSS key
2695 * and redirect table.
2701 toeplitz_get_key(key, sizeof(key));
2702 for (i = 0; i < EMX_NRSSRK; ++i) {
2705 rssrk = EMX_RSSRK_VAL(key, i);
2706 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2708 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2712 * Configure RSS redirect table in following fashion:
2713 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2716 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2719 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2720 reta |= q << (8 * i);
2722 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2724 for (i = 0; i < EMX_NRETA; ++i)
2725 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2728 * Enable multiple receive queues.
2729 * Enable IPv4 RSS standard hash functions.
2730 * Disable RSS interrupt.
2732 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2733 E1000_MRQC_ENABLE_RSS_2Q |
2734 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2735 E1000_MRQC_RSS_FIELD_IPV4);
2739 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2740 * long latencies are observed, like Lenovo X60. This
2741 * change eliminates the problem, but since having positive
2742 * values in RDTR is a known source of problems on other
2743 * platforms another solution is being sought.
2745 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2746 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2747 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2750 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2751 struct emx_rxdata *rdata = &sc->rx_data[i];
2754 * Setup the Base and Length of the Rx Descriptor Ring
2756 bus_addr = rdata->rx_desc_paddr;
2757 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2758 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2759 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2760 (uint32_t)(bus_addr >> 32));
2761 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2762 (uint32_t)bus_addr);
2765 * Setup the HW Rx Head and Tail Descriptor Pointers
2767 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2768 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2769 sc->rx_data[i].num_rx_desc - 1);
2772 /* Setup the Receive Control Register */
2773 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2774 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2775 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2776 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2778 /* Make sure VLAN Filters are off */
2779 rctl &= ~E1000_RCTL_VFE;
2781 /* Don't store bad paket */
2782 rctl &= ~E1000_RCTL_SBP;
2785 rctl |= E1000_RCTL_SZ_2048;
2787 if (ifp->if_mtu > ETHERMTU)
2788 rctl |= E1000_RCTL_LPE;
2790 rctl &= ~E1000_RCTL_LPE;
2792 /* Enable Receives */
2793 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2797 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2799 struct emx_rxbuf *rx_buffer;
2802 /* Free Receive Descriptor ring */
2803 if (rdata->rx_desc) {
2804 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2805 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2806 rdata->rx_desc_dmap);
2807 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2809 rdata->rx_desc = NULL;
2812 if (rdata->rx_buf == NULL)
2815 for (i = 0; i < ndesc; i++) {
2816 rx_buffer = &rdata->rx_buf[i];
2818 KKASSERT(rx_buffer->m_head == NULL);
2819 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2821 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2822 bus_dma_tag_destroy(rdata->rxtag);
2824 kfree(rdata->rx_buf, M_DEVBUF);
2825 rdata->rx_buf = NULL;
2829 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2831 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2832 struct ifnet *ifp = &sc->arpcom.ac_if;
2834 emx_rxdesc_t *current_desc;
2838 i = rdata->next_rx_desc_to_check;
2839 current_desc = &rdata->rx_desc[i];
2840 staterr = le32toh(current_desc->rxd_staterr);
2842 if (!(staterr & E1000_RXD_STAT_DD))
2845 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2846 struct pktinfo *pi = NULL, pi0;
2847 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2848 struct mbuf *m = NULL;
2853 mp = rx_buf->m_head;
2856 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2857 * needs to access the last received byte in the mbuf.
2859 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2860 BUS_DMASYNC_POSTREAD);
2862 len = le16toh(current_desc->rxd_length);
2863 if (staterr & E1000_RXD_STAT_EOP) {
2870 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2872 uint32_t mrq, rss_hash;
2875 * Save several necessary information,
2876 * before emx_newbuf() destroy it.
2878 if ((staterr & E1000_RXD_STAT_VP) && eop)
2879 vlan = le16toh(current_desc->rxd_vlan);
2881 mrq = le32toh(current_desc->rxd_mrq);
2882 rss_hash = le32toh(current_desc->rxd_rss);
2884 EMX_RSS_DPRINTF(sc, 10,
2885 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2886 ring_idx, mrq, rss_hash);
2888 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2893 /* Assign correct length to the current fragment */
2896 if (rdata->fmp == NULL) {
2897 mp->m_pkthdr.len = len;
2898 rdata->fmp = mp; /* Store the first mbuf */
2902 * Chain mbuf's together
2904 rdata->lmp->m_next = mp;
2905 rdata->lmp = rdata->lmp->m_next;
2906 rdata->fmp->m_pkthdr.len += len;
2910 rdata->fmp->m_pkthdr.rcvif = ifp;
2913 if (ifp->if_capenable & IFCAP_RXCSUM)
2914 emx_rxcsum(staterr, rdata->fmp);
2916 if (staterr & E1000_RXD_STAT_VP) {
2917 rdata->fmp->m_pkthdr.ether_vlantag =
2919 rdata->fmp->m_flags |= M_VLANTAG;
2925 if (ifp->if_capenable & IFCAP_RSS) {
2926 pi = emx_rssinfo(m, &pi0, mrq,
2929 #ifdef EMX_RSS_DEBUG
2936 emx_setup_rxdesc(current_desc, rx_buf);
2937 if (rdata->fmp != NULL) {
2938 m_freem(rdata->fmp);
2946 ether_input_pkt(ifp, m, pi);
2948 /* Advance our pointers to the next descriptor. */
2949 if (++i == rdata->num_rx_desc)
2952 current_desc = &rdata->rx_desc[i];
2953 staterr = le32toh(current_desc->rxd_staterr);
2955 rdata->next_rx_desc_to_check = i;
2957 /* Advance the E1000's Receive Queue "Tail Pointer". */
2959 i = rdata->num_rx_desc - 1;
2960 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2964 emx_enable_intr(struct emx_softc *sc)
2966 uint32_t ims_mask = IMS_ENABLE_MASK;
2968 lwkt_serialize_handler_enable(&sc->main_serialize);
2971 if (sc->hw.mac.type == e1000_82574) {
2972 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2973 ims_mask |= EM_MSIX_MASK;
2976 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
2980 emx_disable_intr(struct emx_softc *sc)
2982 if (sc->hw.mac.type == e1000_82574)
2983 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
2984 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2986 lwkt_serialize_handler_disable(&sc->main_serialize);
2990 * Bit of a misnomer, what this really means is
2991 * to enable OS management of the system... aka
2992 * to disable special hardware management features
2995 emx_get_mgmt(struct emx_softc *sc)
2997 /* A shared code workaround */
2998 if (sc->has_manage) {
2999 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3000 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3002 /* disable hardware interception of ARP */
3003 manc &= ~(E1000_MANC_ARP_EN);
3005 /* enable receiving management packets to the host */
3006 manc |= E1000_MANC_EN_MNG2HOST;
3007 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3008 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3009 manc2h |= E1000_MNG2HOST_PORT_623;
3010 manc2h |= E1000_MNG2HOST_PORT_664;
3011 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3013 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3018 * Give control back to hardware management
3019 * controller if there is one.
3022 emx_rel_mgmt(struct emx_softc *sc)
3024 if (sc->has_manage) {
3025 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3027 /* re-enable hardware interception of ARP */
3028 manc |= E1000_MANC_ARP_EN;
3029 manc &= ~E1000_MANC_EN_MNG2HOST;
3031 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3036 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3037 * For ASF and Pass Through versions of f/w this means that
3038 * the driver is loaded. For AMT version (only with 82573)
3039 * of the f/w this means that the network i/f is open.
3042 emx_get_hw_control(struct emx_softc *sc)
3044 /* Let firmware know the driver has taken over */
3045 if (sc->hw.mac.type == e1000_82573) {
3048 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3049 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3050 swsm | E1000_SWSM_DRV_LOAD);
3054 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3055 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3056 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3062 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3063 * For ASF and Pass Through versions of f/w this means that the
3064 * driver is no longer loaded. For AMT version (only with 82573)
3065 * of the f/w this means that the network i/f is closed.
3068 emx_rel_hw_control(struct emx_softc *sc)
3070 if (!sc->control_hw)
3074 /* Let firmware taken over control of h/w */
3075 if (sc->hw.mac.type == e1000_82573) {
3078 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3079 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3080 swsm & ~E1000_SWSM_DRV_LOAD);
3084 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3085 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3086 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3091 emx_is_valid_eaddr(const uint8_t *addr)
3093 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3095 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3102 * Enable PCI Wake On Lan capability
3105 emx_enable_wol(device_t dev)
3107 uint16_t cap, status;
3110 /* First find the capabilities pointer*/
3111 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3113 /* Read the PM Capabilities */
3114 id = pci_read_config(dev, cap, 1);
3115 if (id != PCIY_PMG) /* Something wrong */
3119 * OK, we have the power capabilities,
3120 * so now get the status register
3122 cap += PCIR_POWER_STATUS;
3123 status = pci_read_config(dev, cap, 2);
3124 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3125 pci_write_config(dev, cap, status, 2);
3129 emx_update_stats(struct emx_softc *sc)
3131 struct ifnet *ifp = &sc->arpcom.ac_if;
3133 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3134 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3135 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3136 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3138 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3139 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3140 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3141 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3143 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3144 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3145 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3146 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3147 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3148 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3149 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3150 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3151 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3152 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3153 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3154 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3155 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3156 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3157 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3158 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3159 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3160 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3161 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3162 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3164 /* For the 64-bit byte counters the low dword must be read first. */
3165 /* Both registers clear on the read of the high dword */
3167 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3168 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3170 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3171 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3172 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3173 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3174 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3176 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3177 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3179 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3180 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3181 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3182 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3183 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3184 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3185 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3186 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3187 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3188 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3190 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3191 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3192 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3193 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3194 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3195 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3197 ifp->if_collisions = sc->stats.colc;
3200 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3201 sc->stats.crcerrs + sc->stats.algnerrc +
3202 sc->stats.ruc + sc->stats.roc +
3203 sc->stats.mpc + sc->stats.cexterr;
3206 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3207 sc->watchdog_events;
3211 emx_print_debug_info(struct emx_softc *sc)
3213 device_t dev = sc->dev;
3214 uint8_t *hw_addr = sc->hw.hw_addr;
3216 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3217 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3218 E1000_READ_REG(&sc->hw, E1000_CTRL),
3219 E1000_READ_REG(&sc->hw, E1000_RCTL));
3220 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3221 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3222 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3223 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3224 sc->hw.fc.high_water, sc->hw.fc.low_water);
3225 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3226 E1000_READ_REG(&sc->hw, E1000_TIDV),
3227 E1000_READ_REG(&sc->hw, E1000_TADV));
3228 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3229 E1000_READ_REG(&sc->hw, E1000_RDTR),
3230 E1000_READ_REG(&sc->hw, E1000_RADV));
3231 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3232 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3233 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3234 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3235 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3236 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3237 device_printf(dev, "Num Tx descriptors avail = %d\n",
3238 sc->num_tx_desc_avail);
3239 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3240 sc->no_tx_desc_avail1);
3241 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3242 sc->no_tx_desc_avail2);
3243 device_printf(dev, "Std mbuf failed = %ld\n",
3244 sc->mbuf_alloc_failed);
3245 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3246 sc->rx_data[0].mbuf_cluster_failed);
3247 device_printf(dev, "Driver dropped packets = %ld\n",
3249 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3250 sc->no_tx_dma_setup);
3252 device_printf(dev, "TXCSUM try pullup = %lu\n",
3253 sc->tx_csum_try_pullup);
3254 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3255 sc->tx_csum_pullup1);
3256 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3257 sc->tx_csum_pullup1_failed);
3258 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3259 sc->tx_csum_pullup2);
3260 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3261 sc->tx_csum_pullup2_failed);
3262 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3264 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3269 emx_print_hw_stats(struct emx_softc *sc)
3271 device_t dev = sc->dev;
3273 device_printf(dev, "Excessive collisions = %lld\n",
3274 (long long)sc->stats.ecol);
3275 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3276 device_printf(dev, "Symbol errors = %lld\n",
3277 (long long)sc->stats.symerrs);
3279 device_printf(dev, "Sequence errors = %lld\n",
3280 (long long)sc->stats.sec);
3281 device_printf(dev, "Defer count = %lld\n",
3282 (long long)sc->stats.dc);
3283 device_printf(dev, "Missed Packets = %lld\n",
3284 (long long)sc->stats.mpc);
3285 device_printf(dev, "Receive No Buffers = %lld\n",
3286 (long long)sc->stats.rnbc);
3287 /* RLEC is inaccurate on some hardware, calculate our own. */
3288 device_printf(dev, "Receive Length Errors = %lld\n",
3289 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3290 device_printf(dev, "Receive errors = %lld\n",
3291 (long long)sc->stats.rxerrc);
3292 device_printf(dev, "Crc errors = %lld\n",
3293 (long long)sc->stats.crcerrs);
3294 device_printf(dev, "Alignment errors = %lld\n",
3295 (long long)sc->stats.algnerrc);
3296 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3297 (long long)sc->stats.cexterr);
3298 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3299 device_printf(dev, "watchdog timeouts = %ld\n",
3300 sc->watchdog_events);
3301 device_printf(dev, "XON Rcvd = %lld\n",
3302 (long long)sc->stats.xonrxc);
3303 device_printf(dev, "XON Xmtd = %lld\n",
3304 (long long)sc->stats.xontxc);
3305 device_printf(dev, "XOFF Rcvd = %lld\n",
3306 (long long)sc->stats.xoffrxc);
3307 device_printf(dev, "XOFF Xmtd = %lld\n",
3308 (long long)sc->stats.xofftxc);
3309 device_printf(dev, "Good Packets Rcvd = %lld\n",
3310 (long long)sc->stats.gprc);
3311 device_printf(dev, "Good Packets Xmtd = %lld\n",
3312 (long long)sc->stats.gptc);
3316 emx_print_nvm_info(struct emx_softc *sc)
3318 uint16_t eeprom_data;
3321 /* Its a bit crude, but it gets the job done */
3322 kprintf("\nInterface EEPROM Dump:\n");
3323 kprintf("Offset\n0x0000 ");
3324 for (i = 0, j = 0; i < 32; i++, j++) {
3325 if (j == 8) { /* Make the offset block */
3327 kprintf("\n0x00%x0 ",row);
3329 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3330 kprintf("%04x ", eeprom_data);
3336 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3338 struct emx_softc *sc;
3343 error = sysctl_handle_int(oidp, &result, 0, req);
3344 if (error || !req->newptr)
3347 sc = (struct emx_softc *)arg1;
3348 ifp = &sc->arpcom.ac_if;
3350 ifnet_serialize_all(ifp);
3353 emx_print_debug_info(sc);
3356 * This value will cause a hex dump of the
3357 * first 32 16-bit words of the EEPROM to
3361 emx_print_nvm_info(sc);
3363 ifnet_deserialize_all(ifp);
3369 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3374 error = sysctl_handle_int(oidp, &result, 0, req);
3375 if (error || !req->newptr)
3379 struct emx_softc *sc = (struct emx_softc *)arg1;
3380 struct ifnet *ifp = &sc->arpcom.ac_if;
3382 ifnet_serialize_all(ifp);
3383 emx_print_hw_stats(sc);
3384 ifnet_deserialize_all(ifp);
3390 emx_add_sysctl(struct emx_softc *sc)
3392 #ifdef EMX_RSS_DEBUG
3397 sysctl_ctx_init(&sc->sysctl_ctx);
3398 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3399 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3400 device_get_nameunit(sc->dev),
3402 if (sc->sysctl_tree == NULL) {
3403 device_printf(sc->dev, "can't add sysctl node\n");
3407 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3408 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3409 emx_sysctl_debug_info, "I", "Debug Information");
3411 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3412 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3413 emx_sysctl_stats, "I", "Statistics");
3415 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3416 OID_AUTO, "rxd", CTLFLAG_RD,
3417 &sc->rx_data[0].num_rx_desc, 0, NULL);
3418 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3419 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3421 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3422 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3423 sc, 0, emx_sysctl_int_throttle, "I",
3424 "interrupt throttling rate");
3425 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3426 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3427 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3428 "# segments per TX interrupt");
3430 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3431 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3432 &sc->rx_ring_cnt, 0, "RX ring count");
3434 #ifdef EMX_RSS_DEBUG
3435 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3436 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3437 0, "RSS debug level");
3438 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3439 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3440 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3441 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3443 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3449 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3451 struct emx_softc *sc = (void *)arg1;
3452 struct ifnet *ifp = &sc->arpcom.ac_if;
3453 int error, throttle;
3455 throttle = sc->int_throttle_ceil;
3456 error = sysctl_handle_int(oidp, &throttle, 0, req);
3457 if (error || req->newptr == NULL)
3459 if (throttle < 0 || throttle > 1000000000 / 256)
3464 * Set the interrupt throttling rate in 256ns increments,
3465 * recalculate sysctl value assignment to get exact frequency.
3467 throttle = 1000000000 / 256 / throttle;
3469 /* Upper 16bits of ITR is reserved and should be zero */
3470 if (throttle & 0xffff0000)
3474 ifnet_serialize_all(ifp);
3477 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3479 sc->int_throttle_ceil = 0;
3481 if (ifp->if_flags & IFF_RUNNING)
3482 emx_set_itr(sc, throttle);
3484 ifnet_deserialize_all(ifp);
3487 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3488 sc->int_throttle_ceil);
3494 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3496 struct emx_softc *sc = (void *)arg1;
3497 struct ifnet *ifp = &sc->arpcom.ac_if;
3500 segs = sc->tx_int_nsegs;
3501 error = sysctl_handle_int(oidp, &segs, 0, req);
3502 if (error || req->newptr == NULL)
3507 ifnet_serialize_all(ifp);
3510 * Don't allow int_tx_nsegs to become:
3511 * o Less the oact_tx_desc
3512 * o Too large that no TX desc will cause TX interrupt to
3513 * be generated (OACTIVE will never recover)
3514 * o Too small that will cause tx_dd[] overflow
3516 if (segs < sc->oact_tx_desc ||
3517 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3518 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3522 sc->tx_int_nsegs = segs;
3525 ifnet_deserialize_all(ifp);
3531 emx_dma_alloc(struct emx_softc *sc)
3536 * Create top level busdma tag
3538 error = bus_dma_tag_create(NULL, 1, 0,
3539 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3541 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3542 0, &sc->parent_dtag);
3544 device_printf(sc->dev, "could not create top level DMA tag\n");
3549 * Allocate transmit descriptors ring and buffers
3551 error = emx_create_tx_ring(sc);
3553 device_printf(sc->dev, "Could not setup transmit structures\n");
3558 * Allocate receive descriptors ring and buffers
3560 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3561 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3563 device_printf(sc->dev,
3564 "Could not setup receive structures\n");
3572 emx_dma_free(struct emx_softc *sc)
3576 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3578 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3579 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3580 sc->rx_data[i].num_rx_desc);
3583 /* Free top level busdma tag */
3584 if (sc->parent_dtag != NULL)
3585 bus_dma_tag_destroy(sc->parent_dtag);
3589 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3591 struct emx_softc *sc = ifp->if_softc;
3594 case IFNET_SERIALIZE_ALL:
3595 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0);
3598 case IFNET_SERIALIZE_MAIN:
3599 lwkt_serialize_enter(&sc->main_serialize);
3602 case IFNET_SERIALIZE_TX:
3603 lwkt_serialize_enter(&sc->tx_serialize);
3606 case IFNET_SERIALIZE_RX(0):
3607 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize);
3610 case IFNET_SERIALIZE_RX(1):
3611 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize);
3615 panic("%s unsupported serialize type\n", ifp->if_xname);
3620 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3622 struct emx_softc *sc = ifp->if_softc;
3625 case IFNET_SERIALIZE_ALL:
3626 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0);
3629 case IFNET_SERIALIZE_MAIN:
3630 lwkt_serialize_exit(&sc->main_serialize);
3633 case IFNET_SERIALIZE_TX:
3634 lwkt_serialize_exit(&sc->tx_serialize);
3637 case IFNET_SERIALIZE_RX(0):
3638 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize);
3641 case IFNET_SERIALIZE_RX(1):
3642 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize);
3646 panic("%s unsupported serialize type\n", ifp->if_xname);
3651 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3653 struct emx_softc *sc = ifp->if_softc;
3656 case IFNET_SERIALIZE_ALL:
3657 return lwkt_serialize_array_try(sc->serializes,
3660 case IFNET_SERIALIZE_MAIN:
3661 return lwkt_serialize_try(&sc->main_serialize);
3663 case IFNET_SERIALIZE_TX:
3664 return lwkt_serialize_try(&sc->tx_serialize);
3666 case IFNET_SERIALIZE_RX(0):
3667 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize);
3669 case IFNET_SERIALIZE_RX(1):
3670 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize);
3673 panic("%s unsupported serialize type\n", ifp->if_xname);
3678 emx_serialize_skipmain(struct emx_softc *sc)
3680 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3684 emx_deserialize_skipmain(struct emx_softc *sc)
3686 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3692 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3693 boolean_t serialized)
3695 struct emx_softc *sc = ifp->if_softc;
3699 case IFNET_SERIALIZE_ALL:
3701 for (i = 0; i < EMX_NSERIALIZE; ++i)
3702 ASSERT_SERIALIZED(sc->serializes[i]);
3704 for (i = 0; i < EMX_NSERIALIZE; ++i)
3705 ASSERT_NOT_SERIALIZED(sc->serializes[i]);
3709 case IFNET_SERIALIZE_MAIN:
3711 ASSERT_SERIALIZED(&sc->main_serialize);
3713 ASSERT_NOT_SERIALIZED(&sc->main_serialize);
3716 case IFNET_SERIALIZE_TX:
3718 ASSERT_SERIALIZED(&sc->tx_serialize);
3720 ASSERT_NOT_SERIALIZED(&sc->tx_serialize);
3723 case IFNET_SERIALIZE_RX(0):
3725 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3727 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3730 case IFNET_SERIALIZE_RX(1):
3732 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3734 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3738 panic("%s unsupported serialize type\n", ifp->if_xname);
3742 #endif /* INVARIANTS */
3744 #ifdef IFPOLL_ENABLE
3747 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3749 struct emx_softc *sc = ifp->if_softc;
3752 ASSERT_SERIALIZED(&sc->main_serialize);
3754 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3755 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3756 emx_serialize_skipmain(sc);
3758 callout_stop(&sc->timer);
3759 sc->hw.mac.get_link_status = 1;
3760 emx_update_link_status(sc);
3761 callout_reset(&sc->timer, hz, emx_timer, sc);
3763 emx_deserialize_skipmain(sc);
3768 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3770 struct emx_softc *sc = ifp->if_softc;
3772 ASSERT_SERIALIZED(&sc->tx_serialize);
3775 if (!ifq_is_empty(&ifp->if_snd))
3780 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3782 struct emx_softc *sc = ifp->if_softc;
3783 struct emx_rxdata *rdata = arg;
3785 ASSERT_SERIALIZED(&rdata->rx_serialize);
3787 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3791 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3793 struct emx_softc *sc = ifp->if_softc;
3795 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3800 info->ifpi_status.status_func = emx_qpoll_status;
3801 info->ifpi_status.serializer = &sc->main_serialize;
3803 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3804 info->ifpi_tx[0].arg = NULL;
3805 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3807 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3808 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3809 info->ifpi_rx[i].arg = &sc->rx_data[i];
3810 info->ifpi_rx[i].serializer =
3811 &sc->rx_data[i].rx_serialize;
3814 if (ifp->if_flags & IFF_RUNNING)
3815 emx_disable_intr(sc);
3816 } else if (ifp->if_flags & IFF_RUNNING) {
3817 emx_enable_intr(sc);
3821 #endif /* IFPOLL_ENABLE */
3824 emx_set_itr(struct emx_softc *sc, uint32_t itr)
3826 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3827 if (sc->hw.mac.type == e1000_82574) {
3831 * When using MSIX interrupts we need to
3832 * throttle using the EITR register
3834 for (i = 0; i < 4; ++i)
3835 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
3840 * Disable the L0s, 82574L Errata #20
3843 emx_disable_aspm(struct emx_softc *sc)
3845 uint16_t link_cap, link_ctrl;
3846 uint8_t pcie_ptr, reg;
3847 device_t dev = sc->dev;
3849 switch (sc->hw.mac.type) {
3858 pcie_ptr = pci_get_pciecap_ptr(dev);
3862 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
3863 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
3867 if_printf(&sc->arpcom.ac_if, "disable L0s\n");
3869 reg = pcie_ptr + PCIER_LINKCTRL;
3870 link_ctrl = pci_read_config(dev, reg, 2);
3871 link_ctrl &= ~PCIEM_LNKCTL_ASPM_L0S;
3872 pci_write_config(dev, reg, link_ctrl, 2);