2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs *ring)
39 struct drm_device *dev = ring->dev;
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
50 return ring->buffer && ring->buffer->obj;
53 int __intel_ring_space(int head, int tail, int size)
55 int space = head - tail;
58 return space - I915_RING_FREE_SPACE;
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
84 void __intel_ring_advance(struct intel_engine_cs *ring)
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
90 ring->write_tail(ring, ringbuf->tail);
94 gen2_render_ring_flush(struct intel_engine_cs *ring,
95 u32 invalidate_domains,
102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
103 cmd |= MI_NO_WRITE_FLUSH;
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
108 ret = intel_ring_begin(ring, 2);
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
120 gen4_render_ring_flush(struct intel_engine_cs *ring,
121 u32 invalidate_domains,
124 struct drm_device *dev = ring->dev;
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
140 * I915_GEM_DOMAIN_COMMAND may not exist?
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
158 cmd &= ~MI_NO_WRITE_FLUSH;
159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
166 ret = intel_ring_begin(ring, 2);
170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
190 * And the workaround for these two requires this workaround first:
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
221 ret = intel_ring_begin(ring, 6);
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
234 ret = intel_ring_begin(ring, 6);
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
250 gen6_render_ring_flush(struct intel_engine_cs *ring,
251 u32 invalidate_domains, u32 flush_domains)
254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
273 flags |= PIPE_CONTROL_CS_STALL;
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
283 * TLB invalidate requires a post-sync write.
285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
288 ret = intel_ring_begin(ring, 4);
292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
295 intel_ring_emit(ring, 0);
296 intel_ring_advance(ring);
302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
306 ret = intel_ring_begin(ring, 4);
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
321 gen7_render_ring_flush(struct intel_engine_cs *ring,
322 u32 invalidate_domains, u32 flush_domains)
325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
329 * Ensure that any following seqno writes only happen when the render
330 * cache is indeed flushed.
332 * Workaround: 4th PIPE_CONTROL command (except the ones with only
333 * read-cache invalidate bits set) must have the CS_STALL bit set. We
334 * don't try to be clever and just set it unconditionally.
336 flags |= PIPE_CONTROL_CS_STALL;
338 /* Just flush everything. Experiments have shown that reducing the
339 * number of bits based on the write domains has little performance
343 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
344 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
346 if (invalidate_domains) {
347 flags |= PIPE_CONTROL_TLB_INVALIDATE;
348 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
349 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
353 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
355 * TLB invalidate requires a post-sync write.
357 flags |= PIPE_CONTROL_QW_WRITE;
358 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
360 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
362 /* Workaround: we must issue a pipe_control with CS-stall bit
363 * set before a pipe_control command that has the state cache
364 * invalidate bit set. */
365 gen7_render_ring_cs_stall_wa(ring);
368 ret = intel_ring_begin(ring, 4);
372 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
373 intel_ring_emit(ring, flags);
374 intel_ring_emit(ring, scratch_addr);
375 intel_ring_emit(ring, 0);
376 intel_ring_advance(ring);
382 gen8_emit_pipe_control(struct intel_engine_cs *ring,
383 u32 flags, u32 scratch_addr)
387 ret = intel_ring_begin(ring, 6);
391 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
392 intel_ring_emit(ring, flags);
393 intel_ring_emit(ring, scratch_addr);
394 intel_ring_emit(ring, 0);
395 intel_ring_emit(ring, 0);
396 intel_ring_emit(ring, 0);
397 intel_ring_advance(ring);
403 gen8_render_ring_flush(struct intel_engine_cs *ring,
404 u32 invalidate_domains, u32 flush_domains)
407 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
410 flags |= PIPE_CONTROL_CS_STALL;
413 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
414 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
416 if (invalidate_domains) {
417 flags |= PIPE_CONTROL_TLB_INVALIDATE;
418 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
419 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
420 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
421 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
422 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
423 flags |= PIPE_CONTROL_QW_WRITE;
424 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
426 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
427 ret = gen8_emit_pipe_control(ring,
428 PIPE_CONTROL_CS_STALL |
429 PIPE_CONTROL_STALL_AT_SCOREBOARD,
435 return gen8_emit_pipe_control(ring, flags, scratch_addr);
438 static void ring_write_tail(struct intel_engine_cs *ring,
441 struct drm_i915_private *dev_priv = ring->dev->dev_private;
442 I915_WRITE_TAIL(ring, value);
445 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
450 if (INTEL_INFO(ring->dev)->gen >= 8)
451 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
452 RING_ACTHD_UDW(ring->mmio_base));
453 else if (INTEL_INFO(ring->dev)->gen >= 4)
454 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
456 acthd = I915_READ(ACTHD);
461 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
463 struct drm_i915_private *dev_priv = ring->dev->dev_private;
466 addr = dev_priv->status_page_dmah->busaddr;
467 if (INTEL_INFO(ring->dev)->gen >= 4)
468 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
469 I915_WRITE(HWS_PGA, addr);
472 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
474 struct drm_device *dev = ring->dev;
475 struct drm_i915_private *dev_priv = ring->dev->dev_private;
478 /* The ring status page addresses are no longer next to the rest of
479 * the ring registers as of gen7.
484 mmio = RENDER_HWS_PGA_GEN7;
487 mmio = BLT_HWS_PGA_GEN7;
490 * VCS2 actually doesn't exist on Gen7. Only shut up
491 * gcc switch check warning
495 mmio = BSD_HWS_PGA_GEN7;
498 mmio = VEBOX_HWS_PGA_GEN7;
501 } else if (IS_GEN6(ring->dev)) {
502 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
504 /* XXX: gen8 returns to sanity */
505 mmio = RING_HWS_PGA(ring->mmio_base);
508 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
512 * Flush the TLB for this page
514 * FIXME: These two bits have disappeared on gen8, so a question
515 * arises: do we still need this and if so how should we go about
516 * invalidating the TLB?
518 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
519 u32 reg = RING_INSTPM(ring->mmio_base);
521 /* ring should be idle before issuing a sync flush*/
522 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
525 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
527 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
529 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
534 static bool stop_ring(struct intel_engine_cs *ring)
536 struct drm_i915_private *dev_priv = to_i915(ring->dev);
538 if (!IS_GEN2(ring->dev)) {
539 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
540 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
541 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
542 /* Sometimes we observe that the idle flag is not
543 * set even though the ring is empty. So double
544 * check before giving up.
546 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
551 I915_WRITE_CTL(ring, 0);
552 I915_WRITE_HEAD(ring, 0);
553 ring->write_tail(ring, 0);
555 if (!IS_GEN2(ring->dev)) {
556 (void)I915_READ_CTL(ring);
557 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
560 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
563 static int init_ring_common(struct intel_engine_cs *ring)
565 struct drm_device *dev = ring->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct intel_ringbuffer *ringbuf = ring->buffer;
568 struct drm_i915_gem_object *obj = ringbuf->obj;
571 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
573 if (!stop_ring(ring)) {
574 /* G45 ring initialization often fails to reset head to zero */
575 DRM_DEBUG_KMS("%s head not reset to zero "
576 "ctl %08x head %08x tail %08x start %08x\n",
579 I915_READ_HEAD(ring),
580 I915_READ_TAIL(ring),
581 I915_READ_START(ring));
583 if (!stop_ring(ring)) {
584 DRM_ERROR("failed to set %s head to zero "
585 "ctl %08x head %08x tail %08x start %08x\n",
588 I915_READ_HEAD(ring),
589 I915_READ_TAIL(ring),
590 I915_READ_START(ring));
596 if (I915_NEED_GFX_HWS(dev))
597 intel_ring_setup_status_page(ring);
599 ring_setup_phys_status_page(ring);
601 /* Enforce ordering by reading HEAD register back */
602 I915_READ_HEAD(ring);
604 /* Initialize the ring. This must happen _after_ we've cleared the ring
605 * registers with the above sequence (the readback of the HEAD registers
606 * also enforces ordering), otherwise the hw might lose the new ring
607 * register values. */
608 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
610 /* WaClearRingBufHeadRegAtInit:ctg,elk */
611 if (I915_READ_HEAD(ring))
612 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
613 ring->name, I915_READ_HEAD(ring));
614 I915_WRITE_HEAD(ring, 0);
615 (void)I915_READ_HEAD(ring);
618 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
621 /* If the head is still not zero, the ring is dead */
622 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
623 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
624 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
625 DRM_ERROR("%s initialization failed "
626 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
628 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
629 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
630 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
635 ringbuf->last_retired_head = -1;
636 ringbuf->head = I915_READ_HEAD(ring);
637 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
638 intel_ring_update_space(ringbuf);
640 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
643 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
649 intel_fini_pipe_control(struct intel_engine_cs *ring)
651 struct drm_device *dev = ring->dev;
653 if (ring->scratch.obj == NULL)
656 if (INTEL_INFO(dev)->gen >= 5) {
657 kunmap(ring->scratch.obj->pages[0]);
658 i915_gem_object_ggtt_unpin(ring->scratch.obj);
661 drm_gem_object_unreference(&ring->scratch.obj->base);
662 ring->scratch.obj = NULL;
666 intel_init_pipe_control(struct intel_engine_cs *ring)
670 WARN_ON(ring->scratch.obj);
672 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
673 if (ring->scratch.obj == NULL) {
674 DRM_ERROR("Failed to allocate seqno page\n");
679 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
683 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
687 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
688 ring->scratch.cpu_page = kmap(ring->scratch.obj->pages[0]);
689 if (ring->scratch.cpu_page == NULL) {
694 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
695 ring->name, ring->scratch.gtt_offset);
699 i915_gem_object_ggtt_unpin(ring->scratch.obj);
701 drm_gem_object_unreference(&ring->scratch.obj->base);
706 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
707 struct intel_context *ctx)
710 struct drm_device *dev = ring->dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
712 struct i915_workarounds *w = &dev_priv->workarounds;
714 if (WARN_ON_ONCE(w->count == 0))
717 ring->gpu_caches_dirty = true;
718 ret = intel_ring_flush_all_caches(ring);
722 ret = intel_ring_begin(ring, (w->count * 2 + 2));
726 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
727 for (i = 0; i < w->count; i++) {
728 intel_ring_emit(ring, w->reg[i].addr);
729 intel_ring_emit(ring, w->reg[i].value);
731 intel_ring_emit(ring, MI_NOOP);
733 intel_ring_advance(ring);
735 ring->gpu_caches_dirty = true;
736 ret = intel_ring_flush_all_caches(ring);
740 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
745 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
746 struct intel_context *ctx)
750 ret = intel_ring_workarounds_emit(ring, ctx);
754 ret = i915_gem_render_state_init(ring);
756 DRM_ERROR("init render state: %d\n", ret);
761 static int wa_add(struct drm_i915_private *dev_priv,
762 const u32 addr, const u32 mask, const u32 val)
764 const u32 idx = dev_priv->workarounds.count;
766 if (WARN_ON(idx >= I915_MAX_WA_REGS))
769 dev_priv->workarounds.reg[idx].addr = addr;
770 dev_priv->workarounds.reg[idx].value = val;
771 dev_priv->workarounds.reg[idx].mask = mask;
773 dev_priv->workarounds.count++;
778 #define WA_REG(addr, mask, val) { \
779 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
784 #define WA_SET_BIT_MASKED(addr, mask) \
785 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
787 #define WA_CLR_BIT_MASKED(addr, mask) \
788 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
790 #define WA_SET_FIELD_MASKED(addr, mask, value) \
791 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
793 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
794 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
796 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
798 static int bdw_init_workarounds(struct intel_engine_cs *ring)
800 struct drm_device *dev = ring->dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
803 /* WaDisablePartialInstShootdown:bdw */
804 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
805 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
806 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
807 STALL_DOP_GATING_DISABLE);
809 /* WaDisableDopClockGating:bdw */
810 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
811 DOP_CLOCK_GATING_DISABLE);
813 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
814 GEN8_SAMPLER_POWER_BYPASS_DIS);
816 /* Use Force Non-Coherent whenever executing a 3D context. This is a
817 * workaround for for a possible hang in the unlikely event a TLB
818 * invalidation occurs during a PSD flush.
820 WA_SET_BIT_MASKED(HDC_CHICKEN0,
821 /* WaForceEnableNonCoherent:bdw */
822 HDC_FORCE_NON_COHERENT |
823 /* WaForceContextSaveRestoreNonCoherent:bdw */
824 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
825 /* WaHdcDisableFetchWhenMasked:bdw */
826 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
827 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
828 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
830 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
831 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
832 * polygons in the same 8x4 pixel/sample area to be processed without
833 * stalling waiting for the earlier ones to write to Hierarchical Z
836 * This optimization is off by default for Broadwell; turn it on.
838 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
840 /* Wa4x4STCOptimizationDisable:bdw */
841 WA_SET_BIT_MASKED(CACHE_MODE_1,
842 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
845 * BSpec recommends 8x4 when MSAA is used,
846 * however in practice 16x4 seems fastest.
848 * Note that PS/WM thread counts depend on the WIZ hashing
849 * disable bit, which we don't touch here, but it's good
850 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
852 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
853 GEN6_WIZ_HASHING_MASK,
854 GEN6_WIZ_HASHING_16x4);
859 static int chv_init_workarounds(struct intel_engine_cs *ring)
861 struct drm_device *dev = ring->dev;
862 struct drm_i915_private *dev_priv = dev->dev_private;
864 /* WaDisablePartialInstShootdown:chv */
865 /* WaDisableThreadStallDopClockGating:chv */
866 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
867 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
868 STALL_DOP_GATING_DISABLE);
870 /* Use Force Non-Coherent whenever executing a 3D context. This is a
871 * workaround for a possible hang in the unlikely event a TLB
872 * invalidation occurs during a PSD flush.
874 /* WaForceEnableNonCoherent:chv */
875 /* WaHdcDisableFetchWhenMasked:chv */
876 WA_SET_BIT_MASKED(HDC_CHICKEN0,
877 HDC_FORCE_NON_COHERENT |
878 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
880 /* According to the CACHE_MODE_0 default value documentation, some
881 * CHV platforms disable this optimization by default. Turn it on.
883 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
885 /* Wa4x4STCOptimizationDisable:chv */
886 WA_SET_BIT_MASKED(CACHE_MODE_1,
887 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
889 /* Improve HiZ throughput on CHV. */
890 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
893 * BSpec recommends 8x4 when MSAA is used,
894 * however in practice 16x4 seems fastest.
896 * Note that PS/WM thread counts depend on the WIZ hashing
897 * disable bit, which we don't touch here, but it's good
898 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
900 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
901 GEN6_WIZ_HASHING_MASK,
902 GEN6_WIZ_HASHING_16x4);
907 static int gen9_init_workarounds(struct intel_engine_cs *ring)
909 struct drm_device *dev = ring->dev;
910 struct drm_i915_private *dev_priv = dev->dev_private;
913 /* WaDisablePartialInstShootdown:skl,bxt */
914 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
915 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
917 /* Syncing dependencies between camera and graphics:skl,bxt */
918 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
919 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
921 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
922 INTEL_REVID(dev) == SKL_REVID_B0)) ||
923 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
924 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
925 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
926 GEN9_DG_MIRROR_FIX_ENABLE);
929 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
930 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
931 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
932 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
933 GEN9_RHWO_OPTIMIZATION_DISABLE);
934 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
935 DISABLE_PIXEL_MASK_CAMMING);
938 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
940 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
941 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
942 GEN9_ENABLE_YV12_BUGFIX);
945 /* Wa4x4STCOptimizationDisable:skl,bxt */
946 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
948 /* WaDisablePartialResolveInVc:skl,bxt */
949 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
951 /* WaCcsTlbPrefetchDisable:skl,bxt */
952 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
953 GEN9_CCS_TLB_PREFETCH_ENABLE);
955 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
956 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
957 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
958 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
959 PIXEL_MASK_CAMMING_DISABLE);
961 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
962 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
963 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
964 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
965 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
966 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
971 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
973 struct drm_device *dev = ring->dev;
974 struct drm_i915_private *dev_priv = dev->dev_private;
975 u8 vals[3] = { 0, 0, 0 };
978 for (i = 0; i < 3; i++) {
982 * Only consider slices where one, and only one, subslice has 7
985 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
989 * subslice_7eu[i] != 0 (because of the check above) and
990 * ss_max == 4 (maximum number of subslices possible per slice)
994 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
998 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1001 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1002 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1003 GEN9_IZ_HASHING_MASK(2) |
1004 GEN9_IZ_HASHING_MASK(1) |
1005 GEN9_IZ_HASHING_MASK(0),
1006 GEN9_IZ_HASHING(2, vals[2]) |
1007 GEN9_IZ_HASHING(1, vals[1]) |
1008 GEN9_IZ_HASHING(0, vals[0]));
1014 static int skl_init_workarounds(struct intel_engine_cs *ring)
1016 struct drm_device *dev = ring->dev;
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1019 gen9_init_workarounds(ring);
1021 /* WaDisablePowerCompilerClockGating:skl */
1022 if (INTEL_REVID(dev) == SKL_REVID_B0)
1023 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1024 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1026 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1027 INTEL_REVID(dev) == SKL_REVID_D0)
1028 /* WaBarrierPerformanceFixDisable:skl */
1029 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1030 HDC_FENCE_DEST_SLM_DISABLE |
1031 HDC_BARRIER_PERFORMANCE_DISABLE);
1033 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1035 *Use Force Non-Coherent whenever executing a 3D context. This
1036 * is a workaround for a possible hang in the unlikely event
1037 * a TLB invalidation occurs during a PSD flush.
1039 /* WaForceEnableNonCoherent:skl */
1040 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1041 HDC_FORCE_NON_COHERENT);
1044 return skl_tune_iz_hashing(ring);
1047 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1049 struct drm_device *dev = ring->dev;
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1052 gen9_init_workarounds(ring);
1054 /* WaDisableThreadStallDopClockGating:bxt */
1055 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1056 STALL_DOP_GATING_DISABLE);
1058 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1059 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1061 GEN7_HALF_SLICE_CHICKEN1,
1062 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1068 int init_workarounds_ring(struct intel_engine_cs *ring)
1070 struct drm_device *dev = ring->dev;
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1073 WARN_ON(ring->id != RCS);
1075 dev_priv->workarounds.count = 0;
1077 if (IS_BROADWELL(dev))
1078 return bdw_init_workarounds(ring);
1080 if (IS_CHERRYVIEW(dev))
1081 return chv_init_workarounds(ring);
1083 if (IS_SKYLAKE(dev))
1084 return skl_init_workarounds(ring);
1086 if (IS_BROXTON(dev))
1087 return bxt_init_workarounds(ring);
1092 static int init_render_ring(struct intel_engine_cs *ring)
1094 struct drm_device *dev = ring->dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 int ret = init_ring_common(ring);
1100 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1101 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1102 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1104 /* We need to disable the AsyncFlip performance optimisations in order
1105 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1106 * programmed to '1' on all products.
1108 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1110 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1111 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1113 /* Required for the hardware to program scanline values for waiting */
1114 /* WaEnableFlushTlbInvalidationMode:snb */
1115 if (INTEL_INFO(dev)->gen == 6)
1116 I915_WRITE(GFX_MODE,
1117 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1119 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1121 I915_WRITE(GFX_MODE_GEN7,
1122 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1123 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1126 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1127 * "If this bit is set, STCunit will have LRA as replacement
1128 * policy. [...] This bit must be reset. LRA replacement
1129 * policy is not supported."
1131 I915_WRITE(CACHE_MODE_0,
1132 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1135 if (INTEL_INFO(dev)->gen >= 6)
1136 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1138 if (HAS_L3_DPF(dev))
1139 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1141 return init_workarounds_ring(ring);
1144 static void render_ring_cleanup(struct intel_engine_cs *ring)
1146 struct drm_device *dev = ring->dev;
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1149 if (dev_priv->semaphore_obj) {
1150 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1151 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1152 dev_priv->semaphore_obj = NULL;
1155 intel_fini_pipe_control(ring);
1158 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1159 unsigned int num_dwords)
1161 #define MBOX_UPDATE_DWORDS 8
1162 struct drm_device *dev = signaller->dev;
1163 struct drm_i915_private *dev_priv = dev->dev_private;
1164 struct intel_engine_cs *waiter;
1165 int i, ret, num_rings;
1167 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1168 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1169 #undef MBOX_UPDATE_DWORDS
1171 ret = intel_ring_begin(signaller, num_dwords);
1175 for_each_ring(waiter, dev_priv, i) {
1177 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1178 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1181 seqno = i915_gem_request_get_seqno(
1182 signaller->outstanding_lazy_request);
1183 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1184 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1185 PIPE_CONTROL_QW_WRITE |
1186 PIPE_CONTROL_FLUSH_ENABLE);
1187 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1188 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1189 intel_ring_emit(signaller, seqno);
1190 intel_ring_emit(signaller, 0);
1191 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1192 MI_SEMAPHORE_TARGET(waiter->id));
1193 intel_ring_emit(signaller, 0);
1199 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1200 unsigned int num_dwords)
1202 #define MBOX_UPDATE_DWORDS 6
1203 struct drm_device *dev = signaller->dev;
1204 struct drm_i915_private *dev_priv = dev->dev_private;
1205 struct intel_engine_cs *waiter;
1206 int i, ret, num_rings;
1208 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1209 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1210 #undef MBOX_UPDATE_DWORDS
1212 ret = intel_ring_begin(signaller, num_dwords);
1216 for_each_ring(waiter, dev_priv, i) {
1218 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1219 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1222 seqno = i915_gem_request_get_seqno(
1223 signaller->outstanding_lazy_request);
1224 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1225 MI_FLUSH_DW_OP_STOREDW);
1226 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1227 MI_FLUSH_DW_USE_GTT);
1228 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1229 intel_ring_emit(signaller, seqno);
1230 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1231 MI_SEMAPHORE_TARGET(waiter->id));
1232 intel_ring_emit(signaller, 0);
1238 static int gen6_signal(struct intel_engine_cs *signaller,
1239 unsigned int num_dwords)
1241 struct drm_device *dev = signaller->dev;
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 struct intel_engine_cs *useless;
1244 int i, ret, num_rings;
1246 #define MBOX_UPDATE_DWORDS 3
1247 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1248 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1249 #undef MBOX_UPDATE_DWORDS
1251 ret = intel_ring_begin(signaller, num_dwords);
1255 for_each_ring(useless, dev_priv, i) {
1256 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1257 if (mbox_reg != GEN6_NOSYNC) {
1258 u32 seqno = i915_gem_request_get_seqno(
1259 signaller->outstanding_lazy_request);
1260 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1261 intel_ring_emit(signaller, mbox_reg);
1262 intel_ring_emit(signaller, seqno);
1266 /* If num_dwords was rounded, make sure the tail pointer is correct */
1267 if (num_rings % 2 == 0)
1268 intel_ring_emit(signaller, MI_NOOP);
1274 * gen6_add_request - Update the semaphore mailbox registers
1276 * @ring - ring that is adding a request
1277 * @seqno - return seqno stuck into the ring
1279 * Update the mailbox registers in the *other* rings with the current seqno.
1280 * This acts like a signal in the canonical semaphore.
1283 gen6_add_request(struct intel_engine_cs *ring)
1287 if (ring->semaphore.signal)
1288 ret = ring->semaphore.signal(ring, 4);
1290 ret = intel_ring_begin(ring, 4);
1295 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1296 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1297 intel_ring_emit(ring,
1298 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1299 intel_ring_emit(ring, MI_USER_INTERRUPT);
1300 __intel_ring_advance(ring);
1305 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1308 struct drm_i915_private *dev_priv = dev->dev_private;
1309 return dev_priv->last_seqno < seqno;
1313 * intel_ring_sync - sync the waiter to the signaller on seqno
1315 * @waiter - ring that is waiting
1316 * @signaller - ring which has, or will signal
1317 * @seqno - seqno which the waiter will block on
1321 gen8_ring_sync(struct intel_engine_cs *waiter,
1322 struct intel_engine_cs *signaller,
1325 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1328 ret = intel_ring_begin(waiter, 4);
1332 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1333 MI_SEMAPHORE_GLOBAL_GTT |
1335 MI_SEMAPHORE_SAD_GTE_SDD);
1336 intel_ring_emit(waiter, seqno);
1337 intel_ring_emit(waiter,
1338 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1339 intel_ring_emit(waiter,
1340 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1341 intel_ring_advance(waiter);
1346 gen6_ring_sync(struct intel_engine_cs *waiter,
1347 struct intel_engine_cs *signaller,
1350 u32 dw1 = MI_SEMAPHORE_MBOX |
1351 MI_SEMAPHORE_COMPARE |
1352 MI_SEMAPHORE_REGISTER;
1353 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1356 /* Throughout all of the GEM code, seqno passed implies our current
1357 * seqno is >= the last seqno executed. However for hardware the
1358 * comparison is strictly greater than.
1362 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1364 ret = intel_ring_begin(waiter, 4);
1368 /* If seqno wrap happened, omit the wait with no-ops */
1369 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1370 intel_ring_emit(waiter, dw1 | wait_mbox);
1371 intel_ring_emit(waiter, seqno);
1372 intel_ring_emit(waiter, 0);
1373 intel_ring_emit(waiter, MI_NOOP);
1375 intel_ring_emit(waiter, MI_NOOP);
1376 intel_ring_emit(waiter, MI_NOOP);
1377 intel_ring_emit(waiter, MI_NOOP);
1378 intel_ring_emit(waiter, MI_NOOP);
1380 intel_ring_advance(waiter);
1385 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1387 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1388 PIPE_CONTROL_DEPTH_STALL); \
1389 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1390 intel_ring_emit(ring__, 0); \
1391 intel_ring_emit(ring__, 0); \
1395 pc_render_add_request(struct intel_engine_cs *ring)
1397 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1400 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1401 * incoherent with writes to memory, i.e. completely fubar,
1402 * so we need to use PIPE_NOTIFY instead.
1404 * However, we also need to workaround the qword write
1405 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1406 * memory before requesting an interrupt.
1408 ret = intel_ring_begin(ring, 32);
1412 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1413 PIPE_CONTROL_WRITE_FLUSH |
1414 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1415 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1416 intel_ring_emit(ring,
1417 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1418 intel_ring_emit(ring, 0);
1419 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1420 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1421 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1422 scratch_addr += 2 * CACHELINE_BYTES;
1423 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1424 scratch_addr += 2 * CACHELINE_BYTES;
1425 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1426 scratch_addr += 2 * CACHELINE_BYTES;
1427 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1428 scratch_addr += 2 * CACHELINE_BYTES;
1429 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1431 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1432 PIPE_CONTROL_WRITE_FLUSH |
1433 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1434 PIPE_CONTROL_NOTIFY);
1435 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1436 intel_ring_emit(ring,
1437 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1438 intel_ring_emit(ring, 0);
1439 __intel_ring_advance(ring);
1445 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1447 /* Workaround to force correct ordering between irq and seqno writes on
1448 * ivb (and maybe also on snb) by reading from a CS register (like
1449 * ACTHD) before reading the status page. */
1450 if (!lazy_coherency) {
1451 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1452 POSTING_READ(RING_ACTHD(ring->mmio_base));
1455 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1459 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1461 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1465 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1467 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1471 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1473 return ring->scratch.cpu_page[0];
1477 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1479 ring->scratch.cpu_page[0] = seqno;
1483 gen5_ring_get_irq(struct intel_engine_cs *ring)
1485 struct drm_device *dev = ring->dev;
1486 struct drm_i915_private *dev_priv = dev->dev_private;
1488 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1491 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1492 if (ring->irq_refcount++ == 0)
1493 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1494 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1500 gen5_ring_put_irq(struct intel_engine_cs *ring)
1502 struct drm_device *dev = ring->dev;
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1505 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1506 if (--ring->irq_refcount == 0)
1507 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1508 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1512 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1514 struct drm_device *dev = ring->dev;
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1517 if (!intel_irqs_enabled(dev_priv))
1520 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1521 if (ring->irq_refcount++ == 0) {
1522 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1523 I915_WRITE(IMR, dev_priv->irq_mask);
1526 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1532 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1534 struct drm_device *dev = ring->dev;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1537 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1538 if (--ring->irq_refcount == 0) {
1539 dev_priv->irq_mask |= ring->irq_enable_mask;
1540 I915_WRITE(IMR, dev_priv->irq_mask);
1543 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1547 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1549 struct drm_device *dev = ring->dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1552 if (!intel_irqs_enabled(dev_priv))
1555 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1556 if (ring->irq_refcount++ == 0) {
1557 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1558 I915_WRITE16(IMR, dev_priv->irq_mask);
1559 POSTING_READ16(IMR);
1561 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1567 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1569 struct drm_device *dev = ring->dev;
1570 struct drm_i915_private *dev_priv = dev->dev_private;
1572 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1573 if (--ring->irq_refcount == 0) {
1574 dev_priv->irq_mask |= ring->irq_enable_mask;
1575 I915_WRITE16(IMR, dev_priv->irq_mask);
1576 POSTING_READ16(IMR);
1578 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1582 bsd_ring_flush(struct intel_engine_cs *ring,
1583 u32 invalidate_domains,
1588 ret = intel_ring_begin(ring, 2);
1592 intel_ring_emit(ring, MI_FLUSH);
1593 intel_ring_emit(ring, MI_NOOP);
1594 intel_ring_advance(ring);
1599 i9xx_add_request(struct intel_engine_cs *ring)
1603 ret = intel_ring_begin(ring, 4);
1607 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1608 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1609 intel_ring_emit(ring,
1610 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1611 intel_ring_emit(ring, MI_USER_INTERRUPT);
1612 __intel_ring_advance(ring);
1618 gen6_ring_get_irq(struct intel_engine_cs *ring)
1620 struct drm_device *dev = ring->dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1623 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1626 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1627 if (ring->irq_refcount++ == 0) {
1628 if (HAS_L3_DPF(dev) && ring->id == RCS)
1629 I915_WRITE_IMR(ring,
1630 ~(ring->irq_enable_mask |
1631 GT_PARITY_ERROR(dev)));
1633 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1634 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1636 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1642 gen6_ring_put_irq(struct intel_engine_cs *ring)
1644 struct drm_device *dev = ring->dev;
1645 struct drm_i915_private *dev_priv = dev->dev_private;
1647 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1648 if (--ring->irq_refcount == 0) {
1649 if (HAS_L3_DPF(dev) && ring->id == RCS)
1650 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1652 I915_WRITE_IMR(ring, ~0);
1653 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1655 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1659 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1661 struct drm_device *dev = ring->dev;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1664 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1667 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1668 if (ring->irq_refcount++ == 0) {
1669 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1670 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1672 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1678 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1680 struct drm_device *dev = ring->dev;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1683 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1684 if (--ring->irq_refcount == 0) {
1685 I915_WRITE_IMR(ring, ~0);
1686 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1688 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1692 gen8_ring_get_irq(struct intel_engine_cs *ring)
1694 struct drm_device *dev = ring->dev;
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1697 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1700 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1701 if (ring->irq_refcount++ == 0) {
1702 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1703 I915_WRITE_IMR(ring,
1704 ~(ring->irq_enable_mask |
1705 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1707 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1709 POSTING_READ(RING_IMR(ring->mmio_base));
1711 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1717 gen8_ring_put_irq(struct intel_engine_cs *ring)
1719 struct drm_device *dev = ring->dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1722 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1723 if (--ring->irq_refcount == 0) {
1724 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1725 I915_WRITE_IMR(ring,
1726 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1728 I915_WRITE_IMR(ring, ~0);
1730 POSTING_READ(RING_IMR(ring->mmio_base));
1732 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1736 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1737 u64 offset, u32 length,
1738 unsigned dispatch_flags)
1742 ret = intel_ring_begin(ring, 2);
1746 intel_ring_emit(ring,
1747 MI_BATCH_BUFFER_START |
1749 (dispatch_flags & I915_DISPATCH_SECURE ?
1750 0 : MI_BATCH_NON_SECURE_I965));
1751 intel_ring_emit(ring, offset);
1752 intel_ring_advance(ring);
1757 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1758 #define I830_BATCH_LIMIT (256*1024)
1759 #define I830_TLB_ENTRIES (2)
1760 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1762 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1763 u64 offset, u32 len,
1764 unsigned dispatch_flags)
1766 u32 cs_offset = ring->scratch.gtt_offset;
1769 ret = intel_ring_begin(ring, 6);
1773 /* Evict the invalid PTE TLBs */
1774 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1775 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1776 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1777 intel_ring_emit(ring, cs_offset);
1778 intel_ring_emit(ring, 0xdeadbeef);
1779 intel_ring_emit(ring, MI_NOOP);
1780 intel_ring_advance(ring);
1782 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1783 if (len > I830_BATCH_LIMIT)
1786 ret = intel_ring_begin(ring, 6 + 2);
1790 /* Blit the batch (which has now all relocs applied) to the
1791 * stable batch scratch bo area (so that the CS never
1792 * stumbles over its tlb invalidation bug) ...
1794 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1795 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1796 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1797 intel_ring_emit(ring, cs_offset);
1798 intel_ring_emit(ring, 4096);
1799 intel_ring_emit(ring, offset);
1801 intel_ring_emit(ring, MI_FLUSH);
1802 intel_ring_emit(ring, MI_NOOP);
1803 intel_ring_advance(ring);
1805 /* ... and execute it. */
1809 ret = intel_ring_begin(ring, 4);
1813 intel_ring_emit(ring, MI_BATCH_BUFFER);
1814 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1815 0 : MI_BATCH_NON_SECURE));
1816 intel_ring_emit(ring, offset + len - 8);
1817 intel_ring_emit(ring, MI_NOOP);
1818 intel_ring_advance(ring);
1824 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1825 u64 offset, u32 len,
1826 unsigned dispatch_flags)
1830 ret = intel_ring_begin(ring, 2);
1834 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1835 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1836 0 : MI_BATCH_NON_SECURE));
1837 intel_ring_advance(ring);
1842 static void cleanup_status_page(struct intel_engine_cs *ring)
1844 struct drm_i915_gem_object *obj;
1846 obj = ring->status_page.obj;
1850 kunmap(obj->pages[0]);
1851 i915_gem_object_ggtt_unpin(obj);
1852 drm_gem_object_unreference(&obj->base);
1853 ring->status_page.obj = NULL;
1856 static int init_status_page(struct intel_engine_cs *ring)
1858 struct drm_i915_gem_object *obj;
1860 if ((obj = ring->status_page.obj) == NULL) {
1864 obj = i915_gem_alloc_object(ring->dev, 4096);
1866 DRM_ERROR("Failed to allocate status page\n");
1870 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1875 if (!HAS_LLC(ring->dev))
1876 /* On g33, we cannot place HWS above 256MiB, so
1877 * restrict its pinning to the low mappable arena.
1878 * Though this restriction is not documented for
1879 * gen4, gen5, or byt, they also behave similarly
1880 * and hang if the HWS is placed at the top of the
1881 * GTT. To generalise, it appears that all !llc
1882 * platforms have issues with us placing the HWS
1883 * above the mappable region (even though we never
1886 flags |= PIN_MAPPABLE;
1887 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1890 drm_gem_object_unreference(&obj->base);
1894 ring->status_page.obj = obj;
1897 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1898 ring->status_page.page_addr = kmap(obj->pages[0]);
1899 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1901 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1902 ring->name, ring->status_page.gfx_addr);
1907 static int init_phys_status_page(struct intel_engine_cs *ring)
1909 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1911 if (!dev_priv->status_page_dmah) {
1912 dev_priv->status_page_dmah =
1913 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1914 if (!dev_priv->status_page_dmah)
1918 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1919 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1924 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1926 iounmap(ringbuf->virtual_start, ringbuf->size);
1927 ringbuf->virtual_start = NULL;
1928 i915_gem_object_ggtt_unpin(ringbuf->obj);
1931 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1932 struct intel_ringbuffer *ringbuf)
1934 struct drm_i915_private *dev_priv = to_i915(dev);
1935 struct drm_i915_gem_object *obj = ringbuf->obj;
1938 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1942 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1944 i915_gem_object_ggtt_unpin(obj);
1948 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1949 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1950 if (ringbuf->virtual_start == NULL) {
1951 i915_gem_object_ggtt_unpin(obj);
1958 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1960 drm_gem_object_unreference(&ringbuf->obj->base);
1961 ringbuf->obj = NULL;
1964 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1965 struct intel_ringbuffer *ringbuf)
1967 struct drm_i915_gem_object *obj;
1971 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1973 obj = i915_gem_alloc_object(dev, ringbuf->size);
1977 /* mark ring buffers as read-only from GPU side by default */
1985 static int intel_init_ring_buffer(struct drm_device *dev,
1986 struct intel_engine_cs *ring)
1988 struct intel_ringbuffer *ringbuf;
1991 WARN_ON(ring->buffer);
1993 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1996 ring->buffer = ringbuf;
1999 INIT_LIST_HEAD(&ring->active_list);
2000 INIT_LIST_HEAD(&ring->request_list);
2001 INIT_LIST_HEAD(&ring->execlist_queue);
2002 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2003 ringbuf->size = 32 * PAGE_SIZE;
2004 ringbuf->ring = ring;
2005 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2007 init_waitqueue_head(&ring->irq_queue);
2009 if (I915_NEED_GFX_HWS(dev)) {
2010 ret = init_status_page(ring);
2014 BUG_ON(ring->id != RCS);
2015 ret = init_phys_status_page(ring);
2020 WARN_ON(ringbuf->obj);
2022 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2024 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2029 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2031 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2033 intel_destroy_ringbuffer_obj(ringbuf);
2037 /* Workaround an erratum on the i830 which causes a hang if
2038 * the TAIL pointer points to within the last 2 cachelines
2041 ringbuf->effective_size = ringbuf->size;
2042 if (IS_I830(dev) || IS_845G(dev))
2043 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2045 ret = i915_cmd_parser_init_ring(ring);
2053 ring->buffer = NULL;
2057 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2059 struct drm_i915_private *dev_priv;
2060 struct intel_ringbuffer *ringbuf;
2062 if (!intel_ring_initialized(ring))
2065 dev_priv = to_i915(ring->dev);
2066 ringbuf = ring->buffer;
2068 intel_stop_ring_buffer(ring);
2069 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2071 intel_unpin_ringbuffer_obj(ringbuf);
2072 intel_destroy_ringbuffer_obj(ringbuf);
2073 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2076 ring->cleanup(ring);
2078 cleanup_status_page(ring);
2080 i915_cmd_parser_fini_ring(ring);
2081 i915_gem_batch_pool_fini(&ring->batch_pool);
2084 ring->buffer = NULL;
2087 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2089 struct intel_ringbuffer *ringbuf = ring->buffer;
2090 struct drm_i915_gem_request *request;
2094 if (intel_ring_space(ringbuf) >= n)
2097 list_for_each_entry(request, &ring->request_list, list) {
2098 space = __intel_ring_space(request->postfix, ringbuf->tail,
2104 if (WARN_ON(&request->list == &ring->request_list))
2107 ret = i915_wait_request(request);
2111 ringbuf->space = space;
2115 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2117 uint32_t __iomem *virt;
2118 struct intel_ringbuffer *ringbuf = ring->buffer;
2119 int rem = ringbuf->size - ringbuf->tail;
2121 if (ringbuf->space < rem) {
2122 int ret = ring_wait_for_space(ring, rem);
2127 virt = (unsigned int *)((char *)ringbuf->virtual_start + ringbuf->tail);
2130 iowrite32(MI_NOOP, virt++);
2133 intel_ring_update_space(ringbuf);
2138 int intel_ring_idle(struct intel_engine_cs *ring)
2140 struct drm_i915_gem_request *req;
2143 /* We need to add any requests required to flush the objects and ring */
2144 if (ring->outstanding_lazy_request) {
2145 ret = i915_add_request(ring);
2150 /* Wait upon the last request to be completed */
2151 if (list_empty(&ring->request_list))
2154 req = list_entry(ring->request_list.prev,
2155 struct drm_i915_gem_request,
2158 /* Make sure we do not trigger any retires */
2159 return __i915_wait_request(req,
2160 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2161 to_i915(ring->dev)->mm.interruptible,
2165 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2167 request->ringbuf = request->ring->buffer;
2171 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2174 struct intel_ringbuffer *ringbuf = ring->buffer;
2177 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2178 ret = intel_wrap_ring_buffer(ring);
2183 if (unlikely(ringbuf->space < bytes)) {
2184 ret = ring_wait_for_space(ring, bytes);
2192 int intel_ring_begin(struct intel_engine_cs *ring,
2195 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2198 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2199 dev_priv->mm.interruptible);
2203 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2207 /* Preallocate the olr before touching the ring */
2208 ret = i915_gem_request_alloc(ring, ring->default_context);
2212 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2216 /* Align the ring tail to a cacheline boundary */
2217 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2219 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2222 if (num_dwords == 0)
2225 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2226 ret = intel_ring_begin(ring, num_dwords);
2230 while (num_dwords--)
2231 intel_ring_emit(ring, MI_NOOP);
2233 intel_ring_advance(ring);
2238 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2240 struct drm_device *dev = ring->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2243 BUG_ON(ring->outstanding_lazy_request);
2245 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2246 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2247 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2249 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2252 ring->set_seqno(ring, seqno);
2253 ring->hangcheck.seqno = seqno;
2256 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2259 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2261 /* Every tail move must follow the sequence below */
2263 /* Disable notification that the ring is IDLE. The GT
2264 * will then assume that it is busy and bring it out of rc6.
2266 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2267 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2269 /* Clear the context id. Here be magic! */
2270 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2272 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2273 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2274 GEN6_BSD_SLEEP_INDICATOR) == 0,
2276 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2278 /* Now that the ring is fully powered up, update the tail */
2279 I915_WRITE_TAIL(ring, value);
2280 POSTING_READ(RING_TAIL(ring->mmio_base));
2282 /* Let the ring send IDLE messages to the GT again,
2283 * and so let it sleep to conserve power when idle.
2285 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2286 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2289 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2290 u32 invalidate, u32 flush)
2295 ret = intel_ring_begin(ring, 4);
2300 if (INTEL_INFO(ring->dev)->gen >= 8)
2303 /* We always require a command barrier so that subsequent
2304 * commands, such as breadcrumb interrupts, are strictly ordered
2305 * wrt the contents of the write cache being flushed to memory
2306 * (and thus being coherent from the CPU).
2308 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2311 * Bspec vol 1c.5 - video engine command streamer:
2312 * "If ENABLED, all TLBs will be invalidated once the flush
2313 * operation is complete. This bit is only valid when the
2314 * Post-Sync Operation field is a value of 1h or 3h."
2316 if (invalidate & I915_GEM_GPU_DOMAINS)
2317 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2319 intel_ring_emit(ring, cmd);
2320 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2321 if (INTEL_INFO(ring->dev)->gen >= 8) {
2322 intel_ring_emit(ring, 0); /* upper addr */
2323 intel_ring_emit(ring, 0); /* value */
2325 intel_ring_emit(ring, 0);
2326 intel_ring_emit(ring, MI_NOOP);
2328 intel_ring_advance(ring);
2333 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2334 u64 offset, u32 len,
2335 unsigned dispatch_flags)
2337 bool ppgtt = USES_PPGTT(ring->dev) &&
2338 !(dispatch_flags & I915_DISPATCH_SECURE);
2341 ret = intel_ring_begin(ring, 4);
2345 /* FIXME(BDW): Address space and security selectors. */
2346 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2347 intel_ring_emit(ring, lower_32_bits(offset));
2348 intel_ring_emit(ring, upper_32_bits(offset));
2349 intel_ring_emit(ring, MI_NOOP);
2350 intel_ring_advance(ring);
2356 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2357 u64 offset, u32 len,
2358 unsigned dispatch_flags)
2362 ret = intel_ring_begin(ring, 2);
2366 intel_ring_emit(ring,
2367 MI_BATCH_BUFFER_START |
2368 (dispatch_flags & I915_DISPATCH_SECURE ?
2369 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2370 /* bit0-7 is the length on GEN6+ */
2371 intel_ring_emit(ring, offset);
2372 intel_ring_advance(ring);
2378 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2379 u64 offset, u32 len,
2380 unsigned dispatch_flags)
2384 ret = intel_ring_begin(ring, 2);
2388 intel_ring_emit(ring,
2389 MI_BATCH_BUFFER_START |
2390 (dispatch_flags & I915_DISPATCH_SECURE ?
2391 0 : MI_BATCH_NON_SECURE_I965));
2392 /* bit0-7 is the length on GEN6+ */
2393 intel_ring_emit(ring, offset);
2394 intel_ring_advance(ring);
2399 /* Blitter support (SandyBridge+) */
2401 static int gen6_ring_flush(struct intel_engine_cs *ring,
2402 u32 invalidate, u32 flush)
2404 struct drm_device *dev = ring->dev;
2408 ret = intel_ring_begin(ring, 4);
2413 if (INTEL_INFO(dev)->gen >= 8)
2416 /* We always require a command barrier so that subsequent
2417 * commands, such as breadcrumb interrupts, are strictly ordered
2418 * wrt the contents of the write cache being flushed to memory
2419 * (and thus being coherent from the CPU).
2421 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2424 * Bspec vol 1c.3 - blitter engine command streamer:
2425 * "If ENABLED, all TLBs will be invalidated once the flush
2426 * operation is complete. This bit is only valid when the
2427 * Post-Sync Operation field is a value of 1h or 3h."
2429 if (invalidate & I915_GEM_DOMAIN_RENDER)
2430 cmd |= MI_INVALIDATE_TLB;
2431 intel_ring_emit(ring, cmd);
2432 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2433 if (INTEL_INFO(dev)->gen >= 8) {
2434 intel_ring_emit(ring, 0); /* upper addr */
2435 intel_ring_emit(ring, 0); /* value */
2437 intel_ring_emit(ring, 0);
2438 intel_ring_emit(ring, MI_NOOP);
2440 intel_ring_advance(ring);
2445 int intel_init_render_ring_buffer(struct drm_device *dev)
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2449 struct drm_i915_gem_object *obj;
2452 ring->name = "render ring";
2454 ring->mmio_base = RENDER_RING_BASE;
2456 if (INTEL_INFO(dev)->gen >= 8) {
2457 if (i915_semaphore_is_enabled(dev)) {
2458 obj = i915_gem_alloc_object(dev, 4096);
2460 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2461 i915.semaphores = 0;
2463 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2464 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2466 drm_gem_object_unreference(&obj->base);
2467 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2468 i915.semaphores = 0;
2470 dev_priv->semaphore_obj = obj;
2474 ring->init_context = intel_rcs_ctx_init;
2475 ring->add_request = gen6_add_request;
2476 ring->flush = gen8_render_ring_flush;
2477 ring->irq_get = gen8_ring_get_irq;
2478 ring->irq_put = gen8_ring_put_irq;
2479 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2480 ring->get_seqno = gen6_ring_get_seqno;
2481 ring->set_seqno = ring_set_seqno;
2482 if (i915_semaphore_is_enabled(dev)) {
2483 WARN_ON(!dev_priv->semaphore_obj);
2484 ring->semaphore.sync_to = gen8_ring_sync;
2485 ring->semaphore.signal = gen8_rcs_signal;
2486 GEN8_RING_SEMAPHORE_INIT;
2488 } else if (INTEL_INFO(dev)->gen >= 6) {
2489 ring->add_request = gen6_add_request;
2490 ring->flush = gen7_render_ring_flush;
2491 if (INTEL_INFO(dev)->gen == 6)
2492 ring->flush = gen6_render_ring_flush;
2493 ring->irq_get = gen6_ring_get_irq;
2494 ring->irq_put = gen6_ring_put_irq;
2495 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2496 ring->get_seqno = gen6_ring_get_seqno;
2497 ring->set_seqno = ring_set_seqno;
2498 if (i915_semaphore_is_enabled(dev)) {
2499 ring->semaphore.sync_to = gen6_ring_sync;
2500 ring->semaphore.signal = gen6_signal;
2502 * The current semaphore is only applied on pre-gen8
2503 * platform. And there is no VCS2 ring on the pre-gen8
2504 * platform. So the semaphore between RCS and VCS2 is
2505 * initialized as INVALID. Gen8 will initialize the
2506 * sema between VCS2 and RCS later.
2508 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2509 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2510 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2511 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2512 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2513 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2514 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2515 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2516 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2517 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2519 } else if (IS_GEN5(dev)) {
2520 ring->add_request = pc_render_add_request;
2521 ring->flush = gen4_render_ring_flush;
2522 ring->get_seqno = pc_render_get_seqno;
2523 ring->set_seqno = pc_render_set_seqno;
2524 ring->irq_get = gen5_ring_get_irq;
2525 ring->irq_put = gen5_ring_put_irq;
2526 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2527 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2529 ring->add_request = i9xx_add_request;
2530 if (INTEL_INFO(dev)->gen < 4)
2531 ring->flush = gen2_render_ring_flush;
2533 ring->flush = gen4_render_ring_flush;
2534 ring->get_seqno = ring_get_seqno;
2535 ring->set_seqno = ring_set_seqno;
2537 ring->irq_get = i8xx_ring_get_irq;
2538 ring->irq_put = i8xx_ring_put_irq;
2540 ring->irq_get = i9xx_ring_get_irq;
2541 ring->irq_put = i9xx_ring_put_irq;
2543 ring->irq_enable_mask = I915_USER_INTERRUPT;
2545 ring->write_tail = ring_write_tail;
2547 if (IS_HASWELL(dev))
2548 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2549 else if (IS_GEN8(dev))
2550 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2551 else if (INTEL_INFO(dev)->gen >= 6)
2552 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2553 else if (INTEL_INFO(dev)->gen >= 4)
2554 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2555 else if (IS_I830(dev) || IS_845G(dev))
2556 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2558 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2559 ring->init_hw = init_render_ring;
2560 ring->cleanup = render_ring_cleanup;
2562 /* Workaround batchbuffer to combat CS tlb bug. */
2563 if (HAS_BROKEN_CS_TLB(dev)) {
2564 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2566 DRM_ERROR("Failed to allocate batch bo\n");
2570 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2572 drm_gem_object_unreference(&obj->base);
2573 DRM_ERROR("Failed to ping batch bo\n");
2577 ring->scratch.obj = obj;
2578 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2581 ret = intel_init_ring_buffer(dev, ring);
2585 if (INTEL_INFO(dev)->gen >= 5) {
2586 ret = intel_init_pipe_control(ring);
2594 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2596 struct drm_i915_private *dev_priv = dev->dev_private;
2597 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2599 ring->name = "bsd ring";
2602 ring->write_tail = ring_write_tail;
2603 if (INTEL_INFO(dev)->gen >= 6) {
2604 ring->mmio_base = GEN6_BSD_RING_BASE;
2605 /* gen6 bsd needs a special wa for tail updates */
2607 ring->write_tail = gen6_bsd_ring_write_tail;
2608 ring->flush = gen6_bsd_ring_flush;
2609 ring->add_request = gen6_add_request;
2610 ring->get_seqno = gen6_ring_get_seqno;
2611 ring->set_seqno = ring_set_seqno;
2612 if (INTEL_INFO(dev)->gen >= 8) {
2613 ring->irq_enable_mask =
2614 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2615 ring->irq_get = gen8_ring_get_irq;
2616 ring->irq_put = gen8_ring_put_irq;
2617 ring->dispatch_execbuffer =
2618 gen8_ring_dispatch_execbuffer;
2619 if (i915_semaphore_is_enabled(dev)) {
2620 ring->semaphore.sync_to = gen8_ring_sync;
2621 ring->semaphore.signal = gen8_xcs_signal;
2622 GEN8_RING_SEMAPHORE_INIT;
2625 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2626 ring->irq_get = gen6_ring_get_irq;
2627 ring->irq_put = gen6_ring_put_irq;
2628 ring->dispatch_execbuffer =
2629 gen6_ring_dispatch_execbuffer;
2630 if (i915_semaphore_is_enabled(dev)) {
2631 ring->semaphore.sync_to = gen6_ring_sync;
2632 ring->semaphore.signal = gen6_signal;
2633 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2634 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2635 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2636 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2637 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2638 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2639 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2640 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2641 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2642 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2646 ring->mmio_base = BSD_RING_BASE;
2647 ring->flush = bsd_ring_flush;
2648 ring->add_request = i9xx_add_request;
2649 ring->get_seqno = ring_get_seqno;
2650 ring->set_seqno = ring_set_seqno;
2652 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2653 ring->irq_get = gen5_ring_get_irq;
2654 ring->irq_put = gen5_ring_put_irq;
2656 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2657 ring->irq_get = i9xx_ring_get_irq;
2658 ring->irq_put = i9xx_ring_put_irq;
2660 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2662 ring->init_hw = init_ring_common;
2664 return intel_init_ring_buffer(dev, ring);
2668 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2670 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2675 ring->name = "bsd2 ring";
2678 ring->write_tail = ring_write_tail;
2679 ring->mmio_base = GEN8_BSD2_RING_BASE;
2680 ring->flush = gen6_bsd_ring_flush;
2681 ring->add_request = gen6_add_request;
2682 ring->get_seqno = gen6_ring_get_seqno;
2683 ring->set_seqno = ring_set_seqno;
2684 ring->irq_enable_mask =
2685 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2686 ring->irq_get = gen8_ring_get_irq;
2687 ring->irq_put = gen8_ring_put_irq;
2688 ring->dispatch_execbuffer =
2689 gen8_ring_dispatch_execbuffer;
2690 if (i915_semaphore_is_enabled(dev)) {
2691 ring->semaphore.sync_to = gen8_ring_sync;
2692 ring->semaphore.signal = gen8_xcs_signal;
2693 GEN8_RING_SEMAPHORE_INIT;
2695 ring->init_hw = init_ring_common;
2697 return intel_init_ring_buffer(dev, ring);
2700 int intel_init_blt_ring_buffer(struct drm_device *dev)
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2705 ring->name = "blitter ring";
2708 ring->mmio_base = BLT_RING_BASE;
2709 ring->write_tail = ring_write_tail;
2710 ring->flush = gen6_ring_flush;
2711 ring->add_request = gen6_add_request;
2712 ring->get_seqno = gen6_ring_get_seqno;
2713 ring->set_seqno = ring_set_seqno;
2714 if (INTEL_INFO(dev)->gen >= 8) {
2715 ring->irq_enable_mask =
2716 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2717 ring->irq_get = gen8_ring_get_irq;
2718 ring->irq_put = gen8_ring_put_irq;
2719 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2720 if (i915_semaphore_is_enabled(dev)) {
2721 ring->semaphore.sync_to = gen8_ring_sync;
2722 ring->semaphore.signal = gen8_xcs_signal;
2723 GEN8_RING_SEMAPHORE_INIT;
2726 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2727 ring->irq_get = gen6_ring_get_irq;
2728 ring->irq_put = gen6_ring_put_irq;
2729 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2730 if (i915_semaphore_is_enabled(dev)) {
2731 ring->semaphore.signal = gen6_signal;
2732 ring->semaphore.sync_to = gen6_ring_sync;
2734 * The current semaphore is only applied on pre-gen8
2735 * platform. And there is no VCS2 ring on the pre-gen8
2736 * platform. So the semaphore between BCS and VCS2 is
2737 * initialized as INVALID. Gen8 will initialize the
2738 * sema between BCS and VCS2 later.
2740 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2741 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2742 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2743 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2744 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2745 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2746 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2747 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2748 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2749 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2752 ring->init_hw = init_ring_common;
2754 return intel_init_ring_buffer(dev, ring);
2757 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2762 ring->name = "video enhancement ring";
2765 ring->mmio_base = VEBOX_RING_BASE;
2766 ring->write_tail = ring_write_tail;
2767 ring->flush = gen6_ring_flush;
2768 ring->add_request = gen6_add_request;
2769 ring->get_seqno = gen6_ring_get_seqno;
2770 ring->set_seqno = ring_set_seqno;
2772 if (INTEL_INFO(dev)->gen >= 8) {
2773 ring->irq_enable_mask =
2774 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2775 ring->irq_get = gen8_ring_get_irq;
2776 ring->irq_put = gen8_ring_put_irq;
2777 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2778 if (i915_semaphore_is_enabled(dev)) {
2779 ring->semaphore.sync_to = gen8_ring_sync;
2780 ring->semaphore.signal = gen8_xcs_signal;
2781 GEN8_RING_SEMAPHORE_INIT;
2784 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2785 ring->irq_get = hsw_vebox_get_irq;
2786 ring->irq_put = hsw_vebox_put_irq;
2787 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2788 if (i915_semaphore_is_enabled(dev)) {
2789 ring->semaphore.sync_to = gen6_ring_sync;
2790 ring->semaphore.signal = gen6_signal;
2791 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2792 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2793 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2794 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2795 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2796 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2797 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2798 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2799 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2800 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2803 ring->init_hw = init_ring_common;
2805 return intel_init_ring_buffer(dev, ring);
2809 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2813 if (!ring->gpu_caches_dirty)
2816 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2820 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2822 ring->gpu_caches_dirty = false;
2827 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2829 uint32_t flush_domains;
2833 if (ring->gpu_caches_dirty)
2834 flush_domains = I915_GEM_GPU_DOMAINS;
2836 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2840 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2842 ring->gpu_caches_dirty = false;
2847 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2851 if (!intel_ring_initialized(ring))
2854 ret = intel_ring_idle(ring);
2855 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2856 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",