2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * $FreeBSD: src/sys/i386/isa/if_le.c,v 1.56.2.4 2002/06/05 23:24:10 paul Exp $
25 * $DragonFly: src/sys/dev/netif/le/if_le.c,v 1.29 2005/10/13 08:50:33 sephe Exp $
29 * DEC EtherWORKS 2 Ethernet Controllers
30 * DEC EtherWORKS 3 Ethernet Controllers
32 * Written by Matt Thomas
33 * BPF support code stolen directly from if_ec.c
35 * This driver supports the DEPCA, DE100, DE101, DE200, DE201,
36 * DE2002, DE203, DE204, DE205, and DE422 cards.
43 #include <sys/param.h>
44 #include <sys/systm.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/thread2.h>
50 #include <sys/malloc.h>
51 #include <sys/linker_set.h>
52 #include <sys/module.h>
54 #include <net/ethernet.h>
56 #include <net/ifq_var.h>
57 #include <net/if_types.h>
58 #include <net/if_dl.h>
60 #include <netinet/in.h>
61 #include <netinet/if_ether.h>
63 #include <bus/isa/i386/isa_device.h>
64 #include <i386/isa/icu.h>
71 typedef u_short le_mcbits_t;
72 #define LE_MC_NBPW_LOG2 4
73 #define LE_MC_NBPW (1 << LE_MC_NBPW_LOG2)
78 int (*bd_probe)(struct le_softc *sc, const struct le_board *bd, int *msize);
82 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
84 * Start of DEC EtherWORKS III (LEMAC) dependent structures
87 #include <i386/isa/ic/lemac.h> /* Include LEMAC definitions */
89 DECLARE_DUMMY_MODULE(if_le);
91 static int lemac_probe(struct le_softc *sc, const struct le_board *bd, int *msize);
93 struct le_lemac_info {
94 u_int lemac__lastpage; /* last 2K page */
95 u_int lemac__memmode; /* Are we in 2K, 32K, or 64K mode */
96 u_int lemac__membase; /* Physical address of start of RAM */
97 u_int lemac__txctl; /* Transmit Control Byte */
98 u_int lemac__txmax; /* Maximum # of outstanding transmits */
99 le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
100 /* local copy of multicast table */
101 u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
102 char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
103 #define lemac_lastpage le_un.un_lemac.lemac__lastpage
104 #define lemac_memmode le_un.un_lemac.lemac__memmode
105 #define lemac_membase le_un.un_lemac.lemac__membase
106 #define lemac_txctl le_un.un_lemac.lemac__txctl
107 #define lemac_txmax le_un.un_lemac.lemac__txmax
108 #define lemac_mctbl le_un.un_lemac.lemac__mctbl
109 #define lemac_eeprom le_un.un_lemac.lemac__eeprom
110 #define lemac_prodname le_un.un_lemac.lemac__prodname
114 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
116 * Start of DEC EtherWORKS II (LANCE) dependent structures
120 #include <i386/isa/ic/am7990.h>
126 static int depca_probe(struct le_softc *sc, const struct le_board *bd, int *msize);
128 typedef struct lance_descinfo lance_descinfo_t;
129 typedef struct lance_ring lance_ring_t;
131 typedef unsigned lance_addr_t;
133 struct lance_descinfo {
134 caddr_t di_addr; /* address of descriptor */
135 lance_addr_t di_bufaddr; /* LANCE address of buffer owned by descriptor */
136 unsigned di_buflen; /* size of buffer owned by descriptor */
137 struct mbuf *di_mbuf; /* mbuf being transmitted/received */
141 lance_descinfo_t *ri_first; /* Pointer to first descriptor in ring */
142 lance_descinfo_t *ri_last; /* Pointer to last + 1 descriptor in ring */
143 lance_descinfo_t *ri_nextin; /* Pointer to next one to be given to HOST */
144 lance_descinfo_t *ri_nextout; /* Pointer to next one to be given to LANCE */
145 unsigned ri_max; /* Size of Ring - 1 */
146 unsigned ri_free; /* Number of free rings entires (owned by HOST) */
147 lance_addr_t ri_heap; /* Start of RAM for this ring */
148 lance_addr_t ri_heapend; /* End + 1 of RAM for this ring */
149 lance_addr_t ri_outptr; /* Pointer to first output byte */
150 unsigned ri_outsize; /* Space remaining for output */
153 struct le_lance_info {
154 unsigned lance__csr1; /* LANCE Address of init block (low 16) */
155 unsigned lance__csr2; /* LANCE Address of init block (high 8) */
156 unsigned lance__csr3; /* Copy of CSR3 */
157 unsigned lance__rap; /* IO Port Offset of RAP */
158 unsigned lance__rdp; /* IO Port Offset of RDP */
159 unsigned lance__ramoffset; /* Offset to valid LANCE RAM */
160 unsigned lance__ramsize; /* Amount of RAM shared by LANCE */
161 unsigned lance__rxbufsize; /* Size of a receive buffer */
162 ln_initb_t lance__initb; /* local copy of LANCE initblock */
163 ln_initb_t *lance__raminitb; /* copy to board's LANCE initblock (debugging) */
164 ln_desc_t *lance__ramdesc; /* copy to board's LANCE descriptors (debugging) */
165 lance_ring_t lance__rxinfo; /* Receive ring information */
166 lance_ring_t lance__txinfo; /* Transmit ring information */
167 #define lance_csr1 le_un.un_lance.lance__csr1
168 #define lance_csr2 le_un.un_lance.lance__csr2
169 #define lance_csr3 le_un.un_lance.lance__csr3
170 #define lance_rap le_un.un_lance.lance__rap
171 #define lance_rdp le_un.un_lance.lance__rdp
172 #define lance_ramoffset le_un.un_lance.lance__ramoffset
173 #define lance_ramsize le_un.un_lance.lance__ramsize
174 #define lance_rxbufsize le_un.un_lance.lance__rxbufsize
175 #define lance_initb le_un.un_lance.lance__initb
176 #define lance_raminitb le_un.un_lance.lance__raminitb
177 #define lance_ramdesc le_un.un_lance.lance__ramdesc
178 #define lance_rxinfo le_un.un_lance.lance__rxinfo
179 #define lance_txinfo le_un.un_lance.lance__txinfo
183 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
185 * Start of Common Code
189 static void (*le_intrvec[NLE])(struct le_softc *sc);
192 * Ethernet status, per interface.
195 struct arpcom le_ac; /* Common Ethernet/ARP Structure */
196 void (*if_init) (void *);/* Interface init routine */
197 void (*if_reset) (struct le_softc*);/* Interface reset routine */
198 caddr_t le_membase; /* Starting memory address (virtual) */
199 unsigned le_iobase; /* Starting I/O base address */
200 unsigned le_irq; /* Interrupt Request Value */
201 unsigned le_flags; /* local copy of if_flags */
202 #define LE_BRDCSTONLY 0x01000000 /* If only broadcast is enabled */
203 u_int le_mcmask; /* bit mask for CRC-32 for multicast hash */
204 le_mcbits_t *le_mctbl; /* pointer to multicast table */
205 const char *le_prodname; /* product name DE20x-xx */
206 u_char le_hwaddr[6]; /* local copy of hwaddr */
208 struct le_lemac_info un_lemac; /* LEMAC specific information */
209 struct le_lance_info un_lance; /* Am7990 specific information */
212 #define le_if le_ac.ac_if
215 static int le_probe(struct isa_device *dvp);
216 static int le_attach(struct isa_device *dvp);
217 static void le_intr(void *);
218 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
220 static void le_input(struct le_softc *sc, caddr_t seg1, size_t total_len,
221 size_t len2, caddr_t seg2);
222 static void le_multi_filter(struct le_softc *sc);
223 static void le_multi_op(struct le_softc *sc, const u_char *mca, int oper_flg);
224 static int le_read_macaddr(struct le_softc *sc, int ioreg, int skippat);
226 static struct le_softc le_softc[NLE];
228 static const struct le_board le_boards[] = {
229 { lemac_probe }, /* DE20[345] */
230 { depca_probe }, /* DE{20[012],422} */
231 { NULL } /* Must Be Last! */
235 * This tells the autoconf code how to set us up.
237 struct isa_driver ledriver = {
238 le_probe, le_attach, "le",
241 static unsigned le_intrs[NLE];
243 #define LE_INL(sc, reg) inl((sc)->le_iobase + (reg))
244 #define LE_OUTL(sc, reg, data) outl((sc)->le_iobase + (reg), data)
245 #define LE_INW(sc, reg) inw((sc)->le_iobase + (reg))
246 #define LE_OUTW(sc, reg, data) outw((sc)->le_iobase + (reg), data)
247 #define LE_INB(sc, reg) inb((sc)->le_iobase + (reg))
248 #define LE_OUTB(sc, reg, data) outb((sc)->le_iobase + (reg), data)
251 le_probe(struct isa_device *dvp)
253 struct le_softc *sc = &le_softc[dvp->id_unit];
254 const struct le_board *bd;
257 if (dvp->id_unit >= NLE) {
258 printf("%s%d not configured -- too many devices\n",
259 ledriver.name, dvp->id_unit);
263 sc->le_iobase = dvp->id_iobase;
264 sc->le_membase = (u_char *) dvp->id_maddr;
265 sc->le_irq = dvp->id_irq;
266 if_initname(&(sc->le_if), ledriver.name, dvp->id_unit);
269 * Find and Initialize board..
272 sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
274 for (bd = le_boards; bd->bd_probe != NULL; bd++) {
275 if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
284 le_attach(struct isa_device *dvp)
286 struct le_softc *sc = &le_softc[dvp->id_unit];
287 struct ifnet *ifp = &sc->le_if;
289 dvp->id_intr = (inthand2_t *)le_intr;
291 ifp->if_mtu = ETHERMTU;
293 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
294 ifp->if_ioctl = le_ioctl;
295 ifp->if_type = IFT_ETHER;
298 ifp->if_init = sc->if_init;
299 ifp->if_baudrate = 10000000;
300 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
301 ifq_set_ready(&ifp->if_snd);
303 ether_ifattach(ifp, sc->le_ac.ac_enaddr);
314 (*le_intrvec[unit])(&le_softc[unit]);
320 le_input(struct le_softc *sc, caddr_t seg1, size_t total_len,
321 size_t len1, caddr_t seg2)
323 struct ether_header eh;
326 if (total_len - sizeof(eh) > ETHERMTU
327 || total_len - sizeof(eh) < ETHERMIN) {
328 sc->le_if.if_ierrors++;
331 bcopy(seg1, &eh, ETHER_HDR_LEN);
333 seg1 += ETHER_HDR_LEN;
334 total_len -= ETHER_HDR_LEN;
335 len1 -= ETHER_HDR_LEN;
337 m = m_getl(total_len + LE_XTRA, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL);
339 sc->le_if.if_ierrors++;
342 m->m_pkthdr.rcvif = &sc->le_if;
343 m->m_data += LE_XTRA;
344 m->m_len = m->m_pkthdr.len = total_len;
346 bcopy(seg1, mtod(m, caddr_t), len1);
348 bcopy(seg2, mtod(m, caddr_t) + len1, total_len - len1);
349 ether_input(&sc->le_if, &eh, m);
353 le_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
355 struct le_softc *sc = ifp->if_softc;
358 if ((sc->le_flags & IFF_UP) == 0)
372 * Update multicast listeners
379 error = ether_ioctl(ifp, cmd, data);
389 * This is the standard method of reading the DEC Address ROMS.
390 * I don't understand it but it does work.
393 le_read_macaddr(struct le_softc *sc, int ioreg, int skippat)
395 int cksum, rom_cksum;
398 int idx, idx2, found, octet;
399 static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
402 for (idx = 0; idx < 32; idx++) {
403 octet = LE_INB(sc, ioreg);
405 if (octet == testpat[idx2]) {
406 if (++idx2 == sizeof testpat) {
420 sc->le_hwaddr[0] = LE_INB(sc, ioreg);
421 sc->le_hwaddr[1] = LE_INB(sc, ioreg);
423 cksum = *(u_short *) &sc->le_hwaddr[0];
425 sc->le_hwaddr[2] = LE_INB(sc, ioreg);
426 sc->le_hwaddr[3] = LE_INB(sc, ioreg);
428 if (cksum > 65535) cksum -= 65535;
429 cksum += *(u_short *) &sc->le_hwaddr[2];
430 if (cksum > 65535) cksum -= 65535;
432 sc->le_hwaddr[4] = LE_INB(sc, ioreg);
433 sc->le_hwaddr[5] = LE_INB(sc, ioreg);
435 if (cksum > 65535) cksum -= 65535;
436 cksum += *(u_short *) &sc->le_hwaddr[4];
437 if (cksum >= 65535) cksum -= 65535;
439 rom_cksum = LE_INB(sc, ioreg);
440 rom_cksum |= LE_INB(sc, ioreg) << 8;
442 if (cksum != rom_cksum)
448 le_multi_filter(struct le_softc *sc)
450 struct ifnet *ifp = &sc->le_ac.ac_if;
451 struct ifmultiaddr *ifma;
453 bzero(sc->le_mctbl, (sc->le_mcmask + 1) / 8);
455 if (sc->le_if.if_flags & IFF_ALLMULTI) {
456 sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
459 sc->le_flags &= ~IFF_MULTICAST;
460 /* if (interface has had an address assigned) { */
461 le_multi_op(sc, ifp->if_broadcastaddr, TRUE);
462 sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
465 sc->le_flags |= IFF_MULTICAST;
467 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
468 if (ifma->ifma_addr->sa_family != AF_LINK)
471 le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
472 sc->le_flags &= ~LE_BRDCSTONLY;
477 le_multi_op(struct le_softc *sc, const u_char *mca, int enable)
479 uint32_t bit, idx, crc;
481 crc = ether_crc32_le(mca, ETHER_ADDR_LEN);
484 * The following two line convert the N bit index into a longword index
485 * and a longword mask.
487 crc &= sc->le_mcmask;
488 bit = 1 << (crc & (LE_MC_NBPW -1));
489 idx = crc >> (LE_MC_NBPW_LOG2);
492 * Set or clear hash filter bit in our table.
495 sc->le_mctbl[idx] |= bit; /* Set Bit */
497 sc->le_mctbl[idx] &= ~bit; /* Clear Bit */
502 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
504 * Start of DEC EtherWORKS III (LEMAC) dependent code
508 #define LEMAC_INTR_ENABLE(sc) \
509 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
511 #define LEMAC_INTR_DISABLE(sc) \
512 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
514 #define LEMAC_64K_MODE(mbase) (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
515 #define LEMAC_32K_MODE(mbase) (((mbase) >= 0x14) && ((mbase) <= 0x1F))
516 #define LEMAC_2K_MODE(mbase) ( (mbase) >= 0x40)
518 static void lemac_init(void *xsc);
519 static void lemac_start(struct ifnet *ifp);
520 static void lemac_reset(struct le_softc *sc);
521 static void lemac_intr(struct le_softc *sc);
522 static void lemac_rne_intr(struct le_softc *sc);
523 static void lemac_tne_intr(struct le_softc *sc);
524 static void lemac_txd_intr(struct le_softc *sc, unsigned cs_value);
525 static void lemac_rxd_intr(struct le_softc *sc, unsigned cs_value);
526 static int lemac_read_eeprom(struct le_softc *sc);
527 static void lemac_init_adapmem(struct le_softc *sc);
529 #define LE_MCBITS_ALL_1S ((le_mcbits_t)~(le_mcbits_t)0)
531 static const le_mcbits_t lemac_allmulti_mctbl[16] = {
532 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
533 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
534 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
535 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
538 * An IRQ mapping table. Less space than switch statement.
540 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
543 * Some tuning/monitoring variables.
545 static unsigned lemac_deftxmax = 16; /* see lemac_max above */
546 static unsigned lemac_txnospc = 0; /* total # of tranmit starvations */
548 static unsigned lemac_tne_intrs = 0; /* total # of tranmit done intrs */
549 static unsigned lemac_rne_intrs = 0; /* total # of receive done intrs */
550 static unsigned lemac_txd_intrs = 0; /* total # of tranmit error intrs */
551 static unsigned lemac_rxd_intrs = 0; /* total # of receive error intrs */
554 lemac_probe(struct le_softc *sc, const struct le_board *bd, int *msize)
558 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
559 DELAY(LEMAC_EEP_DELAY);
562 * Read Ethernet address if card is present.
564 if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
567 bcopy(sc->le_hwaddr, sc->le_ac.ac_enaddr, ETHER_ADDR_LEN);
569 * Clear interrupts and set IRQ.
572 portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
573 irq = lemac_irqs[portval >> 5];
574 LE_OUTB(sc, LEMAC_REG_IC, portval);
577 * Make sure settings match.
580 if (irq != sc->le_irq) {
581 if_printf(&sc->le_if, "lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
587 * Try to reset the unit
589 sc->if_init = lemac_init;
590 sc->le_if.if_start = lemac_start;
591 sc->if_reset = lemac_reset;
592 sc->lemac_memmode = 2;
594 if ((sc->le_flags & IFF_UP) == 0)
598 * Check for correct memory base configuration.
600 if (vtophys(sc->le_membase) != sc->lemac_membase) {
601 if_printf(&sc->le_if, "lemac configuration error: expected iomem 0x%llx actual 0x%x\n",
602 vtophys(sc->le_membase), sc->lemac_membase);
606 sc->le_prodname = sc->lemac_prodname;
607 sc->le_mctbl = sc->lemac_mctbl;
608 sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
609 sc->lemac_txmax = lemac_deftxmax;
611 le_intrvec[sc->le_if.if_dunit] = lemac_intr;
613 return LEMAC_IOSPACE;
617 * Do a hard reset of the board;
620 lemac_reset(struct le_softc *sc)
622 struct ifnet *ifp = &sc->le_if;
629 sc->le_flags &= IFF_UP;
630 ifp->if_flags &= ~IFF_OACTIVE;
631 LEMAC_INTR_DISABLE(sc);
633 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
634 DELAY(LEMAC_EEP_DELAY);
636 /* Disable Interrupts */
637 /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
640 * Read EEPROM information. NOTE - the placement of this function
641 * is important because functions hereafter may rely on information
642 * read from the EEPROM.
644 if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
645 if_printf(ifp, "reset: EEPROM checksum failed (0x%x)\n", cksum);
650 * Force to 2K mode if not already configured.
653 portval = LE_INB(sc, LEMAC_REG_MBR);
654 if (!LEMAC_2K_MODE(portval)) {
655 if (LEMAC_64K_MODE(portval)) {
656 portval = (((portval * 2) & 0xF) << 4);
657 sc->lemac_memmode = 64;
658 } else if (LEMAC_32K_MODE(portval)) {
659 portval = ((portval & 0xF) << 4);
660 sc->lemac_memmode = 32;
662 LE_OUTB(sc, LEMAC_REG_MBR, portval);
664 sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
667 * Initialize Free Memory Queue, Init mcast table with broadcast.
670 lemac_init_adapmem(sc);
671 sc->le_flags |= IFF_UP;
675 lemac_init(void *xsc)
677 struct le_softc *sc = (struct le_softc *)xsc;
679 if ((sc->le_flags & IFF_UP) == 0)
685 * If the interface has the up flag
687 if (sc->le_if.if_flags & IFF_UP) {
688 int saved_cs = LE_INB(sc, LEMAC_REG_CS);
689 LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
690 LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
691 LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
692 LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
693 LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
694 LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
695 LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
697 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
699 if (sc->le_if.if_flags & IFF_PROMISC) {
700 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
702 LEMAC_INTR_DISABLE(sc);
704 LE_OUTB(sc, LEMAC_REG_MPN, 0);
705 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
706 bcopy(lemac_allmulti_mctbl, &sc->le_membase[LEMAC_MCTBL_OFF], sizeof(lemac_allmulti_mctbl));
708 bcopy(sc->lemac_mctbl, &sc->le_membase[LEMAC_MCTBL_OFF], sizeof(sc->lemac_mctbl));
710 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
713 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
715 LEMAC_INTR_ENABLE(sc);
716 sc->le_if.if_flags |= IFF_RUNNING;
718 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
720 LEMAC_INTR_DISABLE(sc);
721 sc->le_if.if_flags &= ~IFF_RUNNING;
728 * What to do upon receipt of an interrupt.
731 lemac_intr(struct le_softc *sc)
735 LEMAC_INTR_DISABLE(sc); /* Mask interrupts */
738 * Determine cause of interrupt. Receive events take
739 * priority over Transmit.
742 cs_value = LE_INB(sc, LEMAC_REG_CS);
745 * Check for Receive Queue not being empty.
746 * Check for Transmit Done Queue not being empty.
749 if (cs_value & LEMAC_CS_RNE)
751 if (cs_value & LEMAC_CS_TNE)
755 * Check for Transmitter Disabled.
756 * Check for Receiver Disabled.
759 if (cs_value & LEMAC_CS_TXD)
760 lemac_txd_intr(sc, cs_value);
761 if (cs_value & LEMAC_CS_RXD)
762 lemac_rxd_intr(sc, cs_value);
765 * Toggle LED and unmask interrupts.
768 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
769 LEMAC_INTR_ENABLE(sc); /* Unmask interrupts */
773 lemac_rne_intr(struct le_softc *sc)
775 int rxcount, rxlen, rxpg;
779 rxcount = LE_INB(sc, LEMAC_REG_RQC);
781 rxpg = LE_INB(sc, LEMAC_REG_RQ);
782 LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
784 rxptr = sc->le_membase;
785 sc->le_if.if_ipackets++;
786 if (*rxptr & LEMAC_RX_OK) {
789 * Get receive length - subtract out checksum.
792 rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
793 le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
794 } else { /* end if (*rxptr & LEMAC_RX_OK) */
795 sc->le_if.if_ierrors++;
797 LE_OUTB(sc, LEMAC_REG_FMQ, rxpg); /* Return this page to Free Memory Queue */
798 } /* end while (recv_count--) */
802 lemac_rxd_intr(struct le_softc *sc, unsigned cs_value)
805 * Handle CS_RXD (Receiver disabled) here.
807 * Check Free Memory Queue Count. If not equal to zero
808 * then just turn Receiver back on. If it is equal to
809 * zero then check to see if transmitter is disabled.
810 * Process transmit TXD loop once more. If all else
811 * fails then do software init (0xC0 to EEPROM Init)
812 * and rebuild Free Memory Queue.
818 * Re-enable Receiver.
821 cs_value &= ~LEMAC_CS_RXD;
822 LE_OUTB(sc, LEMAC_REG_CS, cs_value);
824 if (LE_INB(sc, LEMAC_REG_FMC) > 0)
827 if (cs_value & LEMAC_CS_TXD)
828 lemac_txd_intr(sc, cs_value);
830 if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
833 if_printf(&sc->le_if, "fatal RXD error, attempting recovery\n");
836 if (sc->le_flags & IFF_UP) {
842 * Error during initializion. Mark card as disabled.
844 if_printf(&sc->le_if, "recovery failed -- board disabled\n");
848 lemac_start(struct ifnet *ifp)
850 struct le_softc *sc = (struct le_softc *) ifp;
852 if ((ifp->if_flags & IFF_RUNNING) == 0)
855 LEMAC_INTR_DISABLE(sc);
857 while (!ifq_is_empty(&ifp->if_snd)) {
862 if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
863 ifp->if_flags |= IFF_OACTIVE;
867 tx_pg = LE_INB(sc, LEMAC_REG_FMQ); /* get free memory page */
869 * Check for good transmit page.
871 if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
873 ifp->if_flags |= IFF_OACTIVE;
877 m = ifq_dequeue(&ifp->if_snd);
878 LE_OUTB(sc, LEMAC_REG_MPN, tx_pg); /* Shift 2K window. */
881 * The first four bytes of each transmit buffer are for
882 * control information. The first byte is the control
883 * byte, then the length (why not word aligned?), then
884 * the off to the buffer.
887 txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
888 txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
889 *(u_int *) sc->le_membase = txhdr;
892 * Copy the packet to the board
895 m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
897 LE_OUTB(sc, LEMAC_REG_TQ, tx_pg); /* tell chip to transmit this packet */
901 m_freem(m); /* free the mbuf */
903 LEMAC_INTR_ENABLE(sc);
907 lemac_tne_intr(struct le_softc *sc)
909 int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
913 txsts = LE_INB(sc, LEMAC_REG_TDQ);
914 sc->le_if.if_opackets++; /* another one done */
915 if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
916 sc->le_if.if_collisions++;
918 sc->le_if.if_flags &= ~IFF_OACTIVE;
919 lemac_start(&sc->le_if);
923 lemac_txd_intr(struct le_softc *sc, unsigned cs_value)
926 * Read transmit status, remove transmit buffer from
927 * transmit queue and place on free memory queue,
928 * then reset transmitter.
929 * Increment appropriate counters.
933 sc->le_if.if_oerrors++;
934 if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
935 sc->le_if.if_collisions++;
936 sc->le_if.if_flags &= ~IFF_OACTIVE;
938 LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
939 /* Get Page number and write it back out */
941 LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
942 /* Turn back on transmitter */
946 lemac_read_eeprom(struct le_softc *sc)
953 ep = sc->lemac_eeprom;
954 for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
955 LE_OUTB(sc, LEMAC_REG_PI1, word_off);
956 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
958 DELAY(LEMAC_EEP_DELAY);
960 *ep = LE_INB(sc, LEMAC_REG_EE1); cksum += *ep++;
961 *ep = LE_INB(sc, LEMAC_REG_EE2); cksum += *ep++;
965 * Set up Transmit Control Byte for use later during transmit.
968 sc->lemac_txctl |= LEMAC_TX_FLAGS;
970 if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
971 sc->lemac_txctl &= ~LEMAC_TX_SQE;
973 if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
974 sc->lemac_txctl |= LEMAC_TX_LAB;
976 bcopy(&sc->lemac_eeprom[LEMAC_EEP_PRDNM], sc->lemac_prodname, LEMAC_EEP_PRDNMSZ);
977 sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
983 lemac_init_adapmem(struct le_softc *sc)
987 conf = LE_INB(sc, LEMAC_REG_CNF);
989 if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
990 sc->lemac_lastpage = 63;
991 conf &= ~LEMAC_CNF_DRAM;
993 sc->lemac_lastpage = 127;
994 conf |= LEMAC_CNF_DRAM;
997 LE_OUTB(sc, LEMAC_REG_CNF, conf);
999 for (pg = 1; pg <= sc->lemac_lastpage; pg++)
1000 LE_OUTB(sc, LEMAC_REG_FMQ, pg);
1006 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1008 * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
1011 static void depca_intr(struct le_softc *sc);
1012 static int lance_init_adapmem(struct le_softc *sc);
1013 static int lance_init_ring(struct le_softc *sc, ln_ring_t *rp, lance_ring_t *ri,
1014 unsigned ndescs, unsigned bufoffset,
1015 unsigned descoffset);
1016 static void lance_init(void *xsc);
1017 static void lance_reset(struct le_softc *sc);
1018 static void lance_intr(struct le_softc *sc);
1019 static int lance_rx_intr(struct le_softc *sc);
1020 static void lance_start(struct ifnet *ifp);
1021 static int lance_tx_intr(struct le_softc *sc);
1023 #define LN_BUFSIZE /* 380 */ 304 /* 1520 / 4 */
1024 #define LN_TXDESC_RATIO 2048
1025 #define LN_DESC_MAX 128
1029 unsigned lance_rx_misses;
1030 unsigned lance_rx_badcrc;
1031 unsigned lance_rx_badalign;
1032 unsigned lance_rx_badframe;
1033 unsigned lance_rx_buferror;
1034 unsigned lance_tx_deferred;
1035 unsigned lance_tx_single_collisions;
1036 unsigned lance_tx_multiple_collisions;
1037 unsigned lance_tx_excessive_collisions;
1038 unsigned lance_tx_late_collisions;
1040 unsigned lance_memory_errors;
1041 unsigned lance_inits;
1042 unsigned lance_tx_intrs;
1043 unsigned lance_tx_nospc[2];
1044 unsigned lance_tx_drains[2];
1045 unsigned lance_tx_orphaned;
1046 unsigned lance_tx_adoptions;
1047 unsigned lance_tx_emptied;
1048 unsigned lance_tx_deftxint;
1049 unsigned lance_tx_buferror;
1050 unsigned lance_high_txoutptr;
1051 unsigned lance_low_txheapsize;
1052 unsigned lance_low_txfree;
1053 unsigned lance_tx_intr_hidescs;
1054 /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
1056 unsigned lance_rx_intrs;
1057 unsigned lance_rx_badsop;
1058 unsigned lance_rx_contig;
1059 unsigned lance_rx_noncontig;
1060 unsigned lance_rx_intr_hidescs;
1061 unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
1062 /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
1065 #define LN_STAT(stat) (lance_stats.lance_ ## stat)
1066 #define LN_MINSTAT(stat, val) (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
1067 #define LN_MAXSTAT(stat, val) (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
1070 #define LN_STAT(stat) 0
1071 #define LN_MINSTAT(stat, val) 0
1072 #define LN_MAXSTAT(stat, val) 0
1075 #define LN_SELCSR(sc, csrno) (LE_OUTW(sc, sc->lance_rap, csrno))
1076 #define LN_INQCSR(sc) (LE_INW(sc, sc->lance_rap))
1078 #define LN_WRCSR(sc, val) (LE_OUTW(sc, sc->lance_rdp, val))
1079 #define LN_RDCSR(sc) (LE_INW(sc, sc->lance_rdp))
1082 #define LN_ZERO(sc, vaddr, len) bzero(vaddr, len)
1083 #define LN_COPYTO(sc, from, to, len) bcopy(from, to, len)
1085 #define LN_SETFLAG(sc, vaddr, val) \
1086 (((volatile u_char *) vaddr)[3] = (val))
1088 #define LN_PUTDESC(sc, desc, vaddr) \
1089 (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
1090 ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
1091 ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
1094 * Only get the descriptor flags and length/status. All else
1097 #define LN_GETDESC(sc, desc, vaddr) \
1098 (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
1099 ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
1102 * These definitions are specific to the DEC "DEPCA-style" NICs.
1103 * (DEPCA, DE10x, DE20[012], DE422)
1106 #define DEPCA_REG_NICSR 0 /* (RW;16) NI Control / Status */
1107 #define DEPCA_REG_RDP 4 /* (RW:16) LANCE RDP (data) register */
1108 #define DEPCA_REG_RAP 6 /* (RW:16) LANCE RAP (address) register */
1109 #define DEPCA_REG_ADDRROM 12 /* (R : 8) DEPCA Ethernet Address ROM */
1110 #define DEPCA_IOSPACE 16 /* DEPCAs use 16 bytes of IO space */
1112 #define DEPCA_NICSR_LED 0x0001 /* Light the LED on the back of the DEPCA */
1113 #define DEPCA_NICSR_ENABINTR 0x0002 /* Enable Interrupts */
1114 #define DEPCA_NICSR_MASKINTR 0x0004 /* Mask Interrupts */
1115 #define DEPCA_NICSR_AAC 0x0008 /* Address Counter Clear */
1116 #define DEPCA_NICSR_REMOTEBOOT 0x0010 /* Remote Boot Enabled (ignored) */
1117 #define DEPCA_NICSR_32KRAM 0x0020 /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
1118 #define DEPCA_NICSR_LOW32K 0x0040 /* Bank Select (A15 = !This Bit) */
1119 #define DEPCA_NICSR_SHE 0x0080 /* Shared RAM Enabled (ie hide ROM) */
1120 #define DEPCA_NICSR_BOOTTMO 0x0100 /* Remote Boot Timeout (ignored) */
1122 #define DEPCA_RDNICSR(sc) (LE_INW(sc, DEPCA_REG_NICSR))
1123 #define DEPCA_WRNICSR(sc, val) (LE_OUTW(sc, DEPCA_REG_NICSR, val))
1125 #define DEPCA_IDSTR_OFFSET 0xC006 /* ID String Offset */
1127 #define DEPCA_REG_EISAID 0x80
1128 #define DEPCA_EISAID_MASK 0xf0ffffff
1129 #define DEPCA_EISAID_DE422 0x2042A310
1133 DEPCA_DE100, DEPCA_DE101,
1135 DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
1140 static const char *depca_signatures[] = {
1144 "DE200", "DE201", "DE202",
1150 depca_probe(struct le_softc *sc, const struct le_board *bd, int *msize)
1152 unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
1155 * Find out how memory we are dealing with. Adjust
1156 * the ID string offset approriately if we are at
1157 * 32K. Make sure the ROM is enabled.
1159 nicsr = DEPCA_RDNICSR(sc);
1160 nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
1162 if (nicsr & DEPCA_NICSR_32KRAM) {
1164 * Make we are going to read the upper
1165 * 32K so we do read the ROM.
1167 sc->lance_ramsize = 32 * 1024;
1168 nicsr &= ~DEPCA_NICSR_LOW32K;
1169 sc->lance_ramoffset = 32 * 1024;
1170 idstr_offset -= sc->lance_ramsize;
1172 sc->lance_ramsize = 64 * 1024;
1173 sc->lance_ramoffset = 0;
1175 DEPCA_WRNICSR(sc, nicsr);
1177 sc->le_prodname = NULL;
1178 for (idx = 0; depca_signatures[idx] != NULL; idx++) {
1179 if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
1180 sc->le_prodname = depca_signatures[idx];
1185 if (sc->le_prodname == NULL) {
1187 * Try to get the EISA device if it's a DE422.
1189 if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
1190 && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
1191 == DEPCA_EISAID_DE422) {
1192 sc->le_prodname = "DE422";
1197 if (idx == DEPCA_CLASSIC)
1198 sc->lance_ramsize -= 16384; /* Can't use the ROM area on a DEPCA */
1201 * Try to read the address ROM.
1202 * Stop the LANCE, reset the Address ROM Counter (AAC),
1203 * read the NICSR to "clock" in the reset, and then
1204 * re-enable the Address ROM Counter. Now read the
1207 sc->lance_rdp = DEPCA_REG_RDP;
1208 sc->lance_rap = DEPCA_REG_RAP;
1209 sc->lance_csr3 = LN_CSR3_ALE;
1210 sc->le_mctbl = sc->lance_initb.ln_multi_mask;
1211 sc->le_mcmask = LN_MC_MASK;
1212 LN_SELCSR(sc, LN_CSR0);
1213 LN_WRCSR(sc, LN_CSR0_STOP);
1215 if (idx < DEPCA_DE200) {
1216 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
1217 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
1220 if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
1223 bcopy(sc->le_hwaddr, sc->le_ac.ac_enaddr, ETHER_ADDR_LEN);
1225 * Renable shared RAM.
1227 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
1229 le_intrvec[sc->le_if.if_dunit] = depca_intr;
1230 if (!lance_init_adapmem(sc))
1233 sc->if_reset = lance_reset;
1234 sc->if_init = lance_init;
1235 sc->le_if.if_start = lance_start;
1236 DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
1239 LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
1240 LN_STAT(low_txheapsize = 0xFFFFFFFF);
1241 *msize = sc->lance_ramsize;
1242 return DEPCA_IOSPACE;
1246 depca_intr(struct le_softc *sc)
1248 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
1253 * Here's as good a place to describe our paritioning of the
1254 * LANCE shared RAM space. (NOTE: this driver does not yet support
1255 * the concept of a LANCE being able to DMA).
1257 * First is the 24 (00:23) bytes for LANCE Initialization Block
1258 * Next are the recieve descriptors. The number is calculated from
1259 * how many LN_BUFSIZE buffers we can allocate (this number must
1260 * be a power of 2). Next are the transmit descriptors. The amount
1261 * of transmit descriptors is derived from the size of the RAM
1262 * divided by 1K. Now come the receive buffers (one for each receive
1263 * descriptor). Finally is the transmit heap. (no fixed buffers are
1264 * allocated so as to make the most use of the limited space).
1267 lance_init_adapmem(struct le_softc *sc)
1269 lance_addr_t rxbufoffset;
1270 lance_addr_t rxdescoffset, txdescoffset;
1271 unsigned rxdescs, txdescs;
1274 * First calculate how many descriptors we heap.
1275 * Note this assumes the ramsize is a power of two.
1277 sc->lance_rxbufsize = LN_BUFSIZE;
1279 while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
1282 if (rxdescs > LN_DESC_MAX) {
1283 sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
1284 rxdescs = LN_DESC_MAX;
1286 txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
1287 if (txdescs > LN_DESC_MAX)
1288 txdescs = LN_DESC_MAX;
1291 * Now calculate where everything goes in memory
1293 rxdescoffset = sizeof(ln_initb_t);
1294 txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
1295 rxbufoffset = txdescoffset + sizeof(ln_desc_t) * txdescs;
1297 sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
1299 * Remember these for debugging.
1301 sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
1302 sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
1305 * Initialize the rings.
1307 if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
1308 rxdescs, rxbufoffset, rxdescoffset))
1310 sc->lance_rxinfo.ri_heap = rxbufoffset;
1311 sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
1313 if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
1314 txdescs, 0, txdescoffset))
1316 sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
1317 sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
1320 * Set CSR1 and CSR2 to the address of the init block (which
1321 * for us is always 0.
1323 sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
1324 sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
1329 lance_init_ring(struct le_softc *sc, ln_ring_t *rp, lance_ring_t *ri,
1330 unsigned ndescs, lance_addr_t bufoffset, lance_addr_t descoffset)
1332 lance_descinfo_t *di;
1335 * Initialize the ring pointer in the LANCE InitBlock
1337 rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
1338 rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
1339 rp->r_log2_size = ffs(ndescs) - 1;
1342 * Allocate the ring entry descriptors and initialize
1343 * our ring information data structure. All these are
1344 * our copies and do not live in the LANCE RAM.
1346 ri->ri_first = malloc(ndescs * sizeof(*di), M_DEVBUF, M_WAITOK);
1347 ri->ri_free = ri->ri_max = ndescs;
1348 ri->ri_last = ri->ri_first + ri->ri_max;
1349 for (di = ri->ri_first; di < ri->ri_last; di++) {
1350 di->di_addr = sc->le_membase + descoffset;
1353 di->di_bufaddr = bufoffset;
1354 di->di_buflen = sc->lance_rxbufsize;
1355 bufoffset += sc->lance_rxbufsize;
1357 descoffset += sizeof(ln_desc_t);
1363 lance_dumpcsrs(struct le_softc *sc, const char *id)
1365 if_printf(&sc->le_if, "%s: nicsr=%04x", id, DEPCA_RDNICSR(sc));
1366 LN_SELCSR(sc, LN_CSR0);
1367 printf(" csr0=%04x", LN_RDCSR(sc));
1368 LN_SELCSR(sc, LN_CSR1);
1369 printf(" csr1=%04x", LN_RDCSR(sc));
1370 LN_SELCSR(sc, LN_CSR2);
1371 printf(" csr2=%04x", LN_RDCSR(sc));
1372 LN_SELCSR(sc, LN_CSR3);
1373 printf(" csr3=%04x\n", LN_RDCSR(sc));
1374 LN_SELCSR(sc, LN_CSR0);
1378 lance_reset(struct le_softc *sc)
1382 /* lance_dumpcsrs(sc, "lance_reset: start"); */
1384 LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
1385 LN_WRCSR(sc, LN_CSR0_STOP);
1388 sc->le_flags &= ~IFF_UP;
1389 sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
1391 le_multi_filter(sc); /* initialize the multicast table */
1392 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
1393 sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
1394 sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
1395 sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
1396 sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
1398 sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
1399 sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
1400 sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
1401 if (sc->le_if.if_flags & IFF_PROMISC) {
1402 sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
1404 sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
1407 * We force the init block to be at the start
1408 * of the LANCE's RAM buffer.
1410 LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
1411 LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
1412 LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
1413 LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
1415 /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
1418 * clear INITDONE and INIT the chip
1420 LN_SELCSR(sc, LN_CSR0);
1421 LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
1426 if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
1431 if ((csr & LN_CSR0_INITDONE) == 0) { /* make sure we got out okay */
1432 lance_dumpcsrs(sc, "lance_reset: reset failure");
1434 /* lance_dumpcsrs(sc, "lance_reset: end"); */
1435 sc->le_if.if_flags |= IFF_UP;
1436 sc->le_flags |= IFF_UP;
1441 lance_init(void *xsc)
1443 struct le_softc *sc = (struct le_softc *)xsc;
1445 lance_descinfo_t *di;
1449 if (sc->le_if.if_flags & IFF_RUNNING) {
1453 * If we were running, abort any pending transmits.
1455 ri = &sc->lance_txinfo;
1456 di = ri->ri_nextout;
1457 while (ri->ri_free < ri->ri_max) {
1458 if (--di == ri->ri_first)
1459 di = ri->ri_nextout - 1;
1460 if (di->di_mbuf == NULL)
1462 m_free(di->di_mbuf);
1471 * Reset the transmit ring. Make sure we own all the buffers.
1472 * Also reset the transmit heap.
1474 sc->le_if.if_flags &= ~IFF_OACTIVE;
1475 ri = &sc->lance_txinfo;
1476 for (di = ri->ri_first; di < ri->ri_last; di++) {
1477 if (di->di_mbuf != NULL) {
1478 m_freem(di->di_mbuf);
1482 desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
1483 desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
1485 LN_PUTDESC(sc, &desc, di->di_addr);
1487 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1488 ri->ri_free = ri->ri_max;
1489 ri->ri_outptr = ri->ri_heap;
1490 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1492 ri = &sc->lance_rxinfo;
1493 desc.d_flag = LN_DFLAG_OWNER;
1494 desc.d_buflen = 0 - sc->lance_rxbufsize;
1495 for (di = ri->ri_first; di < ri->ri_last; di++) {
1496 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1497 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1498 LN_PUTDESC(sc, &desc, di->di_addr);
1500 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1501 ri->ri_outptr = ri->ri_heap;
1502 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1505 if (sc->le_if.if_flags & IFF_UP) {
1506 sc->le_if.if_flags |= IFF_RUNNING;
1507 LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
1508 /* lance_dumpcsrs(sc, "lance_init: up"); */
1509 lance_start(&sc->le_if);
1511 /* lance_dumpcsrs(sc, "lance_init: down"); */
1512 sc->le_if.if_flags &= ~IFF_RUNNING;
1517 lance_intr(struct le_softc *sc)
1521 oldcsr = LN_RDCSR(sc);
1522 oldcsr &= ~LN_CSR0_ENABINTR;
1523 LN_WRCSR(sc, oldcsr);
1524 LN_WRCSR(sc, LN_CSR0_ENABINTR);
1526 if (oldcsr & LN_CSR0_ERRSUM) {
1527 if (oldcsr & LN_CSR0_MISS) {
1529 * LN_CSR0_MISS is signaled when the LANCE receiver
1530 * loses a packet because it doesn't own a receive
1531 * descriptor. Rev. D LANCE chips, which are no
1532 * longer used, require a chip reset as described
1535 LN_STAT(rx_misses++);
1537 if (oldcsr & LN_CSR0_MEMERROR) {
1538 LN_STAT(memory_errors++);
1539 if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
1546 if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
1551 if (oldcsr & LN_CSR0_TXINT) {
1552 if (lance_tx_intr(sc))
1553 lance_start(&sc->le_if);
1556 if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
1557 if_printf(&sc->le_if, "lance_intr: stray interrupt\n");
1561 lance_rx_intr(struct le_softc *sc)
1563 lance_ring_t *ri = &sc->lance_rxinfo;
1564 lance_descinfo_t *eop;
1566 int ndescs, total_len, rxdescs;
1568 LN_STAT(rx_intrs++);
1570 for (rxdescs = 0;;) {
1572 * Now to try to find the end of this packet chain.
1574 for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
1576 * If we don't own this descriptor, the packet ain't
1577 * all here so return because we are done.
1579 LN_GETDESC(sc, &desc, eop->di_addr);
1580 if (desc.d_flag & LN_DFLAG_OWNER)
1583 * In case we have missed a packet and gotten the
1584 * LANCE confused, make sure we are pointing at the
1585 * start of a packet. If we aren't, something is really
1586 * strange so reinit the LANCE.
1588 if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
1589 LN_STAT(rx_buferror++);
1592 if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
1593 LN_STAT(rx_badsop++);
1596 if (desc.d_flag & LN_DFLAG_EOP)
1598 if (++eop == ri->ri_last)
1602 total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
1603 if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
1605 * Valid Packet -- If the SOP is less than or equal to the EOP
1606 * or the length is less than the receive buffer size, then the
1607 * packet is contiguous in memory and can be copied in one shot.
1608 * Otherwise we need to copy two segments to get the entire
1611 if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
1612 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1613 total_len, total_len, NULL);
1614 LN_STAT(rx_contig++);
1616 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1618 ri->ri_heapend - ri->ri_nextin->di_bufaddr,
1619 sc->le_membase + ri->ri_first->di_bufaddr);
1620 LN_STAT(rx_noncontig++);
1624 * If the packet is bad, increment the
1627 sc->le_if.if_ierrors++;
1628 if (desc.d_flag & LN_DFLAG_RxBADCRC)
1629 LN_STAT(rx_badcrc++);
1630 if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
1631 LN_STAT(rx_badalign++);
1632 if (desc.d_flag & LN_DFLAG_RxFRAMING)
1633 LN_STAT(rx_badframe++);
1635 sc->le_if.if_ipackets++;
1636 LN_STAT(rx_ndescs[ndescs-1]++);
1638 while (ndescs-- > 0) {
1639 LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
1640 if (++ri->ri_nextin == ri->ri_last)
1641 ri->ri_nextin = ri->ri_first;
1644 /* LN_STAT(rx_intr_descs[rxdescs]++); */
1645 LN_MAXSTAT(rx_intr_hidescs, rxdescs);
1651 lance_start(struct ifnet *ifp)
1653 struct le_softc *sc = (struct le_softc *) ifp;
1654 lance_ring_t *ri = &sc->lance_txinfo;
1655 lance_descinfo_t *di;
1658 struct mbuf *m, *m0;
1661 if ((ifp->if_flags & IFF_RUNNING) == 0)
1665 m = ifq_poll(&ifp->if_snd);
1670 * Make the packet meets the minimum size for Ethernet.
1671 * The slop is so that we also use an even number of longwards.
1673 len = ETHERMIN + sizeof(struct ether_header);
1674 if (m->m_pkthdr.len > len)
1675 len = m->m_pkthdr.len;
1677 slop = (8 - len) & 3;
1679 * If there are no free ring entries (there must be always
1680 * one owned by the host), or there's not enough space for
1681 * this packet, or this packet would wrap around the end
1682 * of LANCE RAM then wait for the transmits to empty for
1683 * space and ring entries to become available.
1685 if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
1687 * Try to see if we can free up anything off the transit ring.
1689 if (lance_tx_intr(sc) > 0) {
1690 LN_STAT(tx_drains[0]++);
1693 LN_STAT(tx_nospc[0]++);
1697 if (len + slop > ri->ri_heapend - ri->ri_outptr) {
1699 * Since the packet won't fit in the end of the transmit
1700 * heap, see if there is space at the beginning of the transmit
1701 * heap. If not, try again when there is space.
1703 LN_STAT(tx_orphaned++);
1704 slop += ri->ri_heapend - ri->ri_outptr;
1705 if (len + slop > ri->ri_outsize) {
1706 LN_STAT(tx_nospc[1]++);
1710 * Point to the beginning of the heap
1712 ri->ri_outptr = ri->ri_heap;
1713 LN_STAT(tx_adoptions++);
1717 * Initialize the descriptor (saving the buffer address,
1718 * buffer length, and mbuf) and write the packet out
1721 di = ri->ri_nextout;
1722 di->di_bufaddr = ri->ri_outptr;
1723 di->di_buflen = len + slop;
1725 bp = sc->le_membase + di->di_bufaddr;
1726 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1727 LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
1731 * Zero out the remainder if needed (< ETHERMIN).
1733 if (m->m_pkthdr.len < len)
1734 LN_ZERO(sc, bp, len - m->m_pkthdr.len);
1736 m = ifq_dequeue(&ifp->if_snd);
1739 * Finally, copy out the descriptor and tell the
1740 * LANCE to transmit!.
1742 desc.d_buflen = 0 - len;
1743 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1744 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1745 desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
1746 LN_PUTDESC(sc, &desc, di->di_addr);
1747 LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
1750 * Do our bookkeeping with our transmit heap.
1751 * (if we wrap, point back to the beginning).
1753 ri->ri_outptr += di->di_buflen;
1754 ri->ri_outsize -= di->di_buflen;
1755 LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
1756 LN_MINSTAT(low_txheapsize, ri->ri_outsize);
1758 if (ri->ri_outptr == ri->ri_heapend)
1759 ri->ri_outptr = ri->ri_heap;
1762 if (++ri->ri_nextout == ri->ri_last)
1763 ri->ri_nextout = ri->ri_first;
1764 LN_MINSTAT(low_txfree, ri->ri_free);
1767 ifp->if_flags |= IFF_OACTIVE;
1771 lance_tx_intr(struct le_softc *sc)
1773 lance_ring_t *ri = &sc->lance_txinfo;
1776 LN_STAT(tx_intrs++);
1777 for (xmits = 0; ri->ri_free < ri->ri_max; ) {
1780 LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
1781 if (desc.d_flag & LN_DFLAG_OWNER)
1784 if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
1785 sc->le_if.if_collisions++;
1786 if (desc.d_flag & LN_DFLAG_TxDEFERRED)
1787 LN_STAT(tx_deferred++);
1788 if (desc.d_flag & LN_DFLAG_TxONECOLL)
1789 LN_STAT(tx_single_collisions++);
1790 if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
1791 LN_STAT(tx_multiple_collisions++);
1793 if (desc.d_flag & LN_DFLAG_TxERRSUM) {
1794 if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
1795 LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
1796 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
1798 LN_STAT(tx_excessive_collisions++);
1799 if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
1801 if_printf(&sc->le_if, "lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
1802 tdr, (tdr*99)/1000, (tdr*117)/1000);
1805 if (desc.d_status & LN_DSTS_TxBUFERROR)
1806 LN_STAT(tx_buferror++);
1807 sc->le_if.if_oerrors++;
1808 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
1812 LN_STAT(tx_late_collisions++);
1816 m_freem(ri->ri_nextin->di_mbuf);
1817 ri->ri_nextin->di_mbuf = NULL;
1818 sc->le_if.if_opackets++;
1820 ri->ri_outsize += ri->ri_nextin->di_buflen;
1821 if (++ri->ri_nextin == ri->ri_last)
1822 ri->ri_nextin = ri->ri_first;
1823 sc->le_if.if_flags &= ~IFF_OACTIVE;
1826 if (ri->ri_free == ri->ri_max)
1827 LN_STAT(tx_emptied++);
1828 /* LN_STAT(tx_intr_descs[xmits]++); */
1829 LN_MAXSTAT(tx_intr_hidescs, xmits);